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net: ep93xx_eth: drop GFP_DMA from call to dma_alloc_coherent()
[linux-2.6/kvm.git] / drivers / net / sky2.c
blob3ee41da130c2e683063799421bb58019dfa4621e
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/ip.h>
36 #include <linux/slab.h>
37 #include <net/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/in.h>
40 #include <linux/delay.h>
41 #include <linux/workqueue.h>
42 #include <linux/if_vlan.h>
43 #include <linux/prefetch.h>
44 #include <linux/debugfs.h>
45 #include <linux/mii.h>
46
47 #include <asm/irq.h>
48
49 #include "sky2.h"
50
51 #define DRV_NAME "sky2"
52 #define DRV_VERSION "1.28"
53
54 /*
55 * The Yukon II chipset takes 64 bit command blocks (called list elements)
56 * that are organized into three (receive, transmit, status) different rings
57 * similar to Tigon3.
58 */
59
60 #define RX_LE_SIZE 1024
61 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
62 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
63 #define RX_DEF_PENDING RX_MAX_PENDING
64
65 /* This is the worst case number of transmit list elements for a single skb:
66 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
67 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
68 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
69 #define TX_MAX_PENDING 1024
70 #define TX_DEF_PENDING 127
71
72 #define TX_WATCHDOG (5 * HZ)
73 #define NAPI_WEIGHT 64
74 #define PHY_RETRIES 1000
75
76 #define SKY2_EEPROM_MAGIC 0x9955aabb
77
78 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
79
80 static const u32 default_msg =
81 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
82 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
83 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
84
85 static int debug = -1; /* defaults above */
86 module_param(debug, int, 0);
87 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
88
89 static int copybreak __read_mostly = 128;
90 module_param(copybreak, int, 0);
91 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
92
93 static int disable_msi = 0;
94 module_param(disable_msi, int, 0);
95 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
96
97 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
98 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
101 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
139 { 0 }
140 };
141
142 MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144 /* Avoid conditionals by using array */
145 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
147 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
148
149 static void sky2_set_multicast(struct net_device *dev);
150
151 /* Access to PHY via serial interconnect */
152 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
153 {
154 int i;
155
156 gma_write16(hw, port, GM_SMI_DATA, val);
157 gma_write16(hw, port, GM_SMI_CTRL,
158 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
159
160 for (i = 0; i < PHY_RETRIES; i++) {
161 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
162 if (ctrl == 0xffff)
163 goto io_error;
164
165 if (!(ctrl & GM_SMI_CT_BUSY))
166 return 0;
167
168 udelay(10);
169 }
170
171 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
172 return -ETIMEDOUT;
173
174 io_error:
175 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
176 return -EIO;
177 }
178
179 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
180 {
181 int i;
182
183 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
184 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
185
186 for (i = 0; i < PHY_RETRIES; i++) {
187 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
188 if (ctrl == 0xffff)
189 goto io_error;
190
191 if (ctrl & GM_SMI_CT_RD_VAL) {
192 *val = gma_read16(hw, port, GM_SMI_DATA);
193 return 0;
194 }
195
196 udelay(10);
197 }
198
199 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
200 return -ETIMEDOUT;
201 io_error:
202 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
203 return -EIO;
204 }
205
206 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
207 {
208 u16 v;
209 __gm_phy_read(hw, port, reg, &v);
210 return v;
211 }
212
213
214 static void sky2_power_on(struct sky2_hw *hw)
215 {
216 /* switch power to VCC (WA for VAUX problem) */
217 sky2_write8(hw, B0_POWER_CTRL,
218 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
219
220 /* disable Core Clock Division, */
221 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
222
223 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
224 /* enable bits are inverted */
225 sky2_write8(hw, B2_Y2_CLK_GATE,
226 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
227 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
228 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
229 else
230 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
231
232 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
233 u32 reg;
234
235 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
236
237 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
238 /* set all bits to 0 except bits 15..12 and 8 */
239 reg &= P_ASPM_CONTROL_MSK;
240 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
241
242 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
243 /* set all bits to 0 except bits 28 & 27 */
244 reg &= P_CTL_TIM_VMAIN_AV_MSK;
245 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
246
247 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
248
249 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
250
251 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
252 reg = sky2_read32(hw, B2_GP_IO);
253 reg |= GLB_GPIO_STAT_RACE_DIS;
254 sky2_write32(hw, B2_GP_IO, reg);
255
256 sky2_read32(hw, B2_GP_IO);
257 }
258
259 /* Turn on "driver loaded" LED */
260 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
261 }
262
263 static void sky2_power_aux(struct sky2_hw *hw)
264 {
265 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
266 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
267 else
268 /* enable bits are inverted */
269 sky2_write8(hw, B2_Y2_CLK_GATE,
270 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
271 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
272 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
273
274 /* switch power to VAUX if supported and PME from D3cold */
275 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
276 pci_pme_capable(hw->pdev, PCI_D3cold))
277 sky2_write8(hw, B0_POWER_CTRL,
278 (PC_VAUX_ENA | PC_VCC_ENA |
279 PC_VAUX_ON | PC_VCC_OFF));
280
281 /* turn off "driver loaded LED" */
282 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
283 }
284
285 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
286 {
287 u16 reg;
288
289 /* disable all GMAC IRQ's */
290 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
291
292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300 }
301
302 /* flow control to advertise bits */
303 static const u16 copper_fc_adv[] = {
304 [FC_NONE] = 0,
305 [FC_TX] = PHY_M_AN_ASP,
306 [FC_RX] = PHY_M_AN_PC,
307 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
308 };
309
310 /* flow control to advertise bits when using 1000BaseX */
311 static const u16 fiber_fc_adv[] = {
312 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
313 [FC_TX] = PHY_M_P_ASYM_MD_X,
314 [FC_RX] = PHY_M_P_SYM_MD_X,
315 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
316 };
317
318 /* flow control to GMA disable bits */
319 static const u16 gm_fc_disable[] = {
320 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
321 [FC_TX] = GM_GPCR_FC_RX_DIS,
322 [FC_RX] = GM_GPCR_FC_TX_DIS,
323 [FC_BOTH] = 0,
324 };
325
326
327 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
328 {
329 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
330 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
331
332 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
333 !(hw->flags & SKY2_HW_NEWER_PHY)) {
334 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
335
336 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
337 PHY_M_EC_MAC_S_MSK);
338 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
339
340 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
341 if (hw->chip_id == CHIP_ID_YUKON_EC)
342 /* set downshift counter to 3x and enable downshift */
343 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
344 else
345 /* set master & slave downshift counter to 1x */
346 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
347
348 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
349 }
350
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 if (sky2_is_copper(hw)) {
353 if (!(hw->flags & SKY2_HW_GIGABIT)) {
354 /* enable automatic crossover */
355 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
356
357 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
358 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
359 u16 spec;
360
361 /* Enable Class A driver for FE+ A0 */
362 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
363 spec |= PHY_M_FESC_SEL_CL_A;
364 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
365 }
366 } else {
367 /* disable energy detect */
368 ctrl &= ~PHY_M_PC_EN_DET_MSK;
369
370 /* enable automatic crossover */
371 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
372
373 /* downshift on PHY 88E1112 and 88E1149 is changed */
374 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
375 (hw->flags & SKY2_HW_NEWER_PHY)) {
376 /* set downshift counter to 3x and enable downshift */
377 ctrl &= ~PHY_M_PC_DSC_MSK;
378 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
379 }
380 }
381 } else {
382 /* workaround for deviation #4.88 (CRC errors) */
383 /* disable Automatic Crossover */
384
385 ctrl &= ~PHY_M_PC_MDIX_MSK;
386 }
387
388 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
389
390 /* special setup for PHY 88E1112 Fiber */
391 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
392 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
393
394 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
396 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
397 ctrl &= ~PHY_M_MAC_MD_MSK;
398 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
399 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
400
401 if (hw->pmd_type == 'P') {
402 /* select page 1 to access Fiber registers */
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
404
405 /* for SFP-module set SIGDET polarity to low */
406 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
407 ctrl |= PHY_M_FIB_SIGD_POL;
408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
409 }
410
411 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
412 }
413
414 ctrl = PHY_CT_RESET;
415 ct1000 = 0;
416 adv = PHY_AN_CSMA;
417 reg = 0;
418
419 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
420 if (sky2_is_copper(hw)) {
421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 ct1000 |= PHY_M_1000C_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 ct1000 |= PHY_M_1000C_AHD;
425 if (sky2->advertising & ADVERTISED_100baseT_Full)
426 adv |= PHY_M_AN_100_FD;
427 if (sky2->advertising & ADVERTISED_100baseT_Half)
428 adv |= PHY_M_AN_100_HD;
429 if (sky2->advertising & ADVERTISED_10baseT_Full)
430 adv |= PHY_M_AN_10_FD;
431 if (sky2->advertising & ADVERTISED_10baseT_Half)
432 adv |= PHY_M_AN_10_HD;
433
434 } else { /* special defines for FIBER (88E1040S only) */
435 if (sky2->advertising & ADVERTISED_1000baseT_Full)
436 adv |= PHY_M_AN_1000X_AFD;
437 if (sky2->advertising & ADVERTISED_1000baseT_Half)
438 adv |= PHY_M_AN_1000X_AHD;
439 }
440
441 /* Restart Auto-negotiation */
442 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
443 } else {
444 /* forced speed/duplex settings */
445 ct1000 = PHY_M_1000C_MSE;
446
447 /* Disable auto update for duplex flow control and duplex */
448 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
449
450 switch (sky2->speed) {
451 case SPEED_1000:
452 ctrl |= PHY_CT_SP1000;
453 reg |= GM_GPCR_SPEED_1000;
454 break;
455 case SPEED_100:
456 ctrl |= PHY_CT_SP100;
457 reg |= GM_GPCR_SPEED_100;
458 break;
459 }
460
461 if (sky2->duplex == DUPLEX_FULL) {
462 reg |= GM_GPCR_DUP_FULL;
463 ctrl |= PHY_CT_DUP_MD;
464 } else if (sky2->speed < SPEED_1000)
465 sky2->flow_mode = FC_NONE;
466 }
467
468 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
469 if (sky2_is_copper(hw))
470 adv |= copper_fc_adv[sky2->flow_mode];
471 else
472 adv |= fiber_fc_adv[sky2->flow_mode];
473 } else {
474 reg |= GM_GPCR_AU_FCT_DIS;
475 reg |= gm_fc_disable[sky2->flow_mode];
476
477 /* Forward pause packets to GMAC? */
478 if (sky2->flow_mode & FC_RX)
479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
480 else
481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
482 }
483
484 gma_write16(hw, port, GM_GP_CTRL, reg);
485
486 if (hw->flags & SKY2_HW_GIGABIT)
487 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
488
489 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
490 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
491
492 /* Setup Phy LED's */
493 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
494 ledover = 0;
495
496 switch (hw->chip_id) {
497 case CHIP_ID_YUKON_FE:
498 /* on 88E3082 these bits are at 11..9 (shifted left) */
499 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
500
501 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
502
503 /* delete ACT LED control bits */
504 ctrl &= ~PHY_M_FELP_LED1_MSK;
505 /* change ACT LED control to blink mode */
506 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
507 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
508 break;
509
510 case CHIP_ID_YUKON_FE_P:
511 /* Enable Link Partner Next Page */
512 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
513 ctrl |= PHY_M_PC_ENA_LIP_NP;
514
515 /* disable Energy Detect and enable scrambler */
516 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
517 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
518
519 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
520 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
521 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
522 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
523
524 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
525 break;
526
527 case CHIP_ID_YUKON_XL:
528 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
529
530 /* select page 3 to access LED control register */
531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
532
533 /* set LED Function Control register */
534 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
535 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
536 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
537 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
538 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
539
540 /* set Polarity Control register */
541 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
542 (PHY_M_POLC_LS1_P_MIX(4) |
543 PHY_M_POLC_IS0_P_MIX(4) |
544 PHY_M_POLC_LOS_CTRL(2) |
545 PHY_M_POLC_INIT_CTRL(2) |
546 PHY_M_POLC_STA1_CTRL(2) |
547 PHY_M_POLC_STA0_CTRL(2)));
548
549 /* restore page register */
550 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
551 break;
552
553 case CHIP_ID_YUKON_EC_U:
554 case CHIP_ID_YUKON_EX:
555 case CHIP_ID_YUKON_SUPR:
556 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
557
558 /* select page 3 to access LED control register */
559 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
560
561 /* set LED Function Control register */
562 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
563 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
564 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
565 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
566 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
567
568 /* set Blink Rate in LED Timer Control Register */
569 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
570 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
571 /* restore page register */
572 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
573 break;
574
575 default:
576 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
577 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
578
579 /* turn off the Rx LED (LED_RX) */
580 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
581 }
582
583 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
584 /* apply fixes in PHY AFE */
585 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
586
587 /* increase differential signal amplitude in 10BASE-T */
588 gm_phy_write(hw, port, 0x18, 0xaa99);
589 gm_phy_write(hw, port, 0x17, 0x2011);
590
591 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
592 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
593 gm_phy_write(hw, port, 0x18, 0xa204);
594 gm_phy_write(hw, port, 0x17, 0x2002);
595 }
596
597 /* set page register to 0 */
598 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
599 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
600 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
601 /* apply workaround for integrated resistors calibration */
602 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
603 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
604 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
605 /* apply fixes in PHY AFE */
606 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
607
608 /* apply RDAC termination workaround */
609 gm_phy_write(hw, port, 24, 0x2800);
610 gm_phy_write(hw, port, 23, 0x2001);
611
612 /* set page register back to 0 */
613 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
614 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
615 hw->chip_id < CHIP_ID_YUKON_SUPR) {
616 /* no effect on Yukon-XL */
617 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
618
619 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
620 sky2->speed == SPEED_100) {
621 /* turn on 100 Mbps LED (LED_LINK100) */
622 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
623 }
624
625 if (ledover)
626 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
627
628 }
629
630 /* Enable phy interrupt on auto-negotiation complete (or link up) */
631 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
632 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
633 else
634 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
635 }
636
637 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
638 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
639
640 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
641 {
642 u32 reg1;
643
644 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
645 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
646 reg1 &= ~phy_power[port];
647
648 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
649 reg1 |= coma_mode[port];
650
651 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
652 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
653 sky2_pci_read32(hw, PCI_DEV_REG1);
654
655 if (hw->chip_id == CHIP_ID_YUKON_FE)
656 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
657 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
658 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
659 }
660
661 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
662 {
663 u32 reg1;
664 u16 ctrl;
665
666 /* release GPHY Control reset */
667 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
668
669 /* release GMAC reset */
670 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
671
672 if (hw->flags & SKY2_HW_NEWER_PHY) {
673 /* select page 2 to access MAC control register */
674 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
675
676 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
677 /* allow GMII Power Down */
678 ctrl &= ~PHY_M_MAC_GMIF_PUP;
679 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
680
681 /* set page register back to 0 */
682 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
683 }
684
685 /* setup General Purpose Control Register */
686 gma_write16(hw, port, GM_GP_CTRL,
687 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
688 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
689 GM_GPCR_AU_SPD_DIS);
690
691 if (hw->chip_id != CHIP_ID_YUKON_EC) {
692 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
693 /* select page 2 to access MAC control register */
694 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
695
696 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
697 /* enable Power Down */
698 ctrl |= PHY_M_PC_POW_D_ENA;
699 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
700
701 /* set page register back to 0 */
702 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
703 }
704
705 /* set IEEE compatible Power Down Mode (dev. #4.99) */
706 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
707 }
708
709 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
710 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
711 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
712 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
713 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
714 }
715
716 /* Enable Rx/Tx */
717 static void sky2_enable_rx_tx(struct sky2_port *sky2)
718 {
719 struct sky2_hw *hw = sky2->hw;
720 unsigned port = sky2->port;
721 u16 reg;
722
723 reg = gma_read16(hw, port, GM_GP_CTRL);
724 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
725 gma_write16(hw, port, GM_GP_CTRL, reg);
726 }
727
728 /* Force a renegotiation */
729 static void sky2_phy_reinit(struct sky2_port *sky2)
730 {
731 spin_lock_bh(&sky2->phy_lock);
732 sky2_phy_init(sky2->hw, sky2->port);
733 sky2_enable_rx_tx(sky2);
734 spin_unlock_bh(&sky2->phy_lock);
735 }
736
737 /* Put device in state to listen for Wake On Lan */
738 static void sky2_wol_init(struct sky2_port *sky2)
739 {
740 struct sky2_hw *hw = sky2->hw;
741 unsigned port = sky2->port;
742 enum flow_control save_mode;
743 u16 ctrl;
744
745 /* Bring hardware out of reset */
746 sky2_write16(hw, B0_CTST, CS_RST_CLR);
747 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
748
749 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
750 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
751
752 /* Force to 10/100
753 * sky2_reset will re-enable on resume
754 */
755 save_mode = sky2->flow_mode;
756 ctrl = sky2->advertising;
757
758 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
759 sky2->flow_mode = FC_NONE;
760
761 spin_lock_bh(&sky2->phy_lock);
762 sky2_phy_power_up(hw, port);
763 sky2_phy_init(hw, port);
764 spin_unlock_bh(&sky2->phy_lock);
765
766 sky2->flow_mode = save_mode;
767 sky2->advertising = ctrl;
768
769 /* Set GMAC to no flow control and auto update for speed/duplex */
770 gma_write16(hw, port, GM_GP_CTRL,
771 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
772 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
773
774 /* Set WOL address */
775 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
776 sky2->netdev->dev_addr, ETH_ALEN);
777
778 /* Turn on appropriate WOL control bits */
779 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
780 ctrl = 0;
781 if (sky2->wol & WAKE_PHY)
782 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
783 else
784 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
785
786 if (sky2->wol & WAKE_MAGIC)
787 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
788 else
789 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
790
791 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
792 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
793
794 /* Disable PiG firmware */
795 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
796
797 /* block receiver */
798 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
799 }
800
801 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
802 {
803 struct net_device *dev = hw->dev[port];
804
805 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
806 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
807 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
808 /* Yukon-Extreme B0 and further Extreme devices */
809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
810 } else if (dev->mtu > ETH_DATA_LEN) {
811 /* set Tx GMAC FIFO Almost Empty Threshold */
812 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
813 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
814
815 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
816 } else
817 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
818 }
819
820 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
821 {
822 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
823 u16 reg;
824 u32 rx_reg;
825 int i;
826 const u8 *addr = hw->dev[port]->dev_addr;
827
828 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
829 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
830
831 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
832
833 if (hw->chip_id == CHIP_ID_YUKON_XL &&
834 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
835 port == 1) {
836 /* WA DEV_472 -- looks like crossed wires on port 2 */
837 /* clear GMAC 1 Control reset */
838 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
839 do {
840 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
841 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
842 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
843 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
844 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
845 }
846
847 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
848
849 /* Enable Transmit FIFO Underrun */
850 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
851
852 spin_lock_bh(&sky2->phy_lock);
853 sky2_phy_power_up(hw, port);
854 sky2_phy_init(hw, port);
855 spin_unlock_bh(&sky2->phy_lock);
856
857 /* MIB clear */
858 reg = gma_read16(hw, port, GM_PHY_ADDR);
859 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
860
861 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
862 gma_read16(hw, port, i);
863 gma_write16(hw, port, GM_PHY_ADDR, reg);
864
865 /* transmit control */
866 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
867
868 /* receive control reg: unicast + multicast + no FCS */
869 gma_write16(hw, port, GM_RX_CTRL,
870 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
871
872 /* transmit flow control */
873 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
874
875 /* transmit parameter */
876 gma_write16(hw, port, GM_TX_PARAM,
877 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
878 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
879 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
880 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
881
882 /* serial mode register */
883 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
884 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
885
886 if (hw->dev[port]->mtu > ETH_DATA_LEN)
887 reg |= GM_SMOD_JUMBO_ENA;
888
889 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
890 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
891 reg |= GM_NEW_FLOW_CTRL;
892
893 gma_write16(hw, port, GM_SERIAL_MODE, reg);
894
895 /* virtual address for data */
896 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
897
898 /* physical address: used for pause frames */
899 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
900
901 /* ignore counter overflows */
902 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
903 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
904 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
905
906 /* Configure Rx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
908 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
909 if (hw->chip_id == CHIP_ID_YUKON_EX ||
910 hw->chip_id == CHIP_ID_YUKON_FE_P)
911 rx_reg |= GMF_RX_OVER_ON;
912
913 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
914
915 if (hw->chip_id == CHIP_ID_YUKON_XL) {
916 /* Hardware errata - clear flush mask */
917 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
918 } else {
919 /* Flush Rx MAC FIFO on any flow control or error */
920 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
921 }
922
923 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
924 reg = RX_GMF_FL_THR_DEF + 1;
925 /* Another magic mystery workaround from sk98lin */
926 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
927 hw->chip_rev == CHIP_REV_YU_FE2_A0)
928 reg = 0x178;
929 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
930
931 /* Configure Tx MAC FIFO */
932 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
933 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
934
935 /* On chips without ram buffer, pause is controlled by MAC level */
936 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
937 /* Pause threshold is scaled by 8 in bytes */
938 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
939 hw->chip_rev == CHIP_REV_YU_FE2_A0)
940 reg = 1568 / 8;
941 else
942 reg = 1024 / 8;
943 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
944 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
945
946 sky2_set_tx_stfwd(hw, port);
947 }
948
949 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
950 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
951 /* disable dynamic watermark */
952 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
953 reg &= ~TX_DYN_WM_ENA;
954 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
955 }
956 }
957
958 /* Assign Ram Buffer allocation to queue */
959 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
960 {
961 u32 end;
962
963 /* convert from K bytes to qwords used for hw register */
964 start *= 1024/8;
965 space *= 1024/8;
966 end = start + space - 1;
967
968 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
969 sky2_write32(hw, RB_ADDR(q, RB_START), start);
970 sky2_write32(hw, RB_ADDR(q, RB_END), end);
971 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
972 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
973
974 if (q == Q_R1 || q == Q_R2) {
975 u32 tp = space - space/4;
976
977 /* On receive queue's set the thresholds
978 * give receiver priority when > 3/4 full
979 * send pause when down to 2K
980 */
981 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
982 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
983
984 tp = space - 2048/8;
985 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
986 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
987 } else {
988 /* Enable store & forward on Tx queue's because
989 * Tx FIFO is only 1K on Yukon
990 */
991 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
992 }
993
994 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
995 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
996 }
997
998 /* Setup Bus Memory Interface */
999 static void sky2_qset(struct sky2_hw *hw, u16 q)
1000 {
1001 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1002 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1003 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1004 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1005 }
1006
1007 /* Setup prefetch unit registers. This is the interface between
1008 * hardware and driver list elements
1009 */
1010 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1011 dma_addr_t addr, u32 last)
1012 {
1013 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1014 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1015 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1017 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1018 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1019
1020 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1021 }
1022
1023 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1024 {
1025 struct sky2_tx_le *le = sky2->tx_le + *slot;
1026
1027 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1028 le->ctrl = 0;
1029 return le;
1030 }
1031
1032 static void tx_init(struct sky2_port *sky2)
1033 {
1034 struct sky2_tx_le *le;
1035
1036 sky2->tx_prod = sky2->tx_cons = 0;
1037 sky2->tx_tcpsum = 0;
1038 sky2->tx_last_mss = 0;
1039
1040 le = get_tx_le(sky2, &sky2->tx_prod);
1041 le->addr = 0;
1042 le->opcode = OP_ADDR64 | HW_OWNER;
1043 sky2->tx_last_upper = 0;
1044 }
1045
1046 /* Update chip's next pointer */
1047 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1048 {
1049 /* Make sure write' to descriptors are complete before we tell hardware */
1050 wmb();
1051 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1052
1053 /* Synchronize I/O on since next processor may write to tail */
1054 mmiowb();
1055 }
1056
1057
1058 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1059 {
1060 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1061 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1062 le->ctrl = 0;
1063 return le;
1064 }
1065
1066 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1067 {
1068 unsigned size;
1069
1070 /* Space needed for frame data + headers rounded up */
1071 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1072
1073 /* Stopping point for hardware truncation */
1074 return (size - 8) / sizeof(u32);
1075 }
1076
1077 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1078 {
1079 struct rx_ring_info *re;
1080 unsigned size;
1081
1082 /* Space needed for frame data + headers rounded up */
1083 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1084
1085 sky2->rx_nfrags = size >> PAGE_SHIFT;
1086 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1087
1088 /* Compute residue after pages */
1089 size -= sky2->rx_nfrags << PAGE_SHIFT;
1090
1091 /* Optimize to handle small packets and headers */
1092 if (size < copybreak)
1093 size = copybreak;
1094 if (size < ETH_HLEN)
1095 size = ETH_HLEN;
1096
1097 return size;
1098 }
1099
1100 /* Build description to hardware for one receive segment */
1101 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1102 dma_addr_t map, unsigned len)
1103 {
1104 struct sky2_rx_le *le;
1105
1106 if (sizeof(dma_addr_t) > sizeof(u32)) {
1107 le = sky2_next_rx(sky2);
1108 le->addr = cpu_to_le32(upper_32_bits(map));
1109 le->opcode = OP_ADDR64 | HW_OWNER;
1110 }
1111
1112 le = sky2_next_rx(sky2);
1113 le->addr = cpu_to_le32(lower_32_bits(map));
1114 le->length = cpu_to_le16(len);
1115 le->opcode = op | HW_OWNER;
1116 }
1117
1118 /* Build description to hardware for one possibly fragmented skb */
1119 static void sky2_rx_submit(struct sky2_port *sky2,
1120 const struct rx_ring_info *re)
1121 {
1122 int i;
1123
1124 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1125
1126 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1127 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1128 }
1129
1130
1131 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1132 unsigned size)
1133 {
1134 struct sk_buff *skb = re->skb;
1135 int i;
1136
1137 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1138 if (pci_dma_mapping_error(pdev, re->data_addr))
1139 goto mapping_error;
1140
1141 dma_unmap_len_set(re, data_size, size);
1142
1143 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1144 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1145
1146 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1147 frag->page_offset,
1148 frag->size,
1149 PCI_DMA_FROMDEVICE);
1150
1151 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1152 goto map_page_error;
1153 }
1154 return 0;
1155
1156 map_page_error:
1157 while (--i >= 0) {
1158 pci_unmap_page(pdev, re->frag_addr[i],
1159 skb_shinfo(skb)->frags[i].size,
1160 PCI_DMA_FROMDEVICE);
1161 }
1162
1163 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1164 PCI_DMA_FROMDEVICE);
1165
1166 mapping_error:
1167 if (net_ratelimit())
1168 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1169 skb->dev->name);
1170 return -EIO;
1171 }
1172
1173 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1174 {
1175 struct sk_buff *skb = re->skb;
1176 int i;
1177
1178 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1179 PCI_DMA_FROMDEVICE);
1180
1181 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1182 pci_unmap_page(pdev, re->frag_addr[i],
1183 skb_shinfo(skb)->frags[i].size,
1184 PCI_DMA_FROMDEVICE);
1185 }
1186
1187 /* Tell chip where to start receive checksum.
1188 * Actually has two checksums, but set both same to avoid possible byte
1189 * order problems.
1190 */
1191 static void rx_set_checksum(struct sky2_port *sky2)
1192 {
1193 struct sky2_rx_le *le = sky2_next_rx(sky2);
1194
1195 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1196 le->ctrl = 0;
1197 le->opcode = OP_TCPSTART | HW_OWNER;
1198
1199 sky2_write32(sky2->hw,
1200 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1201 (sky2->netdev->features & NETIF_F_RXCSUM)
1202 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1203 }
1204
1205 /* Enable/disable receive hash calculation (RSS) */
1206 static void rx_set_rss(struct net_device *dev, u32 features)
1207 {
1208 struct sky2_port *sky2 = netdev_priv(dev);
1209 struct sky2_hw *hw = sky2->hw;
1210 int i, nkeys = 4;
1211
1212 /* Supports IPv6 and other modes */
1213 if (hw->flags & SKY2_HW_NEW_LE) {
1214 nkeys = 10;
1215 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1216 }
1217
1218 /* Program RSS initial values */
1219 if (features & NETIF_F_RXHASH) {
1220 u32 key[nkeys];
1221
1222 get_random_bytes(key, nkeys * sizeof(u32));
1223 for (i = 0; i < nkeys; i++)
1224 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1225 key[i]);
1226
1227 /* Need to turn on (undocumented) flag to make hashing work */
1228 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1229 RX_STFW_ENA);
1230
1231 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1232 BMU_ENA_RX_RSS_HASH);
1233 } else
1234 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1235 BMU_DIS_RX_RSS_HASH);
1236 }
1237
1238 /*
1239 * The RX Stop command will not work for Yukon-2 if the BMU does not
1240 * reach the end of packet and since we can't make sure that we have
1241 * incoming data, we must reset the BMU while it is not doing a DMA
1242 * transfer. Since it is possible that the RX path is still active,
1243 * the RX RAM buffer will be stopped first, so any possible incoming
1244 * data will not trigger a DMA. After the RAM buffer is stopped, the
1245 * BMU is polled until any DMA in progress is ended and only then it
1246 * will be reset.
1247 */
1248 static void sky2_rx_stop(struct sky2_port *sky2)
1249 {
1250 struct sky2_hw *hw = sky2->hw;
1251 unsigned rxq = rxqaddr[sky2->port];
1252 int i;
1253
1254 /* disable the RAM Buffer receive queue */
1255 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1256
1257 for (i = 0; i < 0xffff; i++)
1258 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1259 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1260 goto stopped;
1261
1262 netdev_warn(sky2->netdev, "receiver stop failed\n");
1263 stopped:
1264 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1265
1266 /* reset the Rx prefetch unit */
1267 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1268 mmiowb();
1269 }
1270
1271 /* Clean out receive buffer area, assumes receiver hardware stopped */
1272 static void sky2_rx_clean(struct sky2_port *sky2)
1273 {
1274 unsigned i;
1275
1276 memset(sky2->rx_le, 0, RX_LE_BYTES);
1277 for (i = 0; i < sky2->rx_pending; i++) {
1278 struct rx_ring_info *re = sky2->rx_ring + i;
1279
1280 if (re->skb) {
1281 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1282 kfree_skb(re->skb);
1283 re->skb = NULL;
1284 }
1285 }
1286 }
1287
1288 /* Basic MII support */
1289 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1290 {
1291 struct mii_ioctl_data *data = if_mii(ifr);
1292 struct sky2_port *sky2 = netdev_priv(dev);
1293 struct sky2_hw *hw = sky2->hw;
1294 int err = -EOPNOTSUPP;
1295
1296 if (!netif_running(dev))
1297 return -ENODEV; /* Phy still in reset */
1298
1299 switch (cmd) {
1300 case SIOCGMIIPHY:
1301 data->phy_id = PHY_ADDR_MARV;
1302
1303 /* fallthru */
1304 case SIOCGMIIREG: {
1305 u16 val = 0;
1306
1307 spin_lock_bh(&sky2->phy_lock);
1308 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1309 spin_unlock_bh(&sky2->phy_lock);
1310
1311 data->val_out = val;
1312 break;
1313 }
1314
1315 case SIOCSMIIREG:
1316 spin_lock_bh(&sky2->phy_lock);
1317 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1318 data->val_in);
1319 spin_unlock_bh(&sky2->phy_lock);
1320 break;
1321 }
1322 return err;
1323 }
1324
1325 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1326
1327 static void sky2_vlan_mode(struct net_device *dev, u32 features)
1328 {
1329 struct sky2_port *sky2 = netdev_priv(dev);
1330 struct sky2_hw *hw = sky2->hw;
1331 u16 port = sky2->port;
1332
1333 if (features & NETIF_F_HW_VLAN_RX)
1334 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1335 RX_VLAN_STRIP_ON);
1336 else
1337 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1338 RX_VLAN_STRIP_OFF);
1339
1340 if (features & NETIF_F_HW_VLAN_TX) {
1341 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1342 TX_VLAN_TAG_ON);
1343
1344 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1345 } else {
1346 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1347 TX_VLAN_TAG_OFF);
1348
1349 /* Can't do transmit offload of vlan without hw vlan */
1350 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1351 }
1352 }
1353
1354 /* Amount of required worst case padding in rx buffer */
1355 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1356 {
1357 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1358 }
1359
1360 /*
1361 * Allocate an skb for receiving. If the MTU is large enough
1362 * make the skb non-linear with a fragment list of pages.
1363 */
1364 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1365 {
1366 struct sk_buff *skb;
1367 int i;
1368
1369 skb = netdev_alloc_skb(sky2->netdev,
1370 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1371 if (!skb)
1372 goto nomem;
1373
1374 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1375 unsigned char *start;
1376 /*
1377 * Workaround for a bug in FIFO that cause hang
1378 * if the FIFO if the receive buffer is not 64 byte aligned.
1379 * The buffer returned from netdev_alloc_skb is
1380 * aligned except if slab debugging is enabled.
1381 */
1382 start = PTR_ALIGN(skb->data, 8);
1383 skb_reserve(skb, start - skb->data);
1384 } else
1385 skb_reserve(skb, NET_IP_ALIGN);
1386
1387 for (i = 0; i < sky2->rx_nfrags; i++) {
1388 struct page *page = alloc_page(GFP_ATOMIC);
1389
1390 if (!page)
1391 goto free_partial;
1392 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1393 }
1394
1395 return skb;
1396 free_partial:
1397 kfree_skb(skb);
1398 nomem:
1399 return NULL;
1400 }
1401
1402 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1403 {
1404 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1405 }
1406
1407 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1408 {
1409 struct sky2_hw *hw = sky2->hw;
1410 unsigned i;
1411
1412 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1413
1414 /* Fill Rx ring */
1415 for (i = 0; i < sky2->rx_pending; i++) {
1416 struct rx_ring_info *re = sky2->rx_ring + i;
1417
1418 re->skb = sky2_rx_alloc(sky2);
1419 if (!re->skb)
1420 return -ENOMEM;
1421
1422 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1423 dev_kfree_skb(re->skb);
1424 re->skb = NULL;
1425 return -ENOMEM;
1426 }
1427 }
1428 return 0;
1429 }
1430
1431 /*
1432 * Setup receiver buffer pool.
1433 * Normal case this ends up creating one list element for skb
1434 * in the receive ring. Worst case if using large MTU and each
1435 * allocation falls on a different 64 bit region, that results
1436 * in 6 list elements per ring entry.
1437 * One element is used for checksum enable/disable, and one
1438 * extra to avoid wrap.
1439 */
1440 static void sky2_rx_start(struct sky2_port *sky2)
1441 {
1442 struct sky2_hw *hw = sky2->hw;
1443 struct rx_ring_info *re;
1444 unsigned rxq = rxqaddr[sky2->port];
1445 unsigned i, thresh;
1446
1447 sky2->rx_put = sky2->rx_next = 0;
1448 sky2_qset(hw, rxq);
1449
1450 /* On PCI express lowering the watermark gives better performance */
1451 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1452 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1453
1454 /* These chips have no ram buffer?
1455 * MAC Rx RAM Read is controlled by hardware */
1456 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1457 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1458 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1459
1460 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1461
1462 if (!(hw->flags & SKY2_HW_NEW_LE))
1463 rx_set_checksum(sky2);
1464
1465 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1466 rx_set_rss(sky2->netdev, sky2->netdev->features);
1467
1468 /* submit Rx ring */
1469 for (i = 0; i < sky2->rx_pending; i++) {
1470 re = sky2->rx_ring + i;
1471 sky2_rx_submit(sky2, re);
1472 }
1473
1474 /*
1475 * The receiver hangs if it receives frames larger than the
1476 * packet buffer. As a workaround, truncate oversize frames, but
1477 * the register is limited to 9 bits, so if you do frames > 2052
1478 * you better get the MTU right!
1479 */
1480 thresh = sky2_get_rx_threshold(sky2);
1481 if (thresh > 0x1ff)
1482 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1483 else {
1484 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1485 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1486 }
1487
1488 /* Tell chip about available buffers */
1489 sky2_rx_update(sky2, rxq);
1490
1491 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1492 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1493 /*
1494 * Disable flushing of non ASF packets;
1495 * must be done after initializing the BMUs;
1496 * drivers without ASF support should do this too, otherwise
1497 * it may happen that they cannot run on ASF devices;
1498 * remember that the MAC FIFO isn't reset during initialization.
1499 */
1500 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1501 }
1502
1503 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1504 /* Enable RX Home Address & Routing Header checksum fix */
1505 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1506 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1507
1508 /* Enable TX Home Address & Routing Header checksum fix */
1509 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1510 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1511 }
1512 }
1513
1514 static int sky2_alloc_buffers(struct sky2_port *sky2)
1515 {
1516 struct sky2_hw *hw = sky2->hw;
1517
1518 /* must be power of 2 */
1519 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1520 sky2->tx_ring_size *
1521 sizeof(struct sky2_tx_le),
1522 &sky2->tx_le_map);
1523 if (!sky2->tx_le)
1524 goto nomem;
1525
1526 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1527 GFP_KERNEL);
1528 if (!sky2->tx_ring)
1529 goto nomem;
1530
1531 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1532 &sky2->rx_le_map);
1533 if (!sky2->rx_le)
1534 goto nomem;
1535 memset(sky2->rx_le, 0, RX_LE_BYTES);
1536
1537 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1538 GFP_KERNEL);
1539 if (!sky2->rx_ring)
1540 goto nomem;
1541
1542 return sky2_alloc_rx_skbs(sky2);
1543 nomem:
1544 return -ENOMEM;
1545 }
1546
1547 static void sky2_free_buffers(struct sky2_port *sky2)
1548 {
1549 struct sky2_hw *hw = sky2->hw;
1550
1551 sky2_rx_clean(sky2);
1552
1553 if (sky2->rx_le) {
1554 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1555 sky2->rx_le, sky2->rx_le_map);
1556 sky2->rx_le = NULL;
1557 }
1558 if (sky2->tx_le) {
1559 pci_free_consistent(hw->pdev,
1560 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1561 sky2->tx_le, sky2->tx_le_map);
1562 sky2->tx_le = NULL;
1563 }
1564 kfree(sky2->tx_ring);
1565 kfree(sky2->rx_ring);
1566
1567 sky2->tx_ring = NULL;
1568 sky2->rx_ring = NULL;
1569 }
1570
1571 static void sky2_hw_up(struct sky2_port *sky2)
1572 {
1573 struct sky2_hw *hw = sky2->hw;
1574 unsigned port = sky2->port;
1575 u32 ramsize;
1576 int cap;
1577 struct net_device *otherdev = hw->dev[sky2->port^1];
1578
1579 tx_init(sky2);
1580
1581 /*
1582 * On dual port PCI-X card, there is an problem where status
1583 * can be received out of order due to split transactions
1584 */
1585 if (otherdev && netif_running(otherdev) &&
1586 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1587 u16 cmd;
1588
1589 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1590 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1591 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1592 }
1593
1594 sky2_mac_init(hw, port);
1595
1596 /* Register is number of 4K blocks on internal RAM buffer. */
1597 ramsize = sky2_read8(hw, B2_E_0) * 4;
1598 if (ramsize > 0) {
1599 u32 rxspace;
1600
1601 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1602 if (ramsize < 16)
1603 rxspace = ramsize / 2;
1604 else
1605 rxspace = 8 + (2*(ramsize - 16))/3;
1606
1607 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1608 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1609
1610 /* Make sure SyncQ is disabled */
1611 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1612 RB_RST_SET);
1613 }
1614
1615 sky2_qset(hw, txqaddr[port]);
1616
1617 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1618 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1619 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1620
1621 /* Set almost empty threshold */
1622 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1623 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1624 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1625
1626 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1627 sky2->tx_ring_size - 1);
1628
1629 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1630 netdev_update_features(sky2->netdev);
1631
1632 sky2_rx_start(sky2);
1633 }
1634
1635 /* Bring up network interface. */
1636 static int sky2_up(struct net_device *dev)
1637 {
1638 struct sky2_port *sky2 = netdev_priv(dev);
1639 struct sky2_hw *hw = sky2->hw;
1640 unsigned port = sky2->port;
1641 u32 imask;
1642 int err;
1643
1644 netif_carrier_off(dev);
1645
1646 err = sky2_alloc_buffers(sky2);
1647 if (err)
1648 goto err_out;
1649
1650 sky2_hw_up(sky2);
1651
1652 /* Enable interrupts from phy/mac for port */
1653 imask = sky2_read32(hw, B0_IMSK);
1654 imask |= portirq_msk[port];
1655 sky2_write32(hw, B0_IMSK, imask);
1656 sky2_read32(hw, B0_IMSK);
1657
1658 netif_info(sky2, ifup, dev, "enabling interface\n");
1659
1660 return 0;
1661
1662 err_out:
1663 sky2_free_buffers(sky2);
1664 return err;
1665 }
1666
1667 /* Modular subtraction in ring */
1668 static inline int tx_inuse(const struct sky2_port *sky2)
1669 {
1670 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1671 }
1672
1673 /* Number of list elements available for next tx */
1674 static inline int tx_avail(const struct sky2_port *sky2)
1675 {
1676 return sky2->tx_pending - tx_inuse(sky2);
1677 }
1678
1679 /* Estimate of number of transmit list elements required */
1680 static unsigned tx_le_req(const struct sk_buff *skb)
1681 {
1682 unsigned count;
1683
1684 count = (skb_shinfo(skb)->nr_frags + 1)
1685 * (sizeof(dma_addr_t) / sizeof(u32));
1686
1687 if (skb_is_gso(skb))
1688 ++count;
1689 else if (sizeof(dma_addr_t) == sizeof(u32))
1690 ++count; /* possible vlan */
1691
1692 if (skb->ip_summed == CHECKSUM_PARTIAL)
1693 ++count;
1694
1695 return count;
1696 }
1697
1698 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1699 {
1700 if (re->flags & TX_MAP_SINGLE)
1701 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1702 dma_unmap_len(re, maplen),
1703 PCI_DMA_TODEVICE);
1704 else if (re->flags & TX_MAP_PAGE)
1705 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1706 dma_unmap_len(re, maplen),
1707 PCI_DMA_TODEVICE);
1708 re->flags = 0;
1709 }
1710
1711 /*
1712 * Put one packet in ring for transmit.
1713 * A single packet can generate multiple list elements, and
1714 * the number of ring elements will probably be less than the number
1715 * of list elements used.
1716 */
1717 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1718 struct net_device *dev)
1719 {
1720 struct sky2_port *sky2 = netdev_priv(dev);
1721 struct sky2_hw *hw = sky2->hw;
1722 struct sky2_tx_le *le = NULL;
1723 struct tx_ring_info *re;
1724 unsigned i, len;
1725 dma_addr_t mapping;
1726 u32 upper;
1727 u16 slot;
1728 u16 mss;
1729 u8 ctrl;
1730
1731 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1732 return NETDEV_TX_BUSY;
1733
1734 len = skb_headlen(skb);
1735 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1736
1737 if (pci_dma_mapping_error(hw->pdev, mapping))
1738 goto mapping_error;
1739
1740 slot = sky2->tx_prod;
1741 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1742 "tx queued, slot %u, len %d\n", slot, skb->len);
1743
1744 /* Send high bits if needed */
1745 upper = upper_32_bits(mapping);
1746 if (upper != sky2->tx_last_upper) {
1747 le = get_tx_le(sky2, &slot);
1748 le->addr = cpu_to_le32(upper);
1749 sky2->tx_last_upper = upper;
1750 le->opcode = OP_ADDR64 | HW_OWNER;
1751 }
1752
1753 /* Check for TCP Segmentation Offload */
1754 mss = skb_shinfo(skb)->gso_size;
1755 if (mss != 0) {
1756
1757 if (!(hw->flags & SKY2_HW_NEW_LE))
1758 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1759
1760 if (mss != sky2->tx_last_mss) {
1761 le = get_tx_le(sky2, &slot);
1762 le->addr = cpu_to_le32(mss);
1763
1764 if (hw->flags & SKY2_HW_NEW_LE)
1765 le->opcode = OP_MSS | HW_OWNER;
1766 else
1767 le->opcode = OP_LRGLEN | HW_OWNER;
1768 sky2->tx_last_mss = mss;
1769 }
1770 }
1771
1772 ctrl = 0;
1773
1774 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1775 if (vlan_tx_tag_present(skb)) {
1776 if (!le) {
1777 le = get_tx_le(sky2, &slot);
1778 le->addr = 0;
1779 le->opcode = OP_VLAN|HW_OWNER;
1780 } else
1781 le->opcode |= OP_VLAN;
1782 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1783 ctrl |= INS_VLAN;
1784 }
1785
1786 /* Handle TCP checksum offload */
1787 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1788 /* On Yukon EX (some versions) encoding change. */
1789 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1790 ctrl |= CALSUM; /* auto checksum */
1791 else {
1792 const unsigned offset = skb_transport_offset(skb);
1793 u32 tcpsum;
1794
1795 tcpsum = offset << 16; /* sum start */
1796 tcpsum |= offset + skb->csum_offset; /* sum write */
1797
1798 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1799 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1800 ctrl |= UDPTCP;
1801
1802 if (tcpsum != sky2->tx_tcpsum) {
1803 sky2->tx_tcpsum = tcpsum;
1804
1805 le = get_tx_le(sky2, &slot);
1806 le->addr = cpu_to_le32(tcpsum);
1807 le->length = 0; /* initial checksum value */
1808 le->ctrl = 1; /* one packet */
1809 le->opcode = OP_TCPLISW | HW_OWNER;
1810 }
1811 }
1812 }
1813
1814 re = sky2->tx_ring + slot;
1815 re->flags = TX_MAP_SINGLE;
1816 dma_unmap_addr_set(re, mapaddr, mapping);
1817 dma_unmap_len_set(re, maplen, len);
1818
1819 le = get_tx_le(sky2, &slot);
1820 le->addr = cpu_to_le32(lower_32_bits(mapping));
1821 le->length = cpu_to_le16(len);
1822 le->ctrl = ctrl;
1823 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1824
1825
1826 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1827 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1828
1829 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1830 frag->size, PCI_DMA_TODEVICE);
1831
1832 if (pci_dma_mapping_error(hw->pdev, mapping))
1833 goto mapping_unwind;
1834
1835 upper = upper_32_bits(mapping);
1836 if (upper != sky2->tx_last_upper) {
1837 le = get_tx_le(sky2, &slot);
1838 le->addr = cpu_to_le32(upper);
1839 sky2->tx_last_upper = upper;
1840 le->opcode = OP_ADDR64 | HW_OWNER;
1841 }
1842
1843 re = sky2->tx_ring + slot;
1844 re->flags = TX_MAP_PAGE;
1845 dma_unmap_addr_set(re, mapaddr, mapping);
1846 dma_unmap_len_set(re, maplen, frag->size);
1847
1848 le = get_tx_le(sky2, &slot);
1849 le->addr = cpu_to_le32(lower_32_bits(mapping));
1850 le->length = cpu_to_le16(frag->size);
1851 le->ctrl = ctrl;
1852 le->opcode = OP_BUFFER | HW_OWNER;
1853 }
1854
1855 re->skb = skb;
1856 le->ctrl |= EOP;
1857
1858 sky2->tx_prod = slot;
1859
1860 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1861 netif_stop_queue(dev);
1862
1863 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1864
1865 return NETDEV_TX_OK;
1866
1867 mapping_unwind:
1868 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1869 re = sky2->tx_ring + i;
1870
1871 sky2_tx_unmap(hw->pdev, re);
1872 }
1873
1874 mapping_error:
1875 if (net_ratelimit())
1876 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1877 dev_kfree_skb(skb);
1878 return NETDEV_TX_OK;
1879 }
1880
1881 /*
1882 * Free ring elements from starting at tx_cons until "done"
1883 *
1884 * NB:
1885 * 1. The hardware will tell us about partial completion of multi-part
1886 * buffers so make sure not to free skb to early.
1887 * 2. This may run in parallel start_xmit because the it only
1888 * looks at the tail of the queue of FIFO (tx_cons), not
1889 * the head (tx_prod)
1890 */
1891 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1892 {
1893 struct net_device *dev = sky2->netdev;
1894 unsigned idx;
1895
1896 BUG_ON(done >= sky2->tx_ring_size);
1897
1898 for (idx = sky2->tx_cons; idx != done;
1899 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1900 struct tx_ring_info *re = sky2->tx_ring + idx;
1901 struct sk_buff *skb = re->skb;
1902
1903 sky2_tx_unmap(sky2->hw->pdev, re);
1904
1905 if (skb) {
1906 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1907 "tx done %u\n", idx);
1908
1909 u64_stats_update_begin(&sky2->tx_stats.syncp);
1910 ++sky2->tx_stats.packets;
1911 sky2->tx_stats.bytes += skb->len;
1912 u64_stats_update_end(&sky2->tx_stats.syncp);
1913
1914 re->skb = NULL;
1915 dev_kfree_skb_any(skb);
1916
1917 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1918 }
1919 }
1920
1921 sky2->tx_cons = idx;
1922 smp_mb();
1923 }
1924
1925 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1926 {
1927 /* Disable Force Sync bit and Enable Alloc bit */
1928 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1929 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1930
1931 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1932 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1933 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1934
1935 /* Reset the PCI FIFO of the async Tx queue */
1936 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1937 BMU_RST_SET | BMU_FIFO_RST);
1938
1939 /* Reset the Tx prefetch units */
1940 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1941 PREF_UNIT_RST_SET);
1942
1943 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1944 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1945 }
1946
1947 static void sky2_hw_down(struct sky2_port *sky2)
1948 {
1949 struct sky2_hw *hw = sky2->hw;
1950 unsigned port = sky2->port;
1951 u16 ctrl;
1952
1953 /* Force flow control off */
1954 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1955
1956 /* Stop transmitter */
1957 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1958 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1959
1960 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1961 RB_RST_SET | RB_DIS_OP_MD);
1962
1963 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1964 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1965 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1966
1967 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1968
1969 /* Workaround shared GMAC reset */
1970 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1971 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1972 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1973
1974 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1975
1976 /* Force any delayed status interrrupt and NAPI */
1977 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1978 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1979 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1980 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1981
1982 sky2_rx_stop(sky2);
1983
1984 spin_lock_bh(&sky2->phy_lock);
1985 sky2_phy_power_down(hw, port);
1986 spin_unlock_bh(&sky2->phy_lock);
1987
1988 sky2_tx_reset(hw, port);
1989
1990 /* Free any pending frames stuck in HW queue */
1991 sky2_tx_complete(sky2, sky2->tx_prod);
1992 }
1993
1994 /* Network shutdown */
1995 static int sky2_down(struct net_device *dev)
1996 {
1997 struct sky2_port *sky2 = netdev_priv(dev);
1998 struct sky2_hw *hw = sky2->hw;
1999
2000 /* Never really got started! */
2001 if (!sky2->tx_le)
2002 return 0;
2003
2004 netif_info(sky2, ifdown, dev, "disabling interface\n");
2005
2006 /* Disable port IRQ */
2007 sky2_write32(hw, B0_IMSK,
2008 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2009 sky2_read32(hw, B0_IMSK);
2010
2011 synchronize_irq(hw->pdev->irq);
2012 napi_synchronize(&hw->napi);
2013
2014 sky2_hw_down(sky2);
2015
2016 sky2_free_buffers(sky2);
2017
2018 return 0;
2019 }
2020
2021 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2022 {
2023 if (hw->flags & SKY2_HW_FIBRE_PHY)
2024 return SPEED_1000;
2025
2026 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2027 if (aux & PHY_M_PS_SPEED_100)
2028 return SPEED_100;
2029 else
2030 return SPEED_10;
2031 }
2032
2033 switch (aux & PHY_M_PS_SPEED_MSK) {
2034 case PHY_M_PS_SPEED_1000:
2035 return SPEED_1000;
2036 case PHY_M_PS_SPEED_100:
2037 return SPEED_100;
2038 default:
2039 return SPEED_10;
2040 }
2041 }
2042
2043 static void sky2_link_up(struct sky2_port *sky2)
2044 {
2045 struct sky2_hw *hw = sky2->hw;
2046 unsigned port = sky2->port;
2047 static const char *fc_name[] = {
2048 [FC_NONE] = "none",
2049 [FC_TX] = "tx",
2050 [FC_RX] = "rx",
2051 [FC_BOTH] = "both",
2052 };
2053
2054 sky2_enable_rx_tx(sky2);
2055
2056 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2057
2058 netif_carrier_on(sky2->netdev);
2059
2060 mod_timer(&hw->watchdog_timer, jiffies + 1);
2061
2062 /* Turn on link LED */
2063 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2064 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2065
2066 netif_info(sky2, link, sky2->netdev,
2067 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2068 sky2->speed,
2069 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2070 fc_name[sky2->flow_status]);
2071 }
2072
2073 static void sky2_link_down(struct sky2_port *sky2)
2074 {
2075 struct sky2_hw *hw = sky2->hw;
2076 unsigned port = sky2->port;
2077 u16 reg;
2078
2079 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2080
2081 reg = gma_read16(hw, port, GM_GP_CTRL);
2082 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2083 gma_write16(hw, port, GM_GP_CTRL, reg);
2084
2085 netif_carrier_off(sky2->netdev);
2086
2087 /* Turn off link LED */
2088 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2089
2090 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2091
2092 sky2_phy_init(hw, port);
2093 }
2094
2095 static enum flow_control sky2_flow(int rx, int tx)
2096 {
2097 if (rx)
2098 return tx ? FC_BOTH : FC_RX;
2099 else
2100 return tx ? FC_TX : FC_NONE;
2101 }
2102
2103 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2104 {
2105 struct sky2_hw *hw = sky2->hw;
2106 unsigned port = sky2->port;
2107 u16 advert, lpa;
2108
2109 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2110 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2111 if (lpa & PHY_M_AN_RF) {
2112 netdev_err(sky2->netdev, "remote fault\n");
2113 return -1;
2114 }
2115
2116 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2117 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2118 return -1;
2119 }
2120
2121 sky2->speed = sky2_phy_speed(hw, aux);
2122 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2123
2124 /* Since the pause result bits seem to in different positions on
2125 * different chips. look at registers.
2126 */
2127 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2128 /* Shift for bits in fiber PHY */
2129 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2130 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2131
2132 if (advert & ADVERTISE_1000XPAUSE)
2133 advert |= ADVERTISE_PAUSE_CAP;
2134 if (advert & ADVERTISE_1000XPSE_ASYM)
2135 advert |= ADVERTISE_PAUSE_ASYM;
2136 if (lpa & LPA_1000XPAUSE)
2137 lpa |= LPA_PAUSE_CAP;
2138 if (lpa & LPA_1000XPAUSE_ASYM)
2139 lpa |= LPA_PAUSE_ASYM;
2140 }
2141
2142 sky2->flow_status = FC_NONE;
2143 if (advert & ADVERTISE_PAUSE_CAP) {
2144 if (lpa & LPA_PAUSE_CAP)
2145 sky2->flow_status = FC_BOTH;
2146 else if (advert & ADVERTISE_PAUSE_ASYM)
2147 sky2->flow_status = FC_RX;
2148 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2149 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2150 sky2->flow_status = FC_TX;
2151 }
2152
2153 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2154 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2155 sky2->flow_status = FC_NONE;
2156
2157 if (sky2->flow_status & FC_TX)
2158 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2159 else
2160 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2161
2162 return 0;
2163 }
2164
2165 /* Interrupt from PHY */
2166 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2167 {
2168 struct net_device *dev = hw->dev[port];
2169 struct sky2_port *sky2 = netdev_priv(dev);
2170 u16 istatus, phystat;
2171
2172 if (!netif_running(dev))
2173 return;
2174
2175 spin_lock(&sky2->phy_lock);
2176 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2177 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2178
2179 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2180 istatus, phystat);
2181
2182 if (istatus & PHY_M_IS_AN_COMPL) {
2183 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2184 !netif_carrier_ok(dev))
2185 sky2_link_up(sky2);
2186 goto out;
2187 }
2188
2189 if (istatus & PHY_M_IS_LSP_CHANGE)
2190 sky2->speed = sky2_phy_speed(hw, phystat);
2191
2192 if (istatus & PHY_M_IS_DUP_CHANGE)
2193 sky2->duplex =
2194 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2195
2196 if (istatus & PHY_M_IS_LST_CHANGE) {
2197 if (phystat & PHY_M_PS_LINK_UP)
2198 sky2_link_up(sky2);
2199 else
2200 sky2_link_down(sky2);
2201 }
2202 out:
2203 spin_unlock(&sky2->phy_lock);
2204 }
2205
2206 /* Special quick link interrupt (Yukon-2 Optima only) */
2207 static void sky2_qlink_intr(struct sky2_hw *hw)
2208 {
2209 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2210 u32 imask;
2211 u16 phy;
2212
2213 /* disable irq */
2214 imask = sky2_read32(hw, B0_IMSK);
2215 imask &= ~Y2_IS_PHY_QLNK;
2216 sky2_write32(hw, B0_IMSK, imask);
2217
2218 /* reset PHY Link Detect */
2219 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2220 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2221 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2222 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2223
2224 sky2_link_up(sky2);
2225 }
2226
2227 /* Transmit timeout is only called if we are running, carrier is up
2228 * and tx queue is full (stopped).
2229 */
2230 static void sky2_tx_timeout(struct net_device *dev)
2231 {
2232 struct sky2_port *sky2 = netdev_priv(dev);
2233 struct sky2_hw *hw = sky2->hw;
2234
2235 netif_err(sky2, timer, dev, "tx timeout\n");
2236
2237 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2238 sky2->tx_cons, sky2->tx_prod,
2239 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2240 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2241
2242 /* can't restart safely under softirq */
2243 schedule_work(&hw->restart_work);
2244 }
2245
2246 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2247 {
2248 struct sky2_port *sky2 = netdev_priv(dev);
2249 struct sky2_hw *hw = sky2->hw;
2250 unsigned port = sky2->port;
2251 int err;
2252 u16 ctl, mode;
2253 u32 imask;
2254
2255 /* MTU size outside the spec */
2256 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2257 return -EINVAL;
2258
2259 /* MTU > 1500 on yukon FE and FE+ not allowed */
2260 if (new_mtu > ETH_DATA_LEN &&
2261 (hw->chip_id == CHIP_ID_YUKON_FE ||
2262 hw->chip_id == CHIP_ID_YUKON_FE_P))
2263 return -EINVAL;
2264
2265 if (!netif_running(dev)) {
2266 dev->mtu = new_mtu;
2267 netdev_update_features(dev);
2268 return 0;
2269 }
2270
2271 imask = sky2_read32(hw, B0_IMSK);
2272 sky2_write32(hw, B0_IMSK, 0);
2273
2274 dev->trans_start = jiffies; /* prevent tx timeout */
2275 napi_disable(&hw->napi);
2276 netif_tx_disable(dev);
2277
2278 synchronize_irq(hw->pdev->irq);
2279
2280 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2281 sky2_set_tx_stfwd(hw, port);
2282
2283 ctl = gma_read16(hw, port, GM_GP_CTRL);
2284 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2285 sky2_rx_stop(sky2);
2286 sky2_rx_clean(sky2);
2287
2288 dev->mtu = new_mtu;
2289 netdev_update_features(dev);
2290
2291 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2292 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2293
2294 if (dev->mtu > ETH_DATA_LEN)
2295 mode |= GM_SMOD_JUMBO_ENA;
2296
2297 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2298
2299 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2300
2301 err = sky2_alloc_rx_skbs(sky2);
2302 if (!err)
2303 sky2_rx_start(sky2);
2304 else
2305 sky2_rx_clean(sky2);
2306 sky2_write32(hw, B0_IMSK, imask);
2307
2308 sky2_read32(hw, B0_Y2_SP_LISR);
2309 napi_enable(&hw->napi);
2310
2311 if (err)
2312 dev_close(dev);
2313 else {
2314 gma_write16(hw, port, GM_GP_CTRL, ctl);
2315
2316 netif_wake_queue(dev);
2317 }
2318
2319 return err;
2320 }
2321
2322 /* For small just reuse existing skb for next receive */
2323 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2324 const struct rx_ring_info *re,
2325 unsigned length)
2326 {
2327 struct sk_buff *skb;
2328
2329 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2330 if (likely(skb)) {
2331 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2332 length, PCI_DMA_FROMDEVICE);
2333 skb_copy_from_linear_data(re->skb, skb->data, length);
2334 skb->ip_summed = re->skb->ip_summed;
2335 skb->csum = re->skb->csum;
2336 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2337 length, PCI_DMA_FROMDEVICE);
2338 re->skb->ip_summed = CHECKSUM_NONE;
2339 skb_put(skb, length);
2340 }
2341 return skb;
2342 }
2343
2344 /* Adjust length of skb with fragments to match received data */
2345 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2346 unsigned int length)
2347 {
2348 int i, num_frags;
2349 unsigned int size;
2350
2351 /* put header into skb */
2352 size = min(length, hdr_space);
2353 skb->tail += size;
2354 skb->len += size;
2355 length -= size;
2356
2357 num_frags = skb_shinfo(skb)->nr_frags;
2358 for (i = 0; i < num_frags; i++) {
2359 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2360
2361 if (length == 0) {
2362 /* don't need this page */
2363 __free_page(frag->page);
2364 --skb_shinfo(skb)->nr_frags;
2365 } else {
2366 size = min(length, (unsigned) PAGE_SIZE);
2367
2368 frag->size = size;
2369 skb->data_len += size;
2370 skb->truesize += size;
2371 skb->len += size;
2372 length -= size;
2373 }
2374 }
2375 }
2376
2377 /* Normal packet - take skb from ring element and put in a new one */
2378 static struct sk_buff *receive_new(struct sky2_port *sky2,
2379 struct rx_ring_info *re,
2380 unsigned int length)
2381 {
2382 struct sk_buff *skb;
2383 struct rx_ring_info nre;
2384 unsigned hdr_space = sky2->rx_data_size;
2385
2386 nre.skb = sky2_rx_alloc(sky2);
2387 if (unlikely(!nre.skb))
2388 goto nobuf;
2389
2390 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2391 goto nomap;
2392
2393 skb = re->skb;
2394 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2395 prefetch(skb->data);
2396 *re = nre;
2397
2398 if (skb_shinfo(skb)->nr_frags)
2399 skb_put_frags(skb, hdr_space, length);
2400 else
2401 skb_put(skb, length);
2402 return skb;
2403
2404 nomap:
2405 dev_kfree_skb(nre.skb);
2406 nobuf:
2407 return NULL;
2408 }
2409
2410 /*
2411 * Receive one packet.
2412 * For larger packets, get new buffer.
2413 */
2414 static struct sk_buff *sky2_receive(struct net_device *dev,
2415 u16 length, u32 status)
2416 {
2417 struct sky2_port *sky2 = netdev_priv(dev);
2418 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2419 struct sk_buff *skb = NULL;
2420 u16 count = (status & GMR_FS_LEN) >> 16;
2421
2422 if (status & GMR_FS_VLAN)
2423 count -= VLAN_HLEN; /* Account for vlan tag */
2424
2425 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2426 "rx slot %u status 0x%x len %d\n",
2427 sky2->rx_next, status, length);
2428
2429 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2430 prefetch(sky2->rx_ring + sky2->rx_next);
2431
2432 /* This chip has hardware problems that generates bogus status.
2433 * So do only marginal checking and expect higher level protocols
2434 * to handle crap frames.
2435 */
2436 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2437 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2438 length != count)
2439 goto okay;
2440
2441 if (status & GMR_FS_ANY_ERR)
2442 goto error;
2443
2444 if (!(status & GMR_FS_RX_OK))
2445 goto resubmit;
2446
2447 /* if length reported by DMA does not match PHY, packet was truncated */
2448 if (length != count)
2449 goto error;
2450
2451 okay:
2452 if (length < copybreak)
2453 skb = receive_copy(sky2, re, length);
2454 else
2455 skb = receive_new(sky2, re, length);
2456
2457 dev->stats.rx_dropped += (skb == NULL);
2458
2459 resubmit:
2460 sky2_rx_submit(sky2, re);
2461
2462 return skb;
2463
2464 error:
2465 ++dev->stats.rx_errors;
2466
2467 if (net_ratelimit())
2468 netif_info(sky2, rx_err, dev,
2469 "rx error, status 0x%x length %d\n", status, length);
2470
2471 goto resubmit;
2472 }
2473
2474 /* Transmit complete */
2475 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2476 {
2477 struct sky2_port *sky2 = netdev_priv(dev);
2478
2479 if (netif_running(dev)) {
2480 sky2_tx_complete(sky2, last);
2481
2482 /* Wake unless it's detached, and called e.g. from sky2_down() */
2483 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2484 netif_wake_queue(dev);
2485 }
2486 }
2487
2488 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2489 u32 status, struct sk_buff *skb)
2490 {
2491 if (status & GMR_FS_VLAN)
2492 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
2493
2494 if (skb->ip_summed == CHECKSUM_NONE)
2495 netif_receive_skb(skb);
2496 else
2497 napi_gro_receive(&sky2->hw->napi, skb);
2498 }
2499
2500 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2501 unsigned packets, unsigned bytes)
2502 {
2503 struct net_device *dev = hw->dev[port];
2504 struct sky2_port *sky2 = netdev_priv(dev);
2505
2506 if (packets == 0)
2507 return;
2508
2509 u64_stats_update_begin(&sky2->rx_stats.syncp);
2510 sky2->rx_stats.packets += packets;
2511 sky2->rx_stats.bytes += bytes;
2512 u64_stats_update_end(&sky2->rx_stats.syncp);
2513
2514 dev->last_rx = jiffies;
2515 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2516 }
2517
2518 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2519 {
2520 /* If this happens then driver assuming wrong format for chip type */
2521 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2522
2523 /* Both checksum counters are programmed to start at
2524 * the same offset, so unless there is a problem they
2525 * should match. This failure is an early indication that
2526 * hardware receive checksumming won't work.
2527 */
2528 if (likely((u16)(status >> 16) == (u16)status)) {
2529 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2530 skb->ip_summed = CHECKSUM_COMPLETE;
2531 skb->csum = le16_to_cpu(status);
2532 } else {
2533 dev_notice(&sky2->hw->pdev->dev,
2534 "%s: receive checksum problem (status = %#x)\n",
2535 sky2->netdev->name, status);
2536
2537 /* Disable checksum offload
2538 * It will be reenabled on next ndo_set_features, but if it's
2539 * really broken, will get disabled again
2540 */
2541 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2542 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2543 BMU_DIS_RX_CHKSUM);
2544 }
2545 }
2546
2547 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2548 {
2549 struct sk_buff *skb;
2550
2551 skb = sky2->rx_ring[sky2->rx_next].skb;
2552 skb->rxhash = le32_to_cpu(status);
2553 }
2554
2555 /* Process status response ring */
2556 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2557 {
2558 int work_done = 0;
2559 unsigned int total_bytes[2] = { 0 };
2560 unsigned int total_packets[2] = { 0 };
2561
2562 rmb();
2563 do {
2564 struct sky2_port *sky2;
2565 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2566 unsigned port;
2567 struct net_device *dev;
2568 struct sk_buff *skb;
2569 u32 status;
2570 u16 length;
2571 u8 opcode = le->opcode;
2572
2573 if (!(opcode & HW_OWNER))
2574 break;
2575
2576 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2577
2578 port = le->css & CSS_LINK_BIT;
2579 dev = hw->dev[port];
2580 sky2 = netdev_priv(dev);
2581 length = le16_to_cpu(le->length);
2582 status = le32_to_cpu(le->status);
2583
2584 le->opcode = 0;
2585 switch (opcode & ~HW_OWNER) {
2586 case OP_RXSTAT:
2587 total_packets[port]++;
2588 total_bytes[port] += length;
2589
2590 skb = sky2_receive(dev, length, status);
2591 if (!skb)
2592 break;
2593
2594 /* This chip reports checksum status differently */
2595 if (hw->flags & SKY2_HW_NEW_LE) {
2596 if ((dev->features & NETIF_F_RXCSUM) &&
2597 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2598 (le->css & CSS_TCPUDPCSOK))
2599 skb->ip_summed = CHECKSUM_UNNECESSARY;
2600 else
2601 skb->ip_summed = CHECKSUM_NONE;
2602 }
2603
2604 skb->protocol = eth_type_trans(skb, dev);
2605
2606 sky2_skb_rx(sky2, status, skb);
2607
2608 /* Stop after net poll weight */
2609 if (++work_done >= to_do)
2610 goto exit_loop;
2611 break;
2612
2613 case OP_RXVLAN:
2614 sky2->rx_tag = length;
2615 break;
2616
2617 case OP_RXCHKSVLAN:
2618 sky2->rx_tag = length;
2619 /* fall through */
2620 case OP_RXCHKS:
2621 if (likely(dev->features & NETIF_F_RXCSUM))
2622 sky2_rx_checksum(sky2, status);
2623 break;
2624
2625 case OP_RSS_HASH:
2626 sky2_rx_hash(sky2, status);
2627 break;
2628
2629 case OP_TXINDEXLE:
2630 /* TX index reports status for both ports */
2631 sky2_tx_done(hw->dev[0], status & 0xfff);
2632 if (hw->dev[1])
2633 sky2_tx_done(hw->dev[1],
2634 ((status >> 24) & 0xff)
2635 | (u16)(length & 0xf) << 8);
2636 break;
2637
2638 default:
2639 if (net_ratelimit())
2640 pr_warning("unknown status opcode 0x%x\n", opcode);
2641 }
2642 } while (hw->st_idx != idx);
2643
2644 /* Fully processed status ring so clear irq */
2645 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2646
2647 exit_loop:
2648 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2649 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2650
2651 return work_done;
2652 }
2653
2654 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2655 {
2656 struct net_device *dev = hw->dev[port];
2657
2658 if (net_ratelimit())
2659 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2660
2661 if (status & Y2_IS_PAR_RD1) {
2662 if (net_ratelimit())
2663 netdev_err(dev, "ram data read parity error\n");
2664 /* Clear IRQ */
2665 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2666 }
2667
2668 if (status & Y2_IS_PAR_WR1) {
2669 if (net_ratelimit())
2670 netdev_err(dev, "ram data write parity error\n");
2671
2672 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2673 }
2674
2675 if (status & Y2_IS_PAR_MAC1) {
2676 if (net_ratelimit())
2677 netdev_err(dev, "MAC parity error\n");
2678 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2679 }
2680
2681 if (status & Y2_IS_PAR_RX1) {
2682 if (net_ratelimit())
2683 netdev_err(dev, "RX parity error\n");
2684 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2685 }
2686
2687 if (status & Y2_IS_TCP_TXA1) {
2688 if (net_ratelimit())
2689 netdev_err(dev, "TCP segmentation error\n");
2690 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2691 }
2692 }
2693
2694 static void sky2_hw_intr(struct sky2_hw *hw)
2695 {
2696 struct pci_dev *pdev = hw->pdev;
2697 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2698 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2699
2700 status &= hwmsk;
2701
2702 if (status & Y2_IS_TIST_OV)
2703 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2704
2705 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2706 u16 pci_err;
2707
2708 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2709 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2710 if (net_ratelimit())
2711 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2712 pci_err);
2713
2714 sky2_pci_write16(hw, PCI_STATUS,
2715 pci_err | PCI_STATUS_ERROR_BITS);
2716 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2717 }
2718
2719 if (status & Y2_IS_PCI_EXP) {
2720 /* PCI-Express uncorrectable Error occurred */
2721 u32 err;
2722
2723 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2724 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2725 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2726 0xfffffffful);
2727 if (net_ratelimit())
2728 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2729
2730 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2731 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2732 }
2733
2734 if (status & Y2_HWE_L1_MASK)
2735 sky2_hw_error(hw, 0, status);
2736 status >>= 8;
2737 if (status & Y2_HWE_L1_MASK)
2738 sky2_hw_error(hw, 1, status);
2739 }
2740
2741 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2742 {
2743 struct net_device *dev = hw->dev[port];
2744 struct sky2_port *sky2 = netdev_priv(dev);
2745 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2746
2747 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2748
2749 if (status & GM_IS_RX_CO_OV)
2750 gma_read16(hw, port, GM_RX_IRQ_SRC);
2751
2752 if (status & GM_IS_TX_CO_OV)
2753 gma_read16(hw, port, GM_TX_IRQ_SRC);
2754
2755 if (status & GM_IS_RX_FF_OR) {
2756 ++dev->stats.rx_fifo_errors;
2757 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2758 }
2759
2760 if (status & GM_IS_TX_FF_UR) {
2761 ++dev->stats.tx_fifo_errors;
2762 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2763 }
2764 }
2765
2766 /* This should never happen it is a bug. */
2767 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2768 {
2769 struct net_device *dev = hw->dev[port];
2770 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2771
2772 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2773 dev->name, (unsigned) q, (unsigned) idx,
2774 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2775
2776 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2777 }
2778
2779 static int sky2_rx_hung(struct net_device *dev)
2780 {
2781 struct sky2_port *sky2 = netdev_priv(dev);
2782 struct sky2_hw *hw = sky2->hw;
2783 unsigned port = sky2->port;
2784 unsigned rxq = rxqaddr[port];
2785 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2786 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2787 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2788 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2789
2790 /* If idle and MAC or PCI is stuck */
2791 if (sky2->check.last == dev->last_rx &&
2792 ((mac_rp == sky2->check.mac_rp &&
2793 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2794 /* Check if the PCI RX hang */
2795 (fifo_rp == sky2->check.fifo_rp &&
2796 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2797 netdev_printk(KERN_DEBUG, dev,
2798 "hung mac %d:%d fifo %d (%d:%d)\n",
2799 mac_lev, mac_rp, fifo_lev,
2800 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2801 return 1;
2802 } else {
2803 sky2->check.last = dev->last_rx;
2804 sky2->check.mac_rp = mac_rp;
2805 sky2->check.mac_lev = mac_lev;
2806 sky2->check.fifo_rp = fifo_rp;
2807 sky2->check.fifo_lev = fifo_lev;
2808 return 0;
2809 }
2810 }
2811
2812 static void sky2_watchdog(unsigned long arg)
2813 {
2814 struct sky2_hw *hw = (struct sky2_hw *) arg;
2815
2816 /* Check for lost IRQ once a second */
2817 if (sky2_read32(hw, B0_ISRC)) {
2818 napi_schedule(&hw->napi);
2819 } else {
2820 int i, active = 0;
2821
2822 for (i = 0; i < hw->ports; i++) {
2823 struct net_device *dev = hw->dev[i];
2824 if (!netif_running(dev))
2825 continue;
2826 ++active;
2827
2828 /* For chips with Rx FIFO, check if stuck */
2829 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2830 sky2_rx_hung(dev)) {
2831 netdev_info(dev, "receiver hang detected\n");
2832 schedule_work(&hw->restart_work);
2833 return;
2834 }
2835 }
2836
2837 if (active == 0)
2838 return;
2839 }
2840
2841 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2842 }
2843
2844 /* Hardware/software error handling */
2845 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2846 {
2847 if (net_ratelimit())
2848 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2849
2850 if (status & Y2_IS_HW_ERR)
2851 sky2_hw_intr(hw);
2852
2853 if (status & Y2_IS_IRQ_MAC1)
2854 sky2_mac_intr(hw, 0);
2855
2856 if (status & Y2_IS_IRQ_MAC2)
2857 sky2_mac_intr(hw, 1);
2858
2859 if (status & Y2_IS_CHK_RX1)
2860 sky2_le_error(hw, 0, Q_R1);
2861
2862 if (status & Y2_IS_CHK_RX2)
2863 sky2_le_error(hw, 1, Q_R2);
2864
2865 if (status & Y2_IS_CHK_TXA1)
2866 sky2_le_error(hw, 0, Q_XA1);
2867
2868 if (status & Y2_IS_CHK_TXA2)
2869 sky2_le_error(hw, 1, Q_XA2);
2870 }
2871
2872 static int sky2_poll(struct napi_struct *napi, int work_limit)
2873 {
2874 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2875 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2876 int work_done = 0;
2877 u16 idx;
2878
2879 if (unlikely(status & Y2_IS_ERROR))
2880 sky2_err_intr(hw, status);
2881
2882 if (status & Y2_IS_IRQ_PHY1)
2883 sky2_phy_intr(hw, 0);
2884
2885 if (status & Y2_IS_IRQ_PHY2)
2886 sky2_phy_intr(hw, 1);
2887
2888 if (status & Y2_IS_PHY_QLNK)
2889 sky2_qlink_intr(hw);
2890
2891 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2892 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2893
2894 if (work_done >= work_limit)
2895 goto done;
2896 }
2897
2898 napi_complete(napi);
2899 sky2_read32(hw, B0_Y2_SP_LISR);
2900 done:
2901
2902 return work_done;
2903 }
2904
2905 static irqreturn_t sky2_intr(int irq, void *dev_id)
2906 {
2907 struct sky2_hw *hw = dev_id;
2908 u32 status;
2909
2910 /* Reading this mask interrupts as side effect */
2911 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2912 if (status == 0 || status == ~0)
2913 return IRQ_NONE;
2914
2915 prefetch(&hw->st_le[hw->st_idx]);
2916
2917 napi_schedule(&hw->napi);
2918
2919 return IRQ_HANDLED;
2920 }
2921
2922 #ifdef CONFIG_NET_POLL_CONTROLLER
2923 static void sky2_netpoll(struct net_device *dev)
2924 {
2925 struct sky2_port *sky2 = netdev_priv(dev);
2926
2927 napi_schedule(&sky2->hw->napi);
2928 }
2929 #endif
2930
2931 /* Chip internal frequency for clock calculations */
2932 static u32 sky2_mhz(const struct sky2_hw *hw)
2933 {
2934 switch (hw->chip_id) {
2935 case CHIP_ID_YUKON_EC:
2936 case CHIP_ID_YUKON_EC_U:
2937 case CHIP_ID_YUKON_EX:
2938 case CHIP_ID_YUKON_SUPR:
2939 case CHIP_ID_YUKON_UL_2:
2940 case CHIP_ID_YUKON_OPT:
2941 return 125;
2942
2943 case CHIP_ID_YUKON_FE:
2944 return 100;
2945
2946 case CHIP_ID_YUKON_FE_P:
2947 return 50;
2948
2949 case CHIP_ID_YUKON_XL:
2950 return 156;
2951
2952 default:
2953 BUG();
2954 }
2955 }
2956
2957 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2958 {
2959 return sky2_mhz(hw) * us;
2960 }
2961
2962 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2963 {
2964 return clk / sky2_mhz(hw);
2965 }
2966
2967
2968 static int __devinit sky2_init(struct sky2_hw *hw)
2969 {
2970 u8 t8;
2971
2972 /* Enable all clocks and check for bad PCI access */
2973 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2974
2975 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2976
2977 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2978 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2979
2980 switch (hw->chip_id) {
2981 case CHIP_ID_YUKON_XL:
2982 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2983 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
2984 hw->flags |= SKY2_HW_RSS_BROKEN;
2985 break;
2986
2987 case CHIP_ID_YUKON_EC_U:
2988 hw->flags = SKY2_HW_GIGABIT
2989 | SKY2_HW_NEWER_PHY
2990 | SKY2_HW_ADV_POWER_CTL;
2991 break;
2992
2993 case CHIP_ID_YUKON_EX:
2994 hw->flags = SKY2_HW_GIGABIT
2995 | SKY2_HW_NEWER_PHY
2996 | SKY2_HW_NEW_LE
2997 | SKY2_HW_ADV_POWER_CTL;
2998
2999 /* New transmit checksum */
3000 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3001 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3002 break;
3003
3004 case CHIP_ID_YUKON_EC:
3005 /* This rev is really old, and requires untested workarounds */
3006 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3007 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3008 return -EOPNOTSUPP;
3009 }
3010 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3011 break;
3012
3013 case CHIP_ID_YUKON_FE:
3014 hw->flags = SKY2_HW_RSS_BROKEN;
3015 break;
3016
3017 case CHIP_ID_YUKON_FE_P:
3018 hw->flags = SKY2_HW_NEWER_PHY
3019 | SKY2_HW_NEW_LE
3020 | SKY2_HW_AUTO_TX_SUM
3021 | SKY2_HW_ADV_POWER_CTL;
3022
3023 /* The workaround for status conflicts VLAN tag detection. */
3024 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3025 hw->flags |= SKY2_HW_VLAN_BROKEN;
3026 break;
3027
3028 case CHIP_ID_YUKON_SUPR:
3029 hw->flags = SKY2_HW_GIGABIT
3030 | SKY2_HW_NEWER_PHY
3031 | SKY2_HW_NEW_LE
3032 | SKY2_HW_AUTO_TX_SUM
3033 | SKY2_HW_ADV_POWER_CTL;
3034 break;
3035
3036 case CHIP_ID_YUKON_UL_2:
3037 hw->flags = SKY2_HW_GIGABIT
3038 | SKY2_HW_ADV_POWER_CTL;
3039 break;
3040
3041 case CHIP_ID_YUKON_OPT:
3042 hw->flags = SKY2_HW_GIGABIT
3043 | SKY2_HW_NEW_LE
3044 | SKY2_HW_ADV_POWER_CTL;
3045 break;
3046
3047 default:
3048 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3049 hw->chip_id);
3050 return -EOPNOTSUPP;
3051 }
3052
3053 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3054 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3055 hw->flags |= SKY2_HW_FIBRE_PHY;
3056
3057 hw->ports = 1;
3058 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3059 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3060 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3061 ++hw->ports;
3062 }
3063
3064 if (sky2_read8(hw, B2_E_0))
3065 hw->flags |= SKY2_HW_RAM_BUFFER;
3066
3067 return 0;
3068 }
3069
3070 static void sky2_reset(struct sky2_hw *hw)
3071 {
3072 struct pci_dev *pdev = hw->pdev;
3073 u16 status;
3074 int i, cap;
3075 u32 hwe_mask = Y2_HWE_ALL_MASK;
3076
3077 /* disable ASF */
3078 if (hw->chip_id == CHIP_ID_YUKON_EX
3079 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3080 sky2_write32(hw, CPU_WDOG, 0);
3081 status = sky2_read16(hw, HCU_CCSR);
3082 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3083 HCU_CCSR_UC_STATE_MSK);
3084 /*
3085 * CPU clock divider shouldn't be used because
3086 * - ASF firmware may malfunction
3087 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3088 */
3089 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3090 sky2_write16(hw, HCU_CCSR, status);
3091 sky2_write32(hw, CPU_WDOG, 0);
3092 } else
3093 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3094 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3095
3096 /* do a SW reset */
3097 sky2_write8(hw, B0_CTST, CS_RST_SET);
3098 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3099
3100 /* allow writes to PCI config */
3101 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3102
3103 /* clear PCI errors, if any */
3104 status = sky2_pci_read16(hw, PCI_STATUS);
3105 status |= PCI_STATUS_ERROR_BITS;
3106 sky2_pci_write16(hw, PCI_STATUS, status);
3107
3108 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3109
3110 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3111 if (cap) {
3112 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3113 0xfffffffful);
3114
3115 /* If error bit is stuck on ignore it */
3116 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3117 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3118 else
3119 hwe_mask |= Y2_IS_PCI_EXP;
3120 }
3121
3122 sky2_power_on(hw);
3123 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3124
3125 for (i = 0; i < hw->ports; i++) {
3126 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3127 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3128
3129 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3130 hw->chip_id == CHIP_ID_YUKON_SUPR)
3131 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3132 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3133 | GMC_BYP_RETR_ON);
3134
3135 }
3136
3137 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3138 /* enable MACSec clock gating */
3139 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3140 }
3141
3142 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3143 u16 reg;
3144 u32 msk;
3145
3146 if (hw->chip_rev == 0) {
3147 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3148 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3149
3150 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3151 reg = 10;
3152 } else {
3153 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3154 reg = 3;
3155 }
3156
3157 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3158
3159 /* reset PHY Link Detect */
3160 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3161 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3162 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3163 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3164
3165
3166 /* enable PHY Quick Link */
3167 msk = sky2_read32(hw, B0_IMSK);
3168 msk |= Y2_IS_PHY_QLNK;
3169 sky2_write32(hw, B0_IMSK, msk);
3170
3171 /* check if PSMv2 was running before */
3172 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3173 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3174 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3175 /* restore the PCIe Link Control register */
3176 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3177 }
3178 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3179
3180 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3181 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3182 }
3183
3184 /* Clear I2C IRQ noise */
3185 sky2_write32(hw, B2_I2C_IRQ, 1);
3186
3187 /* turn off hardware timer (unused) */
3188 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3189 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3190
3191 /* Turn off descriptor polling */
3192 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3193
3194 /* Turn off receive timestamp */
3195 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3196 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3197
3198 /* enable the Tx Arbiters */
3199 for (i = 0; i < hw->ports; i++)
3200 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3201
3202 /* Initialize ram interface */
3203 for (i = 0; i < hw->ports; i++) {
3204 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3205
3206 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3207 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3208 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3209 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3210 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3211 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3212 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3213 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3214 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3215 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3216 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3217 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3218 }
3219
3220 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3221
3222 for (i = 0; i < hw->ports; i++)
3223 sky2_gmac_reset(hw, i);
3224
3225 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3226 hw->st_idx = 0;
3227
3228 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3229 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3230
3231 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3232 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3233
3234 /* Set the list last index */
3235 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3236
3237 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3238 sky2_write8(hw, STAT_FIFO_WM, 16);
3239
3240 /* set Status-FIFO ISR watermark */
3241 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3242 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3243 else
3244 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3245
3246 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3247 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3248 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3249
3250 /* enable status unit */
3251 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3252
3253 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3254 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3255 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3256 }
3257
3258 /* Take device down (offline).
3259 * Equivalent to doing dev_stop() but this does not
3260 * inform upper layers of the transition.
3261 */
3262 static void sky2_detach(struct net_device *dev)
3263 {
3264 if (netif_running(dev)) {
3265 netif_tx_lock(dev);
3266 netif_device_detach(dev); /* stop txq */
3267 netif_tx_unlock(dev);
3268 sky2_down(dev);
3269 }
3270 }
3271
3272 /* Bring device back after doing sky2_detach */
3273 static int sky2_reattach(struct net_device *dev)
3274 {
3275 int err = 0;
3276
3277 if (netif_running(dev)) {
3278 err = sky2_up(dev);
3279 if (err) {
3280 netdev_info(dev, "could not restart %d\n", err);
3281 dev_close(dev);
3282 } else {
3283 netif_device_attach(dev);
3284 sky2_set_multicast(dev);
3285 }
3286 }
3287
3288 return err;
3289 }
3290
3291 static void sky2_all_down(struct sky2_hw *hw)
3292 {
3293 int i;
3294
3295 sky2_read32(hw, B0_IMSK);
3296 sky2_write32(hw, B0_IMSK, 0);
3297 synchronize_irq(hw->pdev->irq);
3298 napi_disable(&hw->napi);
3299
3300 for (i = 0; i < hw->ports; i++) {
3301 struct net_device *dev = hw->dev[i];
3302 struct sky2_port *sky2 = netdev_priv(dev);
3303
3304 if (!netif_running(dev))
3305 continue;
3306
3307 netif_carrier_off(dev);
3308 netif_tx_disable(dev);
3309 sky2_hw_down(sky2);
3310 }
3311 }
3312
3313 static void sky2_all_up(struct sky2_hw *hw)
3314 {
3315 u32 imask = Y2_IS_BASE;
3316 int i;
3317
3318 for (i = 0; i < hw->ports; i++) {
3319 struct net_device *dev = hw->dev[i];
3320 struct sky2_port *sky2 = netdev_priv(dev);
3321
3322 if (!netif_running(dev))
3323 continue;
3324
3325 sky2_hw_up(sky2);
3326 sky2_set_multicast(dev);
3327 imask |= portirq_msk[i];
3328 netif_wake_queue(dev);
3329 }
3330
3331 sky2_write32(hw, B0_IMSK, imask);
3332 sky2_read32(hw, B0_IMSK);
3333
3334 sky2_read32(hw, B0_Y2_SP_LISR);
3335 napi_enable(&hw->napi);
3336 }
3337
3338 static void sky2_restart(struct work_struct *work)
3339 {
3340 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3341
3342 rtnl_lock();
3343
3344 sky2_all_down(hw);
3345 sky2_reset(hw);
3346 sky2_all_up(hw);
3347
3348 rtnl_unlock();
3349 }
3350
3351 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3352 {
3353 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3354 }
3355
3356 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3357 {
3358 const struct sky2_port *sky2 = netdev_priv(dev);
3359
3360 wol->supported = sky2_wol_supported(sky2->hw);
3361 wol->wolopts = sky2->wol;
3362 }
3363
3364 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3365 {
3366 struct sky2_port *sky2 = netdev_priv(dev);
3367 struct sky2_hw *hw = sky2->hw;
3368 bool enable_wakeup = false;
3369 int i;
3370
3371 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3372 !device_can_wakeup(&hw->pdev->dev))
3373 return -EOPNOTSUPP;
3374
3375 sky2->wol = wol->wolopts;
3376
3377 for (i = 0; i < hw->ports; i++) {
3378 struct net_device *dev = hw->dev[i];
3379 struct sky2_port *sky2 = netdev_priv(dev);
3380
3381 if (sky2->wol)
3382 enable_wakeup = true;
3383 }
3384 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3385
3386 return 0;
3387 }
3388
3389 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3390 {
3391 if (sky2_is_copper(hw)) {
3392 u32 modes = SUPPORTED_10baseT_Half
3393 | SUPPORTED_10baseT_Full
3394 | SUPPORTED_100baseT_Half
3395 | SUPPORTED_100baseT_Full;
3396
3397 if (hw->flags & SKY2_HW_GIGABIT)
3398 modes |= SUPPORTED_1000baseT_Half
3399 | SUPPORTED_1000baseT_Full;
3400 return modes;
3401 } else
3402 return SUPPORTED_1000baseT_Half
3403 | SUPPORTED_1000baseT_Full;
3404 }
3405
3406 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3407 {
3408 struct sky2_port *sky2 = netdev_priv(dev);
3409 struct sky2_hw *hw = sky2->hw;
3410
3411 ecmd->transceiver = XCVR_INTERNAL;
3412 ecmd->supported = sky2_supported_modes(hw);
3413 ecmd->phy_address = PHY_ADDR_MARV;
3414 if (sky2_is_copper(hw)) {
3415 ecmd->port = PORT_TP;
3416 ethtool_cmd_speed_set(ecmd, sky2->speed);
3417 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3418 } else {
3419 ethtool_cmd_speed_set(ecmd, SPEED_1000);
3420 ecmd->port = PORT_FIBRE;
3421 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3422 }
3423
3424 ecmd->advertising = sky2->advertising;
3425 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3426 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3427 ecmd->duplex = sky2->duplex;
3428 return 0;
3429 }
3430
3431 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3432 {
3433 struct sky2_port *sky2 = netdev_priv(dev);
3434 const struct sky2_hw *hw = sky2->hw;
3435 u32 supported = sky2_supported_modes(hw);
3436
3437 if (ecmd->autoneg == AUTONEG_ENABLE) {
3438 if (ecmd->advertising & ~supported)
3439 return -EINVAL;
3440
3441 if (sky2_is_copper(hw))
3442 sky2->advertising = ecmd->advertising |
3443 ADVERTISED_TP |
3444 ADVERTISED_Autoneg;
3445 else
3446 sky2->advertising = ecmd->advertising |
3447 ADVERTISED_FIBRE |
3448 ADVERTISED_Autoneg;
3449
3450 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3451 sky2->duplex = -1;
3452 sky2->speed = -1;
3453 } else {
3454 u32 setting;
3455 u32 speed = ethtool_cmd_speed(ecmd);
3456
3457 switch (speed) {
3458 case SPEED_1000:
3459 if (ecmd->duplex == DUPLEX_FULL)
3460 setting = SUPPORTED_1000baseT_Full;
3461 else if (ecmd->duplex == DUPLEX_HALF)
3462 setting = SUPPORTED_1000baseT_Half;
3463 else
3464 return -EINVAL;
3465 break;
3466 case SPEED_100:
3467 if (ecmd->duplex == DUPLEX_FULL)
3468 setting = SUPPORTED_100baseT_Full;
3469 else if (ecmd->duplex == DUPLEX_HALF)
3470 setting = SUPPORTED_100baseT_Half;
3471 else
3472 return -EINVAL;
3473 break;
3474
3475 case SPEED_10:
3476 if (ecmd->duplex == DUPLEX_FULL)
3477 setting = SUPPORTED_10baseT_Full;
3478 else if (ecmd->duplex == DUPLEX_HALF)
3479 setting = SUPPORTED_10baseT_Half;
3480 else
3481 return -EINVAL;
3482 break;
3483 default:
3484 return -EINVAL;
3485 }
3486
3487 if ((setting & supported) == 0)
3488 return -EINVAL;
3489
3490 sky2->speed = speed;
3491 sky2->duplex = ecmd->duplex;
3492 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3493 }
3494
3495 if (netif_running(dev)) {
3496 sky2_phy_reinit(sky2);
3497 sky2_set_multicast(dev);
3498 }
3499
3500 return 0;
3501 }
3502
3503 static void sky2_get_drvinfo(struct net_device *dev,
3504 struct ethtool_drvinfo *info)
3505 {
3506 struct sky2_port *sky2 = netdev_priv(dev);
3507
3508 strcpy(info->driver, DRV_NAME);
3509 strcpy(info->version, DRV_VERSION);
3510 strcpy(info->fw_version, "N/A");
3511 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3512 }
3513
3514 static const struct sky2_stat {
3515 char name[ETH_GSTRING_LEN];
3516 u16 offset;
3517 } sky2_stats[] = {
3518 { "tx_bytes", GM_TXO_OK_HI },
3519 { "rx_bytes", GM_RXO_OK_HI },
3520 { "tx_broadcast", GM_TXF_BC_OK },
3521 { "rx_broadcast", GM_RXF_BC_OK },
3522 { "tx_multicast", GM_TXF_MC_OK },
3523 { "rx_multicast", GM_RXF_MC_OK },
3524 { "tx_unicast", GM_TXF_UC_OK },
3525 { "rx_unicast", GM_RXF_UC_OK },
3526 { "tx_mac_pause", GM_TXF_MPAUSE },
3527 { "rx_mac_pause", GM_RXF_MPAUSE },
3528 { "collisions", GM_TXF_COL },
3529 { "late_collision",GM_TXF_LAT_COL },
3530 { "aborted", GM_TXF_ABO_COL },
3531 { "single_collisions", GM_TXF_SNG_COL },
3532 { "multi_collisions", GM_TXF_MUL_COL },
3533
3534 { "rx_short", GM_RXF_SHT },
3535 { "rx_runt", GM_RXE_FRAG },
3536 { "rx_64_byte_packets", GM_RXF_64B },
3537 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3538 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3539 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3540 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3541 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3542 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3543 { "rx_too_long", GM_RXF_LNG_ERR },
3544 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3545 { "rx_jabber", GM_RXF_JAB_PKT },
3546 { "rx_fcs_error", GM_RXF_FCS_ERR },
3547
3548 { "tx_64_byte_packets", GM_TXF_64B },
3549 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3550 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3551 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3552 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3553 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3554 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3555 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3556 };
3557
3558 static u32 sky2_get_msglevel(struct net_device *netdev)
3559 {
3560 struct sky2_port *sky2 = netdev_priv(netdev);
3561 return sky2->msg_enable;
3562 }
3563
3564 static int sky2_nway_reset(struct net_device *dev)
3565 {
3566 struct sky2_port *sky2 = netdev_priv(dev);
3567
3568 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3569 return -EINVAL;
3570
3571 sky2_phy_reinit(sky2);
3572 sky2_set_multicast(dev);
3573
3574 return 0;
3575 }
3576
3577 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3578 {
3579 struct sky2_hw *hw = sky2->hw;
3580 unsigned port = sky2->port;
3581 int i;
3582
3583 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3584 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3585
3586 for (i = 2; i < count; i++)
3587 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3588 }
3589
3590 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3591 {
3592 struct sky2_port *sky2 = netdev_priv(netdev);
3593 sky2->msg_enable = value;
3594 }
3595
3596 static int sky2_get_sset_count(struct net_device *dev, int sset)
3597 {
3598 switch (sset) {
3599 case ETH_SS_STATS:
3600 return ARRAY_SIZE(sky2_stats);
3601 default:
3602 return -EOPNOTSUPP;
3603 }
3604 }
3605
3606 static void sky2_get_ethtool_stats(struct net_device *dev,
3607 struct ethtool_stats *stats, u64 * data)
3608 {
3609 struct sky2_port *sky2 = netdev_priv(dev);
3610
3611 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3612 }
3613
3614 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3615 {
3616 int i;
3617
3618 switch (stringset) {
3619 case ETH_SS_STATS:
3620 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3621 memcpy(data + i * ETH_GSTRING_LEN,
3622 sky2_stats[i].name, ETH_GSTRING_LEN);
3623 break;
3624 }
3625 }
3626
3627 static int sky2_set_mac_address(struct net_device *dev, void *p)
3628 {
3629 struct sky2_port *sky2 = netdev_priv(dev);
3630 struct sky2_hw *hw = sky2->hw;
3631 unsigned port = sky2->port;
3632 const struct sockaddr *addr = p;
3633
3634 if (!is_valid_ether_addr(addr->sa_data))
3635 return -EADDRNOTAVAIL;
3636
3637 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3638 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3639 dev->dev_addr, ETH_ALEN);
3640 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3641 dev->dev_addr, ETH_ALEN);
3642
3643 /* virtual address for data */
3644 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3645
3646 /* physical address: used for pause frames */
3647 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3648
3649 return 0;
3650 }
3651
3652 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3653 {
3654 u32 bit;
3655
3656 bit = ether_crc(ETH_ALEN, addr) & 63;
3657 filter[bit >> 3] |= 1 << (bit & 7);
3658 }
3659
3660 static void sky2_set_multicast(struct net_device *dev)
3661 {
3662 struct sky2_port *sky2 = netdev_priv(dev);
3663 struct sky2_hw *hw = sky2->hw;
3664 unsigned port = sky2->port;
3665 struct netdev_hw_addr *ha;
3666 u16 reg;
3667 u8 filter[8];
3668 int rx_pause;
3669 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3670
3671 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3672 memset(filter, 0, sizeof(filter));
3673
3674 reg = gma_read16(hw, port, GM_RX_CTRL);
3675 reg |= GM_RXCR_UCF_ENA;
3676
3677 if (dev->flags & IFF_PROMISC) /* promiscuous */
3678 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3679 else if (dev->flags & IFF_ALLMULTI)
3680 memset(filter, 0xff, sizeof(filter));
3681 else if (netdev_mc_empty(dev) && !rx_pause)
3682 reg &= ~GM_RXCR_MCF_ENA;
3683 else {
3684 reg |= GM_RXCR_MCF_ENA;
3685
3686 if (rx_pause)
3687 sky2_add_filter(filter, pause_mc_addr);
3688
3689 netdev_for_each_mc_addr(ha, dev)
3690 sky2_add_filter(filter, ha->addr);
3691 }
3692
3693 gma_write16(hw, port, GM_MC_ADDR_H1,
3694 (u16) filter[0] | ((u16) filter[1] << 8));
3695 gma_write16(hw, port, GM_MC_ADDR_H2,
3696 (u16) filter[2] | ((u16) filter[3] << 8));
3697 gma_write16(hw, port, GM_MC_ADDR_H3,
3698 (u16) filter[4] | ((u16) filter[5] << 8));
3699 gma_write16(hw, port, GM_MC_ADDR_H4,
3700 (u16) filter[6] | ((u16) filter[7] << 8));
3701
3702 gma_write16(hw, port, GM_RX_CTRL, reg);
3703 }
3704
3705 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3706 struct rtnl_link_stats64 *stats)
3707 {
3708 struct sky2_port *sky2 = netdev_priv(dev);
3709 struct sky2_hw *hw = sky2->hw;
3710 unsigned port = sky2->port;
3711 unsigned int start;
3712 u64 _bytes, _packets;
3713
3714 do {
3715 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3716 _bytes = sky2->rx_stats.bytes;
3717 _packets = sky2->rx_stats.packets;
3718 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3719
3720 stats->rx_packets = _packets;
3721 stats->rx_bytes = _bytes;
3722
3723 do {
3724 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3725 _bytes = sky2->tx_stats.bytes;
3726 _packets = sky2->tx_stats.packets;
3727 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3728
3729 stats->tx_packets = _packets;
3730 stats->tx_bytes = _bytes;
3731
3732 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3733 + get_stats32(hw, port, GM_RXF_BC_OK);
3734
3735 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3736
3737 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3738 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3739 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3740 + get_stats32(hw, port, GM_RXE_FRAG);
3741 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3742
3743 stats->rx_dropped = dev->stats.rx_dropped;
3744 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3745 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3746
3747 return stats;
3748 }
3749
3750 /* Can have one global because blinking is controlled by
3751 * ethtool and that is always under RTNL mutex
3752 */
3753 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3754 {
3755 struct sky2_hw *hw = sky2->hw;
3756 unsigned port = sky2->port;
3757
3758 spin_lock_bh(&sky2->phy_lock);
3759 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3760 hw->chip_id == CHIP_ID_YUKON_EX ||
3761 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3762 u16 pg;
3763 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3764 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3765
3766 switch (mode) {
3767 case MO_LED_OFF:
3768 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3769 PHY_M_LEDC_LOS_CTRL(8) |
3770 PHY_M_LEDC_INIT_CTRL(8) |
3771 PHY_M_LEDC_STA1_CTRL(8) |
3772 PHY_M_LEDC_STA0_CTRL(8));
3773 break;
3774 case MO_LED_ON:
3775 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3776 PHY_M_LEDC_LOS_CTRL(9) |
3777 PHY_M_LEDC_INIT_CTRL(9) |
3778 PHY_M_LEDC_STA1_CTRL(9) |
3779 PHY_M_LEDC_STA0_CTRL(9));
3780 break;
3781 case MO_LED_BLINK:
3782 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3783 PHY_M_LEDC_LOS_CTRL(0xa) |
3784 PHY_M_LEDC_INIT_CTRL(0xa) |
3785 PHY_M_LEDC_STA1_CTRL(0xa) |
3786 PHY_M_LEDC_STA0_CTRL(0xa));
3787 break;
3788 case MO_LED_NORM:
3789 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3790 PHY_M_LEDC_LOS_CTRL(1) |
3791 PHY_M_LEDC_INIT_CTRL(8) |
3792 PHY_M_LEDC_STA1_CTRL(7) |
3793 PHY_M_LEDC_STA0_CTRL(7));
3794 }
3795
3796 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3797 } else
3798 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3799 PHY_M_LED_MO_DUP(mode) |
3800 PHY_M_LED_MO_10(mode) |
3801 PHY_M_LED_MO_100(mode) |
3802 PHY_M_LED_MO_1000(mode) |
3803 PHY_M_LED_MO_RX(mode) |
3804 PHY_M_LED_MO_TX(mode));
3805
3806 spin_unlock_bh(&sky2->phy_lock);
3807 }
3808
3809 /* blink LED's for finding board */
3810 static int sky2_set_phys_id(struct net_device *dev,
3811 enum ethtool_phys_id_state state)
3812 {
3813 struct sky2_port *sky2 = netdev_priv(dev);
3814
3815 switch (state) {
3816 case ETHTOOL_ID_ACTIVE:
3817 return 1; /* cycle on/off once per second */
3818 case ETHTOOL_ID_INACTIVE:
3819 sky2_led(sky2, MO_LED_NORM);
3820 break;
3821 case ETHTOOL_ID_ON:
3822 sky2_led(sky2, MO_LED_ON);
3823 break;
3824 case ETHTOOL_ID_OFF:
3825 sky2_led(sky2, MO_LED_OFF);
3826 break;
3827 }
3828
3829 return 0;
3830 }
3831
3832 static void sky2_get_pauseparam(struct net_device *dev,
3833 struct ethtool_pauseparam *ecmd)
3834 {
3835 struct sky2_port *sky2 = netdev_priv(dev);
3836
3837 switch (sky2->flow_mode) {
3838 case FC_NONE:
3839 ecmd->tx_pause = ecmd->rx_pause = 0;
3840 break;
3841 case FC_TX:
3842 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3843 break;
3844 case FC_RX:
3845 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3846 break;
3847 case FC_BOTH:
3848 ecmd->tx_pause = ecmd->rx_pause = 1;
3849 }
3850
3851 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3852 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3853 }
3854
3855 static int sky2_set_pauseparam(struct net_device *dev,
3856 struct ethtool_pauseparam *ecmd)
3857 {
3858 struct sky2_port *sky2 = netdev_priv(dev);
3859
3860 if (ecmd->autoneg == AUTONEG_ENABLE)
3861 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3862 else
3863 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3864
3865 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3866
3867 if (netif_running(dev))
3868 sky2_phy_reinit(sky2);
3869
3870 return 0;
3871 }
3872
3873 static int sky2_get_coalesce(struct net_device *dev,
3874 struct ethtool_coalesce *ecmd)
3875 {
3876 struct sky2_port *sky2 = netdev_priv(dev);
3877 struct sky2_hw *hw = sky2->hw;
3878
3879 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3880 ecmd->tx_coalesce_usecs = 0;
3881 else {
3882 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3883 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3884 }
3885 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3886
3887 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3888 ecmd->rx_coalesce_usecs = 0;
3889 else {
3890 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3891 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3892 }
3893 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3894
3895 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3896 ecmd->rx_coalesce_usecs_irq = 0;
3897 else {
3898 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3899 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3900 }
3901
3902 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3903
3904 return 0;
3905 }
3906
3907 /* Note: this affect both ports */
3908 static int sky2_set_coalesce(struct net_device *dev,
3909 struct ethtool_coalesce *ecmd)
3910 {
3911 struct sky2_port *sky2 = netdev_priv(dev);
3912 struct sky2_hw *hw = sky2->hw;
3913 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3914
3915 if (ecmd->tx_coalesce_usecs > tmax ||
3916 ecmd->rx_coalesce_usecs > tmax ||
3917 ecmd->rx_coalesce_usecs_irq > tmax)
3918 return -EINVAL;
3919
3920 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3921 return -EINVAL;
3922 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3923 return -EINVAL;
3924 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
3925 return -EINVAL;
3926
3927 if (ecmd->tx_coalesce_usecs == 0)
3928 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3929 else {
3930 sky2_write32(hw, STAT_TX_TIMER_INI,
3931 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3932 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3933 }
3934 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3935
3936 if (ecmd->rx_coalesce_usecs == 0)
3937 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3938 else {
3939 sky2_write32(hw, STAT_LEV_TIMER_INI,
3940 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3941 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3942 }
3943 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3944
3945 if (ecmd->rx_coalesce_usecs_irq == 0)
3946 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3947 else {
3948 sky2_write32(hw, STAT_ISR_TIMER_INI,
3949 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3950 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3951 }
3952 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3953 return 0;
3954 }
3955
3956 static void sky2_get_ringparam(struct net_device *dev,
3957 struct ethtool_ringparam *ering)
3958 {
3959 struct sky2_port *sky2 = netdev_priv(dev);
3960
3961 ering->rx_max_pending = RX_MAX_PENDING;
3962 ering->rx_mini_max_pending = 0;
3963 ering->rx_jumbo_max_pending = 0;
3964 ering->tx_max_pending = TX_MAX_PENDING;
3965
3966 ering->rx_pending = sky2->rx_pending;
3967 ering->rx_mini_pending = 0;
3968 ering->rx_jumbo_pending = 0;
3969 ering->tx_pending = sky2->tx_pending;
3970 }
3971
3972 static int sky2_set_ringparam(struct net_device *dev,
3973 struct ethtool_ringparam *ering)
3974 {
3975 struct sky2_port *sky2 = netdev_priv(dev);
3976
3977 if (ering->rx_pending > RX_MAX_PENDING ||
3978 ering->rx_pending < 8 ||
3979 ering->tx_pending < TX_MIN_PENDING ||
3980 ering->tx_pending > TX_MAX_PENDING)
3981 return -EINVAL;
3982
3983 sky2_detach(dev);
3984
3985 sky2->rx_pending = ering->rx_pending;
3986 sky2->tx_pending = ering->tx_pending;
3987 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3988
3989 return sky2_reattach(dev);
3990 }
3991
3992 static int sky2_get_regs_len(struct net_device *dev)
3993 {
3994 return 0x4000;
3995 }
3996
3997 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3998 {
3999 /* This complicated switch statement is to make sure and
4000 * only access regions that are unreserved.
4001 * Some blocks are only valid on dual port cards.
4002 */
4003 switch (b) {
4004 /* second port */
4005 case 5: /* Tx Arbiter 2 */
4006 case 9: /* RX2 */
4007 case 14 ... 15: /* TX2 */
4008 case 17: case 19: /* Ram Buffer 2 */
4009 case 22 ... 23: /* Tx Ram Buffer 2 */
4010 case 25: /* Rx MAC Fifo 1 */
4011 case 27: /* Tx MAC Fifo 2 */
4012 case 31: /* GPHY 2 */
4013 case 40 ... 47: /* Pattern Ram 2 */
4014 case 52: case 54: /* TCP Segmentation 2 */
4015 case 112 ... 116: /* GMAC 2 */
4016 return hw->ports > 1;
4017
4018 case 0: /* Control */
4019 case 2: /* Mac address */
4020 case 4: /* Tx Arbiter 1 */
4021 case 7: /* PCI express reg */
4022 case 8: /* RX1 */
4023 case 12 ... 13: /* TX1 */
4024 case 16: case 18:/* Rx Ram Buffer 1 */
4025 case 20 ... 21: /* Tx Ram Buffer 1 */
4026 case 24: /* Rx MAC Fifo 1 */
4027 case 26: /* Tx MAC Fifo 1 */
4028 case 28 ... 29: /* Descriptor and status unit */
4029 case 30: /* GPHY 1*/
4030 case 32 ... 39: /* Pattern Ram 1 */
4031 case 48: case 50: /* TCP Segmentation 1 */
4032 case 56 ... 60: /* PCI space */
4033 case 80 ... 84: /* GMAC 1 */
4034 return 1;
4035
4036 default:
4037 return 0;
4038 }
4039 }
4040
4041 /*
4042 * Returns copy of control register region
4043 * Note: ethtool_get_regs always provides full size (16k) buffer
4044 */
4045 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4046 void *p)
4047 {
4048 const struct sky2_port *sky2 = netdev_priv(dev);
4049 const void __iomem *io = sky2->hw->regs;
4050 unsigned int b;
4051
4052 regs->version = 1;
4053
4054 for (b = 0; b < 128; b++) {
4055 /* skip poisonous diagnostic ram region in block 3 */
4056 if (b == 3)
4057 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4058 else if (sky2_reg_access_ok(sky2->hw, b))
4059 memcpy_fromio(p, io, 128);
4060 else
4061 memset(p, 0, 128);
4062
4063 p += 128;
4064 io += 128;
4065 }
4066 }
4067
4068 static int sky2_get_eeprom_len(struct net_device *dev)
4069 {
4070 struct sky2_port *sky2 = netdev_priv(dev);
4071 struct sky2_hw *hw = sky2->hw;
4072 u16 reg2;
4073
4074 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4075 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4076 }
4077
4078 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4079 {
4080 unsigned long start = jiffies;
4081
4082 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4083 /* Can take up to 10.6 ms for write */
4084 if (time_after(jiffies, start + HZ/4)) {
4085 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4086 return -ETIMEDOUT;
4087 }
4088 mdelay(1);
4089 }
4090
4091 return 0;
4092 }
4093
4094 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4095 u16 offset, size_t length)
4096 {
4097 int rc = 0;
4098
4099 while (length > 0) {
4100 u32 val;
4101
4102 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4103 rc = sky2_vpd_wait(hw, cap, 0);
4104 if (rc)
4105 break;
4106
4107 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4108
4109 memcpy(data, &val, min(sizeof(val), length));
4110 offset += sizeof(u32);
4111 data += sizeof(u32);
4112 length -= sizeof(u32);
4113 }
4114
4115 return rc;
4116 }
4117
4118 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4119 u16 offset, unsigned int length)
4120 {
4121 unsigned int i;
4122 int rc = 0;
4123
4124 for (i = 0; i < length; i += sizeof(u32)) {
4125 u32 val = *(u32 *)(data + i);
4126
4127 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4128 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4129
4130 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4131 if (rc)
4132 break;
4133 }
4134 return rc;
4135 }
4136
4137 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4138 u8 *data)
4139 {
4140 struct sky2_port *sky2 = netdev_priv(dev);
4141 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4142
4143 if (!cap)
4144 return -EINVAL;
4145
4146 eeprom->magic = SKY2_EEPROM_MAGIC;
4147
4148 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4149 }
4150
4151 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4152 u8 *data)
4153 {
4154 struct sky2_port *sky2 = netdev_priv(dev);
4155 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4156
4157 if (!cap)
4158 return -EINVAL;
4159
4160 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4161 return -EINVAL;
4162
4163 /* Partial writes not supported */
4164 if ((eeprom->offset & 3) || (eeprom->len & 3))
4165 return -EINVAL;
4166
4167 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4168 }
4169
4170 static u32 sky2_fix_features(struct net_device *dev, u32 features)
4171 {
4172 const struct sky2_port *sky2 = netdev_priv(dev);
4173 const struct sky2_hw *hw = sky2->hw;
4174
4175 /* In order to do Jumbo packets on these chips, need to turn off the
4176 * transmit store/forward. Therefore checksum offload won't work.
4177 */
4178 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
4179 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
4180
4181 return features;
4182 }
4183
4184 static int sky2_set_features(struct net_device *dev, u32 features)
4185 {
4186 struct sky2_port *sky2 = netdev_priv(dev);
4187 u32 changed = dev->features ^ features;
4188
4189 if (changed & NETIF_F_RXCSUM) {
4190 u32 on = features & NETIF_F_RXCSUM;
4191 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4192 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4193 }
4194
4195 if (changed & NETIF_F_RXHASH)
4196 rx_set_rss(dev, features);
4197
4198 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4199 sky2_vlan_mode(dev, features);
4200
4201 return 0;
4202 }
4203
4204 static const struct ethtool_ops sky2_ethtool_ops = {
4205 .get_settings = sky2_get_settings,
4206 .set_settings = sky2_set_settings,
4207 .get_drvinfo = sky2_get_drvinfo,
4208 .get_wol = sky2_get_wol,
4209 .set_wol = sky2_set_wol,
4210 .get_msglevel = sky2_get_msglevel,
4211 .set_msglevel = sky2_set_msglevel,
4212 .nway_reset = sky2_nway_reset,
4213 .get_regs_len = sky2_get_regs_len,
4214 .get_regs = sky2_get_regs,
4215 .get_link = ethtool_op_get_link,
4216 .get_eeprom_len = sky2_get_eeprom_len,
4217 .get_eeprom = sky2_get_eeprom,
4218 .set_eeprom = sky2_set_eeprom,
4219 .get_strings = sky2_get_strings,
4220 .get_coalesce = sky2_get_coalesce,
4221 .set_coalesce = sky2_set_coalesce,
4222 .get_ringparam = sky2_get_ringparam,
4223 .set_ringparam = sky2_set_ringparam,
4224 .get_pauseparam = sky2_get_pauseparam,
4225 .set_pauseparam = sky2_set_pauseparam,
4226 .set_phys_id = sky2_set_phys_id,
4227 .get_sset_count = sky2_get_sset_count,
4228 .get_ethtool_stats = sky2_get_ethtool_stats,
4229 };
4230
4231 #ifdef CONFIG_SKY2_DEBUG
4232
4233 static struct dentry *sky2_debug;
4234
4235
4236 /*
4237 * Read and parse the first part of Vital Product Data
4238 */
4239 #define VPD_SIZE 128
4240 #define VPD_MAGIC 0x82
4241
4242 static const struct vpd_tag {
4243 char tag[2];
4244 char *label;
4245 } vpd_tags[] = {
4246 { "PN", "Part Number" },
4247 { "EC", "Engineering Level" },
4248 { "MN", "Manufacturer" },
4249 { "SN", "Serial Number" },
4250 { "YA", "Asset Tag" },
4251 { "VL", "First Error Log Message" },
4252 { "VF", "Second Error Log Message" },
4253 { "VB", "Boot Agent ROM Configuration" },
4254 { "VE", "EFI UNDI Configuration" },
4255 };
4256
4257 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4258 {
4259 size_t vpd_size;
4260 loff_t offs;
4261 u8 len;
4262 unsigned char *buf;
4263 u16 reg2;
4264
4265 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4266 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4267
4268 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4269 buf = kmalloc(vpd_size, GFP_KERNEL);
4270 if (!buf) {
4271 seq_puts(seq, "no memory!\n");
4272 return;
4273 }
4274
4275 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4276 seq_puts(seq, "VPD read failed\n");
4277 goto out;
4278 }
4279
4280 if (buf[0] != VPD_MAGIC) {
4281 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4282 goto out;
4283 }
4284 len = buf[1];
4285 if (len == 0 || len > vpd_size - 4) {
4286 seq_printf(seq, "Invalid id length: %d\n", len);
4287 goto out;
4288 }
4289
4290 seq_printf(seq, "%.*s\n", len, buf + 3);
4291 offs = len + 3;
4292
4293 while (offs < vpd_size - 4) {
4294 int i;
4295
4296 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4297 break;
4298 len = buf[offs + 2];
4299 if (offs + len + 3 >= vpd_size)
4300 break;
4301
4302 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4303 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4304 seq_printf(seq, " %s: %.*s\n",
4305 vpd_tags[i].label, len, buf + offs + 3);
4306 break;
4307 }
4308 }
4309 offs += len + 3;
4310 }
4311 out:
4312 kfree(buf);
4313 }
4314
4315 static int sky2_debug_show(struct seq_file *seq, void *v)
4316 {
4317 struct net_device *dev = seq->private;
4318 const struct sky2_port *sky2 = netdev_priv(dev);
4319 struct sky2_hw *hw = sky2->hw;
4320 unsigned port = sky2->port;
4321 unsigned idx, last;
4322 int sop;
4323
4324 sky2_show_vpd(seq, hw);
4325
4326 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4327 sky2_read32(hw, B0_ISRC),
4328 sky2_read32(hw, B0_IMSK),
4329 sky2_read32(hw, B0_Y2_SP_ICR));
4330
4331 if (!netif_running(dev)) {
4332 seq_printf(seq, "network not running\n");
4333 return 0;
4334 }
4335
4336 napi_disable(&hw->napi);
4337 last = sky2_read16(hw, STAT_PUT_IDX);
4338
4339 seq_printf(seq, "Status ring %u\n", hw->st_size);
4340 if (hw->st_idx == last)
4341 seq_puts(seq, "Status ring (empty)\n");
4342 else {
4343 seq_puts(seq, "Status ring\n");
4344 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4345 idx = RING_NEXT(idx, hw->st_size)) {
4346 const struct sky2_status_le *le = hw->st_le + idx;
4347 seq_printf(seq, "[%d] %#x %d %#x\n",
4348 idx, le->opcode, le->length, le->status);
4349 }
4350 seq_puts(seq, "\n");
4351 }
4352
4353 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4354 sky2->tx_cons, sky2->tx_prod,
4355 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4356 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4357
4358 /* Dump contents of tx ring */
4359 sop = 1;
4360 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4361 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4362 const struct sky2_tx_le *le = sky2->tx_le + idx;
4363 u32 a = le32_to_cpu(le->addr);
4364
4365 if (sop)
4366 seq_printf(seq, "%u:", idx);
4367 sop = 0;
4368
4369 switch (le->opcode & ~HW_OWNER) {
4370 case OP_ADDR64:
4371 seq_printf(seq, " %#x:", a);
4372 break;
4373 case OP_LRGLEN:
4374 seq_printf(seq, " mtu=%d", a);
4375 break;
4376 case OP_VLAN:
4377 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4378 break;
4379 case OP_TCPLISW:
4380 seq_printf(seq, " csum=%#x", a);
4381 break;
4382 case OP_LARGESEND:
4383 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4384 break;
4385 case OP_PACKET:
4386 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4387 break;
4388 case OP_BUFFER:
4389 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4390 break;
4391 default:
4392 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4393 a, le16_to_cpu(le->length));
4394 }
4395
4396 if (le->ctrl & EOP) {
4397 seq_putc(seq, '\n');
4398 sop = 1;
4399 }
4400 }
4401
4402 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4403 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4404 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4405 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4406
4407 sky2_read32(hw, B0_Y2_SP_LISR);
4408 napi_enable(&hw->napi);
4409 return 0;
4410 }
4411
4412 static int sky2_debug_open(struct inode *inode, struct file *file)
4413 {
4414 return single_open(file, sky2_debug_show, inode->i_private);
4415 }
4416
4417 static const struct file_operations sky2_debug_fops = {
4418 .owner = THIS_MODULE,
4419 .open = sky2_debug_open,
4420 .read = seq_read,
4421 .llseek = seq_lseek,
4422 .release = single_release,
4423 };
4424
4425 /*
4426 * Use network device events to create/remove/rename
4427 * debugfs file entries
4428 */
4429 static int sky2_device_event(struct notifier_block *unused,
4430 unsigned long event, void *ptr)
4431 {
4432 struct net_device *dev = ptr;
4433 struct sky2_port *sky2 = netdev_priv(dev);
4434
4435 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4436 return NOTIFY_DONE;
4437
4438 switch (event) {
4439 case NETDEV_CHANGENAME:
4440 if (sky2->debugfs) {
4441 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4442 sky2_debug, dev->name);
4443 }
4444 break;
4445
4446 case NETDEV_GOING_DOWN:
4447 if (sky2->debugfs) {
4448 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4449 debugfs_remove(sky2->debugfs);
4450 sky2->debugfs = NULL;
4451 }
4452 break;
4453
4454 case NETDEV_UP:
4455 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4456 sky2_debug, dev,
4457 &sky2_debug_fops);
4458 if (IS_ERR(sky2->debugfs))
4459 sky2->debugfs = NULL;
4460 }
4461
4462 return NOTIFY_DONE;
4463 }
4464
4465 static struct notifier_block sky2_notifier = {
4466 .notifier_call = sky2_device_event,
4467 };
4468
4469
4470 static __init void sky2_debug_init(void)
4471 {
4472 struct dentry *ent;
4473
4474 ent = debugfs_create_dir("sky2", NULL);
4475 if (!ent || IS_ERR(ent))
4476 return;
4477
4478 sky2_debug = ent;
4479 register_netdevice_notifier(&sky2_notifier);
4480 }
4481
4482 static __exit void sky2_debug_cleanup(void)
4483 {
4484 if (sky2_debug) {
4485 unregister_netdevice_notifier(&sky2_notifier);
4486 debugfs_remove(sky2_debug);
4487 sky2_debug = NULL;
4488 }
4489 }
4490
4491 #else
4492 #define sky2_debug_init()
4493 #define sky2_debug_cleanup()
4494 #endif
4495
4496 /* Two copies of network device operations to handle special case of
4497 not allowing netpoll on second port */
4498 static const struct net_device_ops sky2_netdev_ops[2] = {
4499 {
4500 .ndo_open = sky2_up,
4501 .ndo_stop = sky2_down,
4502 .ndo_start_xmit = sky2_xmit_frame,
4503 .ndo_do_ioctl = sky2_ioctl,
4504 .ndo_validate_addr = eth_validate_addr,
4505 .ndo_set_mac_address = sky2_set_mac_address,
4506 .ndo_set_multicast_list = sky2_set_multicast,
4507 .ndo_change_mtu = sky2_change_mtu,
4508 .ndo_fix_features = sky2_fix_features,
4509 .ndo_set_features = sky2_set_features,
4510 .ndo_tx_timeout = sky2_tx_timeout,
4511 .ndo_get_stats64 = sky2_get_stats,
4512 #ifdef CONFIG_NET_POLL_CONTROLLER
4513 .ndo_poll_controller = sky2_netpoll,
4514 #endif
4515 },
4516 {
4517 .ndo_open = sky2_up,
4518 .ndo_stop = sky2_down,
4519 .ndo_start_xmit = sky2_xmit_frame,
4520 .ndo_do_ioctl = sky2_ioctl,
4521 .ndo_validate_addr = eth_validate_addr,
4522 .ndo_set_mac_address = sky2_set_mac_address,
4523 .ndo_set_multicast_list = sky2_set_multicast,
4524 .ndo_change_mtu = sky2_change_mtu,
4525 .ndo_fix_features = sky2_fix_features,
4526 .ndo_set_features = sky2_set_features,
4527 .ndo_tx_timeout = sky2_tx_timeout,
4528 .ndo_get_stats64 = sky2_get_stats,
4529 },
4530 };
4531
4532 /* Initialize network device */
4533 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4534 unsigned port,
4535 int highmem, int wol)
4536 {
4537 struct sky2_port *sky2;
4538 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4539
4540 if (!dev) {
4541 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4542 return NULL;
4543 }
4544
4545 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4546 dev->irq = hw->pdev->irq;
4547 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4548 dev->watchdog_timeo = TX_WATCHDOG;
4549 dev->netdev_ops = &sky2_netdev_ops[port];
4550
4551 sky2 = netdev_priv(dev);
4552 sky2->netdev = dev;
4553 sky2->hw = hw;
4554 sky2->msg_enable = netif_msg_init(debug, default_msg);
4555
4556 /* Auto speed and flow control */
4557 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4558 if (hw->chip_id != CHIP_ID_YUKON_XL)
4559 dev->hw_features |= NETIF_F_RXCSUM;
4560
4561 sky2->flow_mode = FC_BOTH;
4562
4563 sky2->duplex = -1;
4564 sky2->speed = -1;
4565 sky2->advertising = sky2_supported_modes(hw);
4566 sky2->wol = wol;
4567
4568 spin_lock_init(&sky2->phy_lock);
4569
4570 sky2->tx_pending = TX_DEF_PENDING;
4571 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4572 sky2->rx_pending = RX_DEF_PENDING;
4573
4574 hw->dev[port] = dev;
4575
4576 sky2->port = port;
4577
4578 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4579
4580 if (highmem)
4581 dev->features |= NETIF_F_HIGHDMA;
4582
4583 /* Enable receive hashing unless hardware is known broken */
4584 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4585 dev->hw_features |= NETIF_F_RXHASH;
4586
4587 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4588 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4589 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4590 }
4591
4592 dev->features |= dev->hw_features;
4593
4594 /* read the mac address */
4595 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4596 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4597
4598 return dev;
4599 }
4600
4601 static void __devinit sky2_show_addr(struct net_device *dev)
4602 {
4603 const struct sky2_port *sky2 = netdev_priv(dev);
4604
4605 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4606 }
4607
4608 /* Handle software interrupt used during MSI test */
4609 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4610 {
4611 struct sky2_hw *hw = dev_id;
4612 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4613
4614 if (status == 0)
4615 return IRQ_NONE;
4616
4617 if (status & Y2_IS_IRQ_SW) {
4618 hw->flags |= SKY2_HW_USE_MSI;
4619 wake_up(&hw->msi_wait);
4620 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4621 }
4622 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4623
4624 return IRQ_HANDLED;
4625 }
4626
4627 /* Test interrupt path by forcing a a software IRQ */
4628 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4629 {
4630 struct pci_dev *pdev = hw->pdev;
4631 int err;
4632
4633 init_waitqueue_head(&hw->msi_wait);
4634
4635 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4636
4637 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4638 if (err) {
4639 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4640 return err;
4641 }
4642
4643 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4644 sky2_read8(hw, B0_CTST);
4645
4646 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4647
4648 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4649 /* MSI test failed, go back to INTx mode */
4650 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4651 "switching to INTx mode.\n");
4652
4653 err = -EOPNOTSUPP;
4654 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4655 }
4656
4657 sky2_write32(hw, B0_IMSK, 0);
4658 sky2_read32(hw, B0_IMSK);
4659
4660 free_irq(pdev->irq, hw);
4661
4662 return err;
4663 }
4664
4665 /* This driver supports yukon2 chipset only */
4666 static const char *sky2_name(u8 chipid, char *buf, int sz)
4667 {
4668 const char *name[] = {
4669 "XL", /* 0xb3 */
4670 "EC Ultra", /* 0xb4 */
4671 "Extreme", /* 0xb5 */
4672 "EC", /* 0xb6 */
4673 "FE", /* 0xb7 */
4674 "FE+", /* 0xb8 */
4675 "Supreme", /* 0xb9 */
4676 "UL 2", /* 0xba */
4677 "Unknown", /* 0xbb */
4678 "Optima", /* 0xbc */
4679 };
4680
4681 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4682 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4683 else
4684 snprintf(buf, sz, "(chip %#x)", chipid);
4685 return buf;
4686 }
4687
4688 static int __devinit sky2_probe(struct pci_dev *pdev,
4689 const struct pci_device_id *ent)
4690 {
4691 struct net_device *dev;
4692 struct sky2_hw *hw;
4693 int err, using_dac = 0, wol_default;
4694 u32 reg;
4695 char buf1[16];
4696
4697 err = pci_enable_device(pdev);
4698 if (err) {
4699 dev_err(&pdev->dev, "cannot enable PCI device\n");
4700 goto err_out;
4701 }
4702
4703 /* Get configuration information
4704 * Note: only regular PCI config access once to test for HW issues
4705 * other PCI access through shared memory for speed and to
4706 * avoid MMCONFIG problems.
4707 */
4708 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4709 if (err) {
4710 dev_err(&pdev->dev, "PCI read config failed\n");
4711 goto err_out;
4712 }
4713
4714 if (~reg == 0) {
4715 dev_err(&pdev->dev, "PCI configuration read error\n");
4716 goto err_out;
4717 }
4718
4719 err = pci_request_regions(pdev, DRV_NAME);
4720 if (err) {
4721 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4722 goto err_out_disable;
4723 }
4724
4725 pci_set_master(pdev);
4726
4727 if (sizeof(dma_addr_t) > sizeof(u32) &&
4728 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4729 using_dac = 1;
4730 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4731 if (err < 0) {
4732 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4733 "for consistent allocations\n");
4734 goto err_out_free_regions;
4735 }
4736 } else {
4737 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4738 if (err) {
4739 dev_err(&pdev->dev, "no usable DMA configuration\n");
4740 goto err_out_free_regions;
4741 }
4742 }
4743
4744
4745 #ifdef __BIG_ENDIAN
4746 /* The sk98lin vendor driver uses hardware byte swapping but
4747 * this driver uses software swapping.
4748 */
4749 reg &= ~PCI_REV_DESC;
4750 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4751 if (err) {
4752 dev_err(&pdev->dev, "PCI write config failed\n");
4753 goto err_out_free_regions;
4754 }
4755 #endif
4756
4757 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4758
4759 err = -ENOMEM;
4760
4761 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4762 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4763 if (!hw) {
4764 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4765 goto err_out_free_regions;
4766 }
4767
4768 hw->pdev = pdev;
4769 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4770
4771 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4772 if (!hw->regs) {
4773 dev_err(&pdev->dev, "cannot map device registers\n");
4774 goto err_out_free_hw;
4775 }
4776
4777 err = sky2_init(hw);
4778 if (err)
4779 goto err_out_iounmap;
4780
4781 /* ring for status responses */
4782 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4783 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4784 &hw->st_dma);
4785 if (!hw->st_le)
4786 goto err_out_reset;
4787
4788 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4789 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4790
4791 sky2_reset(hw);
4792
4793 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4794 if (!dev) {
4795 err = -ENOMEM;
4796 goto err_out_free_pci;
4797 }
4798
4799 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4800 err = sky2_test_msi(hw);
4801 if (err == -EOPNOTSUPP)
4802 pci_disable_msi(pdev);
4803 else if (err)
4804 goto err_out_free_netdev;
4805 }
4806
4807 err = register_netdev(dev);
4808 if (err) {
4809 dev_err(&pdev->dev, "cannot register net device\n");
4810 goto err_out_free_netdev;
4811 }
4812
4813 netif_carrier_off(dev);
4814
4815 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4816
4817 err = request_irq(pdev->irq, sky2_intr,
4818 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4819 hw->irq_name, hw);
4820 if (err) {
4821 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4822 goto err_out_unregister;
4823 }
4824 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4825 napi_enable(&hw->napi);
4826
4827 sky2_show_addr(dev);
4828
4829 if (hw->ports > 1) {
4830 struct net_device *dev1;
4831
4832 err = -ENOMEM;
4833 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4834 if (dev1 && (err = register_netdev(dev1)) == 0)
4835 sky2_show_addr(dev1);
4836 else {
4837 dev_warn(&pdev->dev,
4838 "register of second port failed (%d)\n", err);
4839 hw->dev[1] = NULL;
4840 hw->ports = 1;
4841 if (dev1)
4842 free_netdev(dev1);
4843 }
4844 }
4845
4846 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4847 INIT_WORK(&hw->restart_work, sky2_restart);
4848
4849 pci_set_drvdata(pdev, hw);
4850 pdev->d3_delay = 150;
4851
4852 return 0;
4853
4854 err_out_unregister:
4855 if (hw->flags & SKY2_HW_USE_MSI)
4856 pci_disable_msi(pdev);
4857 unregister_netdev(dev);
4858 err_out_free_netdev:
4859 free_netdev(dev);
4860 err_out_free_pci:
4861 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4862 hw->st_le, hw->st_dma);
4863 err_out_reset:
4864 sky2_write8(hw, B0_CTST, CS_RST_SET);
4865 err_out_iounmap:
4866 iounmap(hw->regs);
4867 err_out_free_hw:
4868 kfree(hw);
4869 err_out_free_regions:
4870 pci_release_regions(pdev);
4871 err_out_disable:
4872 pci_disable_device(pdev);
4873 err_out:
4874 pci_set_drvdata(pdev, NULL);
4875 return err;
4876 }
4877
4878 static void __devexit sky2_remove(struct pci_dev *pdev)
4879 {
4880 struct sky2_hw *hw = pci_get_drvdata(pdev);
4881 int i;
4882
4883 if (!hw)
4884 return;
4885
4886 del_timer_sync(&hw->watchdog_timer);
4887 cancel_work_sync(&hw->restart_work);
4888
4889 for (i = hw->ports-1; i >= 0; --i)
4890 unregister_netdev(hw->dev[i]);
4891
4892 sky2_write32(hw, B0_IMSK, 0);
4893
4894 sky2_power_aux(hw);
4895
4896 sky2_write8(hw, B0_CTST, CS_RST_SET);
4897 sky2_read8(hw, B0_CTST);
4898
4899 free_irq(pdev->irq, hw);
4900 if (hw->flags & SKY2_HW_USE_MSI)
4901 pci_disable_msi(pdev);
4902 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4903 hw->st_le, hw->st_dma);
4904 pci_release_regions(pdev);
4905 pci_disable_device(pdev);
4906
4907 for (i = hw->ports-1; i >= 0; --i)
4908 free_netdev(hw->dev[i]);
4909
4910 iounmap(hw->regs);
4911 kfree(hw);
4912
4913 pci_set_drvdata(pdev, NULL);
4914 }
4915
4916 static int sky2_suspend(struct device *dev)
4917 {
4918 struct pci_dev *pdev = to_pci_dev(dev);
4919 struct sky2_hw *hw = pci_get_drvdata(pdev);
4920 int i;
4921
4922 if (!hw)
4923 return 0;
4924
4925 del_timer_sync(&hw->watchdog_timer);
4926 cancel_work_sync(&hw->restart_work);
4927
4928 rtnl_lock();
4929
4930 sky2_all_down(hw);
4931 for (i = 0; i < hw->ports; i++) {
4932 struct net_device *dev = hw->dev[i];
4933 struct sky2_port *sky2 = netdev_priv(dev);
4934
4935 if (sky2->wol)
4936 sky2_wol_init(sky2);
4937 }
4938
4939 sky2_power_aux(hw);
4940 rtnl_unlock();
4941
4942 return 0;
4943 }
4944
4945 #ifdef CONFIG_PM_SLEEP
4946 static int sky2_resume(struct device *dev)
4947 {
4948 struct pci_dev *pdev = to_pci_dev(dev);
4949 struct sky2_hw *hw = pci_get_drvdata(pdev);
4950 int err;
4951
4952 if (!hw)
4953 return 0;
4954
4955 /* Re-enable all clocks */
4956 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4957 if (err) {
4958 dev_err(&pdev->dev, "PCI write config failed\n");
4959 goto out;
4960 }
4961
4962 rtnl_lock();
4963 sky2_reset(hw);
4964 sky2_all_up(hw);
4965 rtnl_unlock();
4966
4967 return 0;
4968 out:
4969
4970 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4971 pci_disable_device(pdev);
4972 return err;
4973 }
4974
4975 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
4976 #define SKY2_PM_OPS (&sky2_pm_ops)
4977
4978 #else
4979
4980 #define SKY2_PM_OPS NULL
4981 #endif
4982
4983 static void sky2_shutdown(struct pci_dev *pdev)
4984 {
4985 sky2_suspend(&pdev->dev);
4986 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4987 pci_set_power_state(pdev, PCI_D3hot);
4988 }
4989
4990 static struct pci_driver sky2_driver = {
4991 .name = DRV_NAME,
4992 .id_table = sky2_id_table,
4993 .probe = sky2_probe,
4994 .remove = __devexit_p(sky2_remove),
4995 .shutdown = sky2_shutdown,
4996 .driver.pm = SKY2_PM_OPS,
4997 };
4998
4999 static int __init sky2_init_module(void)
5000 {
5001 pr_info("driver version " DRV_VERSION "\n");
5002
5003 sky2_debug_init();
5004 return pci_register_driver(&sky2_driver);
5005 }
5006
5007 static void __exit sky2_cleanup_module(void)
5008 {
5009 pci_unregister_driver(&sky2_driver);
5010 sky2_debug_cleanup();
5011 }
5012
5013 module_init(sky2_init_module);
5014 module_exit(sky2_cleanup_module);
5015
5016 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5017 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5018 MODULE_LICENSE("GPL");
5019 MODULE_VERSION(DRV_VERSION);
kernel-based virtual machine