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net: ep93xx_eth: drop GFP_DMA from call to dma_alloc_coherent()
[linux-2.6/kvm.git] / drivers / net / benet / be_cmds.h
blob8148cc66cbe90350e358d468f40aabcced9e3f9a
1 /*
2 * Copyright (C) 2005 - 2011 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 /*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26 struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30 };
31
32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35 struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45 };
46
47 #define CQE_FLAGS_VALID_MASK (1 << 31)
48 #define CQE_FLAGS_ASYNC_MASK (1 << 30)
49 #define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50 #define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52 /* Completion Status */
53 enum {
54 MCC_STATUS_SUCCESS = 0x0,
55 /* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57 /* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59 /* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61 /* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63 /* The command is completing with a DMA error */
64 MCC_STATUS_DMA_FAILED = 0x5,
65 MCC_STATUS_NOT_SUPPORTED = 66
66 };
67
68 #define CQE_STATUS_COMPL_MASK 0xFFFF
69 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70 #define CQE_STATUS_EXTD_MASK 0xFFFF
71 #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
72
73 struct be_mcc_compl {
74 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
78 };
79
80 /* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
82 */
83 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
85 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
86 #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
87 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
88 #define ASYNC_EVENT_CODE_GRP_5 0x5
89 #define ASYNC_EVENT_QOS_SPEED 0x1
90 #define ASYNC_EVENT_COS_PRIORITY 0x2
91 #define ASYNC_EVENT_PVID_STATE 0x3
92 struct be_async_event_trailer {
93 u32 code;
94 };
95
96 enum {
97 ASYNC_EVENT_LINK_DOWN = 0x0,
98 ASYNC_EVENT_LINK_UP = 0x1
99 };
100
101 /* When the event code of an async trailer is link-state, the mcc_compl
102 * must be interpreted as follows
103 */
104 struct be_async_event_link_state {
105 u8 physical_port;
106 u8 port_link_status;
107 u8 port_duplex;
108 u8 port_speed;
109 u8 port_fault;
110 u8 rsvd0[7];
111 struct be_async_event_trailer trailer;
112 } __packed;
113
114 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
115 * the mcc_compl must be interpreted as follows
116 */
117 struct be_async_event_grp5_qos_link_speed {
118 u8 physical_port;
119 u8 rsvd[5];
120 u16 qos_link_speed;
121 u32 event_tag;
122 struct be_async_event_trailer trailer;
123 } __packed;
124
125 /* When the event code of an async trailer is GRP5 and event type is
126 * CoS-Priority, the mcc_compl must be interpreted as follows
127 */
128 struct be_async_event_grp5_cos_priority {
129 u8 physical_port;
130 u8 available_priority_bmap;
131 u8 reco_default_priority;
132 u8 valid;
133 u8 rsvd0;
134 u8 event_tag;
135 struct be_async_event_trailer trailer;
136 } __packed;
137
138 /* When the event code of an async trailer is GRP5 and event type is
139 * PVID state, the mcc_compl must be interpreted as follows
140 */
141 struct be_async_event_grp5_pvid_state {
142 u8 enabled;
143 u8 rsvd0;
144 u16 tag;
145 u32 event_tag;
146 u32 rsvd1;
147 struct be_async_event_trailer trailer;
148 } __packed;
149
150 struct be_mcc_mailbox {
151 struct be_mcc_wrb wrb;
152 struct be_mcc_compl compl;
153 };
154
155 #define CMD_SUBSYSTEM_COMMON 0x1
156 #define CMD_SUBSYSTEM_ETH 0x3
157 #define CMD_SUBSYSTEM_LOWLEVEL 0xb
158
159 #define OPCODE_COMMON_NTWK_MAC_QUERY 1
160 #define OPCODE_COMMON_NTWK_MAC_SET 2
161 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3
162 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
163 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
164 #define OPCODE_COMMON_READ_FLASHROM 6
165 #define OPCODE_COMMON_WRITE_FLASHROM 7
166 #define OPCODE_COMMON_CQ_CREATE 12
167 #define OPCODE_COMMON_EQ_CREATE 13
168 #define OPCODE_COMMON_MCC_CREATE 21
169 #define OPCODE_COMMON_SET_QOS 28
170 #define OPCODE_COMMON_MCC_CREATE_EXT 90
171 #define OPCODE_COMMON_SEEPROM_READ 30
172 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
173 #define OPCODE_COMMON_NTWK_RX_FILTER 34
174 #define OPCODE_COMMON_GET_FW_VERSION 35
175 #define OPCODE_COMMON_SET_FLOW_CONTROL 36
176 #define OPCODE_COMMON_GET_FLOW_CONTROL 37
177 #define OPCODE_COMMON_SET_FRAME_SIZE 39
178 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41
179 #define OPCODE_COMMON_FIRMWARE_CONFIG 42
180 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
181 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
182 #define OPCODE_COMMON_MCC_DESTROY 53
183 #define OPCODE_COMMON_CQ_DESTROY 54
184 #define OPCODE_COMMON_EQ_DESTROY 55
185 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
186 #define OPCODE_COMMON_NTWK_PMAC_ADD 59
187 #define OPCODE_COMMON_NTWK_PMAC_DEL 60
188 #define OPCODE_COMMON_FUNCTION_RESET 61
189 #define OPCODE_COMMON_MANAGE_FAT 68
190 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
191 #define OPCODE_COMMON_GET_BEACON_STATE 70
192 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73
193 #define OPCODE_COMMON_GET_PHY_DETAILS 102
194 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
195 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
196 #define OPCODE_COMMON_WRITE_OBJECT 172
197
198 #define OPCODE_ETH_RSS_CONFIG 1
199 #define OPCODE_ETH_ACPI_CONFIG 2
200 #define OPCODE_ETH_PROMISCUOUS 3
201 #define OPCODE_ETH_GET_STATISTICS 4
202 #define OPCODE_ETH_TX_CREATE 7
203 #define OPCODE_ETH_RX_CREATE 8
204 #define OPCODE_ETH_TX_DESTROY 9
205 #define OPCODE_ETH_RX_DESTROY 10
206 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
207 #define OPCODE_ETH_GET_PPORT_STATS 18
208
209 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
210 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
211 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
212
213 struct be_cmd_req_hdr {
214 u8 opcode; /* dword 0 */
215 u8 subsystem; /* dword 0 */
216 u8 port_number; /* dword 0 */
217 u8 domain; /* dword 0 */
218 u32 timeout; /* dword 1 */
219 u32 request_length; /* dword 2 */
220 u8 version; /* dword 3 */
221 u8 rsvd[3]; /* dword 3 */
222 };
223
224 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
225 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
226 struct be_cmd_resp_hdr {
227 u32 info; /* dword 0 */
228 u32 status; /* dword 1 */
229 u32 response_length; /* dword 2 */
230 u32 actual_resp_len; /* dword 3 */
231 };
232
233 struct phys_addr {
234 u32 lo;
235 u32 hi;
236 };
237
238 /**************************
239 * BE Command definitions *
240 **************************/
241
242 /* Pseudo amap definition in which each bit of the actual structure is defined
243 * as a byte: used to calculate offset/shift/mask of each field */
244 struct amap_eq_context {
245 u8 cidx[13]; /* dword 0*/
246 u8 rsvd0[3]; /* dword 0*/
247 u8 epidx[13]; /* dword 0*/
248 u8 valid; /* dword 0*/
249 u8 rsvd1; /* dword 0*/
250 u8 size; /* dword 0*/
251 u8 pidx[13]; /* dword 1*/
252 u8 rsvd2[3]; /* dword 1*/
253 u8 pd[10]; /* dword 1*/
254 u8 count[3]; /* dword 1*/
255 u8 solevent; /* dword 1*/
256 u8 stalled; /* dword 1*/
257 u8 armed; /* dword 1*/
258 u8 rsvd3[4]; /* dword 2*/
259 u8 func[8]; /* dword 2*/
260 u8 rsvd4; /* dword 2*/
261 u8 delaymult[10]; /* dword 2*/
262 u8 rsvd5[2]; /* dword 2*/
263 u8 phase[2]; /* dword 2*/
264 u8 nodelay; /* dword 2*/
265 u8 rsvd6[4]; /* dword 2*/
266 u8 rsvd7[32]; /* dword 3*/
267 } __packed;
268
269 struct be_cmd_req_eq_create {
270 struct be_cmd_req_hdr hdr;
271 u16 num_pages; /* sword */
272 u16 rsvd0; /* sword */
273 u8 context[sizeof(struct amap_eq_context) / 8];
274 struct phys_addr pages[8];
275 } __packed;
276
277 struct be_cmd_resp_eq_create {
278 struct be_cmd_resp_hdr resp_hdr;
279 u16 eq_id; /* sword */
280 u16 rsvd0; /* sword */
281 } __packed;
282
283 /******************** Mac query ***************************/
284 enum {
285 MAC_ADDRESS_TYPE_STORAGE = 0x0,
286 MAC_ADDRESS_TYPE_NETWORK = 0x1,
287 MAC_ADDRESS_TYPE_PD = 0x2,
288 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
289 };
290
291 struct mac_addr {
292 u16 size_of_struct;
293 u8 addr[ETH_ALEN];
294 } __packed;
295
296 struct be_cmd_req_mac_query {
297 struct be_cmd_req_hdr hdr;
298 u8 type;
299 u8 permanent;
300 u16 if_id;
301 } __packed;
302
303 struct be_cmd_resp_mac_query {
304 struct be_cmd_resp_hdr hdr;
305 struct mac_addr mac;
306 };
307
308 /******************** PMac Add ***************************/
309 struct be_cmd_req_pmac_add {
310 struct be_cmd_req_hdr hdr;
311 u32 if_id;
312 u8 mac_address[ETH_ALEN];
313 u8 rsvd0[2];
314 } __packed;
315
316 struct be_cmd_resp_pmac_add {
317 struct be_cmd_resp_hdr hdr;
318 u32 pmac_id;
319 };
320
321 /******************** PMac Del ***************************/
322 struct be_cmd_req_pmac_del {
323 struct be_cmd_req_hdr hdr;
324 u32 if_id;
325 u32 pmac_id;
326 };
327
328 /******************** Create CQ ***************************/
329 /* Pseudo amap definition in which each bit of the actual structure is defined
330 * as a byte: used to calculate offset/shift/mask of each field */
331 struct amap_cq_context_be {
332 u8 cidx[11]; /* dword 0*/
333 u8 rsvd0; /* dword 0*/
334 u8 coalescwm[2]; /* dword 0*/
335 u8 nodelay; /* dword 0*/
336 u8 epidx[11]; /* dword 0*/
337 u8 rsvd1; /* dword 0*/
338 u8 count[2]; /* dword 0*/
339 u8 valid; /* dword 0*/
340 u8 solevent; /* dword 0*/
341 u8 eventable; /* dword 0*/
342 u8 pidx[11]; /* dword 1*/
343 u8 rsvd2; /* dword 1*/
344 u8 pd[10]; /* dword 1*/
345 u8 eqid[8]; /* dword 1*/
346 u8 stalled; /* dword 1*/
347 u8 armed; /* dword 1*/
348 u8 rsvd3[4]; /* dword 2*/
349 u8 func[8]; /* dword 2*/
350 u8 rsvd4[20]; /* dword 2*/
351 u8 rsvd5[32]; /* dword 3*/
352 } __packed;
353
354 struct amap_cq_context_lancer {
355 u8 rsvd0[12]; /* dword 0*/
356 u8 coalescwm[2]; /* dword 0*/
357 u8 nodelay; /* dword 0*/
358 u8 rsvd1[12]; /* dword 0*/
359 u8 count[2]; /* dword 0*/
360 u8 valid; /* dword 0*/
361 u8 rsvd2; /* dword 0*/
362 u8 eventable; /* dword 0*/
363 u8 eqid[16]; /* dword 1*/
364 u8 rsvd3[15]; /* dword 1*/
365 u8 armed; /* dword 1*/
366 u8 rsvd4[32]; /* dword 2*/
367 u8 rsvd5[32]; /* dword 3*/
368 } __packed;
369
370 struct be_cmd_req_cq_create {
371 struct be_cmd_req_hdr hdr;
372 u16 num_pages;
373 u8 page_size;
374 u8 rsvd0;
375 u8 context[sizeof(struct amap_cq_context_be) / 8];
376 struct phys_addr pages[8];
377 } __packed;
378
379
380 struct be_cmd_resp_cq_create {
381 struct be_cmd_resp_hdr hdr;
382 u16 cq_id;
383 u16 rsvd0;
384 } __packed;
385
386 struct be_cmd_req_get_fat {
387 struct be_cmd_req_hdr hdr;
388 u32 fat_operation;
389 u32 read_log_offset;
390 u32 read_log_length;
391 u32 data_buffer_size;
392 u32 data_buffer[1];
393 } __packed;
394
395 struct be_cmd_resp_get_fat {
396 struct be_cmd_resp_hdr hdr;
397 u32 log_size;
398 u32 read_log_length;
399 u32 rsvd[2];
400 u32 data_buffer[1];
401 } __packed;
402
403
404 /******************** Create MCCQ ***************************/
405 /* Pseudo amap definition in which each bit of the actual structure is defined
406 * as a byte: used to calculate offset/shift/mask of each field */
407 struct amap_mcc_context_be {
408 u8 con_index[14];
409 u8 rsvd0[2];
410 u8 ring_size[4];
411 u8 fetch_wrb;
412 u8 fetch_r2t;
413 u8 cq_id[10];
414 u8 prod_index[14];
415 u8 fid[8];
416 u8 pdid[9];
417 u8 valid;
418 u8 rsvd1[32];
419 u8 rsvd2[32];
420 } __packed;
421
422 struct amap_mcc_context_lancer {
423 u8 async_cq_id[16];
424 u8 ring_size[4];
425 u8 rsvd0[12];
426 u8 rsvd1[31];
427 u8 valid;
428 u8 async_cq_valid[1];
429 u8 rsvd2[31];
430 u8 rsvd3[32];
431 } __packed;
432
433 struct be_cmd_req_mcc_create {
434 struct be_cmd_req_hdr hdr;
435 u16 num_pages;
436 u16 cq_id;
437 u32 async_event_bitmap[1];
438 u8 context[sizeof(struct amap_mcc_context_be) / 8];
439 struct phys_addr pages[8];
440 } __packed;
441
442 struct be_cmd_resp_mcc_create {
443 struct be_cmd_resp_hdr hdr;
444 u16 id;
445 u16 rsvd0;
446 } __packed;
447
448 /******************** Create TxQ ***************************/
449 #define BE_ETH_TX_RING_TYPE_STANDARD 2
450 #define BE_ULP1_NUM 1
451
452 /* Pseudo amap definition in which each bit of the actual structure is defined
453 * as a byte: used to calculate offset/shift/mask of each field */
454 struct amap_tx_context {
455 u8 if_id[16]; /* dword 0 */
456 u8 tx_ring_size[4]; /* dword 0 */
457 u8 rsvd1[26]; /* dword 0 */
458 u8 pci_func_id[8]; /* dword 1 */
459 u8 rsvd2[9]; /* dword 1 */
460 u8 ctx_valid; /* dword 1 */
461 u8 cq_id_send[16]; /* dword 2 */
462 u8 rsvd3[16]; /* dword 2 */
463 u8 rsvd4[32]; /* dword 3 */
464 u8 rsvd5[32]; /* dword 4 */
465 u8 rsvd6[32]; /* dword 5 */
466 u8 rsvd7[32]; /* dword 6 */
467 u8 rsvd8[32]; /* dword 7 */
468 u8 rsvd9[32]; /* dword 8 */
469 u8 rsvd10[32]; /* dword 9 */
470 u8 rsvd11[32]; /* dword 10 */
471 u8 rsvd12[32]; /* dword 11 */
472 u8 rsvd13[32]; /* dword 12 */
473 u8 rsvd14[32]; /* dword 13 */
474 u8 rsvd15[32]; /* dword 14 */
475 u8 rsvd16[32]; /* dword 15 */
476 } __packed;
477
478 struct be_cmd_req_eth_tx_create {
479 struct be_cmd_req_hdr hdr;
480 u8 num_pages;
481 u8 ulp_num;
482 u8 type;
483 u8 bound_port;
484 u8 context[sizeof(struct amap_tx_context) / 8];
485 struct phys_addr pages[8];
486 } __packed;
487
488 struct be_cmd_resp_eth_tx_create {
489 struct be_cmd_resp_hdr hdr;
490 u16 cid;
491 u16 rsvd0;
492 } __packed;
493
494 /******************** Create RxQ ***************************/
495 struct be_cmd_req_eth_rx_create {
496 struct be_cmd_req_hdr hdr;
497 u16 cq_id;
498 u8 frag_size;
499 u8 num_pages;
500 struct phys_addr pages[2];
501 u32 interface_id;
502 u16 max_frame_size;
503 u16 rsvd0;
504 u32 rss_queue;
505 } __packed;
506
507 struct be_cmd_resp_eth_rx_create {
508 struct be_cmd_resp_hdr hdr;
509 u16 id;
510 u8 rss_id;
511 u8 rsvd0;
512 } __packed;
513
514 /******************** Q Destroy ***************************/
515 /* Type of Queue to be destroyed */
516 enum {
517 QTYPE_EQ = 1,
518 QTYPE_CQ,
519 QTYPE_TXQ,
520 QTYPE_RXQ,
521 QTYPE_MCCQ
522 };
523
524 struct be_cmd_req_q_destroy {
525 struct be_cmd_req_hdr hdr;
526 u16 id;
527 u16 bypass_flush; /* valid only for rx q destroy */
528 } __packed;
529
530 /************ I/f Create (it's actually I/f Config Create)**********/
531
532 /* Capability flags for the i/f */
533 enum be_if_flags {
534 BE_IF_FLAGS_RSS = 0x4,
535 BE_IF_FLAGS_PROMISCUOUS = 0x8,
536 BE_IF_FLAGS_BROADCAST = 0x10,
537 BE_IF_FLAGS_UNTAGGED = 0x20,
538 BE_IF_FLAGS_ULP = 0x40,
539 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
540 BE_IF_FLAGS_VLAN = 0x100,
541 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
542 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
543 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
544 BE_IF_FLAGS_MULTICAST = 0x1000
545 };
546
547 /* An RX interface is an object with one or more MAC addresses and
548 * filtering capabilities. */
549 struct be_cmd_req_if_create {
550 struct be_cmd_req_hdr hdr;
551 u32 version; /* ignore currently */
552 u32 capability_flags;
553 u32 enable_flags;
554 u8 mac_addr[ETH_ALEN];
555 u8 rsvd0;
556 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
557 u32 vlan_tag; /* not used currently */
558 } __packed;
559
560 struct be_cmd_resp_if_create {
561 struct be_cmd_resp_hdr hdr;
562 u32 interface_id;
563 u32 pmac_id;
564 };
565
566 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
567 struct be_cmd_req_if_destroy {
568 struct be_cmd_req_hdr hdr;
569 u32 interface_id;
570 };
571
572 /*************** HW Stats Get **********************************/
573 struct be_port_rxf_stats_v0 {
574 u32 rx_bytes_lsd; /* dword 0*/
575 u32 rx_bytes_msd; /* dword 1*/
576 u32 rx_total_frames; /* dword 2*/
577 u32 rx_unicast_frames; /* dword 3*/
578 u32 rx_multicast_frames; /* dword 4*/
579 u32 rx_broadcast_frames; /* dword 5*/
580 u32 rx_crc_errors; /* dword 6*/
581 u32 rx_alignment_symbol_errors; /* dword 7*/
582 u32 rx_pause_frames; /* dword 8*/
583 u32 rx_control_frames; /* dword 9*/
584 u32 rx_in_range_errors; /* dword 10*/
585 u32 rx_out_range_errors; /* dword 11*/
586 u32 rx_frame_too_long; /* dword 12*/
587 u32 rx_address_match_errors; /* dword 13*/
588 u32 rx_vlan_mismatch; /* dword 14*/
589 u32 rx_dropped_too_small; /* dword 15*/
590 u32 rx_dropped_too_short; /* dword 16*/
591 u32 rx_dropped_header_too_small; /* dword 17*/
592 u32 rx_dropped_tcp_length; /* dword 18*/
593 u32 rx_dropped_runt; /* dword 19*/
594 u32 rx_64_byte_packets; /* dword 20*/
595 u32 rx_65_127_byte_packets; /* dword 21*/
596 u32 rx_128_256_byte_packets; /* dword 22*/
597 u32 rx_256_511_byte_packets; /* dword 23*/
598 u32 rx_512_1023_byte_packets; /* dword 24*/
599 u32 rx_1024_1518_byte_packets; /* dword 25*/
600 u32 rx_1519_2047_byte_packets; /* dword 26*/
601 u32 rx_2048_4095_byte_packets; /* dword 27*/
602 u32 rx_4096_8191_byte_packets; /* dword 28*/
603 u32 rx_8192_9216_byte_packets; /* dword 29*/
604 u32 rx_ip_checksum_errs; /* dword 30*/
605 u32 rx_tcp_checksum_errs; /* dword 31*/
606 u32 rx_udp_checksum_errs; /* dword 32*/
607 u32 rx_non_rss_packets; /* dword 33*/
608 u32 rx_ipv4_packets; /* dword 34*/
609 u32 rx_ipv6_packets; /* dword 35*/
610 u32 rx_ipv4_bytes_lsd; /* dword 36*/
611 u32 rx_ipv4_bytes_msd; /* dword 37*/
612 u32 rx_ipv6_bytes_lsd; /* dword 38*/
613 u32 rx_ipv6_bytes_msd; /* dword 39*/
614 u32 rx_chute1_packets; /* dword 40*/
615 u32 rx_chute2_packets; /* dword 41*/
616 u32 rx_chute3_packets; /* dword 42*/
617 u32 rx_management_packets; /* dword 43*/
618 u32 rx_switched_unicast_packets; /* dword 44*/
619 u32 rx_switched_multicast_packets; /* dword 45*/
620 u32 rx_switched_broadcast_packets; /* dword 46*/
621 u32 tx_bytes_lsd; /* dword 47*/
622 u32 tx_bytes_msd; /* dword 48*/
623 u32 tx_unicastframes; /* dword 49*/
624 u32 tx_multicastframes; /* dword 50*/
625 u32 tx_broadcastframes; /* dword 51*/
626 u32 tx_pauseframes; /* dword 52*/
627 u32 tx_controlframes; /* dword 53*/
628 u32 tx_64_byte_packets; /* dword 54*/
629 u32 tx_65_127_byte_packets; /* dword 55*/
630 u32 tx_128_256_byte_packets; /* dword 56*/
631 u32 tx_256_511_byte_packets; /* dword 57*/
632 u32 tx_512_1023_byte_packets; /* dword 58*/
633 u32 tx_1024_1518_byte_packets; /* dword 59*/
634 u32 tx_1519_2047_byte_packets; /* dword 60*/
635 u32 tx_2048_4095_byte_packets; /* dword 61*/
636 u32 tx_4096_8191_byte_packets; /* dword 62*/
637 u32 tx_8192_9216_byte_packets; /* dword 63*/
638 u32 rx_fifo_overflow; /* dword 64*/
639 u32 rx_input_fifo_overflow; /* dword 65*/
640 };
641
642 struct be_rxf_stats_v0 {
643 struct be_port_rxf_stats_v0 port[2];
644 u32 rx_drops_no_pbuf; /* dword 132*/
645 u32 rx_drops_no_txpb; /* dword 133*/
646 u32 rx_drops_no_erx_descr; /* dword 134*/
647 u32 rx_drops_no_tpre_descr; /* dword 135*/
648 u32 management_rx_port_packets; /* dword 136*/
649 u32 management_rx_port_bytes; /* dword 137*/
650 u32 management_rx_port_pause_frames; /* dword 138*/
651 u32 management_rx_port_errors; /* dword 139*/
652 u32 management_tx_port_packets; /* dword 140*/
653 u32 management_tx_port_bytes; /* dword 141*/
654 u32 management_tx_port_pause; /* dword 142*/
655 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
656 u32 rx_drops_too_many_frags; /* dword 144*/
657 u32 rx_drops_invalid_ring; /* dword 145*/
658 u32 forwarded_packets; /* dword 146*/
659 u32 rx_drops_mtu; /* dword 147*/
660 u32 rsvd0[7];
661 u32 port0_jabber_events;
662 u32 port1_jabber_events;
663 u32 rsvd1[6];
664 };
665
666 struct be_erx_stats_v0 {
667 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
668 u32 rsvd[4];
669 };
670
671 struct be_pmem_stats {
672 u32 eth_red_drops;
673 u32 rsvd[5];
674 };
675
676 struct be_hw_stats_v0 {
677 struct be_rxf_stats_v0 rxf;
678 u32 rsvd[48];
679 struct be_erx_stats_v0 erx;
680 struct be_pmem_stats pmem;
681 };
682
683 struct be_cmd_req_get_stats_v0 {
684 struct be_cmd_req_hdr hdr;
685 u8 rsvd[sizeof(struct be_hw_stats_v0)];
686 };
687
688 struct be_cmd_resp_get_stats_v0 {
689 struct be_cmd_resp_hdr hdr;
690 struct be_hw_stats_v0 hw_stats;
691 };
692
693 #define make_64bit_val(hi_32, lo_32) (((u64)hi_32<<32) | lo_32)
694 struct lancer_cmd_pport_stats {
695 u32 tx_packets_lo;
696 u32 tx_packets_hi;
697 u32 tx_unicast_packets_lo;
698 u32 tx_unicast_packets_hi;
699 u32 tx_multicast_packets_lo;
700 u32 tx_multicast_packets_hi;
701 u32 tx_broadcast_packets_lo;
702 u32 tx_broadcast_packets_hi;
703 u32 tx_bytes_lo;
704 u32 tx_bytes_hi;
705 u32 tx_unicast_bytes_lo;
706 u32 tx_unicast_bytes_hi;
707 u32 tx_multicast_bytes_lo;
708 u32 tx_multicast_bytes_hi;
709 u32 tx_broadcast_bytes_lo;
710 u32 tx_broadcast_bytes_hi;
711 u32 tx_discards_lo;
712 u32 tx_discards_hi;
713 u32 tx_errors_lo;
714 u32 tx_errors_hi;
715 u32 tx_pause_frames_lo;
716 u32 tx_pause_frames_hi;
717 u32 tx_pause_on_frames_lo;
718 u32 tx_pause_on_frames_hi;
719 u32 tx_pause_off_frames_lo;
720 u32 tx_pause_off_frames_hi;
721 u32 tx_internal_mac_errors_lo;
722 u32 tx_internal_mac_errors_hi;
723 u32 tx_control_frames_lo;
724 u32 tx_control_frames_hi;
725 u32 tx_packets_64_bytes_lo;
726 u32 tx_packets_64_bytes_hi;
727 u32 tx_packets_65_to_127_bytes_lo;
728 u32 tx_packets_65_to_127_bytes_hi;
729 u32 tx_packets_128_to_255_bytes_lo;
730 u32 tx_packets_128_to_255_bytes_hi;
731 u32 tx_packets_256_to_511_bytes_lo;
732 u32 tx_packets_256_to_511_bytes_hi;
733 u32 tx_packets_512_to_1023_bytes_lo;
734 u32 tx_packets_512_to_1023_bytes_hi;
735 u32 tx_packets_1024_to_1518_bytes_lo;
736 u32 tx_packets_1024_to_1518_bytes_hi;
737 u32 tx_packets_1519_to_2047_bytes_lo;
738 u32 tx_packets_1519_to_2047_bytes_hi;
739 u32 tx_packets_2048_to_4095_bytes_lo;
740 u32 tx_packets_2048_to_4095_bytes_hi;
741 u32 tx_packets_4096_to_8191_bytes_lo;
742 u32 tx_packets_4096_to_8191_bytes_hi;
743 u32 tx_packets_8192_to_9216_bytes_lo;
744 u32 tx_packets_8192_to_9216_bytes_hi;
745 u32 tx_lso_packets_lo;
746 u32 tx_lso_packets_hi;
747 u32 rx_packets_lo;
748 u32 rx_packets_hi;
749 u32 rx_unicast_packets_lo;
750 u32 rx_unicast_packets_hi;
751 u32 rx_multicast_packets_lo;
752 u32 rx_multicast_packets_hi;
753 u32 rx_broadcast_packets_lo;
754 u32 rx_broadcast_packets_hi;
755 u32 rx_bytes_lo;
756 u32 rx_bytes_hi;
757 u32 rx_unicast_bytes_lo;
758 u32 rx_unicast_bytes_hi;
759 u32 rx_multicast_bytes_lo;
760 u32 rx_multicast_bytes_hi;
761 u32 rx_broadcast_bytes_lo;
762 u32 rx_broadcast_bytes_hi;
763 u32 rx_unknown_protos;
764 u32 rsvd_69; /* Word 69 is reserved */
765 u32 rx_discards_lo;
766 u32 rx_discards_hi;
767 u32 rx_errors_lo;
768 u32 rx_errors_hi;
769 u32 rx_crc_errors_lo;
770 u32 rx_crc_errors_hi;
771 u32 rx_alignment_errors_lo;
772 u32 rx_alignment_errors_hi;
773 u32 rx_symbol_errors_lo;
774 u32 rx_symbol_errors_hi;
775 u32 rx_pause_frames_lo;
776 u32 rx_pause_frames_hi;
777 u32 rx_pause_on_frames_lo;
778 u32 rx_pause_on_frames_hi;
779 u32 rx_pause_off_frames_lo;
780 u32 rx_pause_off_frames_hi;
781 u32 rx_frames_too_long_lo;
782 u32 rx_frames_too_long_hi;
783 u32 rx_internal_mac_errors_lo;
784 u32 rx_internal_mac_errors_hi;
785 u32 rx_undersize_packets;
786 u32 rx_oversize_packets;
787 u32 rx_fragment_packets;
788 u32 rx_jabbers;
789 u32 rx_control_frames_lo;
790 u32 rx_control_frames_hi;
791 u32 rx_control_frames_unknown_opcode_lo;
792 u32 rx_control_frames_unknown_opcode_hi;
793 u32 rx_in_range_errors;
794 u32 rx_out_of_range_errors;
795 u32 rx_address_match_errors;
796 u32 rx_vlan_mismatch_errors;
797 u32 rx_dropped_too_small;
798 u32 rx_dropped_too_short;
799 u32 rx_dropped_header_too_small;
800 u32 rx_dropped_invalid_tcp_length;
801 u32 rx_dropped_runt;
802 u32 rx_ip_checksum_errors;
803 u32 rx_tcp_checksum_errors;
804 u32 rx_udp_checksum_errors;
805 u32 rx_non_rss_packets;
806 u32 rsvd_111;
807 u32 rx_ipv4_packets_lo;
808 u32 rx_ipv4_packets_hi;
809 u32 rx_ipv6_packets_lo;
810 u32 rx_ipv6_packets_hi;
811 u32 rx_ipv4_bytes_lo;
812 u32 rx_ipv4_bytes_hi;
813 u32 rx_ipv6_bytes_lo;
814 u32 rx_ipv6_bytes_hi;
815 u32 rx_nic_packets_lo;
816 u32 rx_nic_packets_hi;
817 u32 rx_tcp_packets_lo;
818 u32 rx_tcp_packets_hi;
819 u32 rx_iscsi_packets_lo;
820 u32 rx_iscsi_packets_hi;
821 u32 rx_management_packets_lo;
822 u32 rx_management_packets_hi;
823 u32 rx_switched_unicast_packets_lo;
824 u32 rx_switched_unicast_packets_hi;
825 u32 rx_switched_multicast_packets_lo;
826 u32 rx_switched_multicast_packets_hi;
827 u32 rx_switched_broadcast_packets_lo;
828 u32 rx_switched_broadcast_packets_hi;
829 u32 num_forwards_lo;
830 u32 num_forwards_hi;
831 u32 rx_fifo_overflow;
832 u32 rx_input_fifo_overflow;
833 u32 rx_drops_too_many_frags_lo;
834 u32 rx_drops_too_many_frags_hi;
835 u32 rx_drops_invalid_queue;
836 u32 rsvd_141;
837 u32 rx_drops_mtu_lo;
838 u32 rx_drops_mtu_hi;
839 u32 rx_packets_64_bytes_lo;
840 u32 rx_packets_64_bytes_hi;
841 u32 rx_packets_65_to_127_bytes_lo;
842 u32 rx_packets_65_to_127_bytes_hi;
843 u32 rx_packets_128_to_255_bytes_lo;
844 u32 rx_packets_128_to_255_bytes_hi;
845 u32 rx_packets_256_to_511_bytes_lo;
846 u32 rx_packets_256_to_511_bytes_hi;
847 u32 rx_packets_512_to_1023_bytes_lo;
848 u32 rx_packets_512_to_1023_bytes_hi;
849 u32 rx_packets_1024_to_1518_bytes_lo;
850 u32 rx_packets_1024_to_1518_bytes_hi;
851 u32 rx_packets_1519_to_2047_bytes_lo;
852 u32 rx_packets_1519_to_2047_bytes_hi;
853 u32 rx_packets_2048_to_4095_bytes_lo;
854 u32 rx_packets_2048_to_4095_bytes_hi;
855 u32 rx_packets_4096_to_8191_bytes_lo;
856 u32 rx_packets_4096_to_8191_bytes_hi;
857 u32 rx_packets_8192_to_9216_bytes_lo;
858 u32 rx_packets_8192_to_9216_bytes_hi;
859 };
860
861 struct pport_stats_params {
862 u16 pport_num;
863 u8 rsvd;
864 u8 reset_stats;
865 };
866
867 struct lancer_cmd_req_pport_stats {
868 struct be_cmd_req_hdr hdr;
869 union {
870 struct pport_stats_params params;
871 u8 rsvd[sizeof(struct lancer_cmd_pport_stats)];
872 } cmd_params;
873 };
874
875 struct lancer_cmd_resp_pport_stats {
876 struct be_cmd_resp_hdr hdr;
877 struct lancer_cmd_pport_stats pport_stats;
878 };
879
880 static inline struct lancer_cmd_pport_stats*
881 pport_stats_from_cmd(struct be_adapter *adapter)
882 {
883 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
884 return &cmd->pport_stats;
885 }
886
887 struct be_cmd_req_get_cntl_addnl_attribs {
888 struct be_cmd_req_hdr hdr;
889 u8 rsvd[8];
890 };
891
892 struct be_cmd_resp_get_cntl_addnl_attribs {
893 struct be_cmd_resp_hdr hdr;
894 u16 ipl_file_number;
895 u8 ipl_file_version;
896 u8 rsvd0;
897 u8 on_die_temperature; /* in degrees centigrade*/
898 u8 rsvd1[3];
899 };
900
901 struct be_cmd_req_vlan_config {
902 struct be_cmd_req_hdr hdr;
903 u8 interface_id;
904 u8 promiscuous;
905 u8 untagged;
906 u8 num_vlan;
907 u16 normal_vlan[64];
908 } __packed;
909
910 /******************** Multicast MAC Config *******************/
911 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */
912 struct macaddr {
913 u8 byte[ETH_ALEN];
914 };
915
916 struct be_cmd_req_mcast_mac_config {
917 struct be_cmd_req_hdr hdr;
918 u16 num_mac;
919 u8 promiscuous;
920 u8 interface_id;
921 struct macaddr mac[BE_MAX_MC];
922 } __packed;
923
924 /******************* RX FILTER ******************************/
925 struct be_cmd_req_rx_filter {
926 struct be_cmd_req_hdr hdr;
927 u32 global_flags_mask;
928 u32 global_flags;
929 u32 if_flags_mask;
930 u32 if_flags;
931 u32 if_id;
932 u32 multicast_num;
933 struct macaddr mac[BE_MAX_MC];
934 };
935
936
937 /******************** Link Status Query *******************/
938 struct be_cmd_req_link_status {
939 struct be_cmd_req_hdr hdr;
940 u32 rsvd;
941 };
942
943 enum {
944 PHY_LINK_DUPLEX_NONE = 0x0,
945 PHY_LINK_DUPLEX_HALF = 0x1,
946 PHY_LINK_DUPLEX_FULL = 0x2
947 };
948
949 enum {
950 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
951 PHY_LINK_SPEED_10MBPS = 0x1,
952 PHY_LINK_SPEED_100MBPS = 0x2,
953 PHY_LINK_SPEED_1GBPS = 0x3,
954 PHY_LINK_SPEED_10GBPS = 0x4
955 };
956
957 struct be_cmd_resp_link_status {
958 struct be_cmd_resp_hdr hdr;
959 u8 physical_port;
960 u8 mac_duplex;
961 u8 mac_speed;
962 u8 mac_fault;
963 u8 mgmt_mac_duplex;
964 u8 mgmt_mac_speed;
965 u16 link_speed;
966 u32 rsvd0;
967 } __packed;
968
969 /******************** Port Identification ***************************/
970 /* Identifies the type of port attached to NIC */
971 struct be_cmd_req_port_type {
972 struct be_cmd_req_hdr hdr;
973 u32 page_num;
974 u32 port;
975 };
976
977 enum {
978 TR_PAGE_A0 = 0xa0,
979 TR_PAGE_A2 = 0xa2
980 };
981
982 struct be_cmd_resp_port_type {
983 struct be_cmd_resp_hdr hdr;
984 u32 page_num;
985 u32 port;
986 struct data {
987 u8 identifier;
988 u8 identifier_ext;
989 u8 connector;
990 u8 transceiver[8];
991 u8 rsvd0[3];
992 u8 length_km;
993 u8 length_hm;
994 u8 length_om1;
995 u8 length_om2;
996 u8 length_cu;
997 u8 length_cu_m;
998 u8 vendor_name[16];
999 u8 rsvd;
1000 u8 vendor_oui[3];
1001 u8 vendor_pn[16];
1002 u8 vendor_rev[4];
1003 } data;
1004 };
1005
1006 /******************** Get FW Version *******************/
1007 struct be_cmd_req_get_fw_version {
1008 struct be_cmd_req_hdr hdr;
1009 u8 rsvd0[FW_VER_LEN];
1010 u8 rsvd1[FW_VER_LEN];
1011 } __packed;
1012
1013 struct be_cmd_resp_get_fw_version {
1014 struct be_cmd_resp_hdr hdr;
1015 u8 firmware_version_string[FW_VER_LEN];
1016 u8 fw_on_flash_version_string[FW_VER_LEN];
1017 } __packed;
1018
1019 /******************** Set Flow Contrl *******************/
1020 struct be_cmd_req_set_flow_control {
1021 struct be_cmd_req_hdr hdr;
1022 u16 tx_flow_control;
1023 u16 rx_flow_control;
1024 } __packed;
1025
1026 /******************** Get Flow Contrl *******************/
1027 struct be_cmd_req_get_flow_control {
1028 struct be_cmd_req_hdr hdr;
1029 u32 rsvd;
1030 };
1031
1032 struct be_cmd_resp_get_flow_control {
1033 struct be_cmd_resp_hdr hdr;
1034 u16 tx_flow_control;
1035 u16 rx_flow_control;
1036 } __packed;
1037
1038 /******************** Modify EQ Delay *******************/
1039 struct be_cmd_req_modify_eq_delay {
1040 struct be_cmd_req_hdr hdr;
1041 u32 num_eq;
1042 struct {
1043 u32 eq_id;
1044 u32 phase;
1045 u32 delay_multiplier;
1046 } delay[8];
1047 } __packed;
1048
1049 struct be_cmd_resp_modify_eq_delay {
1050 struct be_cmd_resp_hdr hdr;
1051 u32 rsvd0;
1052 } __packed;
1053
1054 /******************** Get FW Config *******************/
1055 #define BE_FUNCTION_CAPS_RSS 0x2
1056 struct be_cmd_req_query_fw_cfg {
1057 struct be_cmd_req_hdr hdr;
1058 u32 rsvd[31];
1059 };
1060
1061 struct be_cmd_resp_query_fw_cfg {
1062 struct be_cmd_resp_hdr hdr;
1063 u32 be_config_number;
1064 u32 asic_revision;
1065 u32 phys_port;
1066 u32 function_mode;
1067 u32 rsvd[26];
1068 u32 function_caps;
1069 };
1070
1071 /******************** RSS Config *******************/
1072 /* RSS types */
1073 #define RSS_ENABLE_NONE 0x0
1074 #define RSS_ENABLE_IPV4 0x1
1075 #define RSS_ENABLE_TCP_IPV4 0x2
1076 #define RSS_ENABLE_IPV6 0x4
1077 #define RSS_ENABLE_TCP_IPV6 0x8
1078
1079 struct be_cmd_req_rss_config {
1080 struct be_cmd_req_hdr hdr;
1081 u32 if_id;
1082 u16 enable_rss;
1083 u16 cpu_table_size_log2;
1084 u32 hash[10];
1085 u8 cpu_table[128];
1086 u8 flush;
1087 u8 rsvd0[3];
1088 };
1089
1090 /******************** Port Beacon ***************************/
1091
1092 #define BEACON_STATE_ENABLED 0x1
1093 #define BEACON_STATE_DISABLED 0x0
1094
1095 struct be_cmd_req_enable_disable_beacon {
1096 struct be_cmd_req_hdr hdr;
1097 u8 port_num;
1098 u8 beacon_state;
1099 u8 beacon_duration;
1100 u8 status_duration;
1101 } __packed;
1102
1103 struct be_cmd_resp_enable_disable_beacon {
1104 struct be_cmd_resp_hdr resp_hdr;
1105 u32 rsvd0;
1106 } __packed;
1107
1108 struct be_cmd_req_get_beacon_state {
1109 struct be_cmd_req_hdr hdr;
1110 u8 port_num;
1111 u8 rsvd0;
1112 u16 rsvd1;
1113 } __packed;
1114
1115 struct be_cmd_resp_get_beacon_state {
1116 struct be_cmd_resp_hdr resp_hdr;
1117 u8 beacon_state;
1118 u8 rsvd0[3];
1119 } __packed;
1120
1121 /****************** Firmware Flash ******************/
1122 struct flashrom_params {
1123 u32 op_code;
1124 u32 op_type;
1125 u32 data_buf_size;
1126 u32 offset;
1127 u8 data_buf[4];
1128 };
1129
1130 struct be_cmd_write_flashrom {
1131 struct be_cmd_req_hdr hdr;
1132 struct flashrom_params params;
1133 };
1134
1135 /**************** Lancer Firmware Flash ************/
1136 struct amap_lancer_write_obj_context {
1137 u8 write_length[24];
1138 u8 reserved1[7];
1139 u8 eof;
1140 } __packed;
1141
1142 struct lancer_cmd_req_write_object {
1143 struct be_cmd_req_hdr hdr;
1144 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1145 u32 write_offset;
1146 u8 object_name[104];
1147 u32 descriptor_count;
1148 u32 buf_len;
1149 u32 addr_low;
1150 u32 addr_high;
1151 };
1152
1153 struct lancer_cmd_resp_write_object {
1154 u8 opcode;
1155 u8 subsystem;
1156 u8 rsvd1[2];
1157 u8 status;
1158 u8 additional_status;
1159 u8 rsvd2[2];
1160 u32 resp_len;
1161 u32 actual_resp_len;
1162 u32 actual_write_len;
1163 };
1164
1165 /************************ WOL *******************************/
1166 struct be_cmd_req_acpi_wol_magic_config{
1167 struct be_cmd_req_hdr hdr;
1168 u32 rsvd0[145];
1169 u8 magic_mac[6];
1170 u8 rsvd2[2];
1171 } __packed;
1172
1173 /********************** LoopBack test *********************/
1174 struct be_cmd_req_loopback_test {
1175 struct be_cmd_req_hdr hdr;
1176 u32 loopback_type;
1177 u32 num_pkts;
1178 u64 pattern;
1179 u32 src_port;
1180 u32 dest_port;
1181 u32 pkt_size;
1182 };
1183
1184 struct be_cmd_resp_loopback_test {
1185 struct be_cmd_resp_hdr resp_hdr;
1186 u32 status;
1187 u32 num_txfer;
1188 u32 num_rx;
1189 u32 miscomp_off;
1190 u32 ticks_compl;
1191 };
1192
1193 struct be_cmd_req_set_lmode {
1194 struct be_cmd_req_hdr hdr;
1195 u8 src_port;
1196 u8 dest_port;
1197 u8 loopback_type;
1198 u8 loopback_state;
1199 };
1200
1201 struct be_cmd_resp_set_lmode {
1202 struct be_cmd_resp_hdr resp_hdr;
1203 u8 rsvd0[4];
1204 };
1205
1206 /********************** DDR DMA test *********************/
1207 struct be_cmd_req_ddrdma_test {
1208 struct be_cmd_req_hdr hdr;
1209 u64 pattern;
1210 u32 byte_count;
1211 u32 rsvd0;
1212 u8 snd_buff[4096];
1213 u8 rsvd1[4096];
1214 };
1215
1216 struct be_cmd_resp_ddrdma_test {
1217 struct be_cmd_resp_hdr hdr;
1218 u64 pattern;
1219 u32 byte_cnt;
1220 u32 snd_err;
1221 u8 rsvd0[4096];
1222 u8 rcv_buff[4096];
1223 };
1224
1225 /*********************** SEEPROM Read ***********************/
1226
1227 #define BE_READ_SEEPROM_LEN 1024
1228 struct be_cmd_req_seeprom_read {
1229 struct be_cmd_req_hdr hdr;
1230 u8 rsvd0[BE_READ_SEEPROM_LEN];
1231 };
1232
1233 struct be_cmd_resp_seeprom_read {
1234 struct be_cmd_req_hdr hdr;
1235 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1236 };
1237
1238 enum {
1239 PHY_TYPE_CX4_10GB = 0,
1240 PHY_TYPE_XFP_10GB,
1241 PHY_TYPE_SFP_1GB,
1242 PHY_TYPE_SFP_PLUS_10GB,
1243 PHY_TYPE_KR_10GB,
1244 PHY_TYPE_KX4_10GB,
1245 PHY_TYPE_BASET_10GB,
1246 PHY_TYPE_BASET_1GB,
1247 PHY_TYPE_DISABLED = 255
1248 };
1249
1250 struct be_cmd_req_get_phy_info {
1251 struct be_cmd_req_hdr hdr;
1252 u8 rsvd0[24];
1253 };
1254 struct be_cmd_resp_get_phy_info {
1255 struct be_cmd_req_hdr hdr;
1256 u16 phy_type;
1257 u16 interface_type;
1258 u32 misc_params;
1259 u32 future_use[4];
1260 };
1261
1262 /*********************** Set QOS ***********************/
1263
1264 #define BE_QOS_BITS_NIC 1
1265
1266 struct be_cmd_req_set_qos {
1267 struct be_cmd_req_hdr hdr;
1268 u32 valid_bits;
1269 u32 max_bps_nic;
1270 u32 rsvd[7];
1271 };
1272
1273 struct be_cmd_resp_set_qos {
1274 struct be_cmd_resp_hdr hdr;
1275 u32 rsvd;
1276 };
1277
1278 /*********************** Controller Attributes ***********************/
1279 struct be_cmd_req_cntl_attribs {
1280 struct be_cmd_req_hdr hdr;
1281 };
1282
1283 struct be_cmd_resp_cntl_attribs {
1284 struct be_cmd_resp_hdr hdr;
1285 struct mgmt_controller_attrib attribs;
1286 };
1287
1288 /*********************** Set driver function ***********************/
1289 #define CAPABILITY_SW_TIMESTAMPS 2
1290 #define CAPABILITY_BE3_NATIVE_ERX_API 4
1291
1292 struct be_cmd_req_set_func_cap {
1293 struct be_cmd_req_hdr hdr;
1294 u32 valid_cap_flags;
1295 u32 cap_flags;
1296 u8 rsvd[212];
1297 };
1298
1299 struct be_cmd_resp_set_func_cap {
1300 struct be_cmd_resp_hdr hdr;
1301 u32 valid_cap_flags;
1302 u32 cap_flags;
1303 u8 rsvd[212];
1304 };
1305
1306 /*************** HW Stats Get v1 **********************************/
1307 #define BE_TXP_SW_SZ 48
1308 struct be_port_rxf_stats_v1 {
1309 u32 rsvd0[12];
1310 u32 rx_crc_errors;
1311 u32 rx_alignment_symbol_errors;
1312 u32 rx_pause_frames;
1313 u32 rx_priority_pause_frames;
1314 u32 rx_control_frames;
1315 u32 rx_in_range_errors;
1316 u32 rx_out_range_errors;
1317 u32 rx_frame_too_long;
1318 u32 rx_address_match_errors;
1319 u32 rx_dropped_too_small;
1320 u32 rx_dropped_too_short;
1321 u32 rx_dropped_header_too_small;
1322 u32 rx_dropped_tcp_length;
1323 u32 rx_dropped_runt;
1324 u32 rsvd1[10];
1325 u32 rx_ip_checksum_errs;
1326 u32 rx_tcp_checksum_errs;
1327 u32 rx_udp_checksum_errs;
1328 u32 rsvd2[7];
1329 u32 rx_switched_unicast_packets;
1330 u32 rx_switched_multicast_packets;
1331 u32 rx_switched_broadcast_packets;
1332 u32 rsvd3[3];
1333 u32 tx_pauseframes;
1334 u32 tx_priority_pauseframes;
1335 u32 tx_controlframes;
1336 u32 rsvd4[10];
1337 u32 rxpp_fifo_overflow_drop;
1338 u32 rx_input_fifo_overflow_drop;
1339 u32 pmem_fifo_overflow_drop;
1340 u32 jabber_events;
1341 u32 rsvd5[3];
1342 };
1343
1344
1345 struct be_rxf_stats_v1 {
1346 struct be_port_rxf_stats_v1 port[4];
1347 u32 rsvd0[2];
1348 u32 rx_drops_no_pbuf;
1349 u32 rx_drops_no_txpb;
1350 u32 rx_drops_no_erx_descr;
1351 u32 rx_drops_no_tpre_descr;
1352 u32 rsvd1[6];
1353 u32 rx_drops_too_many_frags;
1354 u32 rx_drops_invalid_ring;
1355 u32 forwarded_packets;
1356 u32 rx_drops_mtu;
1357 u32 rsvd2[14];
1358 };
1359
1360 struct be_erx_stats_v1 {
1361 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
1362 u32 rsvd[4];
1363 };
1364
1365 struct be_hw_stats_v1 {
1366 struct be_rxf_stats_v1 rxf;
1367 u32 rsvd0[BE_TXP_SW_SZ];
1368 struct be_erx_stats_v1 erx;
1369 struct be_pmem_stats pmem;
1370 u32 rsvd1[3];
1371 };
1372
1373 struct be_cmd_req_get_stats_v1 {
1374 struct be_cmd_req_hdr hdr;
1375 u8 rsvd[sizeof(struct be_hw_stats_v1)];
1376 };
1377
1378 struct be_cmd_resp_get_stats_v1 {
1379 struct be_cmd_resp_hdr hdr;
1380 struct be_hw_stats_v1 hw_stats;
1381 };
1382
1383 static inline void *
1384 hw_stats_from_cmd(struct be_adapter *adapter)
1385 {
1386 if (adapter->generation == BE_GEN3) {
1387 struct be_cmd_resp_get_stats_v1 *cmd = adapter->stats_cmd.va;
1388
1389 return &cmd->hw_stats;
1390 } else {
1391 struct be_cmd_resp_get_stats_v0 *cmd = adapter->stats_cmd.va;
1392
1393 return &cmd->hw_stats;
1394 }
1395 }
1396
1397 static inline void *be_port_rxf_stats_from_cmd(struct be_adapter *adapter)
1398 {
1399 if (adapter->generation == BE_GEN3) {
1400 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1401 struct be_rxf_stats_v1 *rxf_stats = &hw_stats->rxf;
1402
1403 return &rxf_stats->port[adapter->port_num];
1404 } else {
1405 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1406 struct be_rxf_stats_v0 *rxf_stats = &hw_stats->rxf;
1407
1408 return &rxf_stats->port[adapter->port_num];
1409 }
1410 }
1411
1412 static inline void *be_rxf_stats_from_cmd(struct be_adapter *adapter)
1413 {
1414 if (adapter->generation == BE_GEN3) {
1415 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1416
1417 return &hw_stats->rxf;
1418 } else {
1419 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1420
1421 return &hw_stats->rxf;
1422 }
1423 }
1424
1425 static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter)
1426 {
1427 if (adapter->generation == BE_GEN3) {
1428 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1429
1430 return &hw_stats->erx;
1431 } else {
1432 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1433
1434 return &hw_stats->erx;
1435 }
1436 }
1437
1438 static inline void *be_pmem_stats_from_cmd(struct be_adapter *adapter)
1439 {
1440 if (adapter->generation == BE_GEN3) {
1441 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1442
1443 return &hw_stats->pmem;
1444 } else {
1445 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1446
1447 return &hw_stats->pmem;
1448 }
1449 }
1450
1451 extern int be_pci_fnum_get(struct be_adapter *adapter);
1452 extern int be_cmd_POST(struct be_adapter *adapter);
1453 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1454 u8 type, bool permanent, u32 if_handle);
1455 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1456 u32 if_id, u32 *pmac_id, u32 domain);
1457 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1458 u32 pmac_id, u32 domain);
1459 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1460 u32 en_flags, u8 *mac, bool pmac_invalid,
1461 u32 *if_handle, u32 *pmac_id, u32 domain);
1462 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle,
1463 u32 domain);
1464 extern int be_cmd_eq_create(struct be_adapter *adapter,
1465 struct be_queue_info *eq, int eq_delay);
1466 extern int be_cmd_cq_create(struct be_adapter *adapter,
1467 struct be_queue_info *cq, struct be_queue_info *eq,
1468 bool sol_evts, bool no_delay,
1469 int num_cqe_dma_coalesce);
1470 extern int be_cmd_mccq_create(struct be_adapter *adapter,
1471 struct be_queue_info *mccq,
1472 struct be_queue_info *cq);
1473 extern int be_cmd_txq_create(struct be_adapter *adapter,
1474 struct be_queue_info *txq,
1475 struct be_queue_info *cq);
1476 extern int be_cmd_rxq_create(struct be_adapter *adapter,
1477 struct be_queue_info *rxq, u16 cq_id,
1478 u16 frag_size, u16 max_frame_size, u32 if_id,
1479 u32 rss, u8 *rss_id);
1480 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1481 int type);
1482 extern int be_cmd_link_status_query(struct be_adapter *adapter,
1483 bool *link_up, u8 *mac_speed, u16 *link_speed, u32 dom);
1484 extern int be_cmd_reset(struct be_adapter *adapter);
1485 extern int be_cmd_get_stats(struct be_adapter *adapter,
1486 struct be_dma_mem *nonemb_cmd);
1487 extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1488 struct be_dma_mem *nonemb_cmd);
1489 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
1490
1491 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1492 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
1493 u16 *vtag_array, u32 num, bool untagged,
1494 bool promiscuous);
1495 extern int be_cmd_promiscuous_config(struct be_adapter *adapter, bool en);
1496 extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1497 struct net_device *netdev, struct be_dma_mem *mem);
1498 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
1499 u32 tx_fc, u32 rx_fc);
1500 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
1501 u32 *tx_fc, u32 *rx_fc);
1502 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
1503 u32 *port_num, u32 *function_mode, u32 *function_caps);
1504 extern int be_cmd_reset_function(struct be_adapter *adapter);
1505 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1506 u16 table_size);
1507 extern int be_process_mcc(struct be_adapter *adapter, int *status);
1508 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1509 u8 port_num, u8 beacon, u8 status, u8 state);
1510 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1511 u8 port_num, u32 *state);
1512 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1513 struct be_dma_mem *cmd, u32 flash_oper,
1514 u32 flash_opcode, u32 buf_size);
1515 extern int lancer_cmd_write_object(struct be_adapter *adapter,
1516 struct be_dma_mem *cmd,
1517 u32 data_size, u32 data_offset,
1518 const char *obj_name,
1519 u32 *data_written, u8 *addn_status);
1520 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1521 int offset);
1522 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1523 struct be_dma_mem *nonemb_cmd);
1524 extern int be_cmd_fw_init(struct be_adapter *adapter);
1525 extern int be_cmd_fw_clean(struct be_adapter *adapter);
1526 extern void be_async_mcc_enable(struct be_adapter *adapter);
1527 extern void be_async_mcc_disable(struct be_adapter *adapter);
1528 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1529 u32 loopback_type, u32 pkt_size,
1530 u32 num_pkts, u64 pattern);
1531 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1532 u32 byte_cnt, struct be_dma_mem *cmd);
1533 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1534 struct be_dma_mem *nonemb_cmd);
1535 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1536 u8 loopback_type, u8 enable);
1537 extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1538 struct be_dma_mem *cmd);
1539 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
1540 extern void be_detect_dump_ue(struct be_adapter *adapter);
1541 extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
1542 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
1543 extern int be_cmd_check_native_mode(struct be_adapter *adapter);
1544 extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
1545 extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
1546
kernel-based virtual machine