drivers/media/dvb/frontends/ves1820.c

   1 /*
   2     VES1820  - Single Chip Cable Channel Receiver driver module
   3
   4     Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21 #include <linux/config.h>
  22 #include <linux/delay.h>
  23 #include <linux/errno.h>
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/string.h>
  28 #include <linux/slab.h>
  29 #include <asm/div64.h>
  30
  31 #include "dvb_frontend.h"
  32 #include "ves1820.h"
  33
  34
  35
  36 struct ves1820_state {
  37         struct i2c_adapter* i2c;
  38         struct dvb_frontend_ops ops;
  39         /* configuration settings */
  40         const struct ves1820_config* config;
  41         struct dvb_frontend frontend;
  42
  43         /* private demodulator data */
  44         u8 reg0;
  45         u8 pwm;
  46 };
  47
  48
  49 static int verbose;
  50
  51 static u8 ves1820_inittab[] = {
  52         0x69, 0x6A, 0x93, 0x12, 0x12, 0x46, 0x26, 0x1A,
  53         0x43, 0x6A, 0xAA, 0xAA, 0x1E, 0x85, 0x43, 0x20,
  54         0xE0, 0x00, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00,
  55         0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
  56         0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  57         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  58         0x00, 0x00, 0x00, 0x00, 0x40
  59 };
  60
  61 static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)
  62 {
  63         u8 buf[] = { 0x00, reg, data };
  64         struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 };
  65         int ret;
  66
  67         ret = i2c_transfer(state->i2c, &msg, 1);
  68
  69         if (ret != 1)
  70                 printk("ves1820: %s(): writereg error (reg == 0x%02x,"
  71                         "val == 0x%02x, ret == %i)\n", __FUNCTION__, reg, data, ret);
  72
  73         msleep(10);
  74         return (ret != 1) ? -EREMOTEIO : 0;
  75 }
  76
  77 static u8 ves1820_readreg(struct ves1820_state *state, u8 reg)
  78 {
  79         u8 b0[] = { 0x00, reg };
  80         u8 b1[] = { 0 };
  81         struct i2c_msg msg[] = {
  82                 {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2},
  83                 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
  84         };
  85         int ret;
  86
  87         ret = i2c_transfer(state->i2c, msg, 2);
  88
  89         if (ret != 2)
  90                 printk("ves1820: %s(): readreg error (reg == 0x%02x,"
  91                 "ret == %i)\n", __FUNCTION__, reg, ret);
  92
  93         return b1[0];
  94 }
  95
  96 static int ves1820_setup_reg0(struct ves1820_state *state, u8 reg0, fe_spectral_inversion_t inversion)
  97 {
  98         reg0 |= state->reg0 & 0x62;
  99
 100         if (INVERSION_ON == inversion) {
 101                 if (!state->config->invert) reg0 |= 0x20;
 102                 else reg0 &= ~0x20;
 103         } else if (INVERSION_OFF == inversion) {
 104                 if (!state->config->invert) reg0 &= ~0x20;
 105                 else reg0 |= 0x20;
 106         }
 107
 108         ves1820_writereg(state, 0x00, reg0 & 0xfe);
 109         ves1820_writereg(state, 0x00, reg0 | 0x01);
 110
 111         state->reg0 = reg0;
 112
 113         return 0;
 114 }
 115
 116 static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate)
 117 {
 118         s32 BDR;
 119         s32 BDRI;
 120         s16 SFIL = 0;
 121         u16 NDEC = 0;
 122         u32 ratio;
 123         u32 fin;
 124         u32 tmp;
 125         u64 fptmp;
 126         u64 fpxin;
 127
 128         if (symbolrate > state->config->xin / 2)
 129                 symbolrate = state->config->xin / 2;
 130
 131         if (symbolrate < 500000)
 132                 symbolrate = 500000;
 133
 134         if (symbolrate < state->config->xin / 16)
 135                 NDEC = 1;
 136         if (symbolrate < state->config->xin / 32)
 137                 NDEC = 2;
 138         if (symbolrate < state->config->xin / 64)
 139                 NDEC = 3;
 140
 141         /* yeuch! */
 142         fpxin = state->config->xin * 10;
 143         fptmp = fpxin; do_div(fptmp, 123);
 144         if (symbolrate < fptmp);
 145                 SFIL = 1;
 146         fptmp = fpxin; do_div(fptmp, 160);
 147         if (symbolrate < fptmp);
 148                 SFIL = 0;
 149         fptmp = fpxin; do_div(fptmp, 246);
 150         if (symbolrate < fptmp);
 151                 SFIL = 1;
 152         fptmp = fpxin; do_div(fptmp, 320);
 153         if (symbolrate < fptmp);
 154                 SFIL = 0;
 155         fptmp = fpxin; do_div(fptmp, 492);
 156         if (symbolrate < fptmp);
 157                 SFIL = 1;
 158         fptmp = fpxin; do_div(fptmp, 640);
 159         if (symbolrate < fptmp);
 160                 SFIL = 0;
 161         fptmp = fpxin; do_div(fptmp, 984);
 162         if (symbolrate < fptmp);
 163                 SFIL = 1;
 164
 165         fin = state->config->xin >> 4;
 166         symbolrate <<= NDEC;
 167         ratio = (symbolrate << 4) / fin;
 168         tmp = ((symbolrate << 4) % fin) << 8;
 169         ratio = (ratio << 8) + tmp / fin;
 170         tmp = (tmp % fin) << 8;
 171         ratio = (ratio << 8) + (tmp + fin / 2) / fin;
 172
 173         BDR = ratio;
 174         BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2;
 175
 176         if (BDRI > 0xFF)
 177                 BDRI = 0xFF;
 178
 179         SFIL = (SFIL << 4) | ves1820_inittab[0x0E];
 180
 181         NDEC = (NDEC << 6) | ves1820_inittab[0x03];
 182
 183         ves1820_writereg(state, 0x03, NDEC);
 184         ves1820_writereg(state, 0x0a, BDR & 0xff);
 185         ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);
 186         ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);
 187
 188         ves1820_writereg(state, 0x0d, BDRI);
 189         ves1820_writereg(state, 0x0e, SFIL);
 190
 191         return 0;
 192 }
 193
 194 static int ves1820_init(struct dvb_frontend* fe)
 195 {
 196         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 197         int i;
 198         int val;
 199
 200         ves1820_writereg(state, 0, 0);
 201
 202         for (i = 0; i < 53; i++) {
 203                 val = ves1820_inittab[i];
 204                 if ((i == 2) && (state->config->selagc)) val |= 0x08;
 205                 ves1820_writereg(state, i, val);
 206         }
 207
 208         ves1820_writereg(state, 0x34, state->pwm);
 209
 210         if (state->config->pll_init) state->config->pll_init(fe);
 211
 212         return 0;
 213 }
 214
 215 static int ves1820_set_parameters(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 216 {
 217         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 218         static const u8 reg0x00[] = { 0x00, 0x04, 0x08, 0x0c, 0x10 };
 219         static const u8 reg0x01[] = { 140, 140, 106, 100, 92 };
 220         static const u8 reg0x05[] = { 135, 100, 70, 54, 38 };
 221         static const u8 reg0x08[] = { 162, 116, 67, 52, 35 };
 222         static const u8 reg0x09[] = { 145, 150, 106, 126, 107 };
 223         int real_qam = p->u.qam.modulation - QAM_16;
 224
 225         if (real_qam < 0 || real_qam > 4)
 226                 return -EINVAL;
 227
 228         state->config->pll_set(fe, p);
 229         ves1820_set_symbolrate(state, p->u.qam.symbol_rate);
 230         ves1820_writereg(state, 0x34, state->pwm);
 231
 232         ves1820_writereg(state, 0x01, reg0x01[real_qam]);
 233         ves1820_writereg(state, 0x05, reg0x05[real_qam]);
 234         ves1820_writereg(state, 0x08, reg0x08[real_qam]);
 235         ves1820_writereg(state, 0x09, reg0x09[real_qam]);
 236
 237         ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);
 238
 239         return 0;
 240 }
 241
 242 static int ves1820_read_status(struct dvb_frontend* fe, fe_status_t* status)
 243 {
 244         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 245         int sync;
 246
 247         *status = 0;
 248         sync = ves1820_readreg(state, 0x11);
 249
 250         if (sync & 1)
 251                 *status |= FE_HAS_SIGNAL;
 252
 253         if (sync & 2)
 254                 *status |= FE_HAS_CARRIER;
 255
 256         if (sync & 2)   /* XXX FIXME! */
 257                 *status |= FE_HAS_VITERBI;
 258
 259         if (sync & 4)
 260                 *status |= FE_HAS_SYNC;
 261
 262         if (sync & 8)
 263                 *status |= FE_HAS_LOCK;
 264
 265         return 0;
 266 }
 267
 268 static int ves1820_read_ber(struct dvb_frontend* fe, u32* ber)
 269 {
 270         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 271
 272         u32 _ber = ves1820_readreg(state, 0x14) |
 273                         (ves1820_readreg(state, 0x15) << 8) |
 274                         ((ves1820_readreg(state, 0x16) & 0x0f) << 16);
 275         *ber = 10 * _ber;
 276
 277         return 0;
 278 }
 279
 280 static int ves1820_read_signal_strength(struct dvb_frontend* fe, u16* strength)
 281 {
 282         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 283
 284         u8 gain = ves1820_readreg(state, 0x17);
 285         *strength = (gain << 8) | gain;
 286
 287         return 0;
 288 }
 289
 290 static int ves1820_read_snr(struct dvb_frontend* fe, u16* snr)
 291 {
 292         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 293
 294         u8 quality = ~ves1820_readreg(state, 0x18);
 295         *snr = (quality << 8) | quality;
 296
 297         return 0;
 298 }
 299
 300 static int ves1820_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 301 {
 302         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 303
 304         *ucblocks = ves1820_readreg(state, 0x13) & 0x7f;
 305         if (*ucblocks == 0x7f)
 306                 *ucblocks = 0xffffffff;
 307
 308         /* reset uncorrected block counter */
 309         ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);
 310         ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);
 311
 312         return 0;
 313 }
 314
 315 static int ves1820_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 316 {
 317         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 318         int sync;
 319         s8 afc = 0;
 320
 321         sync = ves1820_readreg(state, 0x11);
 322         afc = ves1820_readreg(state, 0x19);
 323         if (verbose) {
 324                 /* AFC only valid when carrier has been recovered */
 325                 printk(sync & 2 ? "ves1820: AFC (%d) %dHz\n" :
 326                         "ves1820: [AFC (%d) %dHz]\n", afc, -((s32) p->u.qam.symbol_rate * afc) >> 10);
 327         }
 328
 329         if (!state->config->invert) {
 330                 p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF;
 331         } else {
 332                 p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF;
 333         }
 334
 335         p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16;
 336
 337         p->u.qam.fec_inner = FEC_NONE;
 338
 339         p->frequency = ((p->frequency + 31250) / 62500) * 62500;
 340         if (sync & 2)
 341                 p->frequency -= ((s32) p->u.qam.symbol_rate * afc) >> 10;
 342
 343         return 0;
 344 }
 345
 346 static int ves1820_sleep(struct dvb_frontend* fe)
 347 {
 348         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 349
 350         ves1820_writereg(state, 0x1b, 0x02);    /* pdown ADC */
 351         ves1820_writereg(state, 0x00, 0x80);    /* standby */
 352
 353         return 0;
 354 }
 355
 356 static int ves1820_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
 357 {
 358
 359         fesettings->min_delay_ms = 200;
 360         fesettings->step_size = 0;
 361         fesettings->max_drift = 0;
 362         return 0;
 363 }
 364
 365 static void ves1820_release(struct dvb_frontend* fe)
 366 {
 367         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 368         kfree(state);
 369 }
 370
 371 static struct dvb_frontend_ops ves1820_ops;
 372
 373 struct dvb_frontend* ves1820_attach(const struct ves1820_config* config,
 374                                     struct i2c_adapter* i2c,
 375                                     u8 pwm)
 376 {
 377         struct ves1820_state* state = NULL;
 378
 379         /* allocate memory for the internal state */
 380         state = (struct ves1820_state*) kmalloc(sizeof(struct ves1820_state), GFP_KERNEL);
 381         if (state == NULL)
 382                 goto error;
 383
 384         /* setup the state */
 385         memcpy(&state->ops, &ves1820_ops, sizeof(struct dvb_frontend_ops));
 386         state->reg0 = ves1820_inittab[0];
 387         state->config = config;
 388         state->i2c = i2c;
 389         state->pwm = pwm;
 390
 391         /* check if the demod is there */
 392         if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70)
 393                 goto error;
 394
 395         if (verbose)
 396                 printk("ves1820: pwm=0x%02x\n", state->pwm);
 397
 398         state->ops.info.symbol_rate_min = (state->config->xin / 2) / 64;      /* SACLK/64 == (XIN/2)/64 */
 399         state->ops.info.symbol_rate_max = (state->config->xin / 2) / 4;       /* SACLK/4 */
 400
 401         /* create dvb_frontend */
 402         state->frontend.ops = &state->ops;
 403         state->frontend.demodulator_priv = state;
 404         return &state->frontend;
 405
 406 error:
 407         kfree(state);
 408         return NULL;
 409 }
 410
 411 static struct dvb_frontend_ops ves1820_ops = {
 412
 413         .info = {
 414                 .name = "VLSI VES1820 DVB-C",
 415                 .type = FE_QAM,
 416                 .frequency_stepsize = 62500,
 417                 .frequency_min = 51000000,
 418                 .frequency_max = 858000000,
 419                 .caps = FE_CAN_QAM_16 |
 420                         FE_CAN_QAM_32 |
 421                         FE_CAN_QAM_64 |
 422                         FE_CAN_QAM_128 |
 423                         FE_CAN_QAM_256 |
 424                         FE_CAN_FEC_AUTO
 425         },
 426
 427         .release = ves1820_release,
 428
 429         .init = ves1820_init,
 430         .sleep = ves1820_sleep,
 431
 432         .set_frontend = ves1820_set_parameters,
 433         .get_frontend = ves1820_get_frontend,
 434         .get_tune_settings = ves1820_get_tune_settings,
 435
 436         .read_status = ves1820_read_status,
 437         .read_ber = ves1820_read_ber,
 438         .read_signal_strength = ves1820_read_signal_strength,
 439         .read_snr = ves1820_read_snr,
 440         .read_ucblocks = ves1820_read_ucblocks,
 441 };
 442
 443 module_param(verbose, int, 0644);
 444 MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");
 445
 446 MODULE_DESCRIPTION("VLSI VES1820 DVB-C Demodulator driver");
 447 MODULE_AUTHOR("Ralph Metzler, Holger Waechtler");
 448 MODULE_LICENSE("GPL");
 449
 450 EXPORT_SYMBOL(ves1820_attach);