Linux-2.6.12-rc2
[linux-2.6/kvm.git] / drivers / media / dvb / frontends / l64781.c
blob9ac95de9834d5604afd6de10316c149d3eb6cf07
1 /*
2 driver for LSI L64781 COFDM demodulator
4 Copyright (C) 2001 Holger Waechtler for Convergence Integrated Media GmbH
5 Marko Kohtala <marko.kohtala@luukku.com>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/string.h>
28 #include <linux/slab.h>
29 #include "dvb_frontend.h"
30 #include "l64781.h"
33 struct l64781_state {
34 struct i2c_adapter* i2c;
35 struct dvb_frontend_ops ops;
36 const struct l64781_config* config;
37 struct dvb_frontend frontend;
39 /* private demodulator data */
40 int first:1;
43 #define dprintk(args...) \
44 do { \
45 if (debug) printk(KERN_DEBUG "l64781: " args); \
46 } while (0)
48 static int debug;
50 module_param(debug, int, 0644);
51 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
54 static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data)
56 int ret;
57 u8 buf [] = { reg, data };
58 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
60 if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1)
61 dprintk ("%s: write_reg error (reg == %02x) = %02x!\n",
62 __FUNCTION__, reg, ret);
64 return (ret != 1) ? -1 : 0;
67 static int l64781_readreg (struct l64781_state* state, u8 reg)
69 int ret;
70 u8 b0 [] = { reg };
71 u8 b1 [] = { 0 };
72 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
73 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
75 ret = i2c_transfer(state->i2c, msg, 2);
77 if (ret != 2) return ret;
79 return b1[0];
82 static void apply_tps (struct l64781_state* state)
84 l64781_writereg (state, 0x2a, 0x00);
85 l64781_writereg (state, 0x2a, 0x01);
87 /* This here is a little bit questionable because it enables
88 the automatic update of TPS registers. I think we'd need to
89 handle the IRQ from FE to update some other registers as
90 well, or at least implement some magic to tuning to correct
91 to the TPS received from transmission. */
92 l64781_writereg (state, 0x2a, 0x02);
96 static void reset_afc (struct l64781_state* state)
98 /* Set AFC stall for the AFC_INIT_FRQ setting, TIM_STALL for
99 timing offset */
100 l64781_writereg (state, 0x07, 0x9e); /* stall AFC */
101 l64781_writereg (state, 0x08, 0); /* AFC INIT FREQ */
102 l64781_writereg (state, 0x09, 0);
103 l64781_writereg (state, 0x0a, 0);
104 l64781_writereg (state, 0x07, 0x8e);
105 l64781_writereg (state, 0x0e, 0); /* AGC gain to zero in beginning */
106 l64781_writereg (state, 0x11, 0x80); /* stall TIM */
107 l64781_writereg (state, 0x10, 0); /* TIM_OFFSET_LSB */
108 l64781_writereg (state, 0x12, 0);
109 l64781_writereg (state, 0x13, 0);
110 l64781_writereg (state, 0x11, 0x00);
113 static int reset_and_configure (struct l64781_state* state)
115 u8 buf [] = { 0x06 };
116 struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 };
117 // NOTE: this is correct in writing to address 0x00
119 return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV;
122 static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_parameters *param)
124 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
125 /* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */
126 static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 };
127 /* QPSK, QAM_16, QAM_64 */
128 static const u8 qam_tab [] = { 2, 4, 0, 6 };
129 static const u8 bw_tab [] = { 8, 7, 6 }; /* 8Mhz, 7MHz, 6MHz */
130 static const u8 guard_tab [] = { 1, 2, 4, 8 };
131 /* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */
132 static const u32 ppm = 8000;
133 struct dvb_ofdm_parameters *p = &param->u.ofdm;
134 u32 ddfs_offset_fixed;
135 /* u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */
136 /* bw_tab[p->bandWidth]<<10)/15625; */
137 u32 init_freq;
138 u32 spi_bias;
139 u8 val0x04;
140 u8 val0x05;
141 u8 val0x06;
142 int bw = p->bandwidth - BANDWIDTH_8_MHZ;
144 state->config->pll_set(fe, param);
146 if (param->inversion != INVERSION_ON &&
147 param->inversion != INVERSION_OFF)
148 return -EINVAL;
150 if (bw < 0 || bw > 2)
151 return -EINVAL;
153 if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 &&
154 p->code_rate_HP != FEC_3_4 && p->code_rate_HP != FEC_5_6 &&
155 p->code_rate_HP != FEC_7_8)
156 return -EINVAL;
158 if (p->hierarchy_information != HIERARCHY_NONE &&
159 (p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 &&
160 p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 &&
161 p->code_rate_LP != FEC_7_8))
162 return -EINVAL;
164 if (p->constellation != QPSK && p->constellation != QAM_16 &&
165 p->constellation != QAM_64)
166 return -EINVAL;
168 if (p->transmission_mode != TRANSMISSION_MODE_2K &&
169 p->transmission_mode != TRANSMISSION_MODE_8K)
170 return -EINVAL;
172 if (p->guard_interval < GUARD_INTERVAL_1_32 ||
173 p->guard_interval > GUARD_INTERVAL_1_4)
174 return -EINVAL;
176 if (p->hierarchy_information < HIERARCHY_NONE ||
177 p->hierarchy_information > HIERARCHY_4)
178 return -EINVAL;
180 ddfs_offset_fixed = 0x4000-(ppm<<16)/bw_tab[p->bandwidth]/1000000;
182 /* This works up to 20000 ppm, it overflows if too large ppm! */
183 init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) /
184 bw_tab[p->bandwidth] & 0xFFFFFF);
186 /* SPI bias calculation is slightly modified to fit in 32bit */
187 /* will work for high ppm only... */
188 spi_bias = 378 * (1 << 10);
189 spi_bias *= 16;
190 spi_bias *= bw_tab[p->bandwidth];
191 spi_bias *= qam_tab[p->constellation];
192 spi_bias /= p->code_rate_HP + 1;
193 spi_bias /= (guard_tab[p->guard_interval] + 32);
194 spi_bias *= 1000ULL;
195 spi_bias /= 1000ULL + ppm/1000;
196 spi_bias *= p->code_rate_HP;
198 val0x04 = (p->transmission_mode << 2) | p->guard_interval;
199 val0x05 = fec_tab[p->code_rate_HP];
201 if (p->hierarchy_information != HIERARCHY_NONE)
202 val0x05 |= (p->code_rate_LP - FEC_1_2) << 3;
204 val0x06 = (p->hierarchy_information << 2) | p->constellation;
206 l64781_writereg (state, 0x04, val0x04);
207 l64781_writereg (state, 0x05, val0x05);
208 l64781_writereg (state, 0x06, val0x06);
210 reset_afc (state);
212 /* Technical manual section 2.6.1, TIM_IIR_GAIN optimal values */
213 l64781_writereg (state, 0x15,
214 p->transmission_mode == TRANSMISSION_MODE_2K ? 1 : 3);
215 l64781_writereg (state, 0x16, init_freq & 0xff);
216 l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff);
217 l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff);
219 l64781_writereg (state, 0x1b, spi_bias & 0xff);
220 l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);
221 l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |
222 (param->inversion == INVERSION_ON ? 0x80 : 0x00));
224 l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);
225 l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);
227 l64781_readreg (state, 0x00); /* clear interrupt registers... */
228 l64781_readreg (state, 0x01); /* dto. */
230 apply_tps (state);
232 return 0;
235 static int get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters* param)
237 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
238 int tmp;
241 tmp = l64781_readreg(state, 0x04);
242 switch(tmp & 3) {
243 case 0:
244 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
245 break;
246 case 1:
247 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
248 break;
249 case 2:
250 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
251 break;
252 case 3:
253 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
254 break;
256 switch((tmp >> 2) & 3) {
257 case 0:
258 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
259 break;
260 case 1:
261 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
262 break;
263 default:
264 printk("Unexpected value for transmission_mode\n");
269 tmp = l64781_readreg(state, 0x05);
270 switch(tmp & 7) {
271 case 0:
272 param->u.ofdm.code_rate_HP = FEC_1_2;
273 break;
274 case 1:
275 param->u.ofdm.code_rate_HP = FEC_2_3;
276 break;
277 case 2:
278 param->u.ofdm.code_rate_HP = FEC_3_4;
279 break;
280 case 3:
281 param->u.ofdm.code_rate_HP = FEC_5_6;
282 break;
283 case 4:
284 param->u.ofdm.code_rate_HP = FEC_7_8;
285 break;
286 default:
287 printk("Unexpected value for code_rate_HP\n");
289 switch((tmp >> 3) & 7) {
290 case 0:
291 param->u.ofdm.code_rate_LP = FEC_1_2;
292 break;
293 case 1:
294 param->u.ofdm.code_rate_LP = FEC_2_3;
295 break;
296 case 2:
297 param->u.ofdm.code_rate_LP = FEC_3_4;
298 break;
299 case 3:
300 param->u.ofdm.code_rate_LP = FEC_5_6;
301 break;
302 case 4:
303 param->u.ofdm.code_rate_LP = FEC_7_8;
304 break;
305 default:
306 printk("Unexpected value for code_rate_LP\n");
310 tmp = l64781_readreg(state, 0x06);
311 switch(tmp & 3) {
312 case 0:
313 param->u.ofdm.constellation = QPSK;
314 break;
315 case 1:
316 param->u.ofdm.constellation = QAM_16;
317 break;
318 case 2:
319 param->u.ofdm.constellation = QAM_64;
320 break;
321 default:
322 printk("Unexpected value for constellation\n");
324 switch((tmp >> 2) & 7) {
325 case 0:
326 param->u.ofdm.hierarchy_information = HIERARCHY_NONE;
327 break;
328 case 1:
329 param->u.ofdm.hierarchy_information = HIERARCHY_1;
330 break;
331 case 2:
332 param->u.ofdm.hierarchy_information = HIERARCHY_2;
333 break;
334 case 3:
335 param->u.ofdm.hierarchy_information = HIERARCHY_4;
336 break;
337 default:
338 printk("Unexpected value for hierarchy\n");
342 tmp = l64781_readreg (state, 0x1d);
343 param->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF;
345 tmp = (int) (l64781_readreg (state, 0x08) |
346 (l64781_readreg (state, 0x09) << 8) |
347 (l64781_readreg (state, 0x0a) << 16));
348 param->frequency += tmp;
350 return 0;
353 static int l64781_read_status(struct dvb_frontend* fe, fe_status_t* status)
355 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
356 int sync = l64781_readreg (state, 0x32);
357 int gain = l64781_readreg (state, 0x0e);
359 l64781_readreg (state, 0x00); /* clear interrupt registers... */
360 l64781_readreg (state, 0x01); /* dto. */
362 *status = 0;
364 if (gain > 5)
365 *status |= FE_HAS_SIGNAL;
367 if (sync & 0x02) /* VCXO locked, this criteria should be ok */
368 *status |= FE_HAS_CARRIER;
370 if (sync & 0x20)
371 *status |= FE_HAS_VITERBI;
373 if (sync & 0x40)
374 *status |= FE_HAS_SYNC;
376 if (sync == 0x7f)
377 *status |= FE_HAS_LOCK;
379 return 0;
382 static int l64781_read_ber(struct dvb_frontend* fe, u32* ber)
384 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
386 /* XXX FIXME: set up counting period (reg 0x26...0x28)
388 *ber = l64781_readreg (state, 0x39)
389 | (l64781_readreg (state, 0x3a) << 8);
391 return 0;
394 static int l64781_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
396 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
398 u8 gain = l64781_readreg (state, 0x0e);
399 *signal_strength = (gain << 8) | gain;
401 return 0;
404 static int l64781_read_snr(struct dvb_frontend* fe, u16* snr)
406 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
408 u8 avg_quality = 0xff - l64781_readreg (state, 0x33);
409 *snr = (avg_quality << 8) | avg_quality; /* not exact, but...*/
411 return 0;
414 static int l64781_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
416 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
418 *ucblocks = l64781_readreg (state, 0x37)
419 | (l64781_readreg (state, 0x38) << 8);
421 return 0;
424 static int l64781_sleep(struct dvb_frontend* fe)
426 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
428 /* Power down */
429 return l64781_writereg (state, 0x3e, 0x5a);
432 static int l64781_init(struct dvb_frontend* fe)
434 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
436 reset_and_configure (state);
438 /* Power up */
439 l64781_writereg (state, 0x3e, 0xa5);
441 /* Reset hard */
442 l64781_writereg (state, 0x2a, 0x04);
443 l64781_writereg (state, 0x2a, 0x00);
445 /* Set tuner specific things */
446 /* AFC_POL, set also in reset_afc */
447 l64781_writereg (state, 0x07, 0x8e);
449 /* Use internal ADC */
450 l64781_writereg (state, 0x0b, 0x81);
452 /* AGC loop gain, and polarity is positive */
453 l64781_writereg (state, 0x0c, 0x84);
455 /* Internal ADC outputs two's complement */
456 l64781_writereg (state, 0x0d, 0x8c);
458 /* With ppm=8000, it seems the DTR_SENSITIVITY will result in
459 value of 2 with all possible bandwidths and guard
460 intervals, which is the initial value anyway. */
461 /*l64781_writereg (state, 0x19, 0x92);*/
463 /* Everything is two's complement, soft bit and CSI_OUT too */
464 l64781_writereg (state, 0x1e, 0x09);
466 if (state->config->pll_init) state->config->pll_init(fe);
468 /* delay a bit after first init attempt */
469 if (state->first) {
470 state->first = 0;
471 msleep(200);
474 return 0;
477 static int l64781_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
479 fesettings->min_delay_ms = 200;
480 fesettings->step_size = 166667;
481 fesettings->max_drift = 166667*2;
482 return 0;
485 static void l64781_release(struct dvb_frontend* fe)
487 struct l64781_state* state = (struct l64781_state*) fe->demodulator_priv;
488 kfree(state);
491 static struct dvb_frontend_ops l64781_ops;
493 struct dvb_frontend* l64781_attach(const struct l64781_config* config,
494 struct i2c_adapter* i2c)
496 struct l64781_state* state = NULL;
497 int reg0x3e = -1;
498 u8 b0 [] = { 0x1a };
499 u8 b1 [] = { 0x00 };
500 struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 },
501 { .addr = config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
503 /* allocate memory for the internal state */
504 state = (struct l64781_state*) kmalloc(sizeof(struct l64781_state), GFP_KERNEL);
505 if (state == NULL) goto error;
507 /* setup the state */
508 state->config = config;
509 state->i2c = i2c;
510 memcpy(&state->ops, &l64781_ops, sizeof(struct dvb_frontend_ops));
511 state->first = 1;
514 * the L64781 won't show up before we send the reset_and_configure()
515 * broadcast. If nothing responds there is no L64781 on the bus...
517 if (reset_and_configure(state) < 0) {
518 dprintk("No response to reset and configure broadcast...\n");
519 goto error;
522 /* The chip always responds to reads */
523 if (i2c_transfer(state->i2c, msg, 2) != 2) {
524 dprintk("No response to read on I2C bus\n");
525 goto error;
528 /* Save current register contents for bailout */
529 reg0x3e = l64781_readreg(state, 0x3e);
531 /* Reading the POWER_DOWN register always returns 0 */
532 if (reg0x3e != 0) {
533 dprintk("Device doesn't look like L64781\n");
534 goto error;
537 /* Turn the chip off */
538 l64781_writereg (state, 0x3e, 0x5a);
540 /* Responds to all reads with 0 */
541 if (l64781_readreg(state, 0x1a) != 0) {
542 dprintk("Read 1 returned unexpcted value\n");
543 goto error;
546 /* Turn the chip on */
547 l64781_writereg (state, 0x3e, 0xa5);
549 /* Responds with register default value */
550 if (l64781_readreg(state, 0x1a) != 0xa1) {
551 dprintk("Read 2 returned unexpcted value\n");
552 goto error;
555 /* create dvb_frontend */
556 state->frontend.ops = &state->ops;
557 state->frontend.demodulator_priv = state;
558 return &state->frontend;
560 error:
561 if (reg0x3e >= 0) l64781_writereg (state, 0x3e, reg0x3e); /* restore reg 0x3e */
562 kfree(state);
563 return NULL;
566 static struct dvb_frontend_ops l64781_ops = {
568 .info = {
569 .name = "LSI L64781 DVB-T",
570 .type = FE_OFDM,
571 /* .frequency_min = ???,*/
572 /* .frequency_max = ???,*/
573 .frequency_stepsize = 166666,
574 /* .frequency_tolerance = ???,*/
575 /* .symbol_rate_tolerance = ???,*/
576 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
577 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
578 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
579 FE_CAN_MUTE_TS
582 .release = l64781_release,
584 .init = l64781_init,
585 .sleep = l64781_sleep,
587 .set_frontend = apply_frontend_param,
588 .get_frontend = get_frontend,
589 .get_tune_settings = l64781_get_tune_settings,
591 .read_status = l64781_read_status,
592 .read_ber = l64781_read_ber,
593 .read_signal_strength = l64781_read_signal_strength,
594 .read_snr = l64781_read_snr,
595 .read_ucblocks = l64781_read_ucblocks,
598 MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver");
599 MODULE_AUTHOR("Holger Waechtler, Marko Kohtala");
600 MODULE_LICENSE("GPL");
602 EXPORT_SYMBOL(l64781_attach);