Linux-2.6.12-rc2
[linux-2.6/kvm.git] / drivers / ide / pci / cs5520.c
blob7dc24682d197d44a4be32da254b0beb7b190e3fc
1 /*
2 * IDE tuning and bus mastering support for the CS5510/CS5520
3 * chipsets
5 * The CS5510/CS5520 are slightly unusual devices. Unlike the
6 * typical IDE controllers they do bus mastering with the drive in
7 * PIO mode and smarter silicon.
9 * The practical upshot of this is that we must always tune the
10 * drive for the right PIO mode. We must also ignore all the blacklists
11 * and the drive bus mastering DMA information.
13 * *** This driver is strictly experimental ***
15 * (c) Copyright Red Hat Inc 2002
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2, or (at your option) any
20 * later version.
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25 * General Public License for more details.
27 * For the avoidance of doubt the "preferred form" of this code is one which
28 * is in an open non patent encumbered format. Where cryptographic key signing
29 * forms part of the process of creating an executable the information
30 * including keys needed to generate an equivalently functional executable
31 * are deemed to be part of the source code.
35 #include <linux/config.h>
36 #include <linux/module.h>
37 #include <linux/types.h>
38 #include <linux/kernel.h>
39 #include <linux/delay.h>
40 #include <linux/timer.h>
41 #include <linux/mm.h>
42 #include <linux/ioport.h>
43 #include <linux/blkdev.h>
44 #include <linux/hdreg.h>
46 #include <linux/interrupt.h>
47 #include <linux/init.h>
48 #include <linux/pci.h>
49 #include <linux/ide.h>
50 #include <linux/dma-mapping.h>
52 #include <asm/io.h>
53 #include <asm/irq.h>
55 struct pio_clocks
57 int address;
58 int assert;
59 int recovery;
62 static struct pio_clocks cs5520_pio_clocks[]={
63 {3, 6, 11},
64 {2, 5, 6},
65 {1, 4, 3},
66 {1, 3, 2},
67 {1, 2, 1}
70 static int cs5520_tune_chipset(ide_drive_t *drive, u8 xferspeed)
72 ide_hwif_t *hwif = HWIF(drive);
73 struct pci_dev *pdev = hwif->pci_dev;
74 u8 speed = min((u8)XFER_PIO_4, xferspeed);
75 int pio = speed;
76 u8 reg;
77 int controller = drive->dn > 1 ? 1 : 0;
78 int error;
80 switch(speed)
82 case XFER_PIO_4:
83 case XFER_PIO_3:
84 case XFER_PIO_2:
85 case XFER_PIO_1:
86 case XFER_PIO_0:
87 pio -= XFER_PIO_0;
88 break;
89 default:
90 pio = 0;
91 printk(KERN_ERR "cs55x0: bad ide timing.\n");
94 printk("PIO clocking = %d\n", pio);
96 /* FIXME: if DMA = 1 do we need to set the DMA bit here ? */
98 /* 8bit CAT/CRT - 8bit command timing for channel */
99 pci_write_config_byte(pdev, 0x62 + controller,
100 (cs5520_pio_clocks[pio].recovery << 4) |
101 (cs5520_pio_clocks[pio].assert));
103 /* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
105 /* FIXME: should these use address ? */
106 /* Data read timing */
107 pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
108 (cs5520_pio_clocks[pio].recovery << 4) |
109 (cs5520_pio_clocks[pio].assert));
110 /* Write command timing */
111 pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
112 (cs5520_pio_clocks[pio].recovery << 4) |
113 (cs5520_pio_clocks[pio].assert));
115 /* Set the DMA enable/disable flag */
116 reg = inb(hwif->dma_base + 0x02 + 8*controller);
117 reg |= 1<<((drive->dn&1)+5);
118 outb(reg, hwif->dma_base + 0x02 + 8*controller);
120 error = ide_config_drive_speed(drive, speed);
121 /* ATAPI is harder so leave it for now */
122 if(!error && drive->media == ide_disk)
123 error = hwif->ide_dma_on(drive);
125 return error;
128 static void cs5520_tune_drive(ide_drive_t *drive, u8 pio)
130 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
131 cs5520_tune_chipset(drive, (XFER_PIO_0 + pio));
134 static int cs5520_config_drive_xfer_rate(ide_drive_t *drive)
136 ide_hwif_t *hwif = HWIF(drive);
138 /* Tune the drive for PIO modes up to PIO 4 */
139 cs5520_tune_drive(drive, 4);
140 /* Then tell the core to use DMA operations */
141 return hwif->ide_dma_on(drive);
145 * We provide a callback for our nonstandard DMA location
148 static void __devinit cs5520_init_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
150 unsigned long bmide = pci_resource_start(dev, 2); /* Not the usual 4 */
151 if(hwif->mate && hwif->mate->dma_base) /* Second channel at primary + 8 */
152 bmide += 8;
153 ide_setup_dma(hwif, bmide, 8);
157 * We wrap the DMA activate to set the vdma flag. This is needed
158 * so that the IDE DMA layer issues PIO not DMA commands over the
159 * DMA channel
162 static int cs5520_dma_on(ide_drive_t *drive)
164 drive->vdma = 1;
165 return 0;
168 static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
170 hwif->tuneproc = &cs5520_tune_drive;
171 hwif->speedproc = &cs5520_tune_chipset;
172 hwif->ide_dma_check = &cs5520_config_drive_xfer_rate;
173 hwif->ide_dma_on = &cs5520_dma_on;
175 if(!noautodma)
176 hwif->autodma = 1;
178 if(!hwif->dma_base)
180 hwif->drives[0].autotune = 1;
181 hwif->drives[1].autotune = 1;
182 return;
185 hwif->atapi_dma = 0;
186 hwif->ultra_mask = 0;
187 hwif->swdma_mask = 0;
188 hwif->mwdma_mask = 0;
190 hwif->drives[0].autodma = hwif->autodma;
191 hwif->drives[1].autodma = hwif->autodma;
194 #define DECLARE_CS_DEV(name_str) \
196 .name = name_str, \
197 .init_setup_dma = cs5520_init_setup_dma, \
198 .init_hwif = init_hwif_cs5520, \
199 .channels = 2, \
200 .autodma = AUTODMA, \
201 .bootable = ON_BOARD, \
202 .flags = IDEPCI_FLAG_ISA_PORTS, \
205 static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
206 /* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
207 /* 1 */ DECLARE_CS_DEV("Cyrix 5520")
211 * The 5510/5520 are a bit weird. They don't quite set up the way
212 * the PCI helper layer expects so we must do much of the set up
213 * work longhand.
216 static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
218 ata_index_t index;
219 ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];
221 ide_setup_pci_noise(dev, d);
223 /* We must not grab the entire device, it has 'ISA' space in its
224 BARS too and we will freak out other bits of the kernel */
225 if(pci_enable_device_bars(dev, 1<<2))
227 printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
228 return 1;
230 pci_set_master(dev);
231 if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
232 printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
233 return -ENODEV;
236 index.all = 0xf0f0;
239 * Now the chipset is configured we can let the core
240 * do all the device setup for us
243 ide_pci_setup_ports(dev, d, 14, &index);
245 if((index.b.low & 0xf0) != 0xf0)
246 probe_hwif_init(&ide_hwifs[index.b.low]);
247 if((index.b.high & 0xf0) != 0xf0)
248 probe_hwif_init(&ide_hwifs[index.b.high]);
249 return 0;
252 static struct pci_device_id cs5520_pci_tbl[] = {
253 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
254 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
255 { 0, },
257 MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
259 static struct pci_driver driver = {
260 .name = "Cyrix_IDE",
261 .id_table = cs5520_pci_tbl,
262 .probe = cs5520_init_one,
265 static int cs5520_ide_init(void)
267 return ide_pci_register_driver(&driver);
270 module_init(cs5520_ide_init);
272 MODULE_AUTHOR("Alan Cox");
273 MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
274 MODULE_LICENSE("GPL");