arch/ppc/syslib/cpc710.h

   1 /*
   2  * arch/ppc/syslib/cpc710.h
   3  *
   4  * Definitions for the IBM CPC710 PCI Host Bridge
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
   9  * the terms of the GNU General Public License version 2.  This program
  10  * is licensed "as is" without any warranty of any kind, whether express
  11  * or implied.
  12  */
  13
  14 #ifndef __PPC_PLATFORMS_CPC710_H
  15 #define __PPC_PLATFORMS_CPC710_H
  16
  17 /* General bridge and memory controller registers */
  18 #define PIDR    0xff000008
  19 #define CNFR    0xff00000c
  20 #define RSTR    0xff000010
  21 #define UCTL    0xff001000
  22 #define MPSR    0xff001010
  23 #define SIOC    0xff001020
  24 #define ABCNTL  0xff001030
  25 #define SRST    0xff001040
  26 #define ERRC    0xff001050
  27 #define SESR    0xff001060
  28 #define SEAR    0xff001070
  29 #define SIOC1   0xff001090
  30 #define PGCHP   0xff001100
  31 #define GPDIR   0xff001130
  32 #define GPOUT   0xff001150
  33 #define ATAS    0xff001160
  34 #define AVDG    0xff001170
  35 #define MCCR    0xff001200
  36 #define MESR    0xff001220
  37 #define MEAR    0xff001230
  38 #define MCER0   0xff001300
  39 #define MCER1   0xff001310
  40 #define MCER2   0xff001320
  41 #define MCER3   0xff001330
  42 #define MCER4   0xff001340
  43 #define MCER5   0xff001350
  44 #define MCER6   0xff001360
  45 #define MCER7   0xff001370
  46
  47 /*
  48  * PCI32/64 configuration registers
  49  * Given as offsets from their
  50  * respective physical segment BAR
  51  */
  52 #define PIBAR   0x000f7800
  53 #define PMBAR   0x000f7810
  54 #define MSIZE   0x000f7f40
  55 #define IOSIZE  0x000f7f60
  56 #define SMBAR   0x000f7f80
  57 #define SIBAR   0x000f7fc0
  58 #define PSSIZE  0x000f8100
  59 #define PPSIZE  0x000f8110
  60 #define BARPS   0x000f8120
  61 #define BARPP   0x000f8130
  62 #define PSBAR   0x000f8140
  63 #define PPBAR   0x000f8150
  64 #define BPMDLK  0x000f8200      /* Bottom of Peripheral Memory Space */
  65 #define TPMDLK  0x000f8210      /* Top of Peripheral Memory Space */
  66 #define BIODLK  0x000f8220      /* Bottom of Peripheral I/O Space */
  67 #define TIODLK  0x000f8230      /* Top of Perioheral I/O Space */
  68 #define DLKCTRL 0x000f8240      /* Deadlock control */
  69 #define DLKDEV  0x000f8250      /* Deadlock device */
  70
  71 /* System standard configuration registers space */
  72 #define DCR     0xff200000
  73 #define DID     0xff200004
  74 #define BAR     0xff200018
  75
  76 /* Device specific configuration space */
  77 #define PCIENB  0xff201000
  78
  79 /* Configuration space registers */
  80 #define CPC710_BUS_NUMBER       0x40
  81 #define CPC710_SUB_BUS_NUMBER   0x41
  82
  83 #endif /* __PPC_PLATFORMS_CPC710_H */