arch/ppc/platforms/85xx/mpc85xx_cds_common.h

   1 /*
   2  * arch/ppc/platforms/85xx/mpc85xx_cds_common.h
   3  *
   4  * MPC85xx CDS board definitions
   5  *
   6  * Maintainer: Kumar Gala <kumar.gala@freescale.com>
   7  *
   8  * Copyright 2004 Freescale Semiconductor, Inc
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #ifndef __MACH_MPC85XX_CDS_H__
  18 #define __MACH_MPC85XX_CDS_H__
  19
  20 #include <linux/config.h>
  21 #include <linux/serial.h>
  22 #include <asm/ppcboot.h>
  23 #include <linux/initrd.h>
  24 #include <syslib/ppc85xx_setup.h>
  25
  26 #define BOARD_CCSRBAR           ((uint)0xe0000000)
  27 #define CCSRBAR_SIZE            ((uint)1024*1024)
  28
  29 /* CADMUS info */
  30 #define CADMUS_BASE (0xf8004000)
  31 #define CADMUS_SIZE (256)
  32 #define CM_VER  (0)
  33 #define CM_CSR  (1)
  34 #define CM_RST  (2)
  35
  36 /* CDS NVRAM/RTC */
  37 #define CDS_RTC_ADDR    (0xf8000000)
  38 #define CDS_RTC_SIZE    (8 * 1024)
  39
  40 /* PCI config */
  41 #define PCI1_CFG_ADDR_OFFSET    (0x8000)
  42 #define PCI1_CFG_DATA_OFFSET    (0x8004)
  43
  44 #define PCI2_CFG_ADDR_OFFSET    (0x9000)
  45 #define PCI2_CFG_DATA_OFFSET    (0x9004)
  46
  47 /* PCI interrupt controller */
  48 #define PIRQ0A                   MPC85xx_IRQ_EXT0
  49 #define PIRQ0B                   MPC85xx_IRQ_EXT1
  50 #define PIRQ0C                   MPC85xx_IRQ_EXT2
  51 #define PIRQ0D                   MPC85xx_IRQ_EXT3
  52 #define PIRQ1A                   MPC85xx_IRQ_EXT11
  53
  54 /* PCI 1 memory map */
  55 #define MPC85XX_PCI1_LOWER_IO        0x00000000
  56 #define MPC85XX_PCI1_UPPER_IO        0x00ffffff
  57
  58 #define MPC85XX_PCI1_LOWER_MEM       0x80000000
  59 #define MPC85XX_PCI1_UPPER_MEM       0x9fffffff
  60
  61 #define MPC85XX_PCI1_IO_BASE         0xe2000000
  62 #define MPC85XX_PCI1_MEM_OFFSET      0x00000000
  63
  64 #define MPC85XX_PCI1_IO_SIZE         0x01000000
  65
  66 /* PCI 2 memory map */
  67 /* Note: the standard PPC fixups will cause IO space to get bumped by
  68  * hose->io_base_virt - isa_io_base => MPC85XX_PCI1_IO_SIZE */
  69 #define MPC85XX_PCI2_LOWER_IO        0x00000000
  70 #define MPC85XX_PCI2_UPPER_IO        0x00ffffff
  71
  72 #define MPC85XX_PCI2_LOWER_MEM       0xa0000000
  73 #define MPC85XX_PCI2_UPPER_MEM       0xbfffffff
  74
  75 #define MPC85XX_PCI2_IO_BASE         0xe3000000
  76 #define MPC85XX_PCI2_MEM_OFFSET      0x00000000
  77
  78 #define MPC85XX_PCI2_IO_SIZE         0x01000000
  79
  80 #endif /* __MACH_MPC85XX_CDS_H__ */