arch/ppc/platforms/4xx/ebony.c

   1 /*
   2  * arch/ppc/platforms/4xx/ebony.c
   3  *
   4  * Ebony board specific routines
   5  *
   6  * Matt Porter <mporter@kernel.crashing.org>
   7  * Copyright 2002-2005 MontaVista Software Inc.
   8  *
   9  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  10  * Copyright (c) 2003, 2004 Zultys Technologies
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/types.h>
  27 #include <linux/major.h>
  28 #include <linux/blkdev.h>
  29 #include <linux/console.h>
  30 #include <linux/delay.h>
  31 #include <linux/ide.h>
  32 #include <linux/initrd.h>
  33 #include <linux/irq.h>
  34 #include <linux/seq_file.h>
  35 #include <linux/root_dev.h>
  36 #include <linux/tty.h>
  37 #include <linux/serial.h>
  38 #include <linux/serial_core.h>
  39
  40 #include <asm/system.h>
  41 #include <asm/pgtable.h>
  42 #include <asm/page.h>
  43 #include <asm/dma.h>
  44 #include <asm/io.h>
  45 #include <asm/machdep.h>
  46 #include <asm/ocp.h>
  47 #include <asm/pci-bridge.h>
  48 #include <asm/time.h>
  49 #include <asm/todc.h>
  50 #include <asm/bootinfo.h>
  51 #include <asm/ppc4xx_pic.h>
  52 #include <asm/ppcboot.h>
  53
  54 #include <syslib/gen550.h>
  55 #include <syslib/ibm440gp_common.h>
  56
  57 /*
  58  * This is a horrible kludge, we eventually need to abstract this
  59  * generic PHY stuff, so the  standard phy mode defines can be
  60  * easily used from arch code.
  61  */
  62 #include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
  63
  64 bd_t __res;
  65
  66 static struct ibm44x_clocks clocks __initdata;
  67
  68 /*
  69  * Ebony external IRQ triggering/polarity settings
  70  */
  71 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
  72         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ0: PCI slot 0 */
  73         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ1: PCI slot 1 */
  74         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ2: PCI slot 2 */
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ3: PCI slot 3 */
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ4: IRDA */
  77         (IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE),      /* IRQ5: SMI pushbutton */
  78         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ6: PHYs */
  79         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ7: AUX */
  80         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ8: EXT */
  81         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ9: EXT */
  82         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ10: EXT */
  83         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ11: EXT */
  84         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ12: EXT */
  85 };
  86
  87 static void __init
  88 ebony_calibrate_decr(void)
  89 {
  90         unsigned int freq;
  91
  92         /*
  93          * Determine system clock speed
  94          *
  95          * If we are on Rev. B silicon, then use
  96          * default external system clock.  If we are
  97          * on Rev. C silicon then errata forces us to
  98          * use the internal clock.
  99          */
 100         switch (PVR_REV(mfspr(SPRN_PVR))) {
 101                 case PVR_REV(PVR_440GP_RB):
 102                         freq = EBONY_440GP_RB_SYSCLK;
 103                         break;
 104                 case PVR_REV(PVR_440GP_RC1):
 105                 default:
 106                         freq = EBONY_440GP_RC_SYSCLK;
 107                         break;
 108         }
 109
 110         ibm44x_calibrate_decr(freq);
 111 }
 112
 113 static int
 114 ebony_show_cpuinfo(struct seq_file *m)
 115 {
 116         seq_printf(m, "vendor\t\t: IBM\n");
 117         seq_printf(m, "machine\t\t: Ebony\n");
 118
 119         return 0;
 120 }
 121
 122 static inline int
 123 ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 124 {
 125         static char pci_irq_table[][4] =
 126         /*
 127          *      PCI IDSEL/INTPIN->INTLINE
 128          *         A   B   C   D
 129          */
 130         {
 131                 { 23, 23, 23, 23 },     /* IDSEL 1 - PCI Slot 0 */
 132                 { 24, 24, 24, 24 },     /* IDSEL 2 - PCI Slot 1 */
 133                 { 25, 25, 25, 25 },     /* IDSEL 3 - PCI Slot 2 */
 134                 { 26, 26, 26, 26 },     /* IDSEL 4 - PCI Slot 3 */
 135         };
 136
 137         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 138         return PCI_IRQ_TABLE_LOOKUP;
 139 }
 140
 141 #define PCIX_WRITEL(value, offset) \
 142         (writel(value, pcix_reg_base + offset))
 143
 144 /*
 145  * FIXME: This is only here to "make it work".  This will move
 146  * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
 147  * configuration library. -Matt
 148  */
 149 static void __init
 150 ebony_setup_pcix(void)
 151 {
 152         void *pcix_reg_base;
 153
 154         pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 155
 156         /* Disable all windows */
 157         PCIX_WRITEL(0, PCIX0_POM0SA);
 158         PCIX_WRITEL(0, PCIX0_POM1SA);
 159         PCIX_WRITEL(0, PCIX0_POM2SA);
 160         PCIX_WRITEL(0, PCIX0_PIM0SA);
 161         PCIX_WRITEL(0, PCIX0_PIM1SA);
 162         PCIX_WRITEL(0, PCIX0_PIM2SA);
 163
 164         /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
 165         PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
 166         PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
 167         PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 168         PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
 169         PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
 170
 171         /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 172         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 173         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 174         PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
 175
 176         eieio();
 177 }
 178
 179 static void __init
 180 ebony_setup_hose(void)
 181 {
 182         struct pci_controller *hose;
 183
 184         /* Configure windows on the PCI-X host bridge */
 185         ebony_setup_pcix();
 186
 187         hose = pcibios_alloc_controller();
 188
 189         if (!hose)
 190                 return;
 191
 192         hose->first_busno = 0;
 193         hose->last_busno = 0xff;
 194
 195         hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
 196
 197         pci_init_resource(&hose->io_resource,
 198                         EBONY_PCI_LOWER_IO,
 199                         EBONY_PCI_UPPER_IO,
 200                         IORESOURCE_IO,
 201                         "PCI host bridge");
 202
 203         pci_init_resource(&hose->mem_resources[0],
 204                         EBONY_PCI_LOWER_MEM,
 205                         EBONY_PCI_UPPER_MEM,
 206                         IORESOURCE_MEM,
 207                         "PCI host bridge");
 208
 209         hose->io_space.start = EBONY_PCI_LOWER_IO;
 210         hose->io_space.end = EBONY_PCI_UPPER_IO;
 211         hose->mem_space.start = EBONY_PCI_LOWER_MEM;
 212         hose->mem_space.end = EBONY_PCI_UPPER_MEM;
 213         isa_io_base =
 214                 (unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
 215         hose->io_base_virt = (void *)isa_io_base;
 216
 217         setup_indirect_pci(hose,
 218                         EBONY_PCI_CFGA_PLB32,
 219                         EBONY_PCI_CFGD_PLB32);
 220         hose->set_cfg_type = 1;
 221
 222         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 223
 224         ppc_md.pci_swizzle = common_swizzle;
 225         ppc_md.pci_map_irq = ebony_map_irq;
 226 }
 227
 228 TODC_ALLOC();
 229
 230 static void __init
 231 ebony_early_serial_map(void)
 232 {
 233         struct uart_port port;
 234
 235         /* Setup ioremapped serial port access */
 236         memset(&port, 0, sizeof(port));
 237         port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
 238         port.irq = 0;
 239         port.uartclk = clocks.uart0;
 240         port.regshift = 0;
 241         port.iotype = SERIAL_IO_MEM;
 242         port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
 243         port.line = 0;
 244
 245         if (early_serial_setup(&port) != 0) {
 246                 printk("Early serial init of port 0 failed\n");
 247         }
 248
 249 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 250         /* Configure debug serial access */
 251         gen550_init(0, &port);
 252 #endif
 253
 254         port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
 255         port.irq = 1;
 256         port.uartclk = clocks.uart1;
 257         port.line = 1;
 258
 259         if (early_serial_setup(&port) != 0) {
 260                 printk("Early serial init of port 1 failed\n");
 261         }
 262
 263 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 264         /* Configure debug serial access */
 265         gen550_init(1, &port);
 266 #endif
 267 }
 268
 269 static void __init
 270 ebony_setup_arch(void)
 271 {
 272         struct ocp_def *def;
 273         struct ocp_func_emac_data *emacdata;
 274
 275         /* Set mac_addr for each EMAC */
 276         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 277         emacdata = def->additions;
 278         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 279         emacdata->phy_mode = PHY_MODE_RMII;
 280         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 281
 282         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
 283         emacdata = def->additions;
 284         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 285         emacdata->phy_mode = PHY_MODE_RMII;
 286         memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 287
 288         /*
 289          * Determine various clocks.
 290          * To be completely correct we should get SysClk
 291          * from FPGA, because it can be changed by on-board switches
 292          * --ebs
 293          */
 294         ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
 295         ocp_sys_info.opb_bus_freq = clocks.opb;
 296
 297         /* Setup TODC access */
 298         TODC_INIT(TODC_TYPE_DS1743,
 299                         0,
 300                         0,
 301                         ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
 302                         8);
 303
 304         /* init to some ~sane value until calibrate_delay() runs */
 305         loops_per_jiffy = 50000000/HZ;
 306
 307         /* Setup PCI host bridge */
 308         ebony_setup_hose();
 309
 310 #ifdef CONFIG_BLK_DEV_INITRD
 311         if (initrd_start)
 312                 ROOT_DEV = Root_RAM0;
 313         else
 314 #endif
 315 #ifdef CONFIG_ROOT_NFS
 316                 ROOT_DEV = Root_NFS;
 317 #else
 318                 ROOT_DEV = Root_HDA1;
 319 #endif
 320
 321         ebony_early_serial_map();
 322
 323         /* Identify the system */
 324         printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
 325 }
 326
 327 void __init platform_init(unsigned long r3, unsigned long r4,
 328                 unsigned long r5, unsigned long r6, unsigned long r7)
 329 {
 330         parse_bootinfo(find_bootinfo());
 331
 332         /*
 333          * If we were passed in a board information, copy it into the
 334          * residual data area.
 335          */
 336         if (r3)
 337                 __res = *(bd_t *)(r3 + KERNELBASE);
 338
 339         ibm44x_platform_init();
 340
 341         ppc_md.setup_arch = ebony_setup_arch;
 342         ppc_md.show_cpuinfo = ebony_show_cpuinfo;
 343         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 344
 345         ppc_md.calibrate_decr = ebony_calibrate_decr;
 346         ppc_md.time_init = todc_time_init;
 347         ppc_md.set_rtc_time = todc_set_rtc_time;
 348         ppc_md.get_rtc_time = todc_get_rtc_time;
 349
 350         ppc_md.nvram_read_val = todc_direct_read_val;
 351         ppc_md.nvram_write_val = todc_direct_write_val;
 352 #ifdef CONFIG_KGDB
 353         ppc_md.early_serial_map = ebony_early_serial_map;
 354 #endif
 355 }
 356