arch/ppc/platforms/4xx/ash.c

   1 /*
   2  * arch/ppc/platforms/4xx/ash.c
   3  *
   4  * Support for the IBM NP405H ash eval board
   5  *
   6  * Author: Armin Kuster <akuster@mvista.com>
   7  *
   8  * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
   9  * the terms of the GNU General Public License version 2.  This program
  10  * is licensed "as is" without any warranty of any kind, whether express
  11  * or implied.
  12  */
  13 #include <linux/config.h>
  14 #include <linux/init.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/pci.h>
  17
  18 #include <asm/machdep.h>
  19 #include <asm/pci-bridge.h>
  20 #include <asm/io.h>
  21 #include <asm/ocp.h>
  22 #include <asm/ibm_ocp_pci.h>
  23 #include <asm/todc.h>
  24
  25 #ifdef DEBUG
  26 #define DBG(x...) printk(x)
  27 #else
  28 #define DBG(x...)
  29 #endif
  30
  31 void *ash_rtc_base;
  32
  33 /* Some IRQs unique to Walnut.
  34  * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
  35  */
  36 int __init
  37 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  38 {
  39         static char pci_irq_table[][4] =
  40             /*
  41              *      PCI IDSEL/INTPIN->INTLINE
  42              *      A       B       C       D
  43              */
  44         {
  45                 {24, 24, 24, 24},       /* IDSEL 1 - PCI slot 1 */
  46                 {25, 25, 25, 25},       /* IDSEL 2 - PCI slot 2 */
  47                 {26, 26, 26, 26},       /* IDSEL 3 - PCI slot 3 */
  48                 {27, 27, 27, 27},       /* IDSEL 4 - PCI slot 4 */
  49         };
  50
  51         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
  52         return PCI_IRQ_TABLE_LOOKUP;
  53 }
  54
  55 void __init
  56 ash_setup_arch(void)
  57 {
  58         ppc4xx_setup_arch();
  59
  60         ibm_ocp_set_emac(0, 3);
  61
  62 #ifdef CONFIG_DEBUG_BRINGUP
  63         int i;
  64         printk("\n");
  65         printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
  66         printk("\n");
  67         printk("bi_s_version\t %s\n", bip->bi_s_version);
  68         printk("bi_r_version\t %s\n", bip->bi_r_version);
  69         printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
  70                bip->bi_memsize / (1024 * 1000));
  71         for (i = 0; i < EMAC_NUMS; i++) {
  72                 printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", i,
  73                        bip->bi_enetaddr[i][0], bip->bi_enetaddr[i][1],
  74                        bip->bi_enetaddr[i][2], bip->bi_enetaddr[i][3],
  75                        bip->bi_enetaddr[i][4], bip->bi_enetaddr[i][5]);
  76         }
  77         printk("bi_pci_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
  78                bip->bi_pci_enetaddr[0], bip->bi_pci_enetaddr[1],
  79                bip->bi_pci_enetaddr[2], bip->bi_pci_enetaddr[3],
  80                bip->bi_pci_enetaddr[4], bip->bi_pci_enetaddr[5]);
  81
  82         printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
  83                bip->bi_intfreq, bip->bi_intfreq / 1000000);
  84
  85         printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
  86                bip->bi_busfreq, bip->bi_busfreq / 1000000);
  87         printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n",
  88                bip->bi_pci_busfreq, bip->bi_pci_busfreq / 1000000);
  89
  90         printk("\n");
  91 #endif
  92         /* RTC step for ash */
  93         ash_rtc_base = (void *) ASH_RTC_VADDR;
  94         TODC_INIT(TODC_TYPE_DS1743, ash_rtc_base, ash_rtc_base, ash_rtc_base,
  95                   8);
  96 }
  97
  98 void __init
  99 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 100 {
 101         /*
 102          * Expected PCI mapping:
 103          *
 104          *  PLB addr             PCI memory addr
 105          *  ---------------------       ---------------------
 106          *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
 107          *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
 108          *
 109          *  PLB addr             PCI io addr
 110          *  ---------------------       ---------------------
 111          *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
 112          *
 113          * The following code is simplified by assuming that the bootrom
 114          * has been well behaved in following this mapping.
 115          */
 116
 117 #ifdef DEBUG
 118         int i;
 119
 120         printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
 121         printk("PCI bridge regs before fixup \n");
 122         for (i = 0; i <= 2; i++) {
 123                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 124                 printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 125                 printk(" pmm%dpcila\t0x%x\n", i,
 126                        in_le32(&(pcip->pmm[i].pcila)));
 127                 printk(" pmm%dpciha\t0x%x\n", i,
 128                        in_le32(&(pcip->pmm[i].pciha)));
 129         }
 130         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 131         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 132         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 133         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 134         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 135                 early_read_config_dword(hose, hose->first_busno,
 136                                         PCI_FUNC(hose->first_busno), bar,
 137                                         &bar_response);
 138                 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
 139                     hose->first_busno, PCI_SLOT(hose->first_busno),
 140                     PCI_FUNC(hose->first_busno), bar, bar_response);
 141         }
 142
 143 #endif
 144         if (ppc_md.progress)
 145                 ppc_md.progress("bios_fixup(): enter", 0x800);
 146
 147         /* added for IBM boot rom version 1.15 bios bar changes  -AK */
 148
 149         /* Disable region first */
 150         out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 151         /* PLB starting addr, PCI: 0x80000000 */
 152         out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
 153         /* PCI start addr, 0x80000000 */
 154         out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
 155         /* 512MB range of PLB to PCI */
 156         out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
 157         /* Enable no pre-fetch, enable region */
 158         out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
 159                                                 (PPC405_PCI_UPPER_MEM -
 160                                                  PPC405_PCI_MEM_BASE)) | 0x01));
 161
 162         /* Disable region one */
 163         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 164         out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
 165         out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
 166         out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
 167         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 168
 169         /* Disable region two */
 170         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 171         out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
 172         out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
 173         out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
 174         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 175
 176         /* Enable PTM1 and PTM2, mapped to PLB address 0. */
 177
 178         out_le32((void *) &(pcip->ptm1la), 0x00000000);
 179         out_le32((void *) &(pcip->ptm1ms), 0x00000001);
 180         out_le32((void *) &(pcip->ptm2la), 0x00000000);
 181         out_le32((void *) &(pcip->ptm2ms), 0x00000001);
 182
 183         /* Write zero to PTM1 BAR. */
 184
 185         early_write_config_dword(hose, hose->first_busno,
 186                                  PCI_FUNC(hose->first_busno),
 187                                  PCI_BASE_ADDRESS_1,
 188                                  0x00000000);
 189
 190         /* Disable PTM2 (unused) */
 191
 192         out_le32((void *) &(pcip->ptm2la), 0x00000000);
 193         out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 194
 195         /* end work arround */
 196         if (ppc_md.progress)
 197                 ppc_md.progress("bios_fixup(): done", 0x800);
 198
 199 #ifdef DEBUG
 200         printk("PCI bridge regs after fixup \n");
 201         for (i = 0; i <= 2; i++) {
 202                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 203                 printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 204                 printk(" pmm%dpcila\t0x%x\n", i,
 205                        in_le32(&(pcip->pmm[i].pcila)));
 206                 printk(" pmm%dpciha\t0x%x\n", i,
 207                        in_le32(&(pcip->pmm[i].pciha)));
 208         }
 209         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 210         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 211         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 212         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 213
 214         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 215                 early_read_config_dword(hose, hose->first_busno,
 216                                         PCI_FUNC(hose->first_busno), bar,
 217                                         &bar_response);
 218                 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
 219                     hose->first_busno, PCI_SLOT(hose->first_busno),
 220                     PCI_FUNC(hose->first_busno), bar, bar_response);
 221         }
 222
 223
 224 #endif
 225 }
 226
 227 void __init
 228 ash_map_io(void)
 229 {
 230         ppc4xx_map_io();
 231         io_block_mapping(ASH_RTC_VADDR, ASH_RTC_PADDR, ASH_RTC_SIZE, _PAGE_IO);
 232 }
 233
 234 void __init
 235 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 236               unsigned long r6, unsigned long r7)
 237 {
 238         ppc4xx_init(r3, r4, r5, r6, r7);
 239
 240         ppc_md.setup_arch = ash_setup_arch;
 241         ppc_md.setup_io_mappings = ash_map_io;
 242
 243 #ifdef CONFIG_PPC_RTC
 244         ppc_md.time_init = todc_time_init;
 245         ppc_md.set_rtc_time = todc_set_rtc_time;
 246         ppc_md.get_rtc_time = todc_get_rtc_time;
 247         ppc_md.nvram_read_val = todc_direct_read_val;
 248         ppc_md.nvram_write_val = todc_direct_write_val;
 249 #endif
 250 }