arch/i386/kernel/cpu/mcheck/p4.c

   1 /*
   2  * P4 specific Machine Check Exception Reporting
   3  */
   4
   5 #include <linux/init.h>
   6 #include <linux/types.h>
   7 #include <linux/kernel.h>
   8 #include <linux/config.h>
   9 #include <linux/irq.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/smp.h>
  12
  13 #include <asm/processor.h>
  14 #include <asm/system.h>
  15 #include <asm/msr.h>
  16 #include <asm/apic.h>
  17
  18 #include "mce.h"
  19
  20 /* as supported by the P4/Xeon family */
  21 struct intel_mce_extended_msrs {
  22         u32 eax;
  23         u32 ebx;
  24         u32 ecx;
  25         u32 edx;
  26         u32 esi;
  27         u32 edi;
  28         u32 ebp;
  29         u32 esp;
  30         u32 eflags;
  31         u32 eip;
  32         /* u32 *reserved[]; */
  33 };
  34
  35 static int mce_num_extended_msrs = 0;
  36
  37
  38 #ifdef CONFIG_X86_MCE_P4THERMAL
  39 static void unexpected_thermal_interrupt(struct pt_regs *regs)
  40 {
  41         printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
  42                         smp_processor_id());
  43         add_taint(TAINT_MACHINE_CHECK);
  44 }
  45
  46 /* P4/Xeon Thermal transition interrupt handler */
  47 static void intel_thermal_interrupt(struct pt_regs *regs)
  48 {
  49         u32 l, h;
  50         unsigned int cpu = smp_processor_id();
  51         static unsigned long next[NR_CPUS];
  52
  53         ack_APIC_irq();
  54
  55         if (time_after(next[cpu], jiffies))
  56                 return;
  57
  58         next[cpu] = jiffies + HZ*5;
  59         rdmsr(MSR_IA32_THERM_STATUS, l, h);
  60         if (l & 0x1) {
  61                 printk(KERN_EMERG "CPU%d: Temperature above threshold\n", cpu);
  62                 printk(KERN_EMERG "CPU%d: Running in modulated clock mode\n",
  63                                 cpu);
  64                 add_taint(TAINT_MACHINE_CHECK);
  65         } else {
  66                 printk(KERN_INFO "CPU%d: Temperature/speed normal\n", cpu);
  67         }
  68 }
  69
  70 /* Thermal interrupt handler for this CPU setup */
  71 static void (*vendor_thermal_interrupt)(struct pt_regs *regs) = unexpected_thermal_interrupt;
  72
  73 fastcall void smp_thermal_interrupt(struct pt_regs *regs)
  74 {
  75         irq_enter();
  76         vendor_thermal_interrupt(regs);
  77         irq_exit();
  78 }
  79
  80 /* P4/Xeon Thermal regulation detect and init */
  81 static void __init intel_init_thermal(struct cpuinfo_x86 *c)
  82 {
  83         u32 l, h;
  84         unsigned int cpu = smp_processor_id();
  85
  86         /* Thermal monitoring */
  87         if (!cpu_has(c, X86_FEATURE_ACPI))
  88                 return; /* -ENODEV */
  89
  90         /* Clock modulation */
  91         if (!cpu_has(c, X86_FEATURE_ACC))
  92                 return; /* -ENODEV */
  93
  94         /* first check if its enabled already, in which case there might
  95          * be some SMM goo which handles it, so we can't even put a handler
  96          * since it might be delivered via SMI already -zwanem.
  97          */
  98         rdmsr (MSR_IA32_MISC_ENABLE, l, h);
  99         h = apic_read(APIC_LVTTHMR);
 100         if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
 101                 printk(KERN_DEBUG "CPU%d: Thermal monitoring handled by SMI\n",
 102                                 cpu);
 103                 return; /* -EBUSY */
 104         }
 105
 106         /* check whether a vector already exists, temporarily masked? */
 107         if (h & APIC_VECTOR_MASK) {
 108                 printk(KERN_DEBUG "CPU%d: Thermal LVT vector (%#x) already "
 109                                 "installed\n",
 110                         cpu, (h & APIC_VECTOR_MASK));
 111                 return; /* -EBUSY */
 112         }
 113
 114         /* The temperature transition interrupt handler setup */
 115         h = THERMAL_APIC_VECTOR;                /* our delivery vector */
 116         h |= (APIC_DM_FIXED | APIC_LVT_MASKED); /* we'll mask till we're ready */
 117         apic_write_around(APIC_LVTTHMR, h);
 118
 119         rdmsr (MSR_IA32_THERM_INTERRUPT, l, h);
 120         wrmsr (MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
 121
 122         /* ok we're good to go... */
 123         vendor_thermal_interrupt = intel_thermal_interrupt;
 124
 125         rdmsr (MSR_IA32_MISC_ENABLE, l, h);
 126         wrmsr (MSR_IA32_MISC_ENABLE, l | (1<<3), h);
 127
 128         l = apic_read (APIC_LVTTHMR);
 129         apic_write_around (APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
 130         printk (KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);
 131         return;
 132 }
 133 #endif /* CONFIG_X86_MCE_P4THERMAL */
 134
 135
 136 /* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
 137 static inline int intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
 138 {
 139         u32 h;
 140
 141         if (mce_num_extended_msrs == 0)
 142                 goto done;
 143
 144         rdmsr (MSR_IA32_MCG_EAX, r->eax, h);
 145         rdmsr (MSR_IA32_MCG_EBX, r->ebx, h);
 146         rdmsr (MSR_IA32_MCG_ECX, r->ecx, h);
 147         rdmsr (MSR_IA32_MCG_EDX, r->edx, h);
 148         rdmsr (MSR_IA32_MCG_ESI, r->esi, h);
 149         rdmsr (MSR_IA32_MCG_EDI, r->edi, h);
 150         rdmsr (MSR_IA32_MCG_EBP, r->ebp, h);
 151         rdmsr (MSR_IA32_MCG_ESP, r->esp, h);
 152         rdmsr (MSR_IA32_MCG_EFLAGS, r->eflags, h);
 153         rdmsr (MSR_IA32_MCG_EIP, r->eip, h);
 154
 155         /* can we rely on kmalloc to do a dynamic
 156          * allocation for the reserved registers?
 157          */
 158 done:
 159         return mce_num_extended_msrs;
 160 }
 161
 162 static fastcall void intel_machine_check(struct pt_regs * regs, long error_code)
 163 {
 164         int recover=1;
 165         u32 alow, ahigh, high, low;
 166         u32 mcgstl, mcgsth;
 167         int i;
 168         struct intel_mce_extended_msrs dbg;
 169
 170         rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
 171         if (mcgstl & (1<<0))    /* Recoverable ? */
 172                 recover=0;
 173
 174         printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
 175                 smp_processor_id(), mcgsth, mcgstl);
 176
 177         if (intel_get_extended_msrs(&dbg)) {
 178                 printk (KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n",
 179                         smp_processor_id(), dbg.eip, dbg.eflags);
 180                 printk (KERN_DEBUG "\teax: %08x ebx: %08x ecx: %08x edx: %08x\n",
 181                         dbg.eax, dbg.ebx, dbg.ecx, dbg.edx);
 182                 printk (KERN_DEBUG "\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
 183                         dbg.esi, dbg.edi, dbg.ebp, dbg.esp);
 184         }
 185
 186         for (i=0; i<nr_mce_banks; i++) {
 187                 rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
 188                 if (high & (1<<31)) {
 189                         if (high & (1<<29))
 190                                 recover |= 1;
 191                         if (high & (1<<25))
 192                                 recover |= 2;
 193                         printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
 194                         high &= ~(1<<31);
 195                         if (high & (1<<27)) {
 196                                 rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
 197                                 printk ("[%08x%08x]", ahigh, alow);
 198                         }
 199                         if (high & (1<<26)) {
 200                                 rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
 201                                 printk (" at %08x%08x", ahigh, alow);
 202                         }
 203                         printk ("\n");
 204                 }
 205         }
 206
 207         if (recover & 2)
 208                 panic ("CPU context corrupt");
 209         if (recover & 1)
 210                 panic ("Unable to continue");
 211
 212         printk(KERN_EMERG "Attempting to continue.\n");
 213         /*
 214          * Do not clear the MSR_IA32_MCi_STATUS if the error is not
 215          * recoverable/continuable.This will allow BIOS to look at the MSRs
 216          * for errors if the OS could not log the error.
 217          */
 218         for (i=0; i<nr_mce_banks; i++) {
 219                 u32 msr;
 220                 msr = MSR_IA32_MC0_STATUS+i*4;
 221                 rdmsr (msr, low, high);
 222                 if (high&(1<<31)) {
 223                         /* Clear it */
 224                         wrmsr(msr, 0UL, 0UL);
 225                         /* Serialize */
 226                         wmb();
 227                         add_taint(TAINT_MACHINE_CHECK);
 228                 }
 229         }
 230         mcgstl &= ~(1<<2);
 231         wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
 232 }
 233
 234
 235 void __init intel_p4_mcheck_init(struct cpuinfo_x86 *c)
 236 {
 237         u32 l, h;
 238         int i;
 239
 240         machine_check_vector = intel_machine_check;
 241         wmb();
 242
 243         printk (KERN_INFO "Intel machine check architecture supported.\n");
 244         rdmsr (MSR_IA32_MCG_CAP, l, h);
 245         if (l & (1<<8)) /* Control register present ? */
 246                 wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
 247         nr_mce_banks = l & 0xff;
 248
 249         for (i=0; i<nr_mce_banks; i++) {
 250                 wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
 251                 wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
 252         }
 253
 254         set_in_cr4 (X86_CR4_MCE);
 255         printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
 256                 smp_processor_id());
 257
 258         /* Check for P4/Xeon extended MCE MSRs */
 259         rdmsr (MSR_IA32_MCG_CAP, l, h);
 260         if (l & (1<<9)) {/* MCG_EXT_P */
 261                 mce_num_extended_msrs = (l >> 16) & 0xff;
 262                 printk (KERN_INFO "CPU%d: Intel P4/Xeon Extended MCE MSRs (%d)"
 263                                 " available\n",
 264                         smp_processor_id(), mce_num_extended_msrs);
 265
 266 #ifdef CONFIG_X86_MCE_P4THERMAL
 267                 /* Check for P4/Xeon Thermal monitor */
 268                 intel_init_thermal(c);
 269 #endif
 270         }
 271 }