drivers/net/sfc/net_driver.h

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2005-2008 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 /* Common definitions for all Efx net driver code */
  12
  13 #ifndef EFX_NET_DRIVER_H
  14 #define EFX_NET_DRIVER_H
  15
  16 #include <linux/version.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/timer.h>
  22 #include <linux/mii.h>
  23 #include <linux/list.h>
  24 #include <linux/pci.h>
  25 #include <linux/device.h>
  26 #include <linux/highmem.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/inet_lro.h>
  29 #include <linux/i2c.h>
  30
  31 #include "enum.h"
  32 #include "bitfield.h"
  33
  34 #define EFX_MAX_LRO_DESCRIPTORS 8
  35 #define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS
  36
  37 /**************************************************************************
  38  *
  39  * Build definitions
  40  *
  41  **************************************************************************/
  42 #ifndef EFX_DRIVER_NAME
  43 #define EFX_DRIVER_NAME "sfc"
  44 #endif
  45 #define EFX_DRIVER_VERSION      "2.2"
  46
  47 #ifdef EFX_ENABLE_DEBUG
  48 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
  49 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
  50 #else
  51 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
  52 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
  53 #endif
  54
  55 /* Un-rate-limited logging */
  56 #define EFX_ERR(efx, fmt, args...) \
  57 dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args)
  58
  59 #define EFX_INFO(efx, fmt, args...) \
  60 dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args)
  61
  62 #ifdef EFX_ENABLE_DEBUG
  63 #define EFX_LOG(efx, fmt, args...) \
  64 dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
  65 #else
  66 #define EFX_LOG(efx, fmt, args...) \
  67 dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
  68 #endif
  69
  70 #define EFX_TRACE(efx, fmt, args...) do {} while (0)
  71
  72 #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
  73
  74 /* Rate-limited logging */
  75 #define EFX_ERR_RL(efx, fmt, args...) \
  76 do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
  77
  78 #define EFX_INFO_RL(efx, fmt, args...) \
  79 do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
  80
  81 #define EFX_LOG_RL(efx, fmt, args...) \
  82 do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
  83
  84 /**************************************************************************
  85  *
  86  * Efx data structures
  87  *
  88  **************************************************************************/
  89
  90 #define EFX_MAX_CHANNELS 32
  91 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
  92
  93 #define EFX_TX_QUEUE_OFFLOAD_CSUM       0
  94 #define EFX_TX_QUEUE_NO_CSUM            1
  95 #define EFX_TX_QUEUE_COUNT              2
  96
  97 /**
  98  * struct efx_special_buffer - An Efx special buffer
  99  * @addr: CPU base address of the buffer
 100  * @dma_addr: DMA base address of the buffer
 101  * @len: Buffer length, in bytes
 102  * @index: Buffer index within controller;s buffer table
 103  * @entries: Number of buffer table entries
 104  *
 105  * Special buffers are used for the event queues and the TX and RX
 106  * descriptor queues for each channel.  They are *not* used for the
 107  * actual transmit and receive buffers.
 108  *
 109  * Note that for Falcon, TX and RX descriptor queues live in host memory.
 110  * Allocation and freeing procedures must take this into account.
 111  */
 112 struct efx_special_buffer {
 113         void *addr;
 114         dma_addr_t dma_addr;
 115         unsigned int len;
 116         int index;
 117         int entries;
 118 };
 119
 120 /**
 121  * struct efx_tx_buffer - An Efx TX buffer
 122  * @skb: The associated socket buffer.
 123  *      Set only on the final fragment of a packet; %NULL for all other
 124  *      fragments.  When this fragment completes, then we can free this
 125  *      skb.
 126  * @tsoh: The associated TSO header structure, or %NULL if this
 127  *      buffer is not a TSO header.
 128  * @dma_addr: DMA address of the fragment.
 129  * @len: Length of this fragment.
 130  *      This field is zero when the queue slot is empty.
 131  * @continuation: True if this fragment is not the end of a packet.
 132  * @unmap_single: True if pci_unmap_single should be used.
 133  * @unmap_len: Length of this fragment to unmap
 134  */
 135 struct efx_tx_buffer {
 136         const struct sk_buff *skb;
 137         struct efx_tso_header *tsoh;
 138         dma_addr_t dma_addr;
 139         unsigned short len;
 140         bool continuation;
 141         bool unmap_single;
 142         unsigned short unmap_len;
 143 };
 144
 145 /**
 146  * struct efx_tx_queue - An Efx TX queue
 147  *
 148  * This is a ring buffer of TX fragments.
 149  * Since the TX completion path always executes on the same
 150  * CPU and the xmit path can operate on different CPUs,
 151  * performance is increased by ensuring that the completion
 152  * path and the xmit path operate on different cache lines.
 153  * This is particularly important if the xmit path is always
 154  * executing on one CPU which is different from the completion
 155  * path.  There is also a cache line for members which are
 156  * read but not written on the fast path.
 157  *
 158  * @efx: The associated Efx NIC
 159  * @queue: DMA queue number
 160  * @channel: The associated channel
 161  * @buffer: The software buffer ring
 162  * @txd: The hardware descriptor ring
 163  * @flushed: Used when handling queue flushing
 164  * @read_count: Current read pointer.
 165  *      This is the number of buffers that have been removed from both rings.
 166  * @stopped: Stopped count.
 167  *      Set if this TX queue is currently stopping its port.
 168  * @insert_count: Current insert pointer
 169  *      This is the number of buffers that have been added to the
 170  *      software ring.
 171  * @write_count: Current write pointer
 172  *      This is the number of buffers that have been added to the
 173  *      hardware ring.
 174  * @old_read_count: The value of read_count when last checked.
 175  *      This is here for performance reasons.  The xmit path will
 176  *      only get the up-to-date value of read_count if this
 177  *      variable indicates that the queue is full.  This is to
 178  *      avoid cache-line ping-pong between the xmit path and the
 179  *      completion path.
 180  * @tso_headers_free: A list of TSO headers allocated for this TX queue
 181  *      that are not in use, and so available for new TSO sends. The list
 182  *      is protected by the TX queue lock.
 183  * @tso_bursts: Number of times TSO xmit invoked by kernel
 184  * @tso_long_headers: Number of packets with headers too long for standard
 185  *      blocks
 186  * @tso_packets: Number of packets via the TSO xmit path
 187  */
 188 struct efx_tx_queue {
 189         /* Members which don't change on the fast path */
 190         struct efx_nic *efx ____cacheline_aligned_in_smp;
 191         int queue;
 192         struct efx_channel *channel;
 193         struct efx_nic *nic;
 194         struct efx_tx_buffer *buffer;
 195         struct efx_special_buffer txd;
 196         bool flushed;
 197
 198         /* Members used mainly on the completion path */
 199         unsigned int read_count ____cacheline_aligned_in_smp;
 200         int stopped;
 201
 202         /* Members used only on the xmit path */
 203         unsigned int insert_count ____cacheline_aligned_in_smp;
 204         unsigned int write_count;
 205         unsigned int old_read_count;
 206         struct efx_tso_header *tso_headers_free;
 207         unsigned int tso_bursts;
 208         unsigned int tso_long_headers;
 209         unsigned int tso_packets;
 210 };
 211
 212 /**
 213  * struct efx_rx_buffer - An Efx RX data buffer
 214  * @dma_addr: DMA base address of the buffer
 215  * @skb: The associated socket buffer, if any.
 216  *      If both this and page are %NULL, the buffer slot is currently free.
 217  * @page: The associated page buffer, if any.
 218  *      If both this and skb are %NULL, the buffer slot is currently free.
 219  * @data: Pointer to ethernet header
 220  * @len: Buffer length, in bytes.
 221  * @unmap_addr: DMA address to unmap
 222  */
 223 struct efx_rx_buffer {
 224         dma_addr_t dma_addr;
 225         struct sk_buff *skb;
 226         struct page *page;
 227         char *data;
 228         unsigned int len;
 229         dma_addr_t unmap_addr;
 230 };
 231
 232 /**
 233  * struct efx_rx_queue - An Efx RX queue
 234  * @efx: The associated Efx NIC
 235  * @queue: DMA queue number
 236  * @channel: The associated channel
 237  * @buffer: The software buffer ring
 238  * @rxd: The hardware descriptor ring
 239  * @added_count: Number of buffers added to the receive queue.
 240  * @notified_count: Number of buffers given to NIC (<= @added_count).
 241  * @removed_count: Number of buffers removed from the receive queue.
 242  * @add_lock: Receive queue descriptor add spin lock.
 243  *      This lock must be held in order to add buffers to the RX
 244  *      descriptor ring (rxd and buffer) and to update added_count (but
 245  *      not removed_count).
 246  * @max_fill: RX descriptor maximum fill level (<= ring size)
 247  * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
 248  *      (<= @max_fill)
 249  * @fast_fill_limit: The level to which a fast fill will fill
 250  *      (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
 251  * @min_fill: RX descriptor minimum non-zero fill level.
 252  *      This records the minimum fill level observed when a ring
 253  *      refill was triggered.
 254  * @min_overfill: RX descriptor minimum overflow fill level.
 255  *      This records the minimum fill level at which RX queue
 256  *      overflow was observed.  It should never be set.
 257  * @alloc_page_count: RX allocation strategy counter.
 258  * @alloc_skb_count: RX allocation strategy counter.
 259  * @work: Descriptor push work thread
 260  * @buf_page: Page for next RX buffer.
 261  *      We can use a single page for multiple RX buffers. This tracks
 262  *      the remaining space in the allocation.
 263  * @buf_dma_addr: Page's DMA address.
 264  * @buf_data: Page's host address.
 265  * @flushed: Use when handling queue flushing
 266  */
 267 struct efx_rx_queue {
 268         struct efx_nic *efx;
 269         int queue;
 270         struct efx_channel *channel;
 271         struct efx_rx_buffer *buffer;
 272         struct efx_special_buffer rxd;
 273
 274         int added_count;
 275         int notified_count;
 276         int removed_count;
 277         spinlock_t add_lock;
 278         unsigned int max_fill;
 279         unsigned int fast_fill_trigger;
 280         unsigned int fast_fill_limit;
 281         unsigned int min_fill;
 282         unsigned int min_overfill;
 283         unsigned int alloc_page_count;
 284         unsigned int alloc_skb_count;
 285         struct delayed_work work;
 286         unsigned int slow_fill_count;
 287
 288         struct page *buf_page;
 289         dma_addr_t buf_dma_addr;
 290         char *buf_data;
 291         bool flushed;
 292 };
 293
 294 /**
 295  * struct efx_buffer - An Efx general-purpose buffer
 296  * @addr: host base address of the buffer
 297  * @dma_addr: DMA base address of the buffer
 298  * @len: Buffer length, in bytes
 299  *
 300  * Falcon uses these buffers for its interrupt status registers and
 301  * MAC stats dumps.
 302  */
 303 struct efx_buffer {
 304         void *addr;
 305         dma_addr_t dma_addr;
 306         unsigned int len;
 307 };
 308
 309
 310 /* Flags for channel->used_flags */
 311 #define EFX_USED_BY_RX 1
 312 #define EFX_USED_BY_TX 2
 313 #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
 314
 315 enum efx_rx_alloc_method {
 316         RX_ALLOC_METHOD_AUTO = 0,
 317         RX_ALLOC_METHOD_SKB = 1,
 318         RX_ALLOC_METHOD_PAGE = 2,
 319 };
 320
 321 /**
 322  * struct efx_channel - An Efx channel
 323  *
 324  * A channel comprises an event queue, at least one TX queue, at least
 325  * one RX queue, and an associated tasklet for processing the event
 326  * queue.
 327  *
 328  * @efx: Associated Efx NIC
 329  * @channel: Channel instance number
 330  * @used_flags: Channel is used by net driver
 331  * @enabled: Channel enabled indicator
 332  * @irq: IRQ number (MSI and MSI-X only)
 333  * @irq_moderation: IRQ moderation value (in us)
 334  * @napi_dev: Net device used with NAPI
 335  * @napi_str: NAPI control structure
 336  * @reset_work: Scheduled reset work thread
 337  * @work_pending: Is work pending via NAPI?
 338  * @eventq: Event queue buffer
 339  * @eventq_read_ptr: Event queue read pointer
 340  * @last_eventq_read_ptr: Last event queue read pointer value.
 341  * @eventq_magic: Event queue magic value for driver-generated test events
 342  * @lro_mgr: LRO state
 343  * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
 344  *      and diagnostic counters
 345  * @rx_alloc_push_pages: RX allocation method currently in use for pushing
 346  *      descriptors
 347  * @rx_alloc_pop_pages: RX allocation method currently in use for popping
 348  *      descriptors
 349  * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
 350  * @n_rx_ip_frag_err: Count of RX IP fragment errors
 351  * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
 352  * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
 353  * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
 354  * @n_rx_overlength: Count of RX_OVERLENGTH errors
 355  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
 356  */
 357 struct efx_channel {
 358         struct efx_nic *efx;
 359         int channel;
 360         int used_flags;
 361         bool enabled;
 362         int irq;
 363         unsigned int irq_moderation;
 364         struct net_device *napi_dev;
 365         struct napi_struct napi_str;
 366         bool work_pending;
 367         struct efx_special_buffer eventq;
 368         unsigned int eventq_read_ptr;
 369         unsigned int last_eventq_read_ptr;
 370         unsigned int eventq_magic;
 371
 372         struct net_lro_mgr lro_mgr;
 373         int rx_alloc_level;
 374         int rx_alloc_push_pages;
 375         int rx_alloc_pop_pages;
 376
 377         unsigned n_rx_tobe_disc;
 378         unsigned n_rx_ip_frag_err;
 379         unsigned n_rx_ip_hdr_chksum_err;
 380         unsigned n_rx_tcp_udp_chksum_err;
 381         unsigned n_rx_frm_trunc;
 382         unsigned n_rx_overlength;
 383         unsigned n_skbuff_leaks;
 384
 385         /* Used to pipeline received packets in order to optimise memory
 386          * access with prefetches.
 387          */
 388         struct efx_rx_buffer *rx_pkt;
 389         bool rx_pkt_csummed;
 390
 391 };
 392
 393 /**
 394  * struct efx_blinker - S/W LED blinking context
 395  * @led_num: LED ID (board-specific meaning)
 396  * @state: Current state - on or off
 397  * @resubmit: Timer resubmission flag
 398  * @timer: Control timer for blinking
 399  */
 400 struct efx_blinker {
 401         int led_num;
 402         bool state;
 403         bool resubmit;
 404         struct timer_list timer;
 405 };
 406
 407
 408 /**
 409  * struct efx_board - board information
 410  * @type: Board model type
 411  * @major: Major rev. ('A', 'B' ...)
 412  * @minor: Minor rev. (0, 1, ...)
 413  * @init: Initialisation function
 414  * @init_leds: Sets up board LEDs
 415  * @set_fault_led: Turns the fault LED on or off
 416  * @blink: Starts/stops blinking
 417  * @monitor: Board-specific health check function
 418  * @fini: Cleanup function
 419  * @blinker: used to blink LEDs in software
 420  * @hwmon_client: I2C client for hardware monitor
 421  * @ioexp_client: I2C client for power/port control
 422  */
 423 struct efx_board {
 424         int type;
 425         int major;
 426         int minor;
 427         int (*init) (struct efx_nic *nic);
 428         /* As the LEDs are typically attached to the PHY, LEDs
 429          * have a separate init callback that happens later than
 430          * board init. */
 431         int (*init_leds)(struct efx_nic *efx);
 432         int (*monitor) (struct efx_nic *nic);
 433         void (*set_fault_led) (struct efx_nic *efx, bool state);
 434         void (*blink) (struct efx_nic *efx, bool start);
 435         void (*fini) (struct efx_nic *nic);
 436         struct efx_blinker blinker;
 437         struct i2c_client *hwmon_client, *ioexp_client;
 438 };
 439
 440 #define STRING_TABLE_LOOKUP(val, member)        \
 441         member ## _names[val]
 442
 443 enum efx_int_mode {
 444         /* Be careful if altering to correct macro below */
 445         EFX_INT_MODE_MSIX = 0,
 446         EFX_INT_MODE_MSI = 1,
 447         EFX_INT_MODE_LEGACY = 2,
 448         EFX_INT_MODE_MAX        /* Insert any new items before this */
 449 };
 450 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
 451
 452 enum phy_type {
 453         PHY_TYPE_NONE = 0,
 454         PHY_TYPE_CX4_RTMR = 1,
 455         PHY_TYPE_1G_ALASKA = 2,
 456         PHY_TYPE_10XPRESS = 3,
 457         PHY_TYPE_XFP = 4,
 458         PHY_TYPE_PM8358 = 6,
 459         PHY_TYPE_MAX    /* Insert any new items before this */
 460 };
 461
 462 #define PHY_ADDR_INVALID 0xff
 463
 464 enum nic_state {
 465         STATE_INIT = 0,
 466         STATE_RUNNING = 1,
 467         STATE_FINI = 2,
 468         STATE_DISABLED = 3,
 469         STATE_MAX,
 470 };
 471
 472 /*
 473  * Alignment of page-allocated RX buffers
 474  *
 475  * Controls the number of bytes inserted at the start of an RX buffer.
 476  * This is the equivalent of NET_IP_ALIGN [which controls the alignment
 477  * of the skb->head for hardware DMA].
 478  */
 479 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
 480 #define EFX_PAGE_IP_ALIGN 0
 481 #else
 482 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
 483 #endif
 484
 485 /*
 486  * Alignment of the skb->head which wraps a page-allocated RX buffer
 487  *
 488  * The skb allocated to wrap an rx_buffer can have this alignment. Since
 489  * the data is memcpy'd from the rx_buf, it does not need to be equal to
 490  * EFX_PAGE_IP_ALIGN.
 491  */
 492 #define EFX_PAGE_SKB_ALIGN 2
 493
 494 /* Forward declaration */
 495 struct efx_nic;
 496
 497 /* Pseudo bit-mask flow control field */
 498 enum efx_fc_type {
 499         EFX_FC_RX = 1,
 500         EFX_FC_TX = 2,
 501         EFX_FC_AUTO = 4,
 502 };
 503
 504 /**
 505  * struct efx_phy_operations - Efx PHY operations table
 506  * @init: Initialise PHY
 507  * @fini: Shut down PHY
 508  * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
 509  * @clear_interrupt: Clear down interrupt
 510  * @blink: Blink LEDs
 511  * @check_hw: Check hardware
 512  * @mmds: MMD presence mask
 513  * @loopbacks: Supported loopback modes mask
 514  */
 515 struct efx_phy_operations {
 516         int (*init) (struct efx_nic *efx);
 517         void (*fini) (struct efx_nic *efx);
 518         void (*reconfigure) (struct efx_nic *efx);
 519         void (*clear_interrupt) (struct efx_nic *efx);
 520         int (*check_hw) (struct efx_nic *efx);
 521         int (*test) (struct efx_nic *efx);
 522         int mmds;
 523         unsigned loopbacks;
 524 };
 525
 526 /**
 527  * @enum efx_phy_mode - PHY operating mode flags
 528  * @PHY_MODE_NORMAL: on and should pass traffic
 529  * @PHY_MODE_TX_DISABLED: on with TX disabled
 530  * @PHY_MODE_LOW_POWER: set to low power through MDIO
 531  * @PHY_MODE_OFF: switched off through external control
 532  * @PHY_MODE_SPECIAL: on but will not pass traffic
 533  */
 534 enum efx_phy_mode {
 535         PHY_MODE_NORMAL         = 0,
 536         PHY_MODE_TX_DISABLED    = 1,
 537         PHY_MODE_LOW_POWER      = 2,
 538         PHY_MODE_OFF            = 4,
 539         PHY_MODE_SPECIAL        = 8,
 540 };
 541
 542 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
 543 {
 544         return !!(mode & ~PHY_MODE_TX_DISABLED);
 545 }
 546
 547 /*
 548  * Efx extended statistics
 549  *
 550  * Not all statistics are provided by all supported MACs.  The purpose
 551  * is this structure is to contain the raw statistics provided by each
 552  * MAC.
 553  */
 554 struct efx_mac_stats {
 555         u64 tx_bytes;
 556         u64 tx_good_bytes;
 557         u64 tx_bad_bytes;
 558         unsigned long tx_packets;
 559         unsigned long tx_bad;
 560         unsigned long tx_pause;
 561         unsigned long tx_control;
 562         unsigned long tx_unicast;
 563         unsigned long tx_multicast;
 564         unsigned long tx_broadcast;
 565         unsigned long tx_lt64;
 566         unsigned long tx_64;
 567         unsigned long tx_65_to_127;
 568         unsigned long tx_128_to_255;
 569         unsigned long tx_256_to_511;
 570         unsigned long tx_512_to_1023;
 571         unsigned long tx_1024_to_15xx;
 572         unsigned long tx_15xx_to_jumbo;
 573         unsigned long tx_gtjumbo;
 574         unsigned long tx_collision;
 575         unsigned long tx_single_collision;
 576         unsigned long tx_multiple_collision;
 577         unsigned long tx_excessive_collision;
 578         unsigned long tx_deferred;
 579         unsigned long tx_late_collision;
 580         unsigned long tx_excessive_deferred;
 581         unsigned long tx_non_tcpudp;
 582         unsigned long tx_mac_src_error;
 583         unsigned long tx_ip_src_error;
 584         u64 rx_bytes;
 585         u64 rx_good_bytes;
 586         u64 rx_bad_bytes;
 587         unsigned long rx_packets;
 588         unsigned long rx_good;
 589         unsigned long rx_bad;
 590         unsigned long rx_pause;
 591         unsigned long rx_control;
 592         unsigned long rx_unicast;
 593         unsigned long rx_multicast;
 594         unsigned long rx_broadcast;
 595         unsigned long rx_lt64;
 596         unsigned long rx_64;
 597         unsigned long rx_65_to_127;
 598         unsigned long rx_128_to_255;
 599         unsigned long rx_256_to_511;
 600         unsigned long rx_512_to_1023;
 601         unsigned long rx_1024_to_15xx;
 602         unsigned long rx_15xx_to_jumbo;
 603         unsigned long rx_gtjumbo;
 604         unsigned long rx_bad_lt64;
 605         unsigned long rx_bad_64_to_15xx;
 606         unsigned long rx_bad_15xx_to_jumbo;
 607         unsigned long rx_bad_gtjumbo;
 608         unsigned long rx_overflow;
 609         unsigned long rx_missed;
 610         unsigned long rx_false_carrier;
 611         unsigned long rx_symbol_error;
 612         unsigned long rx_align_error;
 613         unsigned long rx_length_error;
 614         unsigned long rx_internal_error;
 615         unsigned long rx_good_lt64;
 616 };
 617
 618 /* Number of bits used in a multicast filter hash address */
 619 #define EFX_MCAST_HASH_BITS 8
 620
 621 /* Number of (single-bit) entries in a multicast filter hash */
 622 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
 623
 624 /* An Efx multicast filter hash */
 625 union efx_multicast_hash {
 626         u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
 627         efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
 628 };
 629
 630 /**
 631  * struct efx_nic - an Efx NIC
 632  * @name: Device name (net device name or bus id before net device registered)
 633  * @pci_dev: The PCI device
 634  * @type: Controller type attributes
 635  * @legacy_irq: IRQ number
 636  * @workqueue: Workqueue for port reconfigures and the HW monitor.
 637  *      Work items do not hold and must not acquire RTNL.
 638  * @reset_work: Scheduled reset workitem
 639  * @monitor_work: Hardware monitor workitem
 640  * @membase_phys: Memory BAR value as physical address
 641  * @membase: Memory BAR value
 642  * @biu_lock: BIU (bus interface unit) lock
 643  * @interrupt_mode: Interrupt mode
 644  * @i2c_adap: I2C adapter
 645  * @board_info: Board-level information
 646  * @state: Device state flag. Serialised by the rtnl_lock.
 647  * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
 648  * @tx_queue: TX DMA queues
 649  * @rx_queue: RX DMA queues
 650  * @channel: Channels
 651  * @n_rx_queues: Number of RX queues
 652  * @rx_buffer_len: RX buffer length
 653  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
 654  * @irq_status: Interrupt status buffer
 655  * @last_irq_cpu: Last CPU to handle interrupt.
 656  *      This register is written with the SMP processor ID whenever an
 657  *      interrupt is handled.  It is used by falcon_test_interrupt()
 658  *      to verify that an interrupt has occurred.
 659  * @spi_flash: SPI flash device
 660  *      This field will be %NULL if no flash device is present.
 661  * @spi_eeprom: SPI EEPROM device
 662  *      This field will be %NULL if no EEPROM device is present.
 663  * @spi_lock: SPI bus lock
 664  * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
 665  * @nic_data: Hardware dependant state
 666  * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
 667  *      @port_inhibited, efx_monitor() and efx_reconfigure_port()
 668  * @port_enabled: Port enabled indicator.
 669  *      Serialises efx_stop_all(), efx_start_all() and efx_monitor() and
 670  *      efx_reconfigure_work with kernel interfaces. Safe to read under any
 671  *      one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
 672  *      be held to modify it.
 673  * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
 674  * @port_initialized: Port initialized?
 675  * @net_dev: Operating system network device. Consider holding the rtnl lock
 676  * @rx_checksum_enabled: RX checksumming enabled
 677  * @netif_stop_count: Port stop count
 678  * @netif_stop_lock: Port stop lock
 679  * @mac_stats: MAC statistics. These include all statistics the MACs
 680  *      can provide.  Generic code converts these into a standard
 681  *      &struct net_device_stats.
 682  * @stats_buffer: DMA buffer for statistics
 683  * @stats_lock: Statistics update lock. Serialises statistics fetches
 684  * @stats_enabled: Temporarily disable statistics fetches.
 685  *      Serialised by @stats_lock
 686  * @mac_address: Permanent MAC address
 687  * @phy_type: PHY type
 688  * @phy_lock: PHY access lock
 689  * @phy_op: PHY interface
 690  * @phy_data: PHY private data (including PHY-specific stats)
 691  * @mii: PHY interface
 692  * @phy_mode: PHY operating mode. Serialised by @mac_lock.
 693  * @link_up: Link status
 694  * @link_options: Link options (MII/GMII format)
 695  * @n_link_state_changes: Number of times the link has changed state
 696  * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
 697  * @multicast_hash: Multicast hash table
 698  * @flow_control: Flow control flags - separate RX/TX so can't use link_options
 699  * @reconfigure_work: work item for dealing with PHY events
 700  * @loopback_mode: Loopback status
 701  * @loopback_modes: Supported loopback mode bitmask
 702  * @loopback_selftest: Offline self-test private state
 703  *
 704  * The @priv field of the corresponding &struct net_device points to
 705  * this.
 706  */
 707 struct efx_nic {
 708         char name[IFNAMSIZ];
 709         struct pci_dev *pci_dev;
 710         const struct efx_nic_type *type;
 711         int legacy_irq;
 712         struct workqueue_struct *workqueue;
 713         struct work_struct reset_work;
 714         struct delayed_work monitor_work;
 715         resource_size_t membase_phys;
 716         void __iomem *membase;
 717         spinlock_t biu_lock;
 718         enum efx_int_mode interrupt_mode;
 719
 720         struct i2c_adapter i2c_adap;
 721         struct efx_board board_info;
 722
 723         enum nic_state state;
 724         enum reset_type reset_pending;
 725
 726         struct efx_tx_queue tx_queue[EFX_TX_QUEUE_COUNT];
 727         struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
 728         struct efx_channel channel[EFX_MAX_CHANNELS];
 729
 730         int n_rx_queues;
 731         unsigned int rx_buffer_len;
 732         unsigned int rx_buffer_order;
 733
 734         struct efx_buffer irq_status;
 735         volatile signed int last_irq_cpu;
 736
 737         struct efx_spi_device *spi_flash;
 738         struct efx_spi_device *spi_eeprom;
 739         struct mutex spi_lock;
 740
 741         unsigned n_rx_nodesc_drop_cnt;
 742
 743         struct falcon_nic_data *nic_data;
 744
 745         struct mutex mac_lock;
 746         bool port_enabled;
 747         bool port_inhibited;
 748
 749         bool port_initialized;
 750         struct net_device *net_dev;
 751         bool rx_checksum_enabled;
 752
 753         atomic_t netif_stop_count;
 754         spinlock_t netif_stop_lock;
 755
 756         struct efx_mac_stats mac_stats;
 757         struct efx_buffer stats_buffer;
 758         spinlock_t stats_lock;
 759         bool stats_enabled;
 760
 761         unsigned char mac_address[ETH_ALEN];
 762
 763         enum phy_type phy_type;
 764         spinlock_t phy_lock;
 765         struct efx_phy_operations *phy_op;
 766         void *phy_data;
 767         struct mii_if_info mii;
 768         enum efx_phy_mode phy_mode;
 769
 770         bool link_up;
 771         unsigned int link_options;
 772         unsigned int n_link_state_changes;
 773
 774         bool promiscuous;
 775         union efx_multicast_hash multicast_hash;
 776         enum efx_fc_type flow_control;
 777         struct work_struct reconfigure_work;
 778
 779         atomic_t rx_reset;
 780         enum efx_loopback_mode loopback_mode;
 781         unsigned int loopback_modes;
 782
 783         void *loopback_selftest;
 784 };
 785
 786 static inline int efx_dev_registered(struct efx_nic *efx)
 787 {
 788         return efx->net_dev->reg_state == NETREG_REGISTERED;
 789 }
 790
 791 /* Net device name, for inclusion in log messages if it has been registered.
 792  * Use efx->name not efx->net_dev->name so that races with (un)registration
 793  * are harmless.
 794  */
 795 static inline const char *efx_dev_name(struct efx_nic *efx)
 796 {
 797         return efx_dev_registered(efx) ? efx->name : "";
 798 }
 799
 800 /**
 801  * struct efx_nic_type - Efx device type definition
 802  * @mem_bar: Memory BAR number
 803  * @mem_map_size: Memory BAR mapped size
 804  * @txd_ptr_tbl_base: TX descriptor ring base address
 805  * @rxd_ptr_tbl_base: RX descriptor ring base address
 806  * @buf_tbl_base: Buffer table base address
 807  * @evq_ptr_tbl_base: Event queue pointer table base address
 808  * @evq_rptr_tbl_base: Event queue read-pointer table base address
 809  * @txd_ring_mask: TX descriptor ring size - 1 (must be a power of two - 1)
 810  * @rxd_ring_mask: RX descriptor ring size - 1 (must be a power of two - 1)
 811  * @evq_size: Event queue size (must be a power of two)
 812  * @max_dma_mask: Maximum possible DMA mask
 813  * @tx_dma_mask: TX DMA mask
 814  * @bug5391_mask: Address mask for bug 5391 workaround
 815  * @rx_xoff_thresh: RX FIFO XOFF watermark (bytes)
 816  * @rx_xon_thresh: RX FIFO XON watermark (bytes)
 817  * @rx_buffer_padding: Padding added to each RX buffer
 818  * @max_interrupt_mode: Highest capability interrupt mode supported
 819  *      from &enum efx_init_mode.
 820  * @phys_addr_channels: Number of channels with physically addressed
 821  *      descriptors
 822  */
 823 struct efx_nic_type {
 824         unsigned int mem_bar;
 825         unsigned int mem_map_size;
 826         unsigned int txd_ptr_tbl_base;
 827         unsigned int rxd_ptr_tbl_base;
 828         unsigned int buf_tbl_base;
 829         unsigned int evq_ptr_tbl_base;
 830         unsigned int evq_rptr_tbl_base;
 831
 832         unsigned int txd_ring_mask;
 833         unsigned int rxd_ring_mask;
 834         unsigned int evq_size;
 835         u64 max_dma_mask;
 836         unsigned int tx_dma_mask;
 837         unsigned bug5391_mask;
 838
 839         int rx_xoff_thresh;
 840         int rx_xon_thresh;
 841         unsigned int rx_buffer_padding;
 842         unsigned int max_interrupt_mode;
 843         unsigned int phys_addr_channels;
 844 };
 845
 846 /**************************************************************************
 847  *
 848  * Prototypes and inline functions
 849  *
 850  *************************************************************************/
 851
 852 /* Iterate over all used channels */
 853 #define efx_for_each_channel(_channel, _efx)                            \
 854         for (_channel = &_efx->channel[0];                              \
 855              _channel < &_efx->channel[EFX_MAX_CHANNELS];               \
 856              _channel++)                                                \
 857                 if (!_channel->used_flags)                              \
 858                         continue;                                       \
 859                 else
 860
 861 /* Iterate over all used TX queues */
 862 #define efx_for_each_tx_queue(_tx_queue, _efx)                          \
 863         for (_tx_queue = &_efx->tx_queue[0];                            \
 864              _tx_queue < &_efx->tx_queue[EFX_TX_QUEUE_COUNT];           \
 865              _tx_queue++)
 866
 867 /* Iterate over all TX queues belonging to a channel */
 868 #define efx_for_each_channel_tx_queue(_tx_queue, _channel)              \
 869         for (_tx_queue = &_channel->efx->tx_queue[0];                   \
 870              _tx_queue < &_channel->efx->tx_queue[EFX_TX_QUEUE_COUNT];  \
 871              _tx_queue++)                                               \
 872                 if (_tx_queue->channel != _channel)                     \
 873                         continue;                                       \
 874                 else
 875
 876 /* Iterate over all used RX queues */
 877 #define efx_for_each_rx_queue(_rx_queue, _efx)                          \
 878         for (_rx_queue = &_efx->rx_queue[0];                            \
 879              _rx_queue < &_efx->rx_queue[_efx->n_rx_queues];            \
 880              _rx_queue++)
 881
 882 /* Iterate over all RX queues belonging to a channel */
 883 #define efx_for_each_channel_rx_queue(_rx_queue, _channel)              \
 884         for (_rx_queue = &_channel->efx->rx_queue[_channel->channel];   \
 885              _rx_queue;                                                 \
 886              _rx_queue = NULL)                                          \
 887                 if (_rx_queue->channel != _channel)                     \
 888                         continue;                                       \
 889                 else
 890
 891 /* Returns a pointer to the specified receive buffer in the RX
 892  * descriptor queue.
 893  */
 894 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
 895                                                   unsigned int index)
 896 {
 897         return (&rx_queue->buffer[index]);
 898 }
 899
 900 /* Set bit in a little-endian bitfield */
 901 static inline void set_bit_le(unsigned nr, unsigned char *addr)
 902 {
 903         addr[nr / 8] |= (1 << (nr % 8));
 904 }
 905
 906 /* Clear bit in a little-endian bitfield */
 907 static inline void clear_bit_le(unsigned nr, unsigned char *addr)
 908 {
 909         addr[nr / 8] &= ~(1 << (nr % 8));
 910 }
 911
 912
 913 /**
 914  * EFX_MAX_FRAME_LEN - calculate maximum frame length
 915  *
 916  * This calculates the maximum frame length that will be used for a
 917  * given MTU.  The frame length will be equal to the MTU plus a
 918  * constant amount of header space and padding.  This is the quantity
 919  * that the net driver will program into the MAC as the maximum frame
 920  * length.
 921  *
 922  * The 10G MAC used in Falcon requires 8-byte alignment on the frame
 923  * length, so we round up to the nearest 8.
 924  */
 925 #define EFX_MAX_FRAME_LEN(mtu) \
 926         ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */) + 7) & ~7)
 927
 928
 929 #endif /* EFX_NET_DRIVER_H */