?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
OMAP: DSS2: move run_test()
[linux-2.6/kvm.git] / drivers / video / omap2 / dss / dsi.c
blobf01c9ca0fa5fae39db1881c9a09add904b2dc4f8
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/semaphore.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/kthread.h>
35 #include <linux/wait.h>
36
37 #include <plat/display.h>
38 #include <plat/clock.h>
39
40 #include "dss.h"
41
42 /*#define VERBOSE_IRQ*/
43 #define DSI_CATCH_MISSING_TE
44
45 #define DSI_BASE 0x4804FC00
46
47 struct dsi_reg { u16 idx; };
48
49 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
50
51 #define DSI_SZ_REGS SZ_1K
52 /* DSI Protocol Engine */
53
54 #define DSI_REVISION DSI_REG(0x0000)
55 #define DSI_SYSCONFIG DSI_REG(0x0010)
56 #define DSI_SYSSTATUS DSI_REG(0x0014)
57 #define DSI_IRQSTATUS DSI_REG(0x0018)
58 #define DSI_IRQENABLE DSI_REG(0x001C)
59 #define DSI_CTRL DSI_REG(0x0040)
60 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
61 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
62 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
63 #define DSI_CLK_CTRL DSI_REG(0x0054)
64 #define DSI_TIMING1 DSI_REG(0x0058)
65 #define DSI_TIMING2 DSI_REG(0x005C)
66 #define DSI_VM_TIMING1 DSI_REG(0x0060)
67 #define DSI_VM_TIMING2 DSI_REG(0x0064)
68 #define DSI_VM_TIMING3 DSI_REG(0x0068)
69 #define DSI_CLK_TIMING DSI_REG(0x006C)
70 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
71 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
72 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
73 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
74 #define DSI_VM_TIMING4 DSI_REG(0x0080)
75 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
76 #define DSI_VM_TIMING5 DSI_REG(0x0088)
77 #define DSI_VM_TIMING6 DSI_REG(0x008C)
78 #define DSI_VM_TIMING7 DSI_REG(0x0090)
79 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
80 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
81 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
82 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
83 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
84 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
85 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
86 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
87
88 /* DSIPHY_SCP */
89
90 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
91 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
92 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
93 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
94
95 /* DSI_PLL_CTRL_SCP */
96
97 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
98 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
99 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
100 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
101 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
102
103 #define REG_GET(idx, start, end) \
104 FLD_GET(dsi_read_reg(idx), start, end)
105
106 #define REG_FLD_MOD(idx, val, start, end) \
107 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
108
109 /* Global interrupts */
110 #define DSI_IRQ_VC0 (1 << 0)
111 #define DSI_IRQ_VC1 (1 << 1)
112 #define DSI_IRQ_VC2 (1 << 2)
113 #define DSI_IRQ_VC3 (1 << 3)
114 #define DSI_IRQ_WAKEUP (1 << 4)
115 #define DSI_IRQ_RESYNC (1 << 5)
116 #define DSI_IRQ_PLL_LOCK (1 << 7)
117 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
118 #define DSI_IRQ_PLL_RECALL (1 << 9)
119 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
120 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
121 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
122 #define DSI_IRQ_TE_TRIGGER (1 << 16)
123 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
124 #define DSI_IRQ_SYNC_LOST (1 << 18)
125 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
126 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
127 #define DSI_IRQ_ERROR_MASK \
128 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
129 DSI_IRQ_TA_TIMEOUT)
130 #define DSI_IRQ_CHANNEL_MASK 0xf
131
132 /* Virtual channel interrupts */
133 #define DSI_VC_IRQ_CS (1 << 0)
134 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
135 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
136 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
137 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
138 #define DSI_VC_IRQ_BTA (1 << 5)
139 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
140 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
141 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
142 #define DSI_VC_IRQ_ERROR_MASK \
143 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
144 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
145 DSI_VC_IRQ_FIFO_TX_UDF)
146
147 /* ComplexIO interrupts */
148 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
149 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
150 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
151 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
152 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
153 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
154 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
155 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
156 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
157 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
158 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
159 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
160 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
161 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
162 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
163 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
164 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
165 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
166 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
167 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
168
169 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
170 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
171 #define DSI_DT_DCS_READ 0x06
172 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
173 #define DSI_DT_NULL_PACKET 0x09
174 #define DSI_DT_DCS_LONG_WRITE 0x39
175
176 #define DSI_DT_RX_ACK_WITH_ERR 0x02
177 #define DSI_DT_RX_DCS_LONG_READ 0x1c
178 #define DSI_DT_RX_SHORT_READ_1 0x21
179 #define DSI_DT_RX_SHORT_READ_2 0x22
180
181 #define FINT_MAX 2100000
182 #define FINT_MIN 750000
183 #define REGN_MAX (1 << 7)
184 #define REGM_MAX ((1 << 11) - 1)
185 #define REGM3_MAX (1 << 4)
186 #define REGM4_MAX (1 << 4)
187 #define LP_DIV_MAX ((1 << 13) - 1)
188
189 enum fifo_size {
190 DSI_FIFO_SIZE_0 = 0,
191 DSI_FIFO_SIZE_32 = 1,
192 DSI_FIFO_SIZE_64 = 2,
193 DSI_FIFO_SIZE_96 = 3,
194 DSI_FIFO_SIZE_128 = 4,
195 };
196
197 enum dsi_vc_mode {
198 DSI_VC_MODE_L4 = 0,
199 DSI_VC_MODE_VP,
200 };
201
202 struct dsi_update_region {
203 bool dirty;
204 u16 x, y, w, h;
205 struct omap_dss_device *device;
206 };
207
208 struct dsi_irq_stats {
209 unsigned long last_reset;
210 unsigned irq_count;
211 unsigned dsi_irqs[32];
212 unsigned vc_irqs[4][32];
213 unsigned cio_irqs[32];
214 };
215
216 static struct
217 {
218 void __iomem *base;
219
220 struct dsi_clock_info current_cinfo;
221
222 struct regulator *vdds_dsi_reg;
223
224 struct {
225 enum dsi_vc_mode mode;
226 struct omap_dss_device *dssdev;
227 enum fifo_size fifo_size;
228 } vc[4];
229
230 struct mutex lock;
231 struct semaphore bus_lock;
232
233 unsigned pll_locked;
234
235 struct completion bta_completion;
236
237 struct task_struct *thread;
238 wait_queue_head_t waitqueue;
239
240 spinlock_t update_lock;
241 bool framedone_received;
242 struct dsi_update_region update_region;
243 struct dsi_update_region active_update_region;
244 struct completion update_completion;
245
246 enum omap_dss_update_mode user_update_mode;
247 enum omap_dss_update_mode update_mode;
248 bool te_enabled;
249 bool use_ext_te;
250
251 #ifdef DSI_CATCH_MISSING_TE
252 struct timer_list te_timer;
253 #endif
254
255 unsigned long cache_req_pck;
256 unsigned long cache_clk_freq;
257 struct dsi_clock_info cache_cinfo;
258
259 u32 errors;
260 spinlock_t errors_lock;
261 #ifdef DEBUG
262 ktime_t perf_setup_time;
263 ktime_t perf_start_time;
264 #endif
265 int debug_read;
266 int debug_write;
267
268 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
269 spinlock_t irq_stats_lock;
270 struct dsi_irq_stats irq_stats;
271 #endif
272 } dsi;
273
274 #ifdef DEBUG
275 static unsigned int dsi_perf;
276 module_param_named(dsi_perf, dsi_perf, bool, 0644);
277 #endif
278
279 static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
280 {
281 __raw_writel(val, dsi.base + idx.idx);
282 }
283
284 static inline u32 dsi_read_reg(const struct dsi_reg idx)
285 {
286 return __raw_readl(dsi.base + idx.idx);
287 }
288
289
290 void dsi_save_context(void)
291 {
292 }
293
294 void dsi_restore_context(void)
295 {
296 }
297
298 void dsi_bus_lock(void)
299 {
300 down(&dsi.bus_lock);
301 }
302 EXPORT_SYMBOL(dsi_bus_lock);
303
304 void dsi_bus_unlock(void)
305 {
306 up(&dsi.bus_lock);
307 }
308 EXPORT_SYMBOL(dsi_bus_unlock);
309
310 static bool dsi_bus_is_locked(void)
311 {
312 return dsi.bus_lock.count == 0;
313 }
314
315 static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
316 int value)
317 {
318 int t = 100000;
319
320 while (REG_GET(idx, bitnum, bitnum) != value) {
321 if (--t == 0)
322 return !value;
323 }
324
325 return value;
326 }
327
328 #ifdef DEBUG
329 static void dsi_perf_mark_setup(void)
330 {
331 dsi.perf_setup_time = ktime_get();
332 }
333
334 static void dsi_perf_mark_start(void)
335 {
336 dsi.perf_start_time = ktime_get();
337 }
338
339 static void dsi_perf_show(const char *name)
340 {
341 ktime_t t, setup_time, trans_time;
342 u32 total_bytes;
343 u32 setup_us, trans_us, total_us;
344
345 if (!dsi_perf)
346 return;
347
348 if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
349 return;
350
351 t = ktime_get();
352
353 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
354 setup_us = (u32)ktime_to_us(setup_time);
355 if (setup_us == 0)
356 setup_us = 1;
357
358 trans_time = ktime_sub(t, dsi.perf_start_time);
359 trans_us = (u32)ktime_to_us(trans_time);
360 if (trans_us == 0)
361 trans_us = 1;
362
363 total_us = setup_us + trans_us;
364
365 total_bytes = dsi.active_update_region.w *
366 dsi.active_update_region.h *
367 dsi.active_update_region.device->ctrl.pixel_size / 8;
368
369 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
370 "%u bytes, %u kbytes/sec\n",
371 name,
372 setup_us,
373 trans_us,
374 total_us,
375 1000*1000 / total_us,
376 total_bytes,
377 total_bytes * 1000 / total_us);
378 }
379 #else
380 #define dsi_perf_mark_setup()
381 #define dsi_perf_mark_start()
382 #define dsi_perf_show(x)
383 #endif
384
385 static void print_irq_status(u32 status)
386 {
387 #ifndef VERBOSE_IRQ
388 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
389 return;
390 #endif
391 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
392
393 #define PIS(x) \
394 if (status & DSI_IRQ_##x) \
395 printk(#x " ");
396 #ifdef VERBOSE_IRQ
397 PIS(VC0);
398 PIS(VC1);
399 PIS(VC2);
400 PIS(VC3);
401 #endif
402 PIS(WAKEUP);
403 PIS(RESYNC);
404 PIS(PLL_LOCK);
405 PIS(PLL_UNLOCK);
406 PIS(PLL_RECALL);
407 PIS(COMPLEXIO_ERR);
408 PIS(HS_TX_TIMEOUT);
409 PIS(LP_RX_TIMEOUT);
410 PIS(TE_TRIGGER);
411 PIS(ACK_TRIGGER);
412 PIS(SYNC_LOST);
413 PIS(LDO_POWER_GOOD);
414 PIS(TA_TIMEOUT);
415 #undef PIS
416
417 printk("\n");
418 }
419
420 static void print_irq_status_vc(int channel, u32 status)
421 {
422 #ifndef VERBOSE_IRQ
423 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
424 return;
425 #endif
426 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
427
428 #define PIS(x) \
429 if (status & DSI_VC_IRQ_##x) \
430 printk(#x " ");
431 PIS(CS);
432 PIS(ECC_CORR);
433 #ifdef VERBOSE_IRQ
434 PIS(PACKET_SENT);
435 #endif
436 PIS(FIFO_TX_OVF);
437 PIS(FIFO_RX_OVF);
438 PIS(BTA);
439 PIS(ECC_NO_CORR);
440 PIS(FIFO_TX_UDF);
441 PIS(PP_BUSY_CHANGE);
442 #undef PIS
443 printk("\n");
444 }
445
446 static void print_irq_status_cio(u32 status)
447 {
448 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
449
450 #define PIS(x) \
451 if (status & DSI_CIO_IRQ_##x) \
452 printk(#x " ");
453 PIS(ERRSYNCESC1);
454 PIS(ERRSYNCESC2);
455 PIS(ERRSYNCESC3);
456 PIS(ERRESC1);
457 PIS(ERRESC2);
458 PIS(ERRESC3);
459 PIS(ERRCONTROL1);
460 PIS(ERRCONTROL2);
461 PIS(ERRCONTROL3);
462 PIS(STATEULPS1);
463 PIS(STATEULPS2);
464 PIS(STATEULPS3);
465 PIS(ERRCONTENTIONLP0_1);
466 PIS(ERRCONTENTIONLP1_1);
467 PIS(ERRCONTENTIONLP0_2);
468 PIS(ERRCONTENTIONLP1_2);
469 PIS(ERRCONTENTIONLP0_3);
470 PIS(ERRCONTENTIONLP1_3);
471 PIS(ULPSACTIVENOT_ALL0);
472 PIS(ULPSACTIVENOT_ALL1);
473 #undef PIS
474
475 printk("\n");
476 }
477
478 static int debug_irq;
479
480 /* called from dss */
481 void dsi_irq_handler(void)
482 {
483 u32 irqstatus, vcstatus, ciostatus;
484 int i;
485
486 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
487
488 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
489 spin_lock(&dsi.irq_stats_lock);
490 dsi.irq_stats.irq_count++;
491 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
492 #endif
493
494 if (irqstatus & DSI_IRQ_ERROR_MASK) {
495 DSSERR("DSI error, irqstatus %x\n", irqstatus);
496 print_irq_status(irqstatus);
497 spin_lock(&dsi.errors_lock);
498 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
499 spin_unlock(&dsi.errors_lock);
500 } else if (debug_irq) {
501 print_irq_status(irqstatus);
502 }
503
504 #ifdef DSI_CATCH_MISSING_TE
505 if (irqstatus & DSI_IRQ_TE_TRIGGER)
506 del_timer(&dsi.te_timer);
507 #endif
508
509 for (i = 0; i < 4; ++i) {
510 if ((irqstatus & (1<<i)) == 0)
511 continue;
512
513 vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
514
515 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
516 dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
517 #endif
518
519 if (vcstatus & DSI_VC_IRQ_BTA)
520 complete(&dsi.bta_completion);
521
522 if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
523 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
524 i, vcstatus);
525 print_irq_status_vc(i, vcstatus);
526 } else if (debug_irq) {
527 print_irq_status_vc(i, vcstatus);
528 }
529
530 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
531 /* flush posted write */
532 dsi_read_reg(DSI_VC_IRQSTATUS(i));
533 }
534
535 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
536 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
537
538 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
539 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
540 #endif
541
542 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
543 /* flush posted write */
544 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
545
546 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
547 print_irq_status_cio(ciostatus);
548 }
549
550 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
551 /* flush posted write */
552 dsi_read_reg(DSI_IRQSTATUS);
553
554 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
555 spin_unlock(&dsi.irq_stats_lock);
556 #endif
557 }
558
559
560 static void _dsi_initialize_irq(void)
561 {
562 u32 l;
563 int i;
564
565 /* disable all interrupts */
566 dsi_write_reg(DSI_IRQENABLE, 0);
567 for (i = 0; i < 4; ++i)
568 dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
569 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
570
571 /* clear interrupt status */
572 l = dsi_read_reg(DSI_IRQSTATUS);
573 dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
574
575 for (i = 0; i < 4; ++i) {
576 l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
577 dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
578 }
579
580 l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
581 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
582
583 /* enable error irqs */
584 l = DSI_IRQ_ERROR_MASK;
585 #ifdef DSI_CATCH_MISSING_TE
586 l |= DSI_IRQ_TE_TRIGGER;
587 #endif
588 dsi_write_reg(DSI_IRQENABLE, l);
589
590 l = DSI_VC_IRQ_ERROR_MASK;
591 for (i = 0; i < 4; ++i)
592 dsi_write_reg(DSI_VC_IRQENABLE(i), l);
593
594 /* XXX zonda responds incorrectly, causing control error:
595 Exit from LP-ESC mode to LP11 uses wrong transition states on the
596 data lines LP0 and LN0. */
597 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
598 -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
599 }
600
601 static u32 dsi_get_errors(void)
602 {
603 unsigned long flags;
604 u32 e;
605 spin_lock_irqsave(&dsi.errors_lock, flags);
606 e = dsi.errors;
607 dsi.errors = 0;
608 spin_unlock_irqrestore(&dsi.errors_lock, flags);
609 return e;
610 }
611
612 static void dsi_vc_enable_bta_irq(int channel)
613 {
614 u32 l;
615
616 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
617
618 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
619 l |= DSI_VC_IRQ_BTA;
620 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
621 }
622
623 static void dsi_vc_disable_bta_irq(int channel)
624 {
625 u32 l;
626
627 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
628 l &= ~DSI_VC_IRQ_BTA;
629 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
630 }
631
632 /* DSI func clock. this could also be DSI2_PLL_FCLK */
633 static inline void enable_clocks(bool enable)
634 {
635 if (enable)
636 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
637 else
638 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
639 }
640
641 /* source clock for DSI PLL. this could also be PCLKFREE */
642 static inline void dsi_enable_pll_clock(bool enable)
643 {
644 if (enable)
645 dss_clk_enable(DSS_CLK_FCK2);
646 else
647 dss_clk_disable(DSS_CLK_FCK2);
648
649 if (enable && dsi.pll_locked) {
650 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
651 DSSERR("cannot lock PLL when enabling clocks\n");
652 }
653 }
654
655 #ifdef DEBUG
656 static void _dsi_print_reset_status(void)
657 {
658 u32 l;
659
660 if (!dss_debug)
661 return;
662
663 /* A dummy read using the SCP interface to any DSIPHY register is
664 * required after DSIPHY reset to complete the reset of the DSI complex
665 * I/O. */
666 l = dsi_read_reg(DSI_DSIPHY_CFG5);
667
668 printk(KERN_DEBUG "DSI resets: ");
669
670 l = dsi_read_reg(DSI_PLL_STATUS);
671 printk("PLL (%d) ", FLD_GET(l, 0, 0));
672
673 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
674 printk("CIO (%d) ", FLD_GET(l, 29, 29));
675
676 l = dsi_read_reg(DSI_DSIPHY_CFG5);
677 printk("PHY (%x, %d, %d, %d)\n",
678 FLD_GET(l, 28, 26),
679 FLD_GET(l, 29, 29),
680 FLD_GET(l, 30, 30),
681 FLD_GET(l, 31, 31));
682 }
683 #else
684 #define _dsi_print_reset_status()
685 #endif
686
687 static inline int dsi_if_enable(bool enable)
688 {
689 DSSDBG("dsi_if_enable(%d)\n", enable);
690
691 enable = enable ? 1 : 0;
692 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
693
694 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
695 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
696 return -EIO;
697 }
698
699 return 0;
700 }
701
702 unsigned long dsi_get_dsi1_pll_rate(void)
703 {
704 return dsi.current_cinfo.dsi1_pll_fclk;
705 }
706
707 static unsigned long dsi_get_dsi2_pll_rate(void)
708 {
709 return dsi.current_cinfo.dsi2_pll_fclk;
710 }
711
712 static unsigned long dsi_get_txbyteclkhs(void)
713 {
714 return dsi.current_cinfo.clkin4ddr / 16;
715 }
716
717 static unsigned long dsi_fclk_rate(void)
718 {
719 unsigned long r;
720
721 if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
722 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
723 r = dss_clk_get_rate(DSS_CLK_FCK1);
724 } else {
725 /* DSI FCLK source is DSI2_PLL_FCLK */
726 r = dsi_get_dsi2_pll_rate();
727 }
728
729 return r;
730 }
731
732 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
733 {
734 unsigned long dsi_fclk;
735 unsigned lp_clk_div;
736 unsigned long lp_clk;
737
738 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
739
740 if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
741 return -EINVAL;
742
743 dsi_fclk = dsi_fclk_rate();
744
745 lp_clk = dsi_fclk / 2 / lp_clk_div;
746
747 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
748 dsi.current_cinfo.lp_clk = lp_clk;
749 dsi.current_cinfo.lp_clk_div = lp_clk_div;
750
751 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
752
753 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
754 21, 21); /* LP_RX_SYNCHRO_ENABLE */
755
756 return 0;
757 }
758
759
760 enum dsi_pll_power_state {
761 DSI_PLL_POWER_OFF = 0x0,
762 DSI_PLL_POWER_ON_HSCLK = 0x1,
763 DSI_PLL_POWER_ON_ALL = 0x2,
764 DSI_PLL_POWER_ON_DIV = 0x3,
765 };
766
767 static int dsi_pll_power(enum dsi_pll_power_state state)
768 {
769 int t = 0;
770
771 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
772
773 /* PLL_PWR_STATUS */
774 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
775 if (++t > 1000) {
776 DSSERR("Failed to set DSI PLL power mode to %d\n",
777 state);
778 return -ENODEV;
779 }
780 udelay(1);
781 }
782
783 return 0;
784 }
785
786 /* calculate clock rates using dividers in cinfo */
787 static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
788 {
789 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
790 return -EINVAL;
791
792 if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
793 return -EINVAL;
794
795 if (cinfo->regm3 > REGM3_MAX)
796 return -EINVAL;
797
798 if (cinfo->regm4 > REGM4_MAX)
799 return -EINVAL;
800
801 if (cinfo->use_dss2_fck) {
802 cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2);
803 /* XXX it is unclear if highfreq should be used
804 * with DSS2_FCK source also */
805 cinfo->highfreq = 0;
806 } else {
807 cinfo->clkin = dispc_pclk_rate();
808
809 if (cinfo->clkin < 32000000)
810 cinfo->highfreq = 0;
811 else
812 cinfo->highfreq = 1;
813 }
814
815 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
816
817 if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
818 return -EINVAL;
819
820 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
821
822 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
823 return -EINVAL;
824
825 if (cinfo->regm3 > 0)
826 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
827 else
828 cinfo->dsi1_pll_fclk = 0;
829
830 if (cinfo->regm4 > 0)
831 cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
832 else
833 cinfo->dsi2_pll_fclk = 0;
834
835 return 0;
836 }
837
838 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
839 struct dsi_clock_info *dsi_cinfo,
840 struct dispc_clock_info *dispc_cinfo)
841 {
842 struct dsi_clock_info cur, best;
843 struct dispc_clock_info best_dispc;
844 int min_fck_per_pck;
845 int match = 0;
846 unsigned long dss_clk_fck2;
847
848 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
849
850 if (req_pck == dsi.cache_req_pck &&
851 dsi.cache_cinfo.clkin == dss_clk_fck2) {
852 DSSDBG("DSI clock info found from cache\n");
853 *dsi_cinfo = dsi.cache_cinfo;
854 dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
855 dispc_cinfo);
856 return 0;
857 }
858
859 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
860
861 if (min_fck_per_pck &&
862 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
863 DSSERR("Requested pixel clock not possible with the current "
864 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
865 "the constraint off.\n");
866 min_fck_per_pck = 0;
867 }
868
869 DSSDBG("dsi_pll_calc\n");
870
871 retry:
872 memset(&best, 0, sizeof(best));
873 memset(&best_dispc, 0, sizeof(best_dispc));
874
875 memset(&cur, 0, sizeof(cur));
876 cur.clkin = dss_clk_fck2;
877 cur.use_dss2_fck = 1;
878 cur.highfreq = 0;
879
880 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
881 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
882 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
883 for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
884 if (cur.highfreq == 0)
885 cur.fint = cur.clkin / cur.regn;
886 else
887 cur.fint = cur.clkin / (2 * cur.regn);
888
889 if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
890 continue;
891
892 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
893 for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
894 unsigned long a, b;
895
896 a = 2 * cur.regm * (cur.clkin/1000);
897 b = cur.regn * (cur.highfreq + 1);
898 cur.clkin4ddr = a / b * 1000;
899
900 if (cur.clkin4ddr > 1800 * 1000 * 1000)
901 break;
902
903 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
904 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
905 ++cur.regm3) {
906 struct dispc_clock_info cur_dispc;
907 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
908
909 /* this will narrow down the search a bit,
910 * but still give pixclocks below what was
911 * requested */
912 if (cur.dsi1_pll_fclk < req_pck)
913 break;
914
915 if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
916 continue;
917
918 if (min_fck_per_pck &&
919 cur.dsi1_pll_fclk <
920 req_pck * min_fck_per_pck)
921 continue;
922
923 match = 1;
924
925 dispc_find_clk_divs(is_tft, req_pck,
926 cur.dsi1_pll_fclk,
927 &cur_dispc);
928
929 if (abs(cur_dispc.pck - req_pck) <
930 abs(best_dispc.pck - req_pck)) {
931 best = cur;
932 best_dispc = cur_dispc;
933
934 if (cur_dispc.pck == req_pck)
935 goto found;
936 }
937 }
938 }
939 }
940 found:
941 if (!match) {
942 if (min_fck_per_pck) {
943 DSSERR("Could not find suitable clock settings.\n"
944 "Turning FCK/PCK constraint off and"
945 "trying again.\n");
946 min_fck_per_pck = 0;
947 goto retry;
948 }
949
950 DSSERR("Could not find suitable clock settings.\n");
951
952 return -EINVAL;
953 }
954
955 /* DSI2_PLL_FCLK (regm4) is not used */
956 best.regm4 = 0;
957 best.dsi2_pll_fclk = 0;
958
959 if (dsi_cinfo)
960 *dsi_cinfo = best;
961 if (dispc_cinfo)
962 *dispc_cinfo = best_dispc;
963
964 dsi.cache_req_pck = req_pck;
965 dsi.cache_clk_freq = 0;
966 dsi.cache_cinfo = best;
967
968 return 0;
969 }
970
971 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
972 {
973 int r = 0;
974 u32 l;
975 int f;
976
977 DSSDBGF();
978
979 dsi.current_cinfo.fint = cinfo->fint;
980 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
981 dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
982 dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
983
984 dsi.current_cinfo.regn = cinfo->regn;
985 dsi.current_cinfo.regm = cinfo->regm;
986 dsi.current_cinfo.regm3 = cinfo->regm3;
987 dsi.current_cinfo.regm4 = cinfo->regm4;
988
989 DSSDBG("DSI Fint %ld\n", cinfo->fint);
990
991 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
992 cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
993 cinfo->clkin,
994 cinfo->highfreq);
995
996 /* DSIPHY == CLKIN4DDR */
997 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
998 cinfo->regm,
999 cinfo->regn,
1000 cinfo->clkin,
1001 cinfo->highfreq + 1,
1002 cinfo->clkin4ddr);
1003
1004 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1005 cinfo->clkin4ddr / 1000 / 1000 / 2);
1006
1007 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1008
1009 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1010 cinfo->regm3, cinfo->dsi1_pll_fclk);
1011 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1012 cinfo->regm4, cinfo->dsi2_pll_fclk);
1013
1014 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1015
1016 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1017 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1018 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
1019 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
1020 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1021 22, 19); /* DSI_CLOCK_DIV */
1022 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
1023 26, 23); /* DSIPROTO_CLOCK_DIV */
1024 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1025
1026 BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
1027 if (cinfo->fint < 1000000)
1028 f = 0x3;
1029 else if (cinfo->fint < 1250000)
1030 f = 0x4;
1031 else if (cinfo->fint < 1500000)
1032 f = 0x5;
1033 else if (cinfo->fint < 1750000)
1034 f = 0x6;
1035 else
1036 f = 0x7;
1037
1038 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1039 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1040 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
1041 11, 11); /* DSI_PLL_CLKSEL */
1042 l = FLD_MOD(l, cinfo->highfreq,
1043 12, 12); /* DSI_PLL_HIGHFREQ */
1044 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1045 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1046 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1047 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1048
1049 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1050
1051 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1052 DSSERR("dsi pll go bit not going down.\n");
1053 r = -EIO;
1054 goto err;
1055 }
1056
1057 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1058 DSSERR("cannot lock PLL\n");
1059 r = -EIO;
1060 goto err;
1061 }
1062
1063 dsi.pll_locked = 1;
1064
1065 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1066 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1067 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1068 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1069 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1070 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1071 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1072 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1073 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1074 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1075 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1076 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1077 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1078 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1079 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1080 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1081
1082 DSSDBG("PLL config done\n");
1083 err:
1084 return r;
1085 }
1086
1087 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1088 bool enable_hsdiv)
1089 {
1090 int r = 0;
1091 enum dsi_pll_power_state pwstate;
1092
1093 DSSDBG("PLL init\n");
1094
1095 enable_clocks(1);
1096 dsi_enable_pll_clock(1);
1097
1098 r = regulator_enable(dsi.vdds_dsi_reg);
1099 if (r)
1100 goto err0;
1101
1102 /* XXX PLL does not come out of reset without this... */
1103 dispc_pck_free_enable(1);
1104
1105 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1106 DSSERR("PLL not coming out of reset.\n");
1107 r = -ENODEV;
1108 goto err1;
1109 }
1110
1111 /* XXX ... but if left on, we get problems when planes do not
1112 * fill the whole display. No idea about this */
1113 dispc_pck_free_enable(0);
1114
1115 if (enable_hsclk && enable_hsdiv)
1116 pwstate = DSI_PLL_POWER_ON_ALL;
1117 else if (enable_hsclk)
1118 pwstate = DSI_PLL_POWER_ON_HSCLK;
1119 else if (enable_hsdiv)
1120 pwstate = DSI_PLL_POWER_ON_DIV;
1121 else
1122 pwstate = DSI_PLL_POWER_OFF;
1123
1124 r = dsi_pll_power(pwstate);
1125
1126 if (r)
1127 goto err1;
1128
1129 DSSDBG("PLL init done\n");
1130
1131 return 0;
1132 err1:
1133 regulator_disable(dsi.vdds_dsi_reg);
1134 err0:
1135 enable_clocks(0);
1136 dsi_enable_pll_clock(0);
1137 return r;
1138 }
1139
1140 void dsi_pll_uninit(void)
1141 {
1142 enable_clocks(0);
1143 dsi_enable_pll_clock(0);
1144
1145 dsi.pll_locked = 0;
1146 dsi_pll_power(DSI_PLL_POWER_OFF);
1147 regulator_disable(dsi.vdds_dsi_reg);
1148 DSSDBG("PLL uninit done\n");
1149 }
1150
1151 void dsi_dump_clocks(struct seq_file *s)
1152 {
1153 int clksel;
1154 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1155
1156 enable_clocks(1);
1157
1158 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1159
1160 seq_printf(s, "- DSI PLL -\n");
1161
1162 seq_printf(s, "dsi pll source = %s\n",
1163 clksel == 0 ?
1164 "dss2_alwon_fclk" : "pclkfree");
1165
1166 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1167
1168 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1169 cinfo->clkin4ddr, cinfo->regm);
1170
1171 seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1172 cinfo->dsi1_pll_fclk,
1173 cinfo->regm3,
1174 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1175 "off" : "on");
1176
1177 seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1178 cinfo->dsi2_pll_fclk,
1179 cinfo->regm4,
1180 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1181 "off" : "on");
1182
1183 seq_printf(s, "- DSI -\n");
1184
1185 seq_printf(s, "dsi fclk source = %s\n",
1186 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1187 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1188
1189 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1190
1191 seq_printf(s, "DDR_CLK\t\t%lu\n",
1192 cinfo->clkin4ddr / 4);
1193
1194 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1195
1196 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1197
1198 seq_printf(s, "VP_CLK\t\t%lu\n"
1199 "VP_PCLK\t\t%lu\n",
1200 dispc_lclk_rate(),
1201 dispc_pclk_rate());
1202
1203 enable_clocks(0);
1204 }
1205
1206 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1207 void dsi_dump_irqs(struct seq_file *s)
1208 {
1209 unsigned long flags;
1210 struct dsi_irq_stats stats;
1211
1212 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1213
1214 stats = dsi.irq_stats;
1215 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1216 dsi.irq_stats.last_reset = jiffies;
1217
1218 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1219
1220 seq_printf(s, "period %u ms\n",
1221 jiffies_to_msecs(jiffies - stats.last_reset));
1222
1223 seq_printf(s, "irqs %d\n", stats.irq_count);
1224 #define PIS(x) \
1225 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1226
1227 seq_printf(s, "-- DSI interrupts --\n");
1228 PIS(VC0);
1229 PIS(VC1);
1230 PIS(VC2);
1231 PIS(VC3);
1232 PIS(WAKEUP);
1233 PIS(RESYNC);
1234 PIS(PLL_LOCK);
1235 PIS(PLL_UNLOCK);
1236 PIS(PLL_RECALL);
1237 PIS(COMPLEXIO_ERR);
1238 PIS(HS_TX_TIMEOUT);
1239 PIS(LP_RX_TIMEOUT);
1240 PIS(TE_TRIGGER);
1241 PIS(ACK_TRIGGER);
1242 PIS(SYNC_LOST);
1243 PIS(LDO_POWER_GOOD);
1244 PIS(TA_TIMEOUT);
1245 #undef PIS
1246
1247 #define PIS(x) \
1248 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1249 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1250 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1251 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1252 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1253
1254 seq_printf(s, "-- VC interrupts --\n");
1255 PIS(CS);
1256 PIS(ECC_CORR);
1257 PIS(PACKET_SENT);
1258 PIS(FIFO_TX_OVF);
1259 PIS(FIFO_RX_OVF);
1260 PIS(BTA);
1261 PIS(ECC_NO_CORR);
1262 PIS(FIFO_TX_UDF);
1263 PIS(PP_BUSY_CHANGE);
1264 #undef PIS
1265
1266 #define PIS(x) \
1267 seq_printf(s, "%-20s %10d\n", #x, \
1268 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1269
1270 seq_printf(s, "-- CIO interrupts --\n");
1271 PIS(ERRSYNCESC1);
1272 PIS(ERRSYNCESC2);
1273 PIS(ERRSYNCESC3);
1274 PIS(ERRESC1);
1275 PIS(ERRESC2);
1276 PIS(ERRESC3);
1277 PIS(ERRCONTROL1);
1278 PIS(ERRCONTROL2);
1279 PIS(ERRCONTROL3);
1280 PIS(STATEULPS1);
1281 PIS(STATEULPS2);
1282 PIS(STATEULPS3);
1283 PIS(ERRCONTENTIONLP0_1);
1284 PIS(ERRCONTENTIONLP1_1);
1285 PIS(ERRCONTENTIONLP0_2);
1286 PIS(ERRCONTENTIONLP1_2);
1287 PIS(ERRCONTENTIONLP0_3);
1288 PIS(ERRCONTENTIONLP1_3);
1289 PIS(ULPSACTIVENOT_ALL0);
1290 PIS(ULPSACTIVENOT_ALL1);
1291 #undef PIS
1292 }
1293 #endif
1294
1295 void dsi_dump_regs(struct seq_file *s)
1296 {
1297 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1298
1299 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
1300
1301 DUMPREG(DSI_REVISION);
1302 DUMPREG(DSI_SYSCONFIG);
1303 DUMPREG(DSI_SYSSTATUS);
1304 DUMPREG(DSI_IRQSTATUS);
1305 DUMPREG(DSI_IRQENABLE);
1306 DUMPREG(DSI_CTRL);
1307 DUMPREG(DSI_COMPLEXIO_CFG1);
1308 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1309 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1310 DUMPREG(DSI_CLK_CTRL);
1311 DUMPREG(DSI_TIMING1);
1312 DUMPREG(DSI_TIMING2);
1313 DUMPREG(DSI_VM_TIMING1);
1314 DUMPREG(DSI_VM_TIMING2);
1315 DUMPREG(DSI_VM_TIMING3);
1316 DUMPREG(DSI_CLK_TIMING);
1317 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1318 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1319 DUMPREG(DSI_COMPLEXIO_CFG2);
1320 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1321 DUMPREG(DSI_VM_TIMING4);
1322 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1323 DUMPREG(DSI_VM_TIMING5);
1324 DUMPREG(DSI_VM_TIMING6);
1325 DUMPREG(DSI_VM_TIMING7);
1326 DUMPREG(DSI_STOPCLK_TIMING);
1327
1328 DUMPREG(DSI_VC_CTRL(0));
1329 DUMPREG(DSI_VC_TE(0));
1330 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1331 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1332 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1333 DUMPREG(DSI_VC_IRQSTATUS(0));
1334 DUMPREG(DSI_VC_IRQENABLE(0));
1335
1336 DUMPREG(DSI_VC_CTRL(1));
1337 DUMPREG(DSI_VC_TE(1));
1338 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1339 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1340 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1341 DUMPREG(DSI_VC_IRQSTATUS(1));
1342 DUMPREG(DSI_VC_IRQENABLE(1));
1343
1344 DUMPREG(DSI_VC_CTRL(2));
1345 DUMPREG(DSI_VC_TE(2));
1346 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1347 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1348 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1349 DUMPREG(DSI_VC_IRQSTATUS(2));
1350 DUMPREG(DSI_VC_IRQENABLE(2));
1351
1352 DUMPREG(DSI_VC_CTRL(3));
1353 DUMPREG(DSI_VC_TE(3));
1354 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1355 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1356 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1357 DUMPREG(DSI_VC_IRQSTATUS(3));
1358 DUMPREG(DSI_VC_IRQENABLE(3));
1359
1360 DUMPREG(DSI_DSIPHY_CFG0);
1361 DUMPREG(DSI_DSIPHY_CFG1);
1362 DUMPREG(DSI_DSIPHY_CFG2);
1363 DUMPREG(DSI_DSIPHY_CFG5);
1364
1365 DUMPREG(DSI_PLL_CONTROL);
1366 DUMPREG(DSI_PLL_STATUS);
1367 DUMPREG(DSI_PLL_GO);
1368 DUMPREG(DSI_PLL_CONFIGURATION1);
1369 DUMPREG(DSI_PLL_CONFIGURATION2);
1370
1371 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
1372 #undef DUMPREG
1373 }
1374
1375 enum dsi_complexio_power_state {
1376 DSI_COMPLEXIO_POWER_OFF = 0x0,
1377 DSI_COMPLEXIO_POWER_ON = 0x1,
1378 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1379 };
1380
1381 static int dsi_complexio_power(enum dsi_complexio_power_state state)
1382 {
1383 int t = 0;
1384
1385 /* PWR_CMD */
1386 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1387
1388 /* PWR_STATUS */
1389 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
1390 if (++t > 1000) {
1391 DSSERR("failed to set complexio power state to "
1392 "%d\n", state);
1393 return -ENODEV;
1394 }
1395 udelay(1);
1396 }
1397
1398 return 0;
1399 }
1400
1401 static void dsi_complexio_config(struct omap_dss_device *dssdev)
1402 {
1403 u32 r;
1404
1405 int clk_lane = dssdev->phy.dsi.clk_lane;
1406 int data1_lane = dssdev->phy.dsi.data1_lane;
1407 int data2_lane = dssdev->phy.dsi.data2_lane;
1408 int clk_pol = dssdev->phy.dsi.clk_pol;
1409 int data1_pol = dssdev->phy.dsi.data1_pol;
1410 int data2_pol = dssdev->phy.dsi.data2_pol;
1411
1412 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1413 r = FLD_MOD(r, clk_lane, 2, 0);
1414 r = FLD_MOD(r, clk_pol, 3, 3);
1415 r = FLD_MOD(r, data1_lane, 6, 4);
1416 r = FLD_MOD(r, data1_pol, 7, 7);
1417 r = FLD_MOD(r, data2_lane, 10, 8);
1418 r = FLD_MOD(r, data2_pol, 11, 11);
1419 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1420
1421 /* The configuration of the DSI complex I/O (number of data lanes,
1422 position, differential order) should not be changed while
1423 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1424 the hardware to take into account a new configuration of the complex
1425 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1426 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1427 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1428 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1429 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1430 DSI complex I/O configuration is unknown. */
1431
1432 /*
1433 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1434 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1435 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1436 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1437 */
1438 }
1439
1440 static inline unsigned ns2ddr(unsigned ns)
1441 {
1442 /* convert time in ns to ddr ticks, rounding up */
1443 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1444 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1445 }
1446
1447 static inline unsigned ddr2ns(unsigned ddr)
1448 {
1449 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1450 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1451 }
1452
1453 static void dsi_complexio_timings(void)
1454 {
1455 u32 r;
1456 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1457 u32 tlpx_half, tclk_trail, tclk_zero;
1458 u32 tclk_prepare;
1459
1460 /* calculate timings */
1461
1462 /* 1 * DDR_CLK = 2 * UI */
1463
1464 /* min 40ns + 4*UI max 85ns + 6*UI */
1465 ths_prepare = ns2ddr(70) + 2;
1466
1467 /* min 145ns + 10*UI */
1468 ths_prepare_ths_zero = ns2ddr(175) + 2;
1469
1470 /* min max(8*UI, 60ns+4*UI) */
1471 ths_trail = ns2ddr(60) + 5;
1472
1473 /* min 100ns */
1474 ths_exit = ns2ddr(145);
1475
1476 /* tlpx min 50n */
1477 tlpx_half = ns2ddr(25);
1478
1479 /* min 60ns */
1480 tclk_trail = ns2ddr(60) + 2;
1481
1482 /* min 38ns, max 95ns */
1483 tclk_prepare = ns2ddr(65);
1484
1485 /* min tclk-prepare + tclk-zero = 300ns */
1486 tclk_zero = ns2ddr(260);
1487
1488 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1489 ths_prepare, ddr2ns(ths_prepare),
1490 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1491 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1492 ths_trail, ddr2ns(ths_trail),
1493 ths_exit, ddr2ns(ths_exit));
1494
1495 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1496 "tclk_zero %u (%uns)\n",
1497 tlpx_half, ddr2ns(tlpx_half),
1498 tclk_trail, ddr2ns(tclk_trail),
1499 tclk_zero, ddr2ns(tclk_zero));
1500 DSSDBG("tclk_prepare %u (%uns)\n",
1501 tclk_prepare, ddr2ns(tclk_prepare));
1502
1503 /* program timings */
1504
1505 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1506 r = FLD_MOD(r, ths_prepare, 31, 24);
1507 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1508 r = FLD_MOD(r, ths_trail, 15, 8);
1509 r = FLD_MOD(r, ths_exit, 7, 0);
1510 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1511
1512 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1513 r = FLD_MOD(r, tlpx_half, 22, 16);
1514 r = FLD_MOD(r, tclk_trail, 15, 8);
1515 r = FLD_MOD(r, tclk_zero, 7, 0);
1516 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1517
1518 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1519 r = FLD_MOD(r, tclk_prepare, 7, 0);
1520 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1521 }
1522
1523
1524 static int dsi_complexio_init(struct omap_dss_device *dssdev)
1525 {
1526 int r = 0;
1527
1528 DSSDBG("dsi_complexio_init\n");
1529
1530 /* CIO_CLK_ICG, enable L3 clk to CIO */
1531 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1532
1533 /* A dummy read using the SCP interface to any DSIPHY register is
1534 * required after DSIPHY reset to complete the reset of the DSI complex
1535 * I/O. */
1536 dsi_read_reg(DSI_DSIPHY_CFG5);
1537
1538 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1539 DSSERR("ComplexIO PHY not coming out of reset.\n");
1540 r = -ENODEV;
1541 goto err;
1542 }
1543
1544 dsi_complexio_config(dssdev);
1545
1546 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1547
1548 if (r)
1549 goto err;
1550
1551 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1552 DSSERR("ComplexIO not coming out of reset.\n");
1553 r = -ENODEV;
1554 goto err;
1555 }
1556
1557 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1558 DSSERR("ComplexIO LDO power down.\n");
1559 r = -ENODEV;
1560 goto err;
1561 }
1562
1563 dsi_complexio_timings();
1564
1565 /*
1566 The configuration of the DSI complex I/O (number of data lanes,
1567 position, differential order) should not be changed while
1568 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1569 hardware to recognize a new configuration of the complex I/O (done
1570 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1571 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1572 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1573 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1574 bit to 1. If the sequence is not followed, the DSi complex I/O
1575 configuration is undetermined.
1576 */
1577 dsi_if_enable(1);
1578 dsi_if_enable(0);
1579 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1580 dsi_if_enable(1);
1581 dsi_if_enable(0);
1582
1583 DSSDBG("CIO init done\n");
1584 err:
1585 return r;
1586 }
1587
1588 static void dsi_complexio_uninit(void)
1589 {
1590 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1591 }
1592
1593 static int _dsi_wait_reset(void)
1594 {
1595 int t = 0;
1596
1597 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
1598 if (++t > 5) {
1599 DSSERR("soft reset failed\n");
1600 return -ENODEV;
1601 }
1602 udelay(1);
1603 }
1604
1605 return 0;
1606 }
1607
1608 static int _dsi_reset(void)
1609 {
1610 /* Soft reset */
1611 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1612 return _dsi_wait_reset();
1613 }
1614
1615 static void dsi_reset_tx_fifo(int channel)
1616 {
1617 u32 mask;
1618 u32 l;
1619
1620 /* set fifosize of the channel to 0, then return the old size */
1621 l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE);
1622
1623 mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4);
1624 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask);
1625
1626 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l);
1627 }
1628
1629 static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1630 enum fifo_size size3, enum fifo_size size4)
1631 {
1632 u32 r = 0;
1633 int add = 0;
1634 int i;
1635
1636 dsi.vc[0].fifo_size = size1;
1637 dsi.vc[1].fifo_size = size2;
1638 dsi.vc[2].fifo_size = size3;
1639 dsi.vc[3].fifo_size = size4;
1640
1641 for (i = 0; i < 4; i++) {
1642 u8 v;
1643 int size = dsi.vc[i].fifo_size;
1644
1645 if (add + size > 4) {
1646 DSSERR("Illegal FIFO configuration\n");
1647 BUG();
1648 }
1649
1650 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1651 r |= v << (8 * i);
1652 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1653 add += size;
1654 }
1655
1656 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1657 }
1658
1659 static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1660 enum fifo_size size3, enum fifo_size size4)
1661 {
1662 u32 r = 0;
1663 int add = 0;
1664 int i;
1665
1666 dsi.vc[0].fifo_size = size1;
1667 dsi.vc[1].fifo_size = size2;
1668 dsi.vc[2].fifo_size = size3;
1669 dsi.vc[3].fifo_size = size4;
1670
1671 for (i = 0; i < 4; i++) {
1672 u8 v;
1673 int size = dsi.vc[i].fifo_size;
1674
1675 if (add + size > 4) {
1676 DSSERR("Illegal FIFO configuration\n");
1677 BUG();
1678 }
1679
1680 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1681 r |= v << (8 * i);
1682 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1683 add += size;
1684 }
1685
1686 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
1687 }
1688
1689 static int dsi_force_tx_stop_mode_io(void)
1690 {
1691 u32 r;
1692
1693 r = dsi_read_reg(DSI_TIMING1);
1694 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1695 dsi_write_reg(DSI_TIMING1, r);
1696
1697 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
1698 DSSERR("TX_STOP bit not going down\n");
1699 return -EIO;
1700 }
1701
1702 return 0;
1703 }
1704
1705 static int dsi_vc_enable(int channel, bool enable)
1706 {
1707 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
1708 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1709 channel, enable);
1710
1711 enable = enable ? 1 : 0;
1712
1713 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1714
1715 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
1716 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1717 return -EIO;
1718 }
1719
1720 return 0;
1721 }
1722
1723 static void dsi_vc_initial_config(int channel)
1724 {
1725 u32 r;
1726
1727 DSSDBGF("%d", channel);
1728
1729 r = dsi_read_reg(DSI_VC_CTRL(channel));
1730
1731 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1732 DSSERR("VC(%d) busy when trying to configure it!\n",
1733 channel);
1734
1735 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1736 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1737 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1738 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1739 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1740 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1741 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1742
1743 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1744 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1745
1746 dsi_write_reg(DSI_VC_CTRL(channel), r);
1747
1748 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1749 }
1750
1751 static void dsi_vc_config_l4(int channel)
1752 {
1753 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
1754 return;
1755
1756 DSSDBGF("%d", channel);
1757
1758 dsi_vc_enable(channel, 0);
1759
1760 if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
1761 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
1762
1763 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1764
1765 dsi_vc_enable(channel, 1);
1766
1767 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1768 }
1769
1770 static void dsi_vc_config_vp(int channel)
1771 {
1772 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
1773 return;
1774
1775 DSSDBGF("%d", channel);
1776
1777 dsi_vc_enable(channel, 0);
1778
1779 if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
1780 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
1781
1782 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1783
1784 dsi_vc_enable(channel, 1);
1785
1786 dsi.vc[channel].mode = DSI_VC_MODE_VP;
1787 }
1788
1789
1790 void omapdss_dsi_vc_enable_hs(int channel, bool enable)
1791 {
1792 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
1793
1794 WARN_ON(!dsi_bus_is_locked());
1795
1796 dsi_vc_enable(channel, 0);
1797 dsi_if_enable(0);
1798
1799 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1800
1801 dsi_vc_enable(channel, 1);
1802 dsi_if_enable(1);
1803
1804 dsi_force_tx_stop_mode_io();
1805 }
1806 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
1807
1808 static void dsi_vc_flush_long_data(int channel)
1809 {
1810 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1811 u32 val;
1812 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1813 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1814 (val >> 0) & 0xff,
1815 (val >> 8) & 0xff,
1816 (val >> 16) & 0xff,
1817 (val >> 24) & 0xff);
1818 }
1819 }
1820
1821 static void dsi_show_rx_ack_with_err(u16 err)
1822 {
1823 DSSERR("\tACK with ERROR (%#x):\n", err);
1824 if (err & (1 << 0))
1825 DSSERR("\t\tSoT Error\n");
1826 if (err & (1 << 1))
1827 DSSERR("\t\tSoT Sync Error\n");
1828 if (err & (1 << 2))
1829 DSSERR("\t\tEoT Sync Error\n");
1830 if (err & (1 << 3))
1831 DSSERR("\t\tEscape Mode Entry Command Error\n");
1832 if (err & (1 << 4))
1833 DSSERR("\t\tLP Transmit Sync Error\n");
1834 if (err & (1 << 5))
1835 DSSERR("\t\tHS Receive Timeout Error\n");
1836 if (err & (1 << 6))
1837 DSSERR("\t\tFalse Control Error\n");
1838 if (err & (1 << 7))
1839 DSSERR("\t\t(reserved7)\n");
1840 if (err & (1 << 8))
1841 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1842 if (err & (1 << 9))
1843 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1844 if (err & (1 << 10))
1845 DSSERR("\t\tChecksum Error\n");
1846 if (err & (1 << 11))
1847 DSSERR("\t\tData type not recognized\n");
1848 if (err & (1 << 12))
1849 DSSERR("\t\tInvalid VC ID\n");
1850 if (err & (1 << 13))
1851 DSSERR("\t\tInvalid Transmission Length\n");
1852 if (err & (1 << 14))
1853 DSSERR("\t\t(reserved14)\n");
1854 if (err & (1 << 15))
1855 DSSERR("\t\tDSI Protocol Violation\n");
1856 }
1857
1858 static u16 dsi_vc_flush_receive_data(int channel)
1859 {
1860 /* RX_FIFO_NOT_EMPTY */
1861 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1862 u32 val;
1863 u8 dt;
1864 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1865 DSSDBG("\trawval %#08x\n", val);
1866 dt = FLD_GET(val, 5, 0);
1867 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
1868 u16 err = FLD_GET(val, 23, 8);
1869 dsi_show_rx_ack_with_err(err);
1870 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
1871 DSSDBG("\tDCS short response, 1 byte: %#x\n",
1872 FLD_GET(val, 23, 8));
1873 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
1874 DSSDBG("\tDCS short response, 2 byte: %#x\n",
1875 FLD_GET(val, 23, 8));
1876 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
1877 DSSDBG("\tDCS long response, len %d\n",
1878 FLD_GET(val, 23, 8));
1879 dsi_vc_flush_long_data(channel);
1880 } else {
1881 DSSERR("\tunknown datatype 0x%02x\n", dt);
1882 }
1883 }
1884 return 0;
1885 }
1886
1887 static int dsi_vc_send_bta(int channel)
1888 {
1889 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO &&
1890 (dsi.debug_write || dsi.debug_read))
1891 DSSDBG("dsi_vc_send_bta %d\n", channel);
1892
1893 WARN_ON(!dsi_bus_is_locked());
1894
1895 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1896 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1897 dsi_vc_flush_receive_data(channel);
1898 }
1899
1900 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
1901
1902 return 0;
1903 }
1904
1905 int dsi_vc_send_bta_sync(int channel)
1906 {
1907 int r = 0;
1908 u32 err;
1909
1910 INIT_COMPLETION(dsi.bta_completion);
1911
1912 dsi_vc_enable_bta_irq(channel);
1913
1914 r = dsi_vc_send_bta(channel);
1915 if (r)
1916 goto err;
1917
1918 if (wait_for_completion_timeout(&dsi.bta_completion,
1919 msecs_to_jiffies(500)) == 0) {
1920 DSSERR("Failed to receive BTA\n");
1921 r = -EIO;
1922 goto err;
1923 }
1924
1925 err = dsi_get_errors();
1926 if (err) {
1927 DSSERR("Error while sending BTA: %x\n", err);
1928 r = -EIO;
1929 goto err;
1930 }
1931 err:
1932 dsi_vc_disable_bta_irq(channel);
1933
1934 return r;
1935 }
1936 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
1937
1938 static inline void dsi_vc_write_long_header(int channel, u8 data_type,
1939 u16 len, u8 ecc)
1940 {
1941 u32 val;
1942 u8 data_id;
1943
1944 WARN_ON(!dsi_bus_is_locked());
1945
1946 data_id = data_type | channel << 6;
1947
1948 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
1949 FLD_VAL(ecc, 31, 24);
1950
1951 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
1952 }
1953
1954 static inline void dsi_vc_write_long_payload(int channel,
1955 u8 b1, u8 b2, u8 b3, u8 b4)
1956 {
1957 u32 val;
1958
1959 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
1960
1961 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
1962 b1, b2, b3, b4, val); */
1963
1964 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
1965 }
1966
1967 static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
1968 u8 ecc)
1969 {
1970 /*u32 val; */
1971 int i;
1972 u8 *p;
1973 int r = 0;
1974 u8 b1, b2, b3, b4;
1975
1976 if (dsi.debug_write)
1977 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
1978
1979 /* len + header */
1980 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
1981 DSSERR("unable to send long packet: packet too long.\n");
1982 return -EINVAL;
1983 }
1984
1985 dsi_vc_config_l4(channel);
1986
1987 dsi_vc_write_long_header(channel, data_type, len, ecc);
1988
1989 p = data;
1990 for (i = 0; i < len >> 2; i++) {
1991 if (dsi.debug_write)
1992 DSSDBG("\tsending full packet %d\n", i);
1993
1994 b1 = *p++;
1995 b2 = *p++;
1996 b3 = *p++;
1997 b4 = *p++;
1998
1999 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
2000 }
2001
2002 i = len % 4;
2003 if (i) {
2004 b1 = 0; b2 = 0; b3 = 0;
2005
2006 if (dsi.debug_write)
2007 DSSDBG("\tsending remainder bytes %d\n", i);
2008
2009 switch (i) {
2010 case 3:
2011 b1 = *p++;
2012 b2 = *p++;
2013 b3 = *p++;
2014 break;
2015 case 2:
2016 b1 = *p++;
2017 b2 = *p++;
2018 break;
2019 case 1:
2020 b1 = *p++;
2021 break;
2022 }
2023
2024 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2025 }
2026
2027 return r;
2028 }
2029
2030 static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2031 {
2032 u32 r;
2033 u8 data_id;
2034
2035 WARN_ON(!dsi_bus_is_locked());
2036
2037 if (dsi.debug_write)
2038 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2039 channel,
2040 data_type, data & 0xff, (data >> 8) & 0xff);
2041
2042 dsi_vc_config_l4(channel);
2043
2044 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2045 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2046 return -EINVAL;
2047 }
2048
2049 data_id = data_type | channel << 6;
2050
2051 r = (data_id << 0) | (data << 8) | (ecc << 24);
2052
2053 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2054
2055 return 0;
2056 }
2057
2058 int dsi_vc_send_null(int channel)
2059 {
2060 u8 nullpkg[] = {0, 0, 0, 0};
2061 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
2062 }
2063 EXPORT_SYMBOL(dsi_vc_send_null);
2064
2065 int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2066 {
2067 int r;
2068
2069 BUG_ON(len == 0);
2070
2071 if (len == 1) {
2072 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2073 data[0], 0);
2074 } else if (len == 2) {
2075 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2076 data[0] | (data[1] << 8), 0);
2077 } else {
2078 /* 0x39 = DCS Long Write */
2079 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2080 data, len, 0);
2081 }
2082
2083 return r;
2084 }
2085 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2086
2087 int dsi_vc_dcs_write(int channel, u8 *data, int len)
2088 {
2089 int r;
2090
2091 r = dsi_vc_dcs_write_nosync(channel, data, len);
2092 if (r)
2093 return r;
2094
2095 r = dsi_vc_send_bta_sync(channel);
2096
2097 return r;
2098 }
2099 EXPORT_SYMBOL(dsi_vc_dcs_write);
2100
2101 int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2102 {
2103 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2104 }
2105 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2106
2107 int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2108 {
2109 u8 buf[2];
2110 buf[0] = dcs_cmd;
2111 buf[1] = param;
2112 return dsi_vc_dcs_write(channel, buf, 2);
2113 }
2114 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2115
2116 int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2117 {
2118 u32 val;
2119 u8 dt;
2120 int r;
2121
2122 if (dsi.debug_read)
2123 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
2124
2125 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2126 if (r)
2127 return r;
2128
2129 r = dsi_vc_send_bta_sync(channel);
2130 if (r)
2131 return r;
2132
2133 /* RX_FIFO_NOT_EMPTY */
2134 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2135 DSSERR("RX fifo empty when trying to read.\n");
2136 return -EIO;
2137 }
2138
2139 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2140 if (dsi.debug_read)
2141 DSSDBG("\theader: %08x\n", val);
2142 dt = FLD_GET(val, 5, 0);
2143 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2144 u16 err = FLD_GET(val, 23, 8);
2145 dsi_show_rx_ack_with_err(err);
2146 return -EIO;
2147
2148 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2149 u8 data = FLD_GET(val, 15, 8);
2150 if (dsi.debug_read)
2151 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2152
2153 if (buflen < 1)
2154 return -EIO;
2155
2156 buf[0] = data;
2157
2158 return 1;
2159 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2160 u16 data = FLD_GET(val, 23, 8);
2161 if (dsi.debug_read)
2162 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2163
2164 if (buflen < 2)
2165 return -EIO;
2166
2167 buf[0] = data & 0xff;
2168 buf[1] = (data >> 8) & 0xff;
2169
2170 return 2;
2171 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2172 int w;
2173 int len = FLD_GET(val, 23, 8);
2174 if (dsi.debug_read)
2175 DSSDBG("\tDCS long response, len %d\n", len);
2176
2177 if (len > buflen)
2178 return -EIO;
2179
2180 /* two byte checksum ends the packet, not included in len */
2181 for (w = 0; w < len + 2;) {
2182 int b;
2183 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2184 if (dsi.debug_read)
2185 DSSDBG("\t\t%02x %02x %02x %02x\n",
2186 (val >> 0) & 0xff,
2187 (val >> 8) & 0xff,
2188 (val >> 16) & 0xff,
2189 (val >> 24) & 0xff);
2190
2191 for (b = 0; b < 4; ++b) {
2192 if (w < len)
2193 buf[w] = (val >> (b * 8)) & 0xff;
2194 /* we discard the 2 byte checksum */
2195 ++w;
2196 }
2197 }
2198
2199 return len;
2200
2201 } else {
2202 DSSERR("\tunknown datatype 0x%02x\n", dt);
2203 return -EIO;
2204 }
2205 }
2206 EXPORT_SYMBOL(dsi_vc_dcs_read);
2207
2208 int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2209 {
2210 int r;
2211
2212 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2213
2214 if (r < 0)
2215 return r;
2216
2217 if (r != 1)
2218 return -EIO;
2219
2220 return 0;
2221 }
2222 EXPORT_SYMBOL(dsi_vc_dcs_read_1);
2223
2224 int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2225 {
2226 int r;
2227 r = dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
2228 len, 0);
2229
2230 if (r)
2231 return r;
2232
2233 r = dsi_vc_send_bta_sync(channel);
2234
2235 return r;
2236 }
2237 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2238
2239 static void dsi_set_lp_rx_timeout(unsigned long ns)
2240 {
2241 u32 r;
2242 unsigned x4, x16;
2243 unsigned long fck;
2244 unsigned long ticks;
2245
2246 /* ticks in DSI_FCK */
2247
2248 fck = dsi_fclk_rate();
2249 ticks = (fck / 1000 / 1000) * ns / 1000;
2250 x4 = 0;
2251 x16 = 0;
2252
2253 if (ticks > 0x1fff) {
2254 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2255 x4 = 1;
2256 x16 = 0;
2257 }
2258
2259 if (ticks > 0x1fff) {
2260 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2261 x4 = 0;
2262 x16 = 1;
2263 }
2264
2265 if (ticks > 0x1fff) {
2266 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2267 x4 = 1;
2268 x16 = 1;
2269 }
2270
2271 if (ticks > 0x1fff) {
2272 DSSWARN("LP_TX_TO over limit, setting it to max\n");
2273 ticks = 0x1fff;
2274 x4 = 1;
2275 x16 = 1;
2276 }
2277
2278 r = dsi_read_reg(DSI_TIMING2);
2279 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
2280 r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
2281 r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
2282 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2283 dsi_write_reg(DSI_TIMING2, r);
2284
2285 DSSDBG("LP_RX_TO %lu ns (%#lx ticks%s%s)\n",
2286 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2287 (fck / 1000 / 1000),
2288 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2289 }
2290
2291 static void dsi_set_ta_timeout(unsigned long ns)
2292 {
2293 u32 r;
2294 unsigned x8, x16;
2295 unsigned long fck;
2296 unsigned long ticks;
2297
2298 /* ticks in DSI_FCK */
2299 fck = dsi_fclk_rate();
2300 ticks = (fck / 1000 / 1000) * ns / 1000;
2301 x8 = 0;
2302 x16 = 0;
2303
2304 if (ticks > 0x1fff) {
2305 ticks = (fck / 1000 / 1000) * ns / 1000 / 8;
2306 x8 = 1;
2307 x16 = 0;
2308 }
2309
2310 if (ticks > 0x1fff) {
2311 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2312 x8 = 0;
2313 x16 = 1;
2314 }
2315
2316 if (ticks > 0x1fff) {
2317 ticks = (fck / 1000 / 1000) * ns / 1000 / (8 * 16);
2318 x8 = 1;
2319 x16 = 1;
2320 }
2321
2322 if (ticks > 0x1fff) {
2323 DSSWARN("TA_TO over limit, setting it to max\n");
2324 ticks = 0x1fff;
2325 x8 = 1;
2326 x16 = 1;
2327 }
2328
2329 r = dsi_read_reg(DSI_TIMING1);
2330 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
2331 r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
2332 r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
2333 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2334 dsi_write_reg(DSI_TIMING1, r);
2335
2336 DSSDBG("TA_TO %lu ns (%#lx ticks%s%s)\n",
2337 (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
2338 (fck / 1000 / 1000),
2339 ticks, x8 ? " x8" : "", x16 ? " x16" : "");
2340 }
2341
2342 static void dsi_set_stop_state_counter(unsigned long ns)
2343 {
2344 u32 r;
2345 unsigned x4, x16;
2346 unsigned long fck;
2347 unsigned long ticks;
2348
2349 /* ticks in DSI_FCK */
2350
2351 fck = dsi_fclk_rate();
2352 ticks = (fck / 1000 / 1000) * ns / 1000;
2353 x4 = 0;
2354 x16 = 0;
2355
2356 if (ticks > 0x1fff) {
2357 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2358 x4 = 1;
2359 x16 = 0;
2360 }
2361
2362 if (ticks > 0x1fff) {
2363 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2364 x4 = 0;
2365 x16 = 1;
2366 }
2367
2368 if (ticks > 0x1fff) {
2369 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2370 x4 = 1;
2371 x16 = 1;
2372 }
2373
2374 if (ticks > 0x1fff) {
2375 DSSWARN("STOP_STATE_COUNTER_IO over limit, "
2376 "setting it to max\n");
2377 ticks = 0x1fff;
2378 x4 = 1;
2379 x16 = 1;
2380 }
2381
2382 r = dsi_read_reg(DSI_TIMING1);
2383 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2384 r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
2385 r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
2386 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2387 dsi_write_reg(DSI_TIMING1, r);
2388
2389 DSSDBG("STOP_STATE_COUNTER %lu ns (%#lx ticks%s%s)\n",
2390 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2391 (fck / 1000 / 1000),
2392 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2393 }
2394
2395 static void dsi_set_hs_tx_timeout(unsigned long ns)
2396 {
2397 u32 r;
2398 unsigned x4, x16;
2399 unsigned long fck;
2400 unsigned long ticks;
2401
2402 /* ticks in TxByteClkHS */
2403
2404 fck = dsi_get_txbyteclkhs();
2405 ticks = (fck / 1000 / 1000) * ns / 1000;
2406 x4 = 0;
2407 x16 = 0;
2408
2409 if (ticks > 0x1fff) {
2410 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2411 x4 = 1;
2412 x16 = 0;
2413 }
2414
2415 if (ticks > 0x1fff) {
2416 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2417 x4 = 0;
2418 x16 = 1;
2419 }
2420
2421 if (ticks > 0x1fff) {
2422 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2423 x4 = 1;
2424 x16 = 1;
2425 }
2426
2427 if (ticks > 0x1fff) {
2428 DSSWARN("HS_TX_TO over limit, setting it to max\n");
2429 ticks = 0x1fff;
2430 x4 = 1;
2431 x16 = 1;
2432 }
2433
2434 r = dsi_read_reg(DSI_TIMING2);
2435 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
2436 r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
2437 r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
2438 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2439 dsi_write_reg(DSI_TIMING2, r);
2440
2441 DSSDBG("HS_TX_TO %lu ns (%#lx ticks%s%s)\n",
2442 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2443 (fck / 1000 / 1000),
2444 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2445 }
2446 static int dsi_proto_config(struct omap_dss_device *dssdev)
2447 {
2448 u32 r;
2449 int buswidth = 0;
2450
2451 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
2452 DSI_FIFO_SIZE_32,
2453 DSI_FIFO_SIZE_32,
2454 DSI_FIFO_SIZE_32);
2455
2456 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
2457 DSI_FIFO_SIZE_32,
2458 DSI_FIFO_SIZE_32,
2459 DSI_FIFO_SIZE_32);
2460
2461 /* XXX what values for the timeouts? */
2462 dsi_set_stop_state_counter(1000);
2463 dsi_set_ta_timeout(6400000);
2464 dsi_set_lp_rx_timeout(48000);
2465 dsi_set_hs_tx_timeout(1000000);
2466
2467 switch (dssdev->ctrl.pixel_size) {
2468 case 16:
2469 buswidth = 0;
2470 break;
2471 case 18:
2472 buswidth = 1;
2473 break;
2474 case 24:
2475 buswidth = 2;
2476 break;
2477 default:
2478 BUG();
2479 }
2480
2481 r = dsi_read_reg(DSI_CTRL);
2482 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2483 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2484 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2485 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2486 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2487 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2488 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2489 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2490 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2491 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2492 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2493
2494 dsi_write_reg(DSI_CTRL, r);
2495
2496 dsi_vc_initial_config(0);
2497 dsi_vc_initial_config(1);
2498 dsi_vc_initial_config(2);
2499 dsi_vc_initial_config(3);
2500
2501 return 0;
2502 }
2503
2504 static void dsi_proto_timings(struct omap_dss_device *dssdev)
2505 {
2506 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2507 unsigned tclk_pre, tclk_post;
2508 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2509 unsigned ths_trail, ths_exit;
2510 unsigned ddr_clk_pre, ddr_clk_post;
2511 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2512 unsigned ths_eot;
2513 u32 r;
2514
2515 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2516 ths_prepare = FLD_GET(r, 31, 24);
2517 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2518 ths_zero = ths_prepare_ths_zero - ths_prepare;
2519 ths_trail = FLD_GET(r, 15, 8);
2520 ths_exit = FLD_GET(r, 7, 0);
2521
2522 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2523 tlpx = FLD_GET(r, 22, 16) * 2;
2524 tclk_trail = FLD_GET(r, 15, 8);
2525 tclk_zero = FLD_GET(r, 7, 0);
2526
2527 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2528 tclk_prepare = FLD_GET(r, 7, 0);
2529
2530 /* min 8*UI */
2531 tclk_pre = 20;
2532 /* min 60ns + 52*UI */
2533 tclk_post = ns2ddr(60) + 26;
2534
2535 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2536 if (dssdev->phy.dsi.data1_lane != 0 &&
2537 dssdev->phy.dsi.data2_lane != 0)
2538 ths_eot = 2;
2539 else
2540 ths_eot = 4;
2541
2542 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2543 4);
2544 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2545
2546 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2547 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2548
2549 r = dsi_read_reg(DSI_CLK_TIMING);
2550 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2551 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2552 dsi_write_reg(DSI_CLK_TIMING, r);
2553
2554 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2555 ddr_clk_pre,
2556 ddr_clk_post);
2557
2558 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2559 DIV_ROUND_UP(ths_prepare, 4) +
2560 DIV_ROUND_UP(ths_zero + 3, 4);
2561
2562 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2563
2564 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2565 FLD_VAL(exit_hs_mode_lat, 15, 0);
2566 dsi_write_reg(DSI_VM_TIMING7, r);
2567
2568 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2569 enter_hs_mode_lat, exit_hs_mode_lat);
2570 }
2571
2572
2573 #define DSI_DECL_VARS \
2574 int __dsi_cb = 0; u32 __dsi_cv = 0;
2575
2576 #define DSI_FLUSH(ch) \
2577 if (__dsi_cb > 0) { \
2578 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2579 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2580 __dsi_cb = __dsi_cv = 0; \
2581 }
2582
2583 #define DSI_PUSH(ch, data) \
2584 do { \
2585 __dsi_cv |= (data) << (__dsi_cb * 8); \
2586 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2587 if (++__dsi_cb > 3) \
2588 DSI_FLUSH(ch); \
2589 } while (0)
2590
2591 static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2592 int x, int y, int w, int h)
2593 {
2594 /* Note: supports only 24bit colors in 32bit container */
2595 int first = 1;
2596 int fifo_stalls = 0;
2597 int max_dsi_packet_size;
2598 int max_data_per_packet;
2599 int max_pixels_per_packet;
2600 int pixels_left;
2601 int bytespp = dssdev->ctrl.pixel_size / 8;
2602 int scr_width;
2603 u32 __iomem *data;
2604 int start_offset;
2605 int horiz_inc;
2606 int current_x;
2607 struct omap_overlay *ovl;
2608
2609 debug_irq = 0;
2610
2611 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2612 x, y, w, h);
2613
2614 ovl = dssdev->manager->overlays[0];
2615
2616 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2617 return -EINVAL;
2618
2619 if (dssdev->ctrl.pixel_size != 24)
2620 return -EINVAL;
2621
2622 scr_width = ovl->info.screen_width;
2623 data = ovl->info.vaddr;
2624
2625 start_offset = scr_width * y + x;
2626 horiz_inc = scr_width - w;
2627 current_x = x;
2628
2629 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2630 * in fifo */
2631
2632 /* When using CPU, max long packet size is TX buffer size */
2633 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2634
2635 /* we seem to get better perf if we divide the tx fifo to half,
2636 and while the other half is being sent, we fill the other half
2637 max_dsi_packet_size /= 2; */
2638
2639 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2640
2641 max_pixels_per_packet = max_data_per_packet / bytespp;
2642
2643 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2644
2645 pixels_left = w * h;
2646
2647 DSSDBG("total pixels %d\n", pixels_left);
2648
2649 data += start_offset;
2650
2651 while (pixels_left > 0) {
2652 /* 0x2c = write_memory_start */
2653 /* 0x3c = write_memory_continue */
2654 u8 dcs_cmd = first ? 0x2c : 0x3c;
2655 int pixels;
2656 DSI_DECL_VARS;
2657 first = 0;
2658
2659 #if 1
2660 /* using fifo not empty */
2661 /* TX_FIFO_NOT_EMPTY */
2662 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
2663 fifo_stalls++;
2664 if (fifo_stalls > 0xfffff) {
2665 DSSERR("fifo stalls overflow, pixels left %d\n",
2666 pixels_left);
2667 dsi_if_enable(0);
2668 return -EIO;
2669 }
2670 udelay(1);
2671 }
2672 #elif 1
2673 /* using fifo emptiness */
2674 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2675 max_dsi_packet_size) {
2676 fifo_stalls++;
2677 if (fifo_stalls > 0xfffff) {
2678 DSSERR("fifo stalls overflow, pixels left %d\n",
2679 pixels_left);
2680 dsi_if_enable(0);
2681 return -EIO;
2682 }
2683 }
2684 #else
2685 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2686 fifo_stalls++;
2687 if (fifo_stalls > 0xfffff) {
2688 DSSERR("fifo stalls overflow, pixels left %d\n",
2689 pixels_left);
2690 dsi_if_enable(0);
2691 return -EIO;
2692 }
2693 }
2694 #endif
2695 pixels = min(max_pixels_per_packet, pixels_left);
2696
2697 pixels_left -= pixels;
2698
2699 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2700 1 + pixels * bytespp, 0);
2701
2702 DSI_PUSH(0, dcs_cmd);
2703
2704 while (pixels-- > 0) {
2705 u32 pix = __raw_readl(data++);
2706
2707 DSI_PUSH(0, (pix >> 16) & 0xff);
2708 DSI_PUSH(0, (pix >> 8) & 0xff);
2709 DSI_PUSH(0, (pix >> 0) & 0xff);
2710
2711 current_x++;
2712 if (current_x == x+w) {
2713 current_x = x;
2714 data += horiz_inc;
2715 }
2716 }
2717
2718 DSI_FLUSH(0);
2719 }
2720
2721 return 0;
2722 }
2723
2724 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
2725 u16 x, u16 y, u16 w, u16 h)
2726 {
2727 unsigned bytespp;
2728 unsigned bytespl;
2729 unsigned bytespf;
2730 unsigned total_len;
2731 unsigned packet_payload;
2732 unsigned packet_len;
2733 u32 l;
2734 bool use_te_trigger;
2735 const unsigned channel = 0;
2736 /* line buffer is 1024 x 24bits */
2737 /* XXX: for some reason using full buffer size causes considerable TX
2738 * slowdown with update sizes that fill the whole buffer */
2739 const unsigned line_buf_size = 1023 * 3;
2740
2741 use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
2742
2743 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
2744 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2745 x, y, w, h);
2746
2747 bytespp = dssdev->ctrl.pixel_size / 8;
2748 bytespl = w * bytespp;
2749 bytespf = bytespl * h;
2750
2751 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2752 * number of lines in a packet. See errata about VP_CLK_RATIO */
2753
2754 if (bytespf < line_buf_size)
2755 packet_payload = bytespf;
2756 else
2757 packet_payload = (line_buf_size) / bytespl * bytespl;
2758
2759 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
2760 total_len = (bytespf / packet_payload) * packet_len;
2761
2762 if (bytespf % packet_payload)
2763 total_len += (bytespf % packet_payload) + 1;
2764
2765 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
2766 dsi_write_reg(DSI_VC_TE(channel), l);
2767
2768 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
2769
2770 if (use_te_trigger)
2771 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
2772 else
2773 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
2774 dsi_write_reg(DSI_VC_TE(channel), l);
2775
2776 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2777 * because DSS interrupts are not capable of waking up the CPU and the
2778 * framedone interrupt could be delayed for quite a long time. I think
2779 * the same goes for any DSS interrupts, but for some reason I have not
2780 * seen the problem anywhere else than here.
2781 */
2782 dispc_disable_sidle();
2783
2784 dss_start_update(dssdev);
2785
2786 if (use_te_trigger) {
2787 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2788 * for TE is longer than the timer allows */
2789 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2790
2791 dsi_vc_send_bta(channel);
2792
2793 #ifdef DSI_CATCH_MISSING_TE
2794 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
2795 #endif
2796 }
2797 }
2798
2799 #ifdef DSI_CATCH_MISSING_TE
2800 static void dsi_te_timeout(unsigned long arg)
2801 {
2802 DSSERR("TE not received for 250ms!\n");
2803 }
2804 #endif
2805
2806 static void dsi_framedone_irq_callback(void *data, u32 mask)
2807 {
2808 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2809 * turns itself off. However, DSI still has the pixels in its buffers,
2810 * and is sending the data.
2811 */
2812
2813 /* SIDLEMODE back to smart-idle */
2814 dispc_enable_sidle();
2815
2816 dsi.framedone_received = true;
2817 wake_up(&dsi.waitqueue);
2818 }
2819
2820 static void dsi_set_update_region(struct omap_dss_device *dssdev,
2821 u16 x, u16 y, u16 w, u16 h)
2822 {
2823 spin_lock(&dsi.update_lock);
2824 if (dsi.update_region.dirty) {
2825 dsi.update_region.x = min(x, dsi.update_region.x);
2826 dsi.update_region.y = min(y, dsi.update_region.y);
2827 dsi.update_region.w = max(w, dsi.update_region.w);
2828 dsi.update_region.h = max(h, dsi.update_region.h);
2829 } else {
2830 dsi.update_region.x = x;
2831 dsi.update_region.y = y;
2832 dsi.update_region.w = w;
2833 dsi.update_region.h = h;
2834 }
2835
2836 dsi.update_region.device = dssdev;
2837 dsi.update_region.dirty = true;
2838
2839 spin_unlock(&dsi.update_lock);
2840
2841 }
2842
2843 static int dsi_set_update_mode(struct omap_dss_device *dssdev,
2844 enum omap_dss_update_mode mode)
2845 {
2846 int r = 0;
2847 int i;
2848
2849 WARN_ON(!dsi_bus_is_locked());
2850
2851 if (dsi.update_mode != mode) {
2852 dsi.update_mode = mode;
2853
2854 /* Mark the overlays dirty, and do apply(), so that we get the
2855 * overlays configured properly after update mode change. */
2856 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2857 struct omap_overlay *ovl;
2858 ovl = omap_dss_get_overlay(i);
2859 if (ovl->manager == dssdev->manager)
2860 ovl->info_dirty = true;
2861 }
2862
2863 r = dssdev->manager->apply(dssdev->manager);
2864
2865 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE &&
2866 mode == OMAP_DSS_UPDATE_AUTO) {
2867 u16 w, h;
2868
2869 DSSDBG("starting auto update\n");
2870
2871 dssdev->get_resolution(dssdev, &w, &h);
2872
2873 dsi_set_update_region(dssdev, 0, 0, w, h);
2874
2875 wake_up(&dsi.waitqueue);
2876 }
2877 }
2878
2879 return r;
2880 }
2881
2882 static int dsi_set_te(struct omap_dss_device *dssdev, bool enable)
2883 {
2884 int r = 0;
2885
2886 if (dssdev->driver->enable_te) {
2887 r = dssdev->driver->enable_te(dssdev, enable);
2888 /* XXX for some reason, DSI TE breaks if we don't wait here.
2889 * Panel bug? Needs more studying */
2890 msleep(100);
2891 }
2892
2893 return r;
2894 }
2895
2896 static void dsi_handle_framedone(void)
2897 {
2898 int r;
2899 const int channel = 0;
2900 bool use_te_trigger;
2901
2902 use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
2903
2904 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
2905 DSSDBG("FRAMEDONE\n");
2906
2907 if (use_te_trigger) {
2908 /* enable LP_RX_TO again after the TE */
2909 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2910 }
2911
2912 /* Send BTA after the frame. We need this for the TE to work, as TE
2913 * trigger is only sent for BTAs without preceding packet. Thus we need
2914 * to BTA after the pixel packets so that next BTA will cause TE
2915 * trigger.
2916 *
2917 * This is not needed when TE is not in use, but we do it anyway to
2918 * make sure that the transfer has been completed. It would be more
2919 * optimal, but more complex, to wait only just before starting next
2920 * transfer. */
2921 r = dsi_vc_send_bta_sync(channel);
2922 if (r)
2923 DSSERR("BTA after framedone failed\n");
2924
2925 /* RX_FIFO_NOT_EMPTY */
2926 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2927 DSSERR("Received error during frame transfer:\n");
2928 dsi_vc_flush_receive_data(channel);
2929 }
2930
2931 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2932 dispc_fake_vsync_irq();
2933 #endif
2934 }
2935
2936 static int dsi_update_thread(void *data)
2937 {
2938 unsigned long timeout;
2939 struct omap_dss_device *device;
2940 u16 x, y, w, h;
2941
2942 while (1) {
2943 wait_event_interruptible(dsi.waitqueue,
2944 dsi.update_mode == OMAP_DSS_UPDATE_AUTO ||
2945 (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL &&
2946 dsi.update_region.dirty == true) ||
2947 kthread_should_stop());
2948
2949 if (kthread_should_stop())
2950 break;
2951
2952 dsi_bus_lock();
2953
2954 if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED ||
2955 kthread_should_stop()) {
2956 dsi_bus_unlock();
2957 break;
2958 }
2959
2960 dsi_perf_mark_setup();
2961
2962 if (dsi.update_region.dirty) {
2963 spin_lock(&dsi.update_lock);
2964 dsi.active_update_region = dsi.update_region;
2965 dsi.update_region.dirty = false;
2966 spin_unlock(&dsi.update_lock);
2967 }
2968
2969 device = dsi.active_update_region.device;
2970 x = dsi.active_update_region.x;
2971 y = dsi.active_update_region.y;
2972 w = dsi.active_update_region.w;
2973 h = dsi.active_update_region.h;
2974
2975 if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2976
2977 if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
2978 dss_setup_partial_planes(device,
2979 &x, &y, &w, &h);
2980
2981 dispc_set_lcd_size(w, h);
2982 }
2983
2984 if (dsi.active_update_region.dirty) {
2985 dsi.active_update_region.dirty = false;
2986 /* XXX TODO we don't need to send the coords, if they
2987 * are the same that are already programmed to the
2988 * panel. That should speed up manual update a bit */
2989 device->driver->setup_update(device, x, y, w, h);
2990 }
2991
2992 dsi_perf_mark_start();
2993
2994 if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2995 dsi_vc_config_vp(0);
2996
2997 if (dsi.te_enabled && dsi.use_ext_te)
2998 device->driver->wait_for_te(device);
2999
3000 dsi.framedone_received = false;
3001
3002 dsi_update_screen_dispc(device, x, y, w, h);
3003
3004 /* wait for framedone */
3005 timeout = msecs_to_jiffies(1000);
3006 wait_event_timeout(dsi.waitqueue,
3007 dsi.framedone_received == true,
3008 timeout);
3009
3010 if (!dsi.framedone_received) {
3011 DSSERR("framedone timeout\n");
3012 DSSERR("failed update %d,%d %dx%d\n",
3013 x, y, w, h);
3014
3015 dispc_enable_sidle();
3016 dispc_enable_lcd_out(0);
3017
3018 dsi_reset_tx_fifo(0);
3019 } else {
3020 dsi_handle_framedone();
3021 dsi_perf_show("DISPC");
3022 }
3023 } else {
3024 dsi_update_screen_l4(device, x, y, w, h);
3025 dsi_perf_show("L4");
3026 }
3027
3028 complete_all(&dsi.update_completion);
3029
3030 dsi_bus_unlock();
3031 }
3032
3033 DSSDBG("update thread exiting\n");
3034
3035 return 0;
3036 }
3037
3038
3039
3040 /* Display funcs */
3041
3042 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
3043 {
3044 int r;
3045
3046 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
3047 DISPC_IRQ_FRAMEDONE);
3048 if (r) {
3049 DSSERR("can't get FRAMEDONE irq\n");
3050 return r;
3051 }
3052
3053 dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
3054
3055 dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
3056 dispc_enable_fifohandcheck(1);
3057
3058 dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
3059
3060 {
3061 struct omap_video_timings timings = {
3062 .hsw = 1,
3063 .hfp = 1,
3064 .hbp = 1,
3065 .vsw = 1,
3066 .vfp = 0,
3067 .vbp = 0,
3068 };
3069
3070 dispc_set_lcd_timings(&timings);
3071 }
3072
3073 return 0;
3074 }
3075
3076 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
3077 {
3078 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
3079 DISPC_IRQ_FRAMEDONE);
3080 }
3081
3082 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
3083 {
3084 struct dsi_clock_info cinfo;
3085 int r;
3086
3087 /* we always use DSS2_FCK as input clock */
3088 cinfo.use_dss2_fck = true;
3089 cinfo.regn = dssdev->phy.dsi.div.regn;
3090 cinfo.regm = dssdev->phy.dsi.div.regm;
3091 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
3092 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
3093 r = dsi_calc_clock_rates(&cinfo);
3094 if (r)
3095 return r;
3096
3097 r = dsi_pll_set_clock_div(&cinfo);
3098 if (r) {
3099 DSSERR("Failed to set dsi clocks\n");
3100 return r;
3101 }
3102
3103 return 0;
3104 }
3105
3106 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3107 {
3108 struct dispc_clock_info dispc_cinfo;
3109 int r;
3110 unsigned long long fck;
3111
3112 fck = dsi_get_dsi1_pll_rate();
3113
3114 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3115 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3116
3117 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3118 if (r) {
3119 DSSERR("Failed to calc dispc clocks\n");
3120 return r;
3121 }
3122
3123 r = dispc_set_clock_div(&dispc_cinfo);
3124 if (r) {
3125 DSSERR("Failed to set dispc clocks\n");
3126 return r;
3127 }
3128
3129 return 0;
3130 }
3131
3132 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3133 {
3134 int r;
3135
3136 _dsi_print_reset_status();
3137
3138 r = dsi_pll_init(dssdev, true, true);
3139 if (r)
3140 goto err0;
3141
3142 r = dsi_configure_dsi_clocks(dssdev);
3143 if (r)
3144 goto err1;
3145
3146 dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
3147 dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
3148
3149 DSSDBG("PLL OK\n");
3150
3151 r = dsi_configure_dispc_clocks(dssdev);
3152 if (r)
3153 goto err2;
3154
3155 r = dsi_complexio_init(dssdev);
3156 if (r)
3157 goto err2;
3158
3159 _dsi_print_reset_status();
3160
3161 dsi_proto_timings(dssdev);
3162 dsi_set_lp_clk_divisor(dssdev);
3163
3164 if (1)
3165 _dsi_print_reset_status();
3166
3167 r = dsi_proto_config(dssdev);
3168 if (r)
3169 goto err3;
3170
3171 /* enable interface */
3172 dsi_vc_enable(0, 1);
3173 dsi_vc_enable(1, 1);
3174 dsi_vc_enable(2, 1);
3175 dsi_vc_enable(3, 1);
3176 dsi_if_enable(1);
3177 dsi_force_tx_stop_mode_io();
3178
3179 if (dssdev->driver->enable) {
3180 r = dssdev->driver->enable(dssdev);
3181 if (r)
3182 goto err4;
3183 }
3184
3185 /* enable high-speed after initial config */
3186 omapdss_dsi_vc_enable_hs(0, 1);
3187
3188 return 0;
3189 err4:
3190 dsi_if_enable(0);
3191 err3:
3192 dsi_complexio_uninit();
3193 err2:
3194 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3195 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3196 err1:
3197 dsi_pll_uninit();
3198 err0:
3199 return r;
3200 }
3201
3202 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3203 {
3204 if (dssdev->driver->disable)
3205 dssdev->driver->disable(dssdev);
3206
3207 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3208 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3209 dsi_complexio_uninit();
3210 dsi_pll_uninit();
3211 }
3212
3213 static int dsi_core_init(void)
3214 {
3215 /* Autoidle */
3216 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3217
3218 /* ENWAKEUP */
3219 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3220
3221 /* SIDLEMODE smart-idle */
3222 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3223
3224 _dsi_initialize_irq();
3225
3226 return 0;
3227 }
3228
3229 static int dsi_display_enable(struct omap_dss_device *dssdev)
3230 {
3231 int r = 0;
3232
3233 DSSDBG("dsi_display_enable\n");
3234
3235 mutex_lock(&dsi.lock);
3236 dsi_bus_lock();
3237
3238 r = omap_dss_start_device(dssdev);
3239 if (r) {
3240 DSSERR("failed to start device\n");
3241 goto err0;
3242 }
3243
3244 if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
3245 DSSERR("dssdev already enabled\n");
3246 r = -EINVAL;
3247 goto err1;
3248 }
3249
3250 enable_clocks(1);
3251 dsi_enable_pll_clock(1);
3252
3253 r = _dsi_reset();
3254 if (r)
3255 goto err2;
3256
3257 dsi_core_init();
3258
3259 r = dsi_display_init_dispc(dssdev);
3260 if (r)
3261 goto err2;
3262
3263 r = dsi_display_init_dsi(dssdev);
3264 if (r)
3265 goto err3;
3266
3267 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
3268
3269 dsi.use_ext_te = dssdev->phy.dsi.ext_te;
3270 r = dsi_set_te(dssdev, dsi.te_enabled);
3271 if (r)
3272 goto err4;
3273
3274 dsi_set_update_mode(dssdev, dsi.user_update_mode);
3275
3276 dsi_bus_unlock();
3277 mutex_unlock(&dsi.lock);
3278
3279 return 0;
3280
3281 err4:
3282
3283 dsi_display_uninit_dsi(dssdev);
3284 err3:
3285 dsi_display_uninit_dispc(dssdev);
3286 err2:
3287 enable_clocks(0);
3288 dsi_enable_pll_clock(0);
3289 err1:
3290 omap_dss_stop_device(dssdev);
3291 err0:
3292 dsi_bus_unlock();
3293 mutex_unlock(&dsi.lock);
3294 DSSDBG("dsi_display_enable FAILED\n");
3295 return r;
3296 }
3297
3298 static void dsi_display_disable(struct omap_dss_device *dssdev)
3299 {
3300 DSSDBG("dsi_display_disable\n");
3301
3302 mutex_lock(&dsi.lock);
3303 dsi_bus_lock();
3304
3305 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||
3306 dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
3307 goto end;
3308
3309 dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
3310 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
3311
3312 dsi_display_uninit_dispc(dssdev);
3313
3314 dsi_display_uninit_dsi(dssdev);
3315
3316 enable_clocks(0);
3317 dsi_enable_pll_clock(0);
3318
3319 omap_dss_stop_device(dssdev);
3320 end:
3321 dsi_bus_unlock();
3322 mutex_unlock(&dsi.lock);
3323 }
3324
3325 static int dsi_display_suspend(struct omap_dss_device *dssdev)
3326 {
3327 DSSDBG("dsi_display_suspend\n");
3328
3329 mutex_lock(&dsi.lock);
3330 dsi_bus_lock();
3331
3332 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||
3333 dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
3334 goto end;
3335
3336 dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
3337 dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
3338
3339 dsi_display_uninit_dispc(dssdev);
3340
3341 dsi_display_uninit_dsi(dssdev);
3342
3343 enable_clocks(0);
3344 dsi_enable_pll_clock(0);
3345 end:
3346 dsi_bus_unlock();
3347 mutex_unlock(&dsi.lock);
3348
3349 return 0;
3350 }
3351
3352 static int dsi_display_resume(struct omap_dss_device *dssdev)
3353 {
3354 int r;
3355
3356 DSSDBG("dsi_display_resume\n");
3357
3358 mutex_lock(&dsi.lock);
3359 dsi_bus_lock();
3360
3361 if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) {
3362 DSSERR("dssdev not suspended\n");
3363 r = -EINVAL;
3364 goto err0;
3365 }
3366
3367 enable_clocks(1);
3368 dsi_enable_pll_clock(1);
3369
3370 r = _dsi_reset();
3371 if (r)
3372 goto err1;
3373
3374 dsi_core_init();
3375
3376 r = dsi_display_init_dispc(dssdev);
3377 if (r)
3378 goto err1;
3379
3380 r = dsi_display_init_dsi(dssdev);
3381 if (r)
3382 goto err2;
3383
3384 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
3385
3386 r = dsi_set_te(dssdev, dsi.te_enabled);
3387 if (r)
3388 goto err2;
3389
3390 dsi_set_update_mode(dssdev, dsi.user_update_mode);
3391
3392 dsi_bus_unlock();
3393 mutex_unlock(&dsi.lock);
3394
3395 return 0;
3396
3397 err2:
3398 dsi_display_uninit_dispc(dssdev);
3399 err1:
3400 enable_clocks(0);
3401 dsi_enable_pll_clock(0);
3402 err0:
3403 dsi_bus_unlock();
3404 mutex_unlock(&dsi.lock);
3405 DSSDBG("dsi_display_resume FAILED\n");
3406 return r;
3407 }
3408
3409 static int dsi_display_update(struct omap_dss_device *dssdev,
3410 u16 x, u16 y, u16 w, u16 h)
3411 {
3412 int r = 0;
3413 u16 dw, dh;
3414
3415 DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h);
3416
3417 mutex_lock(&dsi.lock);
3418
3419 if (dsi.update_mode != OMAP_DSS_UPDATE_MANUAL)
3420 goto end;
3421
3422 if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
3423 goto end;
3424
3425 dssdev->get_resolution(dssdev, &dw, &dh);
3426
3427 if (x > dw || y > dh)
3428 goto end;
3429
3430 if (x + w > dw)
3431 w = dw - x;
3432
3433 if (y + h > dh)
3434 h = dh - y;
3435
3436 if (w == 0 || h == 0)
3437 goto end;
3438
3439 if (w == 1) {
3440 r = -EINVAL;
3441 goto end;
3442 }
3443
3444 dsi_set_update_region(dssdev, x, y, w, h);
3445
3446 wake_up(&dsi.waitqueue);
3447
3448 end:
3449 mutex_unlock(&dsi.lock);
3450
3451 return r;
3452 }
3453
3454 static int dsi_display_sync(struct omap_dss_device *dssdev)
3455 {
3456 bool wait;
3457
3458 DSSDBG("dsi_display_sync()\n");
3459
3460 mutex_lock(&dsi.lock);
3461 dsi_bus_lock();
3462
3463 if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL &&
3464 dsi.update_region.dirty) {
3465 INIT_COMPLETION(dsi.update_completion);
3466 wait = true;
3467 } else {
3468 wait = false;
3469 }
3470
3471 dsi_bus_unlock();
3472 mutex_unlock(&dsi.lock);
3473
3474 if (wait)
3475 wait_for_completion_interruptible(&dsi.update_completion);
3476
3477 DSSDBG("dsi_display_sync() done\n");
3478 return 0;
3479 }
3480
3481 static int dsi_display_set_update_mode(struct omap_dss_device *dssdev,
3482 enum omap_dss_update_mode mode)
3483 {
3484 int r = 0;
3485
3486 DSSDBGF("%d", mode);
3487
3488 mutex_lock(&dsi.lock);
3489 dsi_bus_lock();
3490
3491 dsi.user_update_mode = mode;
3492 r = dsi_set_update_mode(dssdev, mode);
3493
3494 dsi_bus_unlock();
3495 mutex_unlock(&dsi.lock);
3496
3497 return r;
3498 }
3499
3500 static enum omap_dss_update_mode dsi_display_get_update_mode(
3501 struct omap_dss_device *dssdev)
3502 {
3503 return dsi.update_mode;
3504 }
3505
3506
3507 static int dsi_display_enable_te(struct omap_dss_device *dssdev, bool enable)
3508 {
3509 int r = 0;
3510
3511 DSSDBGF("%d", enable);
3512
3513 if (!dssdev->driver->enable_te)
3514 return -ENOENT;
3515
3516 dsi_bus_lock();
3517
3518 dsi.te_enabled = enable;
3519
3520 if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
3521 goto end;
3522
3523 r = dsi_set_te(dssdev, enable);
3524 end:
3525 dsi_bus_unlock();
3526
3527 return r;
3528 }
3529
3530 static int dsi_display_get_te(struct omap_dss_device *dssdev)
3531 {
3532 return dsi.te_enabled;
3533 }
3534
3535 static int dsi_display_set_rotate(struct omap_dss_device *dssdev, u8 rotate)
3536 {
3537
3538 DSSDBGF("%d", rotate);
3539
3540 if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)
3541 return -EINVAL;
3542
3543 dsi_bus_lock();
3544 dssdev->driver->set_rotate(dssdev, rotate);
3545 if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
3546 u16 w, h;
3547 /* the display dimensions may have changed, so set a new
3548 * update region */
3549 dssdev->get_resolution(dssdev, &w, &h);
3550 dsi_set_update_region(dssdev, 0, 0, w, h);
3551 }
3552 dsi_bus_unlock();
3553
3554 return 0;
3555 }
3556
3557 static u8 dsi_display_get_rotate(struct omap_dss_device *dssdev)
3558 {
3559 if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)
3560 return 0;
3561
3562 return dssdev->driver->get_rotate(dssdev);
3563 }
3564
3565 static int dsi_display_set_mirror(struct omap_dss_device *dssdev, bool mirror)
3566 {
3567 DSSDBGF("%d", mirror);
3568
3569 if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)
3570 return -EINVAL;
3571
3572 dsi_bus_lock();
3573 dssdev->driver->set_mirror(dssdev, mirror);
3574 dsi_bus_unlock();
3575
3576 return 0;
3577 }
3578
3579 static bool dsi_display_get_mirror(struct omap_dss_device *dssdev)
3580 {
3581 if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)
3582 return 0;
3583
3584 return dssdev->driver->get_mirror(dssdev);
3585 }
3586
3587 static int dsi_display_memory_read(struct omap_dss_device *dssdev,
3588 void *buf, size_t size,
3589 u16 x, u16 y, u16 w, u16 h)
3590 {
3591 int r;
3592
3593 DSSDBGF("");
3594
3595 if (!dssdev->driver->memory_read)
3596 return -EINVAL;
3597
3598 if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
3599 return -EIO;
3600
3601 dsi_bus_lock();
3602
3603 r = dssdev->driver->memory_read(dssdev, buf, size,
3604 x, y, w, h);
3605
3606 /* Memory read usually changes the update area. This will
3607 * force the next update to re-set the update area */
3608 dsi.active_update_region.dirty = true;
3609
3610 dsi_bus_unlock();
3611
3612 return r;
3613 }
3614
3615 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3616 u32 fifo_size, enum omap_burst_size *burst_size,
3617 u32 *fifo_low, u32 *fifo_high)
3618 {
3619 unsigned burst_size_bytes;
3620
3621 *burst_size = OMAP_DSS_BURST_16x32;
3622 burst_size_bytes = 16 * 32 / 8;
3623
3624 *fifo_high = fifo_size - burst_size_bytes;
3625 *fifo_low = fifo_size - burst_size_bytes * 8;
3626 }
3627
3628 int dsi_init_display(struct omap_dss_device *dssdev)
3629 {
3630 DSSDBG("DSI init\n");
3631
3632 dssdev->enable = dsi_display_enable;
3633 dssdev->disable = dsi_display_disable;
3634 dssdev->suspend = dsi_display_suspend;
3635 dssdev->resume = dsi_display_resume;
3636 dssdev->update = dsi_display_update;
3637 dssdev->sync = dsi_display_sync;
3638 dssdev->set_update_mode = dsi_display_set_update_mode;
3639 dssdev->get_update_mode = dsi_display_get_update_mode;
3640 dssdev->enable_te = dsi_display_enable_te;
3641 dssdev->get_te = dsi_display_get_te;
3642
3643 dssdev->get_rotate = dsi_display_get_rotate;
3644 dssdev->set_rotate = dsi_display_set_rotate;
3645
3646 dssdev->get_mirror = dsi_display_get_mirror;
3647 dssdev->set_mirror = dsi_display_set_mirror;
3648
3649 dssdev->memory_read = dsi_display_memory_read;
3650
3651 /* XXX these should be figured out dynamically */
3652 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3653 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3654
3655 dsi.vc[0].dssdev = dssdev;
3656 dsi.vc[1].dssdev = dssdev;
3657
3658 return 0;
3659 }
3660
3661 int dsi_init(struct platform_device *pdev)
3662 {
3663 u32 rev;
3664 int r;
3665 struct sched_param param = {
3666 .sched_priority = MAX_USER_RT_PRIO-1
3667 };
3668
3669 spin_lock_init(&dsi.errors_lock);
3670 dsi.errors = 0;
3671
3672 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3673 spin_lock_init(&dsi.irq_stats_lock);
3674 dsi.irq_stats.last_reset = jiffies;
3675 #endif
3676
3677 init_completion(&dsi.bta_completion);
3678 init_completion(&dsi.update_completion);
3679
3680 dsi.thread = kthread_create(dsi_update_thread, NULL, "dsi");
3681 if (IS_ERR(dsi.thread)) {
3682 DSSERR("cannot create kthread\n");
3683 r = PTR_ERR(dsi.thread);
3684 goto err0;
3685 }
3686 sched_setscheduler(dsi.thread, SCHED_FIFO, &param);
3687
3688 init_waitqueue_head(&dsi.waitqueue);
3689 spin_lock_init(&dsi.update_lock);
3690
3691 mutex_init(&dsi.lock);
3692 sema_init(&dsi.bus_lock, 1);
3693
3694 #ifdef DSI_CATCH_MISSING_TE
3695 init_timer(&dsi.te_timer);
3696 dsi.te_timer.function = dsi_te_timeout;
3697 dsi.te_timer.data = 0;
3698 #endif
3699
3700 dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
3701 dsi.user_update_mode = OMAP_DSS_UPDATE_DISABLED;
3702
3703 dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
3704 if (!dsi.base) {
3705 DSSERR("can't ioremap DSI\n");
3706 r = -ENOMEM;
3707 goto err1;
3708 }
3709
3710 dsi.vdds_dsi_reg = dss_get_vdds_dsi();
3711 if (IS_ERR(dsi.vdds_dsi_reg)) {
3712 iounmap(dsi.base);
3713 DSSERR("can't get VDDS_DSI regulator\n");
3714 r = PTR_ERR(dsi.vdds_dsi_reg);
3715 goto err2;
3716 }
3717
3718 enable_clocks(1);
3719
3720 rev = dsi_read_reg(DSI_REVISION);
3721 printk(KERN_INFO "OMAP DSI rev %d.%d\n",
3722 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3723
3724 enable_clocks(0);
3725
3726 wake_up_process(dsi.thread);
3727
3728 return 0;
3729 err2:
3730 iounmap(dsi.base);
3731 err1:
3732 kthread_stop(dsi.thread);
3733 err0:
3734 return r;
3735 }
3736
3737 void dsi_exit(void)
3738 {
3739 kthread_stop(dsi.thread);
3740
3741 iounmap(dsi.base);
3742
3743 DSSDBG("omap_dsi_exit\n");
3744 }
3745
kernel-based virtual machine