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[INET_SOCK]: Move struct inet_sock & helper functions to net/inet_sock.h
[linux-2.6/kvm.git] / drivers / net / skge.c
blobd8cc3aea032ab54d1be5ee91c13d9d4bc1de100d
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/in.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
37 #include <linux/ip.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/mii.h>
42 #include <asm/irq.h>
43
44 #include "skge.h"
45
46 #define DRV_NAME "skge"
47 #define DRV_VERSION "1.2"
48 #define PFX DRV_NAME " "
49
50 #define DEFAULT_TX_RING_SIZE 128
51 #define DEFAULT_RX_RING_SIZE 512
52 #define MAX_TX_RING_SIZE 1024
53 #define MAX_RX_RING_SIZE 4096
54 #define RX_COPY_THRESHOLD 128
55 #define RX_BUF_SIZE 1536
56 #define PHY_RETRIES 1000
57 #define ETH_JUMBO_MTU 9000
58 #define TX_WATCHDOG (5 * HZ)
59 #define NAPI_WEIGHT 64
60 #define BLINK_MS 250
61
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
66
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
83 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
84 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
85 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
86 { 0 }
87 };
88 MODULE_DEVICE_TABLE(pci, skge_id_table);
89
90 static int skge_up(struct net_device *dev);
91 static int skge_down(struct net_device *dev);
92 static void skge_tx_clean(struct skge_port *skge);
93 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
94 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
95 static void genesis_get_stats(struct skge_port *skge, u64 *data);
96 static void yukon_get_stats(struct skge_port *skge, u64 *data);
97 static void yukon_init(struct skge_hw *hw, int port);
98 static void yukon_reset(struct skge_hw *hw, int port);
99 static void genesis_mac_init(struct skge_hw *hw, int port);
100 static void genesis_reset(struct skge_hw *hw, int port);
101 static void genesis_link_up(struct skge_port *skge);
102
103 /* Avoid conditionals by using array */
104 static const int txqaddr[] = { Q_XA1, Q_XA2 };
105 static const int rxqaddr[] = { Q_R1, Q_R2 };
106 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
108 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
109
110 static int skge_get_regs_len(struct net_device *dev)
111 {
112 return 0x4000;
113 }
114
115 /*
116 * Returns copy of whole control register region
117 * Note: skip RAM address register because accessing it will
118 * cause bus hangs!
119 */
120 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
121 void *p)
122 {
123 const struct skge_port *skge = netdev_priv(dev);
124 const void __iomem *io = skge->hw->regs;
125
126 regs->version = 1;
127 memset(p, 0, regs->len);
128 memcpy_fromio(p, io, B3_RAM_ADDR);
129
130 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
131 regs->len - B3_RI_WTO_R1);
132 }
133
134 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
135 static int wol_supported(const struct skge_hw *hw)
136 {
137 return !((hw->chip_id == CHIP_ID_GENESIS ||
138 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
139 }
140
141 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
142 {
143 struct skge_port *skge = netdev_priv(dev);
144
145 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
146 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
147 }
148
149 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
150 {
151 struct skge_port *skge = netdev_priv(dev);
152 struct skge_hw *hw = skge->hw;
153
154 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
155 return -EOPNOTSUPP;
156
157 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
158 return -EOPNOTSUPP;
159
160 skge->wol = wol->wolopts == WAKE_MAGIC;
161
162 if (skge->wol) {
163 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
164
165 skge_write16(hw, WOL_CTRL_STAT,
166 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
167 WOL_CTL_ENA_MAGIC_PKT_UNIT);
168 } else
169 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
170
171 return 0;
172 }
173
174 /* Determine supported/advertised modes based on hardware.
175 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
176 */
177 static u32 skge_supported_modes(const struct skge_hw *hw)
178 {
179 u32 supported;
180
181 if (hw->copper) {
182 supported = SUPPORTED_10baseT_Half
183 | SUPPORTED_10baseT_Full
184 | SUPPORTED_100baseT_Half
185 | SUPPORTED_100baseT_Full
186 | SUPPORTED_1000baseT_Half
187 | SUPPORTED_1000baseT_Full
188 | SUPPORTED_Autoneg| SUPPORTED_TP;
189
190 if (hw->chip_id == CHIP_ID_GENESIS)
191 supported &= ~(SUPPORTED_10baseT_Half
192 | SUPPORTED_10baseT_Full
193 | SUPPORTED_100baseT_Half
194 | SUPPORTED_100baseT_Full);
195
196 else if (hw->chip_id == CHIP_ID_YUKON)
197 supported &= ~SUPPORTED_1000baseT_Half;
198 } else
199 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
200 | SUPPORTED_Autoneg;
201
202 return supported;
203 }
204
205 static int skge_get_settings(struct net_device *dev,
206 struct ethtool_cmd *ecmd)
207 {
208 struct skge_port *skge = netdev_priv(dev);
209 struct skge_hw *hw = skge->hw;
210
211 ecmd->transceiver = XCVR_INTERNAL;
212 ecmd->supported = skge_supported_modes(hw);
213
214 if (hw->copper) {
215 ecmd->port = PORT_TP;
216 ecmd->phy_address = hw->phy_addr;
217 } else
218 ecmd->port = PORT_FIBRE;
219
220 ecmd->advertising = skge->advertising;
221 ecmd->autoneg = skge->autoneg;
222 ecmd->speed = skge->speed;
223 ecmd->duplex = skge->duplex;
224 return 0;
225 }
226
227 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
228 {
229 struct skge_port *skge = netdev_priv(dev);
230 const struct skge_hw *hw = skge->hw;
231 u32 supported = skge_supported_modes(hw);
232
233 if (ecmd->autoneg == AUTONEG_ENABLE) {
234 ecmd->advertising = supported;
235 skge->duplex = -1;
236 skge->speed = -1;
237 } else {
238 u32 setting;
239
240 switch (ecmd->speed) {
241 case SPEED_1000:
242 if (ecmd->duplex == DUPLEX_FULL)
243 setting = SUPPORTED_1000baseT_Full;
244 else if (ecmd->duplex == DUPLEX_HALF)
245 setting = SUPPORTED_1000baseT_Half;
246 else
247 return -EINVAL;
248 break;
249 case SPEED_100:
250 if (ecmd->duplex == DUPLEX_FULL)
251 setting = SUPPORTED_100baseT_Full;
252 else if (ecmd->duplex == DUPLEX_HALF)
253 setting = SUPPORTED_100baseT_Half;
254 else
255 return -EINVAL;
256 break;
257
258 case SPEED_10:
259 if (ecmd->duplex == DUPLEX_FULL)
260 setting = SUPPORTED_10baseT_Full;
261 else if (ecmd->duplex == DUPLEX_HALF)
262 setting = SUPPORTED_10baseT_Half;
263 else
264 return -EINVAL;
265 break;
266 default:
267 return -EINVAL;
268 }
269
270 if ((setting & supported) == 0)
271 return -EINVAL;
272
273 skge->speed = ecmd->speed;
274 skge->duplex = ecmd->duplex;
275 }
276
277 skge->autoneg = ecmd->autoneg;
278 skge->advertising = ecmd->advertising;
279
280 if (netif_running(dev)) {
281 skge_down(dev);
282 skge_up(dev);
283 }
284 return (0);
285 }
286
287 static void skge_get_drvinfo(struct net_device *dev,
288 struct ethtool_drvinfo *info)
289 {
290 struct skge_port *skge = netdev_priv(dev);
291
292 strcpy(info->driver, DRV_NAME);
293 strcpy(info->version, DRV_VERSION);
294 strcpy(info->fw_version, "N/A");
295 strcpy(info->bus_info, pci_name(skge->hw->pdev));
296 }
297
298 static const struct skge_stat {
299 char name[ETH_GSTRING_LEN];
300 u16 xmac_offset;
301 u16 gma_offset;
302 } skge_stats[] = {
303 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
304 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
305
306 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
307 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
308 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
309 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
310 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
311 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
312 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
313 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
314
315 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
316 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
317 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
318 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
319 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
320 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
321
322 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
323 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
324 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
325 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
326 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
327 };
328
329 static int skge_get_stats_count(struct net_device *dev)
330 {
331 return ARRAY_SIZE(skge_stats);
332 }
333
334 static void skge_get_ethtool_stats(struct net_device *dev,
335 struct ethtool_stats *stats, u64 *data)
336 {
337 struct skge_port *skge = netdev_priv(dev);
338
339 if (skge->hw->chip_id == CHIP_ID_GENESIS)
340 genesis_get_stats(skge, data);
341 else
342 yukon_get_stats(skge, data);
343 }
344
345 /* Use hardware MIB variables for critical path statistics and
346 * transmit feedback not reported at interrupt.
347 * Other errors are accounted for in interrupt handler.
348 */
349 static struct net_device_stats *skge_get_stats(struct net_device *dev)
350 {
351 struct skge_port *skge = netdev_priv(dev);
352 u64 data[ARRAY_SIZE(skge_stats)];
353
354 if (skge->hw->chip_id == CHIP_ID_GENESIS)
355 genesis_get_stats(skge, data);
356 else
357 yukon_get_stats(skge, data);
358
359 skge->net_stats.tx_bytes = data[0];
360 skge->net_stats.rx_bytes = data[1];
361 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
362 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
363 skge->net_stats.multicast = data[5] + data[7];
364 skge->net_stats.collisions = data[10];
365 skge->net_stats.tx_aborted_errors = data[12];
366
367 return &skge->net_stats;
368 }
369
370 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
371 {
372 int i;
373
374 switch (stringset) {
375 case ETH_SS_STATS:
376 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
377 memcpy(data + i * ETH_GSTRING_LEN,
378 skge_stats[i].name, ETH_GSTRING_LEN);
379 break;
380 }
381 }
382
383 static void skge_get_ring_param(struct net_device *dev,
384 struct ethtool_ringparam *p)
385 {
386 struct skge_port *skge = netdev_priv(dev);
387
388 p->rx_max_pending = MAX_RX_RING_SIZE;
389 p->tx_max_pending = MAX_TX_RING_SIZE;
390 p->rx_mini_max_pending = 0;
391 p->rx_jumbo_max_pending = 0;
392
393 p->rx_pending = skge->rx_ring.count;
394 p->tx_pending = skge->tx_ring.count;
395 p->rx_mini_pending = 0;
396 p->rx_jumbo_pending = 0;
397 }
398
399 static int skge_set_ring_param(struct net_device *dev,
400 struct ethtool_ringparam *p)
401 {
402 struct skge_port *skge = netdev_priv(dev);
403
404 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
405 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
406 return -EINVAL;
407
408 skge->rx_ring.count = p->rx_pending;
409 skge->tx_ring.count = p->tx_pending;
410
411 if (netif_running(dev)) {
412 skge_down(dev);
413 skge_up(dev);
414 }
415
416 return 0;
417 }
418
419 static u32 skge_get_msglevel(struct net_device *netdev)
420 {
421 struct skge_port *skge = netdev_priv(netdev);
422 return skge->msg_enable;
423 }
424
425 static void skge_set_msglevel(struct net_device *netdev, u32 value)
426 {
427 struct skge_port *skge = netdev_priv(netdev);
428 skge->msg_enable = value;
429 }
430
431 static int skge_nway_reset(struct net_device *dev)
432 {
433 struct skge_port *skge = netdev_priv(dev);
434 struct skge_hw *hw = skge->hw;
435 int port = skge->port;
436
437 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
438 return -EINVAL;
439
440 spin_lock_bh(&hw->phy_lock);
441 if (hw->chip_id == CHIP_ID_GENESIS) {
442 genesis_reset(hw, port);
443 genesis_mac_init(hw, port);
444 } else {
445 yukon_reset(hw, port);
446 yukon_init(hw, port);
447 }
448 spin_unlock_bh(&hw->phy_lock);
449 return 0;
450 }
451
452 static int skge_set_sg(struct net_device *dev, u32 data)
453 {
454 struct skge_port *skge = netdev_priv(dev);
455 struct skge_hw *hw = skge->hw;
456
457 if (hw->chip_id == CHIP_ID_GENESIS && data)
458 return -EOPNOTSUPP;
459 return ethtool_op_set_sg(dev, data);
460 }
461
462 static int skge_set_tx_csum(struct net_device *dev, u32 data)
463 {
464 struct skge_port *skge = netdev_priv(dev);
465 struct skge_hw *hw = skge->hw;
466
467 if (hw->chip_id == CHIP_ID_GENESIS && data)
468 return -EOPNOTSUPP;
469
470 return ethtool_op_set_tx_csum(dev, data);
471 }
472
473 static u32 skge_get_rx_csum(struct net_device *dev)
474 {
475 struct skge_port *skge = netdev_priv(dev);
476
477 return skge->rx_csum;
478 }
479
480 /* Only Yukon supports checksum offload. */
481 static int skge_set_rx_csum(struct net_device *dev, u32 data)
482 {
483 struct skge_port *skge = netdev_priv(dev);
484
485 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
486 return -EOPNOTSUPP;
487
488 skge->rx_csum = data;
489 return 0;
490 }
491
492 static void skge_get_pauseparam(struct net_device *dev,
493 struct ethtool_pauseparam *ecmd)
494 {
495 struct skge_port *skge = netdev_priv(dev);
496
497 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
498 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
499 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
500 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
501
502 ecmd->autoneg = skge->autoneg;
503 }
504
505 static int skge_set_pauseparam(struct net_device *dev,
506 struct ethtool_pauseparam *ecmd)
507 {
508 struct skge_port *skge = netdev_priv(dev);
509
510 skge->autoneg = ecmd->autoneg;
511 if (ecmd->rx_pause && ecmd->tx_pause)
512 skge->flow_control = FLOW_MODE_SYMMETRIC;
513 else if (ecmd->rx_pause && !ecmd->tx_pause)
514 skge->flow_control = FLOW_MODE_REM_SEND;
515 else if (!ecmd->rx_pause && ecmd->tx_pause)
516 skge->flow_control = FLOW_MODE_LOC_SEND;
517 else
518 skge->flow_control = FLOW_MODE_NONE;
519
520 if (netif_running(dev)) {
521 skge_down(dev);
522 skge_up(dev);
523 }
524 return 0;
525 }
526
527 /* Chip internal frequency for clock calculations */
528 static inline u32 hwkhz(const struct skge_hw *hw)
529 {
530 if (hw->chip_id == CHIP_ID_GENESIS)
531 return 53215; /* or: 53.125 MHz */
532 else
533 return 78215; /* or: 78.125 MHz */
534 }
535
536 /* Chip HZ to microseconds */
537 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
538 {
539 return (ticks * 1000) / hwkhz(hw);
540 }
541
542 /* Microseconds to chip HZ */
543 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
544 {
545 return hwkhz(hw) * usec / 1000;
546 }
547
548 static int skge_get_coalesce(struct net_device *dev,
549 struct ethtool_coalesce *ecmd)
550 {
551 struct skge_port *skge = netdev_priv(dev);
552 struct skge_hw *hw = skge->hw;
553 int port = skge->port;
554
555 ecmd->rx_coalesce_usecs = 0;
556 ecmd->tx_coalesce_usecs = 0;
557
558 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
559 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
560 u32 msk = skge_read32(hw, B2_IRQM_MSK);
561
562 if (msk & rxirqmask[port])
563 ecmd->rx_coalesce_usecs = delay;
564 if (msk & txirqmask[port])
565 ecmd->tx_coalesce_usecs = delay;
566 }
567
568 return 0;
569 }
570
571 /* Note: interrupt timer is per board, but can turn on/off per port */
572 static int skge_set_coalesce(struct net_device *dev,
573 struct ethtool_coalesce *ecmd)
574 {
575 struct skge_port *skge = netdev_priv(dev);
576 struct skge_hw *hw = skge->hw;
577 int port = skge->port;
578 u32 msk = skge_read32(hw, B2_IRQM_MSK);
579 u32 delay = 25;
580
581 if (ecmd->rx_coalesce_usecs == 0)
582 msk &= ~rxirqmask[port];
583 else if (ecmd->rx_coalesce_usecs < 25 ||
584 ecmd->rx_coalesce_usecs > 33333)
585 return -EINVAL;
586 else {
587 msk |= rxirqmask[port];
588 delay = ecmd->rx_coalesce_usecs;
589 }
590
591 if (ecmd->tx_coalesce_usecs == 0)
592 msk &= ~txirqmask[port];
593 else if (ecmd->tx_coalesce_usecs < 25 ||
594 ecmd->tx_coalesce_usecs > 33333)
595 return -EINVAL;
596 else {
597 msk |= txirqmask[port];
598 delay = min(delay, ecmd->rx_coalesce_usecs);
599 }
600
601 skge_write32(hw, B2_IRQM_MSK, msk);
602 if (msk == 0)
603 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
604 else {
605 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
606 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
607 }
608 return 0;
609 }
610
611 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
612 static void skge_led(struct skge_port *skge, enum led_mode mode)
613 {
614 struct skge_hw *hw = skge->hw;
615 int port = skge->port;
616
617 spin_lock_bh(&hw->phy_lock);
618 if (hw->chip_id == CHIP_ID_GENESIS) {
619 switch (mode) {
620 case LED_MODE_OFF:
621 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
622 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
623 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
624 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
625 break;
626
627 case LED_MODE_ON:
628 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
629 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
630
631 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
632 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
633
634 break;
635
636 case LED_MODE_TST:
637 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
638 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
639 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
640
641 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
642 break;
643 }
644 } else {
645 switch (mode) {
646 case LED_MODE_OFF:
647 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
648 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
649 PHY_M_LED_MO_DUP(MO_LED_OFF) |
650 PHY_M_LED_MO_10(MO_LED_OFF) |
651 PHY_M_LED_MO_100(MO_LED_OFF) |
652 PHY_M_LED_MO_1000(MO_LED_OFF) |
653 PHY_M_LED_MO_RX(MO_LED_OFF));
654 break;
655 case LED_MODE_ON:
656 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
657 PHY_M_LED_PULS_DUR(PULS_170MS) |
658 PHY_M_LED_BLINK_RT(BLINK_84MS) |
659 PHY_M_LEDC_TX_CTRL |
660 PHY_M_LEDC_DP_CTRL);
661
662 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
663 PHY_M_LED_MO_RX(MO_LED_OFF) |
664 (skge->speed == SPEED_100 ?
665 PHY_M_LED_MO_100(MO_LED_ON) : 0));
666 break;
667 case LED_MODE_TST:
668 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
669 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
670 PHY_M_LED_MO_DUP(MO_LED_ON) |
671 PHY_M_LED_MO_10(MO_LED_ON) |
672 PHY_M_LED_MO_100(MO_LED_ON) |
673 PHY_M_LED_MO_1000(MO_LED_ON) |
674 PHY_M_LED_MO_RX(MO_LED_ON));
675 }
676 }
677 spin_unlock_bh(&hw->phy_lock);
678 }
679
680 /* blink LED's for finding board */
681 static int skge_phys_id(struct net_device *dev, u32 data)
682 {
683 struct skge_port *skge = netdev_priv(dev);
684 unsigned long ms;
685 enum led_mode mode = LED_MODE_TST;
686
687 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
688 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
689 else
690 ms = data * 1000;
691
692 while (ms > 0) {
693 skge_led(skge, mode);
694 mode ^= LED_MODE_TST;
695
696 if (msleep_interruptible(BLINK_MS))
697 break;
698 ms -= BLINK_MS;
699 }
700
701 /* back to regular LED state */
702 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
703
704 return 0;
705 }
706
707 static struct ethtool_ops skge_ethtool_ops = {
708 .get_settings = skge_get_settings,
709 .set_settings = skge_set_settings,
710 .get_drvinfo = skge_get_drvinfo,
711 .get_regs_len = skge_get_regs_len,
712 .get_regs = skge_get_regs,
713 .get_wol = skge_get_wol,
714 .set_wol = skge_set_wol,
715 .get_msglevel = skge_get_msglevel,
716 .set_msglevel = skge_set_msglevel,
717 .nway_reset = skge_nway_reset,
718 .get_link = ethtool_op_get_link,
719 .get_ringparam = skge_get_ring_param,
720 .set_ringparam = skge_set_ring_param,
721 .get_pauseparam = skge_get_pauseparam,
722 .set_pauseparam = skge_set_pauseparam,
723 .get_coalesce = skge_get_coalesce,
724 .set_coalesce = skge_set_coalesce,
725 .get_sg = ethtool_op_get_sg,
726 .set_sg = skge_set_sg,
727 .get_tx_csum = ethtool_op_get_tx_csum,
728 .set_tx_csum = skge_set_tx_csum,
729 .get_rx_csum = skge_get_rx_csum,
730 .set_rx_csum = skge_set_rx_csum,
731 .get_strings = skge_get_strings,
732 .phys_id = skge_phys_id,
733 .get_stats_count = skge_get_stats_count,
734 .get_ethtool_stats = skge_get_ethtool_stats,
735 .get_perm_addr = ethtool_op_get_perm_addr,
736 };
737
738 /*
739 * Allocate ring elements and chain them together
740 * One-to-one association of board descriptors with ring elements
741 */
742 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
743 {
744 struct skge_tx_desc *d;
745 struct skge_element *e;
746 int i;
747
748 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
749 if (!ring->start)
750 return -ENOMEM;
751
752 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
753 e->desc = d;
754 e->skb = NULL;
755 if (i == ring->count - 1) {
756 e->next = ring->start;
757 d->next_offset = base;
758 } else {
759 e->next = e + 1;
760 d->next_offset = base + (i+1) * sizeof(*d);
761 }
762 }
763 ring->to_use = ring->to_clean = ring->start;
764
765 return 0;
766 }
767
768 /* Allocate and setup a new buffer for receiving */
769 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
770 struct sk_buff *skb, unsigned int bufsize)
771 {
772 struct skge_rx_desc *rd = e->desc;
773 u64 map;
774
775 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
776 PCI_DMA_FROMDEVICE);
777
778 rd->dma_lo = map;
779 rd->dma_hi = map >> 32;
780 e->skb = skb;
781 rd->csum1_start = ETH_HLEN;
782 rd->csum2_start = ETH_HLEN;
783 rd->csum1 = 0;
784 rd->csum2 = 0;
785
786 wmb();
787
788 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
789 pci_unmap_addr_set(e, mapaddr, map);
790 pci_unmap_len_set(e, maplen, bufsize);
791 }
792
793 /* Resume receiving using existing skb,
794 * Note: DMA address is not changed by chip.
795 * MTU not changed while receiver active.
796 */
797 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
798 {
799 struct skge_rx_desc *rd = e->desc;
800
801 rd->csum2 = 0;
802 rd->csum2_start = ETH_HLEN;
803
804 wmb();
805
806 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
807 }
808
809
810 /* Free all buffers in receive ring, assumes receiver stopped */
811 static void skge_rx_clean(struct skge_port *skge)
812 {
813 struct skge_hw *hw = skge->hw;
814 struct skge_ring *ring = &skge->rx_ring;
815 struct skge_element *e;
816
817 e = ring->start;
818 do {
819 struct skge_rx_desc *rd = e->desc;
820 rd->control = 0;
821 if (e->skb) {
822 pci_unmap_single(hw->pdev,
823 pci_unmap_addr(e, mapaddr),
824 pci_unmap_len(e, maplen),
825 PCI_DMA_FROMDEVICE);
826 dev_kfree_skb(e->skb);
827 e->skb = NULL;
828 }
829 } while ((e = e->next) != ring->start);
830 }
831
832
833 /* Allocate buffers for receive ring
834 * For receive: to_clean is next received frame.
835 */
836 static int skge_rx_fill(struct skge_port *skge)
837 {
838 struct skge_ring *ring = &skge->rx_ring;
839 struct skge_element *e;
840
841 e = ring->start;
842 do {
843 struct sk_buff *skb;
844
845 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
846 if (!skb)
847 return -ENOMEM;
848
849 skb_reserve(skb, NET_IP_ALIGN);
850 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
851 } while ( (e = e->next) != ring->start);
852
853 ring->to_clean = ring->start;
854 return 0;
855 }
856
857 static void skge_link_up(struct skge_port *skge)
858 {
859 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
860 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
861
862 netif_carrier_on(skge->netdev);
863 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
864 netif_wake_queue(skge->netdev);
865
866 if (netif_msg_link(skge))
867 printk(KERN_INFO PFX
868 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
869 skge->netdev->name, skge->speed,
870 skge->duplex == DUPLEX_FULL ? "full" : "half",
871 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
872 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
873 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
874 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
875 "unknown");
876 }
877
878 static void skge_link_down(struct skge_port *skge)
879 {
880 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
881 netif_carrier_off(skge->netdev);
882 netif_stop_queue(skge->netdev);
883
884 if (netif_msg_link(skge))
885 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
886 }
887
888 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
889 {
890 int i;
891
892 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
893 xm_read16(hw, port, XM_PHY_DATA);
894
895 /* Need to wait for external PHY */
896 for (i = 0; i < PHY_RETRIES; i++) {
897 udelay(1);
898 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
899 goto ready;
900 }
901
902 return -ETIMEDOUT;
903 ready:
904 *val = xm_read16(hw, port, XM_PHY_DATA);
905
906 return 0;
907 }
908
909 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
910 {
911 u16 v = 0;
912 if (__xm_phy_read(hw, port, reg, &v))
913 printk(KERN_WARNING PFX "%s: phy read timed out\n",
914 hw->dev[port]->name);
915 return v;
916 }
917
918 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
919 {
920 int i;
921
922 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
923 for (i = 0; i < PHY_RETRIES; i++) {
924 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
925 goto ready;
926 udelay(1);
927 }
928 return -EIO;
929
930 ready:
931 xm_write16(hw, port, XM_PHY_DATA, val);
932 return 0;
933 }
934
935 static void genesis_init(struct skge_hw *hw)
936 {
937 /* set blink source counter */
938 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
939 skge_write8(hw, B2_BSC_CTRL, BSC_START);
940
941 /* configure mac arbiter */
942 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
943
944 /* configure mac arbiter timeout values */
945 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
946 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
947 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
948 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
949
950 skge_write8(hw, B3_MA_RCINI_RX1, 0);
951 skge_write8(hw, B3_MA_RCINI_RX2, 0);
952 skge_write8(hw, B3_MA_RCINI_TX1, 0);
953 skge_write8(hw, B3_MA_RCINI_TX2, 0);
954
955 /* configure packet arbiter timeout */
956 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
957 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
958 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
959 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
960 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
961 }
962
963 static void genesis_reset(struct skge_hw *hw, int port)
964 {
965 const u8 zero[8] = { 0 };
966
967 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
968
969 /* reset the statistics module */
970 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
971 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
972 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
973 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
974 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
975
976 /* disable Broadcom PHY IRQ */
977 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
978
979 xm_outhash(hw, port, XM_HSM, zero);
980 }
981
982
983 /* Convert mode to MII values */
984 static const u16 phy_pause_map[] = {
985 [FLOW_MODE_NONE] = 0,
986 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
987 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
988 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
989 };
990
991
992 /* Check status of Broadcom phy link */
993 static void bcom_check_link(struct skge_hw *hw, int port)
994 {
995 struct net_device *dev = hw->dev[port];
996 struct skge_port *skge = netdev_priv(dev);
997 u16 status;
998
999 /* read twice because of latch */
1000 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1001 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1002
1003 if ((status & PHY_ST_LSYNC) == 0) {
1004 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1005 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1006 xm_write16(hw, port, XM_MMU_CMD, cmd);
1007 /* dummy read to ensure writing */
1008 (void) xm_read16(hw, port, XM_MMU_CMD);
1009
1010 if (netif_carrier_ok(dev))
1011 skge_link_down(skge);
1012 } else {
1013 if (skge->autoneg == AUTONEG_ENABLE &&
1014 (status & PHY_ST_AN_OVER)) {
1015 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1016 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1017
1018 if (lpa & PHY_B_AN_RF) {
1019 printk(KERN_NOTICE PFX "%s: remote fault\n",
1020 dev->name);
1021 return;
1022 }
1023
1024 /* Check Duplex mismatch */
1025 switch (aux & PHY_B_AS_AN_RES_MSK) {
1026 case PHY_B_RES_1000FD:
1027 skge->duplex = DUPLEX_FULL;
1028 break;
1029 case PHY_B_RES_1000HD:
1030 skge->duplex = DUPLEX_HALF;
1031 break;
1032 default:
1033 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1034 dev->name);
1035 return;
1036 }
1037
1038
1039 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1040 switch (aux & PHY_B_AS_PAUSE_MSK) {
1041 case PHY_B_AS_PAUSE_MSK:
1042 skge->flow_control = FLOW_MODE_SYMMETRIC;
1043 break;
1044 case PHY_B_AS_PRR:
1045 skge->flow_control = FLOW_MODE_REM_SEND;
1046 break;
1047 case PHY_B_AS_PRT:
1048 skge->flow_control = FLOW_MODE_LOC_SEND;
1049 break;
1050 default:
1051 skge->flow_control = FLOW_MODE_NONE;
1052 }
1053
1054 skge->speed = SPEED_1000;
1055 }
1056
1057 if (!netif_carrier_ok(dev))
1058 genesis_link_up(skge);
1059 }
1060 }
1061
1062 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1063 * Phy on for 100 or 10Mbit operation
1064 */
1065 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1066 {
1067 struct skge_hw *hw = skge->hw;
1068 int port = skge->port;
1069 int i;
1070 u16 id1, r, ext, ctl;
1071
1072 /* magic workaround patterns for Broadcom */
1073 static const struct {
1074 u16 reg;
1075 u16 val;
1076 } A1hack[] = {
1077 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1078 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1079 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1080 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1081 }, C0hack[] = {
1082 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1083 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1084 };
1085
1086 /* read Id from external PHY (all have the same address) */
1087 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1088
1089 /* Optimize MDIO transfer by suppressing preamble. */
1090 r = xm_read16(hw, port, XM_MMU_CMD);
1091 r |= XM_MMU_NO_PRE;
1092 xm_write16(hw, port, XM_MMU_CMD,r);
1093
1094 switch (id1) {
1095 case PHY_BCOM_ID1_C0:
1096 /*
1097 * Workaround BCOM Errata for the C0 type.
1098 * Write magic patterns to reserved registers.
1099 */
1100 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1101 xm_phy_write(hw, port,
1102 C0hack[i].reg, C0hack[i].val);
1103
1104 break;
1105 case PHY_BCOM_ID1_A1:
1106 /*
1107 * Workaround BCOM Errata for the A1 type.
1108 * Write magic patterns to reserved registers.
1109 */
1110 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1111 xm_phy_write(hw, port,
1112 A1hack[i].reg, A1hack[i].val);
1113 break;
1114 }
1115
1116 /*
1117 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1118 * Disable Power Management after reset.
1119 */
1120 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1121 r |= PHY_B_AC_DIS_PM;
1122 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1123
1124 /* Dummy read */
1125 xm_read16(hw, port, XM_ISRC);
1126
1127 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1128 ctl = PHY_CT_SP1000; /* always 1000mbit */
1129
1130 if (skge->autoneg == AUTONEG_ENABLE) {
1131 /*
1132 * Workaround BCOM Errata #1 for the C5 type.
1133 * 1000Base-T Link Acquisition Failure in Slave Mode
1134 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1135 */
1136 u16 adv = PHY_B_1000C_RD;
1137 if (skge->advertising & ADVERTISED_1000baseT_Half)
1138 adv |= PHY_B_1000C_AHD;
1139 if (skge->advertising & ADVERTISED_1000baseT_Full)
1140 adv |= PHY_B_1000C_AFD;
1141 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1142
1143 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1144 } else {
1145 if (skge->duplex == DUPLEX_FULL)
1146 ctl |= PHY_CT_DUP_MD;
1147 /* Force to slave */
1148 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1149 }
1150
1151 /* Set autonegotiation pause parameters */
1152 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1153 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1154
1155 /* Handle Jumbo frames */
1156 if (jumbo) {
1157 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1158 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1159
1160 ext |= PHY_B_PEC_HIGH_LA;
1161
1162 }
1163
1164 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1165 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1166
1167 /* Use link status change interrupt */
1168 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1169
1170 bcom_check_link(hw, port);
1171 }
1172
1173 static void genesis_mac_init(struct skge_hw *hw, int port)
1174 {
1175 struct net_device *dev = hw->dev[port];
1176 struct skge_port *skge = netdev_priv(dev);
1177 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1178 int i;
1179 u32 r;
1180 const u8 zero[6] = { 0 };
1181
1182 /* Clear MIB counters */
1183 xm_write16(hw, port, XM_STAT_CMD,
1184 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1185 /* Clear two times according to Errata #3 */
1186 xm_write16(hw, port, XM_STAT_CMD,
1187 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1188
1189 /* Unreset the XMAC. */
1190 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1191
1192 /*
1193 * Perform additional initialization for external PHYs,
1194 * namely for the 1000baseTX cards that use the XMAC's
1195 * GMII mode.
1196 */
1197 /* Take external Phy out of reset */
1198 r = skge_read32(hw, B2_GP_IO);
1199 if (port == 0)
1200 r |= GP_DIR_0|GP_IO_0;
1201 else
1202 r |= GP_DIR_2|GP_IO_2;
1203
1204 skge_write32(hw, B2_GP_IO, r);
1205 skge_read32(hw, B2_GP_IO);
1206
1207 /* Enable GMII interface */
1208 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1209
1210 bcom_phy_init(skge, jumbo);
1211
1212 /* Set Station Address */
1213 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1214
1215 /* We don't use match addresses so clear */
1216 for (i = 1; i < 16; i++)
1217 xm_outaddr(hw, port, XM_EXM(i), zero);
1218
1219 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1220 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1221
1222 /* We don't need the FCS appended to the packet. */
1223 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1224 if (jumbo)
1225 r |= XM_RX_BIG_PK_OK;
1226
1227 if (skge->duplex == DUPLEX_HALF) {
1228 /*
1229 * If in manual half duplex mode the other side might be in
1230 * full duplex mode, so ignore if a carrier extension is not seen
1231 * on frames received
1232 */
1233 r |= XM_RX_DIS_CEXT;
1234 }
1235 xm_write16(hw, port, XM_RX_CMD, r);
1236
1237
1238 /* We want short frames padded to 60 bytes. */
1239 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1240
1241 /*
1242 * Bump up the transmit threshold. This helps hold off transmit
1243 * underruns when we're blasting traffic from both ports at once.
1244 */
1245 xm_write16(hw, port, XM_TX_THR, 512);
1246
1247 /*
1248 * Enable the reception of all error frames. This is is
1249 * a necessary evil due to the design of the XMAC. The
1250 * XMAC's receive FIFO is only 8K in size, however jumbo
1251 * frames can be up to 9000 bytes in length. When bad
1252 * frame filtering is enabled, the XMAC's RX FIFO operates
1253 * in 'store and forward' mode. For this to work, the
1254 * entire frame has to fit into the FIFO, but that means
1255 * that jumbo frames larger than 8192 bytes will be
1256 * truncated. Disabling all bad frame filtering causes
1257 * the RX FIFO to operate in streaming mode, in which
1258 * case the XMAC will start transferring frames out of the
1259 * RX FIFO as soon as the FIFO threshold is reached.
1260 */
1261 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1262
1263
1264 /*
1265 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1266 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1267 * and 'Octets Rx OK Hi Cnt Ov'.
1268 */
1269 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1270
1271 /*
1272 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1273 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1274 * and 'Octets Tx OK Hi Cnt Ov'.
1275 */
1276 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1277
1278 /* Configure MAC arbiter */
1279 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1280
1281 /* configure timeout values */
1282 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1283 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1284 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1285 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1286
1287 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1288 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1289 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1290 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1291
1292 /* Configure Rx MAC FIFO */
1293 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1294 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1295 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1296
1297 /* Configure Tx MAC FIFO */
1298 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1299 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1300 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1301
1302 if (jumbo) {
1303 /* Enable frame flushing if jumbo frames used */
1304 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1305 } else {
1306 /* enable timeout timers if normal frames */
1307 skge_write16(hw, B3_PA_CTRL,
1308 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1309 }
1310 }
1311
1312 static void genesis_stop(struct skge_port *skge)
1313 {
1314 struct skge_hw *hw = skge->hw;
1315 int port = skge->port;
1316 u32 reg;
1317
1318 genesis_reset(hw, port);
1319
1320 /* Clear Tx packet arbiter timeout IRQ */
1321 skge_write16(hw, B3_PA_CTRL,
1322 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1323
1324 /*
1325 * If the transfer sticks at the MAC the STOP command will not
1326 * terminate if we don't flush the XMAC's transmit FIFO !
1327 */
1328 xm_write32(hw, port, XM_MODE,
1329 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1330
1331
1332 /* Reset the MAC */
1333 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1334
1335 /* For external PHYs there must be special handling */
1336 reg = skge_read32(hw, B2_GP_IO);
1337 if (port == 0) {
1338 reg |= GP_DIR_0;
1339 reg &= ~GP_IO_0;
1340 } else {
1341 reg |= GP_DIR_2;
1342 reg &= ~GP_IO_2;
1343 }
1344 skge_write32(hw, B2_GP_IO, reg);
1345 skge_read32(hw, B2_GP_IO);
1346
1347 xm_write16(hw, port, XM_MMU_CMD,
1348 xm_read16(hw, port, XM_MMU_CMD)
1349 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1350
1351 xm_read16(hw, port, XM_MMU_CMD);
1352 }
1353
1354
1355 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1356 {
1357 struct skge_hw *hw = skge->hw;
1358 int port = skge->port;
1359 int i;
1360 unsigned long timeout = jiffies + HZ;
1361
1362 xm_write16(hw, port,
1363 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1364
1365 /* wait for update to complete */
1366 while (xm_read16(hw, port, XM_STAT_CMD)
1367 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1368 if (time_after(jiffies, timeout))
1369 break;
1370 udelay(10);
1371 }
1372
1373 /* special case for 64 bit octet counter */
1374 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1375 | xm_read32(hw, port, XM_TXO_OK_LO);
1376 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1377 | xm_read32(hw, port, XM_RXO_OK_LO);
1378
1379 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1380 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1381 }
1382
1383 static void genesis_mac_intr(struct skge_hw *hw, int port)
1384 {
1385 struct skge_port *skge = netdev_priv(hw->dev[port]);
1386 u16 status = xm_read16(hw, port, XM_ISRC);
1387
1388 if (netif_msg_intr(skge))
1389 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1390 skge->netdev->name, status);
1391
1392 if (status & XM_IS_TXF_UR) {
1393 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1394 ++skge->net_stats.tx_fifo_errors;
1395 }
1396 if (status & XM_IS_RXF_OV) {
1397 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1398 ++skge->net_stats.rx_fifo_errors;
1399 }
1400 }
1401
1402 static void genesis_link_up(struct skge_port *skge)
1403 {
1404 struct skge_hw *hw = skge->hw;
1405 int port = skge->port;
1406 u16 cmd;
1407 u32 mode, msk;
1408
1409 cmd = xm_read16(hw, port, XM_MMU_CMD);
1410
1411 /*
1412 * enabling pause frame reception is required for 1000BT
1413 * because the XMAC is not reset if the link is going down
1414 */
1415 if (skge->flow_control == FLOW_MODE_NONE ||
1416 skge->flow_control == FLOW_MODE_LOC_SEND)
1417 /* Disable Pause Frame Reception */
1418 cmd |= XM_MMU_IGN_PF;
1419 else
1420 /* Enable Pause Frame Reception */
1421 cmd &= ~XM_MMU_IGN_PF;
1422
1423 xm_write16(hw, port, XM_MMU_CMD, cmd);
1424
1425 mode = xm_read32(hw, port, XM_MODE);
1426 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1427 skge->flow_control == FLOW_MODE_LOC_SEND) {
1428 /*
1429 * Configure Pause Frame Generation
1430 * Use internal and external Pause Frame Generation.
1431 * Sending pause frames is edge triggered.
1432 * Send a Pause frame with the maximum pause time if
1433 * internal oder external FIFO full condition occurs.
1434 * Send a zero pause time frame to re-start transmission.
1435 */
1436 /* XM_PAUSE_DA = '010000C28001' (default) */
1437 /* XM_MAC_PTIME = 0xffff (maximum) */
1438 /* remember this value is defined in big endian (!) */
1439 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1440
1441 mode |= XM_PAUSE_MODE;
1442 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1443 } else {
1444 /*
1445 * disable pause frame generation is required for 1000BT
1446 * because the XMAC is not reset if the link is going down
1447 */
1448 /* Disable Pause Mode in Mode Register */
1449 mode &= ~XM_PAUSE_MODE;
1450
1451 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1452 }
1453
1454 xm_write32(hw, port, XM_MODE, mode);
1455
1456 msk = XM_DEF_MSK;
1457 /* disable GP0 interrupt bit for external Phy */
1458 msk |= XM_IS_INP_ASS;
1459
1460 xm_write16(hw, port, XM_IMSK, msk);
1461 xm_read16(hw, port, XM_ISRC);
1462
1463 /* get MMU Command Reg. */
1464 cmd = xm_read16(hw, port, XM_MMU_CMD);
1465 if (skge->duplex == DUPLEX_FULL)
1466 cmd |= XM_MMU_GMII_FD;
1467
1468 /*
1469 * Workaround BCOM Errata (#10523) for all BCom Phys
1470 * Enable Power Management after link up
1471 */
1472 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1473 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1474 & ~PHY_B_AC_DIS_PM);
1475 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1476
1477 /* enable Rx/Tx */
1478 xm_write16(hw, port, XM_MMU_CMD,
1479 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1480 skge_link_up(skge);
1481 }
1482
1483
1484 static inline void bcom_phy_intr(struct skge_port *skge)
1485 {
1486 struct skge_hw *hw = skge->hw;
1487 int port = skge->port;
1488 u16 isrc;
1489
1490 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1491 if (netif_msg_intr(skge))
1492 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1493 skge->netdev->name, isrc);
1494
1495 if (isrc & PHY_B_IS_PSE)
1496 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1497 hw->dev[port]->name);
1498
1499 /* Workaround BCom Errata:
1500 * enable and disable loopback mode if "NO HCD" occurs.
1501 */
1502 if (isrc & PHY_B_IS_NO_HDCL) {
1503 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1504 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1505 ctrl | PHY_CT_LOOP);
1506 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1507 ctrl & ~PHY_CT_LOOP);
1508 }
1509
1510 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1511 bcom_check_link(hw, port);
1512
1513 }
1514
1515 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1516 {
1517 int i;
1518
1519 gma_write16(hw, port, GM_SMI_DATA, val);
1520 gma_write16(hw, port, GM_SMI_CTRL,
1521 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1522 for (i = 0; i < PHY_RETRIES; i++) {
1523 udelay(1);
1524
1525 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1526 return 0;
1527 }
1528
1529 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1530 hw->dev[port]->name);
1531 return -EIO;
1532 }
1533
1534 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1535 {
1536 int i;
1537
1538 gma_write16(hw, port, GM_SMI_CTRL,
1539 GM_SMI_CT_PHY_AD(hw->phy_addr)
1540 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1541
1542 for (i = 0; i < PHY_RETRIES; i++) {
1543 udelay(1);
1544 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1545 goto ready;
1546 }
1547
1548 return -ETIMEDOUT;
1549 ready:
1550 *val = gma_read16(hw, port, GM_SMI_DATA);
1551 return 0;
1552 }
1553
1554 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1555 {
1556 u16 v = 0;
1557 if (__gm_phy_read(hw, port, reg, &v))
1558 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1559 hw->dev[port]->name);
1560 return v;
1561 }
1562
1563 /* Marvell Phy Initialization */
1564 static void yukon_init(struct skge_hw *hw, int port)
1565 {
1566 struct skge_port *skge = netdev_priv(hw->dev[port]);
1567 u16 ctrl, ct1000, adv;
1568
1569 if (skge->autoneg == AUTONEG_ENABLE) {
1570 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1571
1572 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1573 PHY_M_EC_MAC_S_MSK);
1574 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1575
1576 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1577
1578 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1579 }
1580
1581 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1582 if (skge->autoneg == AUTONEG_DISABLE)
1583 ctrl &= ~PHY_CT_ANE;
1584
1585 ctrl |= PHY_CT_RESET;
1586 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1587
1588 ctrl = 0;
1589 ct1000 = 0;
1590 adv = PHY_AN_CSMA;
1591
1592 if (skge->autoneg == AUTONEG_ENABLE) {
1593 if (hw->copper) {
1594 if (skge->advertising & ADVERTISED_1000baseT_Full)
1595 ct1000 |= PHY_M_1000C_AFD;
1596 if (skge->advertising & ADVERTISED_1000baseT_Half)
1597 ct1000 |= PHY_M_1000C_AHD;
1598 if (skge->advertising & ADVERTISED_100baseT_Full)
1599 adv |= PHY_M_AN_100_FD;
1600 if (skge->advertising & ADVERTISED_100baseT_Half)
1601 adv |= PHY_M_AN_100_HD;
1602 if (skge->advertising & ADVERTISED_10baseT_Full)
1603 adv |= PHY_M_AN_10_FD;
1604 if (skge->advertising & ADVERTISED_10baseT_Half)
1605 adv |= PHY_M_AN_10_HD;
1606 } else /* special defines for FIBER (88E1011S only) */
1607 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1608
1609 /* Set Flow-control capabilities */
1610 adv |= phy_pause_map[skge->flow_control];
1611
1612 /* Restart Auto-negotiation */
1613 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1614 } else {
1615 /* forced speed/duplex settings */
1616 ct1000 = PHY_M_1000C_MSE;
1617
1618 if (skge->duplex == DUPLEX_FULL)
1619 ctrl |= PHY_CT_DUP_MD;
1620
1621 switch (skge->speed) {
1622 case SPEED_1000:
1623 ctrl |= PHY_CT_SP1000;
1624 break;
1625 case SPEED_100:
1626 ctrl |= PHY_CT_SP100;
1627 break;
1628 }
1629
1630 ctrl |= PHY_CT_RESET;
1631 }
1632
1633 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1634
1635 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1636 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1637
1638 /* Enable phy interrupt on autonegotiation complete (or link up) */
1639 if (skge->autoneg == AUTONEG_ENABLE)
1640 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1641 else
1642 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1643 }
1644
1645 static void yukon_reset(struct skge_hw *hw, int port)
1646 {
1647 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1648 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1649 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1650 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1651 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1652
1653 gma_write16(hw, port, GM_RX_CTRL,
1654 gma_read16(hw, port, GM_RX_CTRL)
1655 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1656 }
1657
1658 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1659 static int is_yukon_lite_a0(struct skge_hw *hw)
1660 {
1661 u32 reg;
1662 int ret;
1663
1664 if (hw->chip_id != CHIP_ID_YUKON)
1665 return 0;
1666
1667 reg = skge_read32(hw, B2_FAR);
1668 skge_write8(hw, B2_FAR + 3, 0xff);
1669 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1670 skge_write32(hw, B2_FAR, reg);
1671 return ret;
1672 }
1673
1674 static void yukon_mac_init(struct skge_hw *hw, int port)
1675 {
1676 struct skge_port *skge = netdev_priv(hw->dev[port]);
1677 int i;
1678 u32 reg;
1679 const u8 *addr = hw->dev[port]->dev_addr;
1680
1681 /* WA code for COMA mode -- set PHY reset */
1682 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1683 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1684 reg = skge_read32(hw, B2_GP_IO);
1685 reg |= GP_DIR_9 | GP_IO_9;
1686 skge_write32(hw, B2_GP_IO, reg);
1687 }
1688
1689 /* hard reset */
1690 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1691 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1692
1693 /* WA code for COMA mode -- clear PHY reset */
1694 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1695 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1696 reg = skge_read32(hw, B2_GP_IO);
1697 reg |= GP_DIR_9;
1698 reg &= ~GP_IO_9;
1699 skge_write32(hw, B2_GP_IO, reg);
1700 }
1701
1702 /* Set hardware config mode */
1703 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1704 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1705 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1706
1707 /* Clear GMC reset */
1708 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1709 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1710 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1711 if (skge->autoneg == AUTONEG_DISABLE) {
1712 reg = GM_GPCR_AU_ALL_DIS;
1713 gma_write16(hw, port, GM_GP_CTRL,
1714 gma_read16(hw, port, GM_GP_CTRL) | reg);
1715
1716 switch (skge->speed) {
1717 case SPEED_1000:
1718 reg |= GM_GPCR_SPEED_1000;
1719 /* fallthru */
1720 case SPEED_100:
1721 reg |= GM_GPCR_SPEED_100;
1722 }
1723
1724 if (skge->duplex == DUPLEX_FULL)
1725 reg |= GM_GPCR_DUP_FULL;
1726 } else
1727 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1728 switch (skge->flow_control) {
1729 case FLOW_MODE_NONE:
1730 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1731 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1732 break;
1733 case FLOW_MODE_LOC_SEND:
1734 /* disable Rx flow-control */
1735 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1736 }
1737
1738 gma_write16(hw, port, GM_GP_CTRL, reg);
1739 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1740
1741 yukon_init(hw, port);
1742
1743 /* MIB clear */
1744 reg = gma_read16(hw, port, GM_PHY_ADDR);
1745 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1746
1747 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1748 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1749 gma_write16(hw, port, GM_PHY_ADDR, reg);
1750
1751 /* transmit control */
1752 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1753
1754 /* receive control reg: unicast + multicast + no FCS */
1755 gma_write16(hw, port, GM_RX_CTRL,
1756 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1757
1758 /* transmit flow control */
1759 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1760
1761 /* transmit parameter */
1762 gma_write16(hw, port, GM_TX_PARAM,
1763 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1764 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1765 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1766
1767 /* serial mode register */
1768 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1769 if (hw->dev[port]->mtu > 1500)
1770 reg |= GM_SMOD_JUMBO_ENA;
1771
1772 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1773
1774 /* physical address: used for pause frames */
1775 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1776 /* virtual address for data */
1777 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1778
1779 /* enable interrupt mask for counter overflows */
1780 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1781 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1782 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1783
1784 /* Initialize Mac Fifo */
1785
1786 /* Configure Rx MAC FIFO */
1787 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1788 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1789
1790 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1791 if (is_yukon_lite_a0(hw))
1792 reg &= ~GMF_RX_F_FL_ON;
1793
1794 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1795 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1796 /*
1797 * because Pause Packet Truncation in GMAC is not working
1798 * we have to increase the Flush Threshold to 64 bytes
1799 * in order to flush pause packets in Rx FIFO on Yukon-1
1800 */
1801 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1802
1803 /* Configure Tx MAC FIFO */
1804 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1805 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1806 }
1807
1808 /* Go into power down mode */
1809 static void yukon_suspend(struct skge_hw *hw, int port)
1810 {
1811 u16 ctrl;
1812
1813 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1814 ctrl |= PHY_M_PC_POL_R_DIS;
1815 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1816
1817 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1818 ctrl |= PHY_CT_RESET;
1819 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1820
1821 /* switch IEEE compatible power down mode on */
1822 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1823 ctrl |= PHY_CT_PDOWN;
1824 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1825 }
1826
1827 static void yukon_stop(struct skge_port *skge)
1828 {
1829 struct skge_hw *hw = skge->hw;
1830 int port = skge->port;
1831
1832 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1833 yukon_reset(hw, port);
1834
1835 gma_write16(hw, port, GM_GP_CTRL,
1836 gma_read16(hw, port, GM_GP_CTRL)
1837 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1838 gma_read16(hw, port, GM_GP_CTRL);
1839
1840 yukon_suspend(hw, port);
1841
1842 /* set GPHY Control reset */
1843 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1844 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1845 }
1846
1847 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1848 {
1849 struct skge_hw *hw = skge->hw;
1850 int port = skge->port;
1851 int i;
1852
1853 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1854 | gma_read32(hw, port, GM_TXO_OK_LO);
1855 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1856 | gma_read32(hw, port, GM_RXO_OK_LO);
1857
1858 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1859 data[i] = gma_read32(hw, port,
1860 skge_stats[i].gma_offset);
1861 }
1862
1863 static void yukon_mac_intr(struct skge_hw *hw, int port)
1864 {
1865 struct net_device *dev = hw->dev[port];
1866 struct skge_port *skge = netdev_priv(dev);
1867 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1868
1869 if (netif_msg_intr(skge))
1870 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1871 dev->name, status);
1872
1873 if (status & GM_IS_RX_FF_OR) {
1874 ++skge->net_stats.rx_fifo_errors;
1875 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1876 }
1877
1878 if (status & GM_IS_TX_FF_UR) {
1879 ++skge->net_stats.tx_fifo_errors;
1880 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1881 }
1882
1883 }
1884
1885 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1886 {
1887 switch (aux & PHY_M_PS_SPEED_MSK) {
1888 case PHY_M_PS_SPEED_1000:
1889 return SPEED_1000;
1890 case PHY_M_PS_SPEED_100:
1891 return SPEED_100;
1892 default:
1893 return SPEED_10;
1894 }
1895 }
1896
1897 static void yukon_link_up(struct skge_port *skge)
1898 {
1899 struct skge_hw *hw = skge->hw;
1900 int port = skge->port;
1901 u16 reg;
1902
1903 /* Enable Transmit FIFO Underrun */
1904 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1905
1906 reg = gma_read16(hw, port, GM_GP_CTRL);
1907 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1908 reg |= GM_GPCR_DUP_FULL;
1909
1910 /* enable Rx/Tx */
1911 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1912 gma_write16(hw, port, GM_GP_CTRL, reg);
1913
1914 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1915 skge_link_up(skge);
1916 }
1917
1918 static void yukon_link_down(struct skge_port *skge)
1919 {
1920 struct skge_hw *hw = skge->hw;
1921 int port = skge->port;
1922 u16 ctrl;
1923
1924 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1925
1926 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1927 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1928 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1929
1930 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1931 /* restore Asymmetric Pause bit */
1932 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1933 gm_phy_read(hw, port,
1934 PHY_MARV_AUNE_ADV)
1935 | PHY_M_AN_ASP);
1936
1937 }
1938
1939 yukon_reset(hw, port);
1940 skge_link_down(skge);
1941
1942 yukon_init(hw, port);
1943 }
1944
1945 static void yukon_phy_intr(struct skge_port *skge)
1946 {
1947 struct skge_hw *hw = skge->hw;
1948 int port = skge->port;
1949 const char *reason = NULL;
1950 u16 istatus, phystat;
1951
1952 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1953 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1954
1955 if (netif_msg_intr(skge))
1956 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1957 skge->netdev->name, istatus, phystat);
1958
1959 if (istatus & PHY_M_IS_AN_COMPL) {
1960 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1961 & PHY_M_AN_RF) {
1962 reason = "remote fault";
1963 goto failed;
1964 }
1965
1966 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1967 reason = "master/slave fault";
1968 goto failed;
1969 }
1970
1971 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1972 reason = "speed/duplex";
1973 goto failed;
1974 }
1975
1976 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1977 ? DUPLEX_FULL : DUPLEX_HALF;
1978 skge->speed = yukon_speed(hw, phystat);
1979
1980 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1981 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1982 case PHY_M_PS_PAUSE_MSK:
1983 skge->flow_control = FLOW_MODE_SYMMETRIC;
1984 break;
1985 case PHY_M_PS_RX_P_EN:
1986 skge->flow_control = FLOW_MODE_REM_SEND;
1987 break;
1988 case PHY_M_PS_TX_P_EN:
1989 skge->flow_control = FLOW_MODE_LOC_SEND;
1990 break;
1991 default:
1992 skge->flow_control = FLOW_MODE_NONE;
1993 }
1994
1995 if (skge->flow_control == FLOW_MODE_NONE ||
1996 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1997 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1998 else
1999 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2000 yukon_link_up(skge);
2001 return;
2002 }
2003
2004 if (istatus & PHY_M_IS_LSP_CHANGE)
2005 skge->speed = yukon_speed(hw, phystat);
2006
2007 if (istatus & PHY_M_IS_DUP_CHANGE)
2008 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2009 if (istatus & PHY_M_IS_LST_CHANGE) {
2010 if (phystat & PHY_M_PS_LINK_UP)
2011 yukon_link_up(skge);
2012 else
2013 yukon_link_down(skge);
2014 }
2015 return;
2016 failed:
2017 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2018 skge->netdev->name, reason);
2019
2020 /* XXX restart autonegotiation? */
2021 }
2022
2023 /* Basic MII support */
2024 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2025 {
2026 struct mii_ioctl_data *data = if_mii(ifr);
2027 struct skge_port *skge = netdev_priv(dev);
2028 struct skge_hw *hw = skge->hw;
2029 int err = -EOPNOTSUPP;
2030
2031 if (!netif_running(dev))
2032 return -ENODEV; /* Phy still in reset */
2033
2034 switch(cmd) {
2035 case SIOCGMIIPHY:
2036 data->phy_id = hw->phy_addr;
2037
2038 /* fallthru */
2039 case SIOCGMIIREG: {
2040 u16 val = 0;
2041 spin_lock_bh(&hw->phy_lock);
2042 if (hw->chip_id == CHIP_ID_GENESIS)
2043 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2044 else
2045 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2046 spin_unlock_bh(&hw->phy_lock);
2047 data->val_out = val;
2048 break;
2049 }
2050
2051 case SIOCSMIIREG:
2052 if (!capable(CAP_NET_ADMIN))
2053 return -EPERM;
2054
2055 spin_lock_bh(&hw->phy_lock);
2056 if (hw->chip_id == CHIP_ID_GENESIS)
2057 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2058 data->val_in);
2059 else
2060 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2061 data->val_in);
2062 spin_unlock_bh(&hw->phy_lock);
2063 break;
2064 }
2065 return err;
2066 }
2067
2068 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2069 {
2070 u32 end;
2071
2072 start /= 8;
2073 len /= 8;
2074 end = start + len - 1;
2075
2076 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2077 skge_write32(hw, RB_ADDR(q, RB_START), start);
2078 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2079 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2080 skge_write32(hw, RB_ADDR(q, RB_END), end);
2081
2082 if (q == Q_R1 || q == Q_R2) {
2083 /* Set thresholds on receive queue's */
2084 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2085 start + (2*len)/3);
2086 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2087 start + (len/3));
2088 } else {
2089 /* Enable store & forward on Tx queue's because
2090 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2091 */
2092 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2093 }
2094
2095 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2096 }
2097
2098 /* Setup Bus Memory Interface */
2099 static void skge_qset(struct skge_port *skge, u16 q,
2100 const struct skge_element *e)
2101 {
2102 struct skge_hw *hw = skge->hw;
2103 u32 watermark = 0x600;
2104 u64 base = skge->dma + (e->desc - skge->mem);
2105
2106 /* optimization to reduce window on 32bit/33mhz */
2107 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2108 watermark /= 2;
2109
2110 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2111 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2112 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2113 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2114 }
2115
2116 static int skge_up(struct net_device *dev)
2117 {
2118 struct skge_port *skge = netdev_priv(dev);
2119 struct skge_hw *hw = skge->hw;
2120 int port = skge->port;
2121 u32 chunk, ram_addr;
2122 size_t rx_size, tx_size;
2123 int err;
2124
2125 if (netif_msg_ifup(skge))
2126 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2127
2128 if (dev->mtu > RX_BUF_SIZE)
2129 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2130 else
2131 skge->rx_buf_size = RX_BUF_SIZE;
2132
2133
2134 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2135 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2136 skge->mem_size = tx_size + rx_size;
2137 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2138 if (!skge->mem)
2139 return -ENOMEM;
2140
2141 memset(skge->mem, 0, skge->mem_size);
2142
2143 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2144 goto free_pci_mem;
2145
2146 err = skge_rx_fill(skge);
2147 if (err)
2148 goto free_rx_ring;
2149
2150 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2151 skge->dma + rx_size)))
2152 goto free_rx_ring;
2153
2154 skge->tx_avail = skge->tx_ring.count - 1;
2155
2156 /* Enable IRQ from port */
2157 hw->intr_mask |= portirqmask[port];
2158 skge_write32(hw, B0_IMSK, hw->intr_mask);
2159
2160 /* Initialize MAC */
2161 spin_lock_bh(&hw->phy_lock);
2162 if (hw->chip_id == CHIP_ID_GENESIS)
2163 genesis_mac_init(hw, port);
2164 else
2165 yukon_mac_init(hw, port);
2166 spin_unlock_bh(&hw->phy_lock);
2167
2168 /* Configure RAMbuffers */
2169 chunk = hw->ram_size / ((hw->ports + 1)*2);
2170 ram_addr = hw->ram_offset + 2 * chunk * port;
2171
2172 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2173 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2174
2175 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2176 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2177 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2178
2179 /* Start receiver BMU */
2180 wmb();
2181 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2182 skge_led(skge, LED_MODE_ON);
2183
2184 return 0;
2185
2186 free_rx_ring:
2187 skge_rx_clean(skge);
2188 kfree(skge->rx_ring.start);
2189 free_pci_mem:
2190 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2191
2192 return err;
2193 }
2194
2195 static int skge_down(struct net_device *dev)
2196 {
2197 struct skge_port *skge = netdev_priv(dev);
2198 struct skge_hw *hw = skge->hw;
2199 int port = skge->port;
2200
2201 if (netif_msg_ifdown(skge))
2202 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2203
2204 netif_stop_queue(dev);
2205
2206 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2207 if (hw->chip_id == CHIP_ID_GENESIS)
2208 genesis_stop(skge);
2209 else
2210 yukon_stop(skge);
2211
2212 hw->intr_mask &= ~portirqmask[skge->port];
2213 skge_write32(hw, B0_IMSK, hw->intr_mask);
2214
2215 /* Stop transmitter */
2216 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2217 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2218 RB_RST_SET|RB_DIS_OP_MD);
2219
2220
2221 /* Disable Force Sync bit and Enable Alloc bit */
2222 skge_write8(hw, SK_REG(port, TXA_CTRL),
2223 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2224
2225 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2226 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2227 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2228
2229 /* Reset PCI FIFO */
2230 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2231 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2232
2233 /* Reset the RAM Buffer async Tx queue */
2234 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2235 /* stop receiver */
2236 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2237 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2238 RB_RST_SET|RB_DIS_OP_MD);
2239 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2240
2241 if (hw->chip_id == CHIP_ID_GENESIS) {
2242 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2243 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2244 } else {
2245 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2246 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2247 }
2248
2249 skge_led(skge, LED_MODE_OFF);
2250
2251 skge_tx_clean(skge);
2252 skge_rx_clean(skge);
2253
2254 kfree(skge->rx_ring.start);
2255 kfree(skge->tx_ring.start);
2256 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2257 return 0;
2258 }
2259
2260 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2261 {
2262 struct skge_port *skge = netdev_priv(dev);
2263 struct skge_hw *hw = skge->hw;
2264 struct skge_ring *ring = &skge->tx_ring;
2265 struct skge_element *e;
2266 struct skge_tx_desc *td;
2267 int i;
2268 u32 control, len;
2269 u64 map;
2270 unsigned long flags;
2271
2272 skb = skb_padto(skb, ETH_ZLEN);
2273 if (!skb)
2274 return NETDEV_TX_OK;
2275
2276 local_irq_save(flags);
2277 if (!spin_trylock(&skge->tx_lock)) {
2278 /* Collision - tell upper layer to requeue */
2279 local_irq_restore(flags);
2280 return NETDEV_TX_LOCKED;
2281 }
2282
2283 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2284 if (!netif_queue_stopped(dev)) {
2285 netif_stop_queue(dev);
2286
2287 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2288 dev->name);
2289 }
2290 spin_unlock_irqrestore(&skge->tx_lock, flags);
2291 return NETDEV_TX_BUSY;
2292 }
2293
2294 e = ring->to_use;
2295 td = e->desc;
2296 e->skb = skb;
2297 len = skb_headlen(skb);
2298 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2299 pci_unmap_addr_set(e, mapaddr, map);
2300 pci_unmap_len_set(e, maplen, len);
2301
2302 td->dma_lo = map;
2303 td->dma_hi = map >> 32;
2304
2305 if (skb->ip_summed == CHECKSUM_HW) {
2306 int offset = skb->h.raw - skb->data;
2307
2308 /* This seems backwards, but it is what the sk98lin
2309 * does. Looks like hardware is wrong?
2310 */
2311 if (skb->h.ipiph->protocol == IPPROTO_UDP
2312 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2313 control = BMU_TCP_CHECK;
2314 else
2315 control = BMU_UDP_CHECK;
2316
2317 td->csum_offs = 0;
2318 td->csum_start = offset;
2319 td->csum_write = offset + skb->csum;
2320 } else
2321 control = BMU_CHECK;
2322
2323 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2324 control |= BMU_EOF| BMU_IRQ_EOF;
2325 else {
2326 struct skge_tx_desc *tf = td;
2327
2328 control |= BMU_STFWD;
2329 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2330 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2331
2332 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2333 frag->size, PCI_DMA_TODEVICE);
2334
2335 e = e->next;
2336 e->skb = NULL;
2337 tf = e->desc;
2338 tf->dma_lo = map;
2339 tf->dma_hi = (u64) map >> 32;
2340 pci_unmap_addr_set(e, mapaddr, map);
2341 pci_unmap_len_set(e, maplen, frag->size);
2342
2343 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2344 }
2345 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2346 }
2347 /* Make sure all the descriptors written */
2348 wmb();
2349 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2350 wmb();
2351
2352 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2353
2354 if (netif_msg_tx_queued(skge))
2355 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2356 dev->name, e - ring->start, skb->len);
2357
2358 ring->to_use = e->next;
2359 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2360 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2361 pr_debug("%s: transmit queue full\n", dev->name);
2362 netif_stop_queue(dev);
2363 }
2364
2365 dev->trans_start = jiffies;
2366 spin_unlock_irqrestore(&skge->tx_lock, flags);
2367
2368 return NETDEV_TX_OK;
2369 }
2370
2371 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2372 {
2373 /* This ring element can be skb or fragment */
2374 if (e->skb) {
2375 pci_unmap_single(hw->pdev,
2376 pci_unmap_addr(e, mapaddr),
2377 pci_unmap_len(e, maplen),
2378 PCI_DMA_TODEVICE);
2379 dev_kfree_skb_any(e->skb);
2380 e->skb = NULL;
2381 } else {
2382 pci_unmap_page(hw->pdev,
2383 pci_unmap_addr(e, mapaddr),
2384 pci_unmap_len(e, maplen),
2385 PCI_DMA_TODEVICE);
2386 }
2387 }
2388
2389 static void skge_tx_clean(struct skge_port *skge)
2390 {
2391 struct skge_ring *ring = &skge->tx_ring;
2392 struct skge_element *e;
2393 unsigned long flags;
2394
2395 spin_lock_irqsave(&skge->tx_lock, flags);
2396 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2397 ++skge->tx_avail;
2398 skge_tx_free(skge->hw, e);
2399 }
2400 ring->to_clean = e;
2401 spin_unlock_irqrestore(&skge->tx_lock, flags);
2402 }
2403
2404 static void skge_tx_timeout(struct net_device *dev)
2405 {
2406 struct skge_port *skge = netdev_priv(dev);
2407
2408 if (netif_msg_timer(skge))
2409 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2410
2411 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2412 skge_tx_clean(skge);
2413 }
2414
2415 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2416 {
2417 int err = 0;
2418 int running = netif_running(dev);
2419
2420 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2421 return -EINVAL;
2422
2423
2424 if (running)
2425 skge_down(dev);
2426 dev->mtu = new_mtu;
2427 if (running)
2428 skge_up(dev);
2429
2430 return err;
2431 }
2432
2433 static void genesis_set_multicast(struct net_device *dev)
2434 {
2435 struct skge_port *skge = netdev_priv(dev);
2436 struct skge_hw *hw = skge->hw;
2437 int port = skge->port;
2438 int i, count = dev->mc_count;
2439 struct dev_mc_list *list = dev->mc_list;
2440 u32 mode;
2441 u8 filter[8];
2442
2443 mode = xm_read32(hw, port, XM_MODE);
2444 mode |= XM_MD_ENA_HASH;
2445 if (dev->flags & IFF_PROMISC)
2446 mode |= XM_MD_ENA_PROM;
2447 else
2448 mode &= ~XM_MD_ENA_PROM;
2449
2450 if (dev->flags & IFF_ALLMULTI)
2451 memset(filter, 0xff, sizeof(filter));
2452 else {
2453 memset(filter, 0, sizeof(filter));
2454 for (i = 0; list && i < count; i++, list = list->next) {
2455 u32 crc, bit;
2456 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2457 bit = ~crc & 0x3f;
2458 filter[bit/8] |= 1 << (bit%8);
2459 }
2460 }
2461
2462 xm_write32(hw, port, XM_MODE, mode);
2463 xm_outhash(hw, port, XM_HSM, filter);
2464 }
2465
2466 static void yukon_set_multicast(struct net_device *dev)
2467 {
2468 struct skge_port *skge = netdev_priv(dev);
2469 struct skge_hw *hw = skge->hw;
2470 int port = skge->port;
2471 struct dev_mc_list *list = dev->mc_list;
2472 u16 reg;
2473 u8 filter[8];
2474
2475 memset(filter, 0, sizeof(filter));
2476
2477 reg = gma_read16(hw, port, GM_RX_CTRL);
2478 reg |= GM_RXCR_UCF_ENA;
2479
2480 if (dev->flags & IFF_PROMISC) /* promiscuous */
2481 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2482 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2483 memset(filter, 0xff, sizeof(filter));
2484 else if (dev->mc_count == 0) /* no multicast */
2485 reg &= ~GM_RXCR_MCF_ENA;
2486 else {
2487 int i;
2488 reg |= GM_RXCR_MCF_ENA;
2489
2490 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2491 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2492 filter[bit/8] |= 1 << (bit%8);
2493 }
2494 }
2495
2496
2497 gma_write16(hw, port, GM_MC_ADDR_H1,
2498 (u16)filter[0] | ((u16)filter[1] << 8));
2499 gma_write16(hw, port, GM_MC_ADDR_H2,
2500 (u16)filter[2] | ((u16)filter[3] << 8));
2501 gma_write16(hw, port, GM_MC_ADDR_H3,
2502 (u16)filter[4] | ((u16)filter[5] << 8));
2503 gma_write16(hw, port, GM_MC_ADDR_H4,
2504 (u16)filter[6] | ((u16)filter[7] << 8));
2505
2506 gma_write16(hw, port, GM_RX_CTRL, reg);
2507 }
2508
2509 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2510 {
2511 if (hw->chip_id == CHIP_ID_GENESIS)
2512 return status >> XMR_FS_LEN_SHIFT;
2513 else
2514 return status >> GMR_FS_LEN_SHIFT;
2515 }
2516
2517 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2518 {
2519 if (hw->chip_id == CHIP_ID_GENESIS)
2520 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2521 else
2522 return (status & GMR_FS_ANY_ERR) ||
2523 (status & GMR_FS_RX_OK) == 0;
2524 }
2525
2526
2527 /* Get receive buffer from descriptor.
2528 * Handles copy of small buffers and reallocation failures
2529 */
2530 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2531 struct skge_element *e,
2532 u32 control, u32 status, u16 csum)
2533 {
2534 struct sk_buff *skb;
2535 u16 len = control & BMU_BBC;
2536
2537 if (unlikely(netif_msg_rx_status(skge)))
2538 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2539 skge->netdev->name, e - skge->rx_ring.start,
2540 status, len);
2541
2542 if (len > skge->rx_buf_size)
2543 goto error;
2544
2545 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2546 goto error;
2547
2548 if (bad_phy_status(skge->hw, status))
2549 goto error;
2550
2551 if (phy_length(skge->hw, status) != len)
2552 goto error;
2553
2554 if (len < RX_COPY_THRESHOLD) {
2555 skb = dev_alloc_skb(len + 2);
2556 if (!skb)
2557 goto resubmit;
2558
2559 skb_reserve(skb, 2);
2560 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2561 pci_unmap_addr(e, mapaddr),
2562 len, PCI_DMA_FROMDEVICE);
2563 memcpy(skb->data, e->skb->data, len);
2564 pci_dma_sync_single_for_device(skge->hw->pdev,
2565 pci_unmap_addr(e, mapaddr),
2566 len, PCI_DMA_FROMDEVICE);
2567 skge_rx_reuse(e, skge->rx_buf_size);
2568 } else {
2569 struct sk_buff *nskb;
2570 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2571 if (!nskb)
2572 goto resubmit;
2573
2574 pci_unmap_single(skge->hw->pdev,
2575 pci_unmap_addr(e, mapaddr),
2576 pci_unmap_len(e, maplen),
2577 PCI_DMA_FROMDEVICE);
2578 skb = e->skb;
2579 prefetch(skb->data);
2580 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2581 }
2582
2583 skb_put(skb, len);
2584 skb->dev = skge->netdev;
2585 if (skge->rx_csum) {
2586 skb->csum = csum;
2587 skb->ip_summed = CHECKSUM_HW;
2588 }
2589
2590 skb->protocol = eth_type_trans(skb, skge->netdev);
2591
2592 return skb;
2593 error:
2594
2595 if (netif_msg_rx_err(skge))
2596 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2597 skge->netdev->name, e - skge->rx_ring.start,
2598 control, status);
2599
2600 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2601 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2602 skge->net_stats.rx_length_errors++;
2603 if (status & XMR_FS_FRA_ERR)
2604 skge->net_stats.rx_frame_errors++;
2605 if (status & XMR_FS_FCS_ERR)
2606 skge->net_stats.rx_crc_errors++;
2607 } else {
2608 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2609 skge->net_stats.rx_length_errors++;
2610 if (status & GMR_FS_FRAGMENT)
2611 skge->net_stats.rx_frame_errors++;
2612 if (status & GMR_FS_CRC_ERR)
2613 skge->net_stats.rx_crc_errors++;
2614 }
2615
2616 resubmit:
2617 skge_rx_reuse(e, skge->rx_buf_size);
2618 return NULL;
2619 }
2620
2621
2622 static int skge_poll(struct net_device *dev, int *budget)
2623 {
2624 struct skge_port *skge = netdev_priv(dev);
2625 struct skge_hw *hw = skge->hw;
2626 struct skge_ring *ring = &skge->rx_ring;
2627 struct skge_element *e;
2628 unsigned int to_do = min(dev->quota, *budget);
2629 unsigned int work_done = 0;
2630
2631 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2632 struct skge_rx_desc *rd = e->desc;
2633 struct sk_buff *skb;
2634 u32 control;
2635
2636 rmb();
2637 control = rd->control;
2638 if (control & BMU_OWN)
2639 break;
2640
2641 skb = skge_rx_get(skge, e, control, rd->status,
2642 le16_to_cpu(rd->csum2));
2643 if (likely(skb)) {
2644 dev->last_rx = jiffies;
2645 netif_receive_skb(skb);
2646
2647 ++work_done;
2648 } else
2649 skge_rx_reuse(e, skge->rx_buf_size);
2650 }
2651 ring->to_clean = e;
2652
2653 /* restart receiver */
2654 wmb();
2655 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2656 CSR_START | CSR_IRQ_CL_F);
2657
2658 *budget -= work_done;
2659 dev->quota -= work_done;
2660
2661 if (work_done >= to_do)
2662 return 1; /* not done */
2663
2664 netif_rx_complete(dev);
2665 hw->intr_mask |= portirqmask[skge->port];
2666 skge_write32(hw, B0_IMSK, hw->intr_mask);
2667 skge_read32(hw, B0_IMSK);
2668
2669 return 0;
2670 }
2671
2672 static inline void skge_tx_intr(struct net_device *dev)
2673 {
2674 struct skge_port *skge = netdev_priv(dev);
2675 struct skge_hw *hw = skge->hw;
2676 struct skge_ring *ring = &skge->tx_ring;
2677 struct skge_element *e;
2678
2679 spin_lock(&skge->tx_lock);
2680 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
2681 struct skge_tx_desc *td = e->desc;
2682 u32 control;
2683
2684 rmb();
2685 control = td->control;
2686 if (control & BMU_OWN)
2687 break;
2688
2689 if (unlikely(netif_msg_tx_done(skge)))
2690 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2691 dev->name, e - ring->start, td->status);
2692
2693 skge_tx_free(hw, e);
2694 e->skb = NULL;
2695 ++skge->tx_avail;
2696 }
2697 ring->to_clean = e;
2698 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2699
2700 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2701 netif_wake_queue(dev);
2702
2703 spin_unlock(&skge->tx_lock);
2704 }
2705
2706 /* Parity errors seem to happen when Genesis is connected to a switch
2707 * with no other ports present. Heartbeat error??
2708 */
2709 static void skge_mac_parity(struct skge_hw *hw, int port)
2710 {
2711 struct net_device *dev = hw->dev[port];
2712
2713 if (dev) {
2714 struct skge_port *skge = netdev_priv(dev);
2715 ++skge->net_stats.tx_heartbeat_errors;
2716 }
2717
2718 if (hw->chip_id == CHIP_ID_GENESIS)
2719 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2720 MFF_CLR_PERR);
2721 else
2722 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2723 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2724 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2725 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2726 }
2727
2728 static void skge_pci_clear(struct skge_hw *hw)
2729 {
2730 u16 status;
2731
2732 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2733 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2734 pci_write_config_word(hw->pdev, PCI_STATUS,
2735 status | PCI_STATUS_ERROR_BITS);
2736 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2737 }
2738
2739 static void skge_mac_intr(struct skge_hw *hw, int port)
2740 {
2741 if (hw->chip_id == CHIP_ID_GENESIS)
2742 genesis_mac_intr(hw, port);
2743 else
2744 yukon_mac_intr(hw, port);
2745 }
2746
2747 /* Handle device specific framing and timeout interrupts */
2748 static void skge_error_irq(struct skge_hw *hw)
2749 {
2750 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2751
2752 if (hw->chip_id == CHIP_ID_GENESIS) {
2753 /* clear xmac errors */
2754 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2755 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2756 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2757 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2758 } else {
2759 /* Timestamp (unused) overflow */
2760 if (hwstatus & IS_IRQ_TIST_OV)
2761 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2762 }
2763
2764 if (hwstatus & IS_RAM_RD_PAR) {
2765 printk(KERN_ERR PFX "Ram read data parity error\n");
2766 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2767 }
2768
2769 if (hwstatus & IS_RAM_WR_PAR) {
2770 printk(KERN_ERR PFX "Ram write data parity error\n");
2771 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2772 }
2773
2774 if (hwstatus & IS_M1_PAR_ERR)
2775 skge_mac_parity(hw, 0);
2776
2777 if (hwstatus & IS_M2_PAR_ERR)
2778 skge_mac_parity(hw, 1);
2779
2780 if (hwstatus & IS_R1_PAR_ERR)
2781 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2782
2783 if (hwstatus & IS_R2_PAR_ERR)
2784 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2785
2786 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2787 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2788 hwstatus);
2789
2790 skge_pci_clear(hw);
2791
2792 /* if error still set then just ignore it */
2793 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2794 if (hwstatus & IS_IRQ_STAT) {
2795 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2796 hwstatus);
2797 hw->intr_mask &= ~IS_HW_ERR;
2798 }
2799 }
2800 }
2801
2802 /*
2803 * Interrupt from PHY are handled in tasklet (soft irq)
2804 * because accessing phy registers requires spin wait which might
2805 * cause excess interrupt latency.
2806 */
2807 static void skge_extirq(unsigned long data)
2808 {
2809 struct skge_hw *hw = (struct skge_hw *) data;
2810 int port;
2811
2812 spin_lock(&hw->phy_lock);
2813 for (port = 0; port < 2; port++) {
2814 struct net_device *dev = hw->dev[port];
2815
2816 if (dev && netif_running(dev)) {
2817 struct skge_port *skge = netdev_priv(dev);
2818
2819 if (hw->chip_id != CHIP_ID_GENESIS)
2820 yukon_phy_intr(skge);
2821 else
2822 bcom_phy_intr(skge);
2823 }
2824 }
2825 spin_unlock(&hw->phy_lock);
2826
2827 local_irq_disable();
2828 hw->intr_mask |= IS_EXT_REG;
2829 skge_write32(hw, B0_IMSK, hw->intr_mask);
2830 local_irq_enable();
2831 }
2832
2833 static inline void skge_wakeup(struct net_device *dev)
2834 {
2835 struct skge_port *skge = netdev_priv(dev);
2836
2837 prefetch(skge->rx_ring.to_clean);
2838 netif_rx_schedule(dev);
2839 }
2840
2841 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2842 {
2843 struct skge_hw *hw = dev_id;
2844 u32 status = skge_read32(hw, B0_SP_ISRC);
2845
2846 if (status == 0 || status == ~0) /* hotplug or shared irq */
2847 return IRQ_NONE;
2848
2849 status &= hw->intr_mask;
2850 if (status & IS_R1_F) {
2851 hw->intr_mask &= ~IS_R1_F;
2852 skge_wakeup(hw->dev[0]);
2853 }
2854
2855 if (status & IS_R2_F) {
2856 hw->intr_mask &= ~IS_R2_F;
2857 skge_wakeup(hw->dev[1]);
2858 }
2859
2860 if (status & IS_XA1_F)
2861 skge_tx_intr(hw->dev[0]);
2862
2863 if (status & IS_XA2_F)
2864 skge_tx_intr(hw->dev[1]);
2865
2866 if (status & IS_PA_TO_RX1) {
2867 struct skge_port *skge = netdev_priv(hw->dev[0]);
2868 ++skge->net_stats.rx_over_errors;
2869 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2870 }
2871
2872 if (status & IS_PA_TO_RX2) {
2873 struct skge_port *skge = netdev_priv(hw->dev[1]);
2874 ++skge->net_stats.rx_over_errors;
2875 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2876 }
2877
2878 if (status & IS_PA_TO_TX1)
2879 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2880
2881 if (status & IS_PA_TO_TX2)
2882 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2883
2884 if (status & IS_MAC1)
2885 skge_mac_intr(hw, 0);
2886
2887 if (status & IS_MAC2)
2888 skge_mac_intr(hw, 1);
2889
2890 if (status & IS_HW_ERR)
2891 skge_error_irq(hw);
2892
2893 if (status & IS_EXT_REG) {
2894 hw->intr_mask &= ~IS_EXT_REG;
2895 tasklet_schedule(&hw->ext_tasklet);
2896 }
2897
2898 skge_write32(hw, B0_IMSK, hw->intr_mask);
2899
2900 return IRQ_HANDLED;
2901 }
2902
2903 #ifdef CONFIG_NET_POLL_CONTROLLER
2904 static void skge_netpoll(struct net_device *dev)
2905 {
2906 struct skge_port *skge = netdev_priv(dev);
2907
2908 disable_irq(dev->irq);
2909 skge_intr(dev->irq, skge->hw, NULL);
2910 enable_irq(dev->irq);
2911 }
2912 #endif
2913
2914 static int skge_set_mac_address(struct net_device *dev, void *p)
2915 {
2916 struct skge_port *skge = netdev_priv(dev);
2917 struct skge_hw *hw = skge->hw;
2918 unsigned port = skge->port;
2919 const struct sockaddr *addr = p;
2920
2921 if (!is_valid_ether_addr(addr->sa_data))
2922 return -EADDRNOTAVAIL;
2923
2924 spin_lock_bh(&hw->phy_lock);
2925 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2926 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2927 dev->dev_addr, ETH_ALEN);
2928 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2929 dev->dev_addr, ETH_ALEN);
2930
2931 if (hw->chip_id == CHIP_ID_GENESIS)
2932 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2933 else {
2934 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2935 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2936 }
2937 spin_unlock_bh(&hw->phy_lock);
2938
2939 return 0;
2940 }
2941
2942 static const struct {
2943 u8 id;
2944 const char *name;
2945 } skge_chips[] = {
2946 { CHIP_ID_GENESIS, "Genesis" },
2947 { CHIP_ID_YUKON, "Yukon" },
2948 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2949 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2950 };
2951
2952 static const char *skge_board_name(const struct skge_hw *hw)
2953 {
2954 int i;
2955 static char buf[16];
2956
2957 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2958 if (skge_chips[i].id == hw->chip_id)
2959 return skge_chips[i].name;
2960
2961 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2962 return buf;
2963 }
2964
2965
2966 /*
2967 * Setup the board data structure, but don't bring up
2968 * the port(s)
2969 */
2970 static int skge_reset(struct skge_hw *hw)
2971 {
2972 u32 reg;
2973 u16 ctst;
2974 u8 t8, mac_cfg, pmd_type, phy_type;
2975 int i;
2976
2977 ctst = skge_read16(hw, B0_CTST);
2978
2979 /* do a SW reset */
2980 skge_write8(hw, B0_CTST, CS_RST_SET);
2981 skge_write8(hw, B0_CTST, CS_RST_CLR);
2982
2983 /* clear PCI errors, if any */
2984 skge_pci_clear(hw);
2985
2986 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2987
2988 /* restore CLK_RUN bits (for Yukon-Lite) */
2989 skge_write16(hw, B0_CTST,
2990 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2991
2992 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2993 phy_type = skge_read8(hw, B2_E_1) & 0xf;
2994 pmd_type = skge_read8(hw, B2_PMD_TYP);
2995 hw->copper = (pmd_type == 'T' || pmd_type == '1');
2996
2997 switch (hw->chip_id) {
2998 case CHIP_ID_GENESIS:
2999 switch (phy_type) {
3000 case SK_PHY_BCOM:
3001 hw->phy_addr = PHY_ADDR_BCOM;
3002 break;
3003 default:
3004 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3005 pci_name(hw->pdev), phy_type);
3006 return -EOPNOTSUPP;
3007 }
3008 break;
3009
3010 case CHIP_ID_YUKON:
3011 case CHIP_ID_YUKON_LITE:
3012 case CHIP_ID_YUKON_LP:
3013 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3014 hw->copper = 1;
3015
3016 hw->phy_addr = PHY_ADDR_MARV;
3017 break;
3018
3019 default:
3020 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3021 pci_name(hw->pdev), hw->chip_id);
3022 return -EOPNOTSUPP;
3023 }
3024
3025 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3026 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3027 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3028
3029 /* read the adapters RAM size */
3030 t8 = skge_read8(hw, B2_E_0);
3031 if (hw->chip_id == CHIP_ID_GENESIS) {
3032 if (t8 == 3) {
3033 /* special case: 4 x 64k x 36, offset = 0x80000 */
3034 hw->ram_size = 0x100000;
3035 hw->ram_offset = 0x80000;
3036 } else
3037 hw->ram_size = t8 * 512;
3038 }
3039 else if (t8 == 0)
3040 hw->ram_size = 0x20000;
3041 else
3042 hw->ram_size = t8 * 4096;
3043
3044 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
3045 if (hw->chip_id == CHIP_ID_GENESIS)
3046 genesis_init(hw);
3047 else {
3048 /* switch power to VCC (WA for VAUX problem) */
3049 skge_write8(hw, B0_POWER_CTRL,
3050 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3051
3052 /* avoid boards with stuck Hardware error bits */
3053 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3054 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3055 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3056 hw->intr_mask &= ~IS_HW_ERR;
3057 }
3058
3059 /* Clear PHY COMA */
3060 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3061 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3062 reg &= ~PCI_PHY_COMA;
3063 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3064 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3065
3066
3067 for (i = 0; i < hw->ports; i++) {
3068 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3069 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3070 }
3071 }
3072
3073 /* turn off hardware timer (unused) */
3074 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3075 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3076 skge_write8(hw, B0_LED, LED_STAT_ON);
3077
3078 /* enable the Tx Arbiters */
3079 for (i = 0; i < hw->ports; i++)
3080 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3081
3082 /* Initialize ram interface */
3083 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3084
3085 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3086 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3087 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3088 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3089 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3090 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3091 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3092 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3093 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3094 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3095 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3096 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3097
3098 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3099
3100 /* Set interrupt moderation for Transmit only
3101 * Receive interrupts avoided by NAPI
3102 */
3103 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3104 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3105 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3106
3107 skge_write32(hw, B0_IMSK, hw->intr_mask);
3108
3109 spin_lock_bh(&hw->phy_lock);
3110 for (i = 0; i < hw->ports; i++) {
3111 if (hw->chip_id == CHIP_ID_GENESIS)
3112 genesis_reset(hw, i);
3113 else
3114 yukon_reset(hw, i);
3115 }
3116 spin_unlock_bh(&hw->phy_lock);
3117
3118 return 0;
3119 }
3120
3121 /* Initialize network device */
3122 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3123 int highmem)
3124 {
3125 struct skge_port *skge;
3126 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3127
3128 if (!dev) {
3129 printk(KERN_ERR "skge etherdev alloc failed");
3130 return NULL;
3131 }
3132
3133 SET_MODULE_OWNER(dev);
3134 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3135 dev->open = skge_up;
3136 dev->stop = skge_down;
3137 dev->do_ioctl = skge_ioctl;
3138 dev->hard_start_xmit = skge_xmit_frame;
3139 dev->get_stats = skge_get_stats;
3140 if (hw->chip_id == CHIP_ID_GENESIS)
3141 dev->set_multicast_list = genesis_set_multicast;
3142 else
3143 dev->set_multicast_list = yukon_set_multicast;
3144
3145 dev->set_mac_address = skge_set_mac_address;
3146 dev->change_mtu = skge_change_mtu;
3147 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3148 dev->tx_timeout = skge_tx_timeout;
3149 dev->watchdog_timeo = TX_WATCHDOG;
3150 dev->poll = skge_poll;
3151 dev->weight = NAPI_WEIGHT;
3152 #ifdef CONFIG_NET_POLL_CONTROLLER
3153 dev->poll_controller = skge_netpoll;
3154 #endif
3155 dev->irq = hw->pdev->irq;
3156 dev->features = NETIF_F_LLTX;
3157 if (highmem)
3158 dev->features |= NETIF_F_HIGHDMA;
3159
3160 skge = netdev_priv(dev);
3161 skge->netdev = dev;
3162 skge->hw = hw;
3163 skge->msg_enable = netif_msg_init(debug, default_msg);
3164 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3165 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3166
3167 /* Auto speed and flow control */
3168 skge->autoneg = AUTONEG_ENABLE;
3169 skge->flow_control = FLOW_MODE_SYMMETRIC;
3170 skge->duplex = -1;
3171 skge->speed = -1;
3172 skge->advertising = skge_supported_modes(hw);
3173
3174 hw->dev[port] = dev;
3175
3176 skge->port = port;
3177
3178 spin_lock_init(&skge->tx_lock);
3179
3180 if (hw->chip_id != CHIP_ID_GENESIS) {
3181 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3182 skge->rx_csum = 1;
3183 }
3184
3185 /* read the mac address */
3186 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3187 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3188
3189 /* device is off until link detection */
3190 netif_carrier_off(dev);
3191 netif_stop_queue(dev);
3192
3193 return dev;
3194 }
3195
3196 static void __devinit skge_show_addr(struct net_device *dev)
3197 {
3198 const struct skge_port *skge = netdev_priv(dev);
3199
3200 if (netif_msg_probe(skge))
3201 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3202 dev->name,
3203 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3204 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3205 }
3206
3207 static int __devinit skge_probe(struct pci_dev *pdev,
3208 const struct pci_device_id *ent)
3209 {
3210 struct net_device *dev, *dev1;
3211 struct skge_hw *hw;
3212 int err, using_dac = 0;
3213
3214 if ((err = pci_enable_device(pdev))) {
3215 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3216 pci_name(pdev));
3217 goto err_out;
3218 }
3219
3220 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3221 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3222 pci_name(pdev));
3223 goto err_out_disable_pdev;
3224 }
3225
3226 pci_set_master(pdev);
3227
3228 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3229 using_dac = 1;
3230 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3231 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3232 pci_name(pdev));
3233 goto err_out_free_regions;
3234 }
3235
3236 #ifdef __BIG_ENDIAN
3237 /* byte swap descriptors in hardware */
3238 {
3239 u32 reg;
3240
3241 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3242 reg |= PCI_REV_DESC;
3243 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3244 }
3245 #endif
3246
3247 err = -ENOMEM;
3248 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3249 if (!hw) {
3250 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3251 pci_name(pdev));
3252 goto err_out_free_regions;
3253 }
3254
3255 hw->pdev = pdev;
3256 spin_lock_init(&hw->phy_lock);
3257 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3258
3259 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3260 if (!hw->regs) {
3261 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3262 pci_name(pdev));
3263 goto err_out_free_hw;
3264 }
3265
3266 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3267 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3268 pci_name(pdev), pdev->irq);
3269 goto err_out_iounmap;
3270 }
3271 pci_set_drvdata(pdev, hw);
3272
3273 err = skge_reset(hw);
3274 if (err)
3275 goto err_out_free_irq;
3276
3277 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
3278 pci_resource_start(pdev, 0), pdev->irq,
3279 skge_board_name(hw), hw->chip_rev);
3280
3281 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3282 goto err_out_led_off;
3283
3284 if ((err = register_netdev(dev))) {
3285 printk(KERN_ERR PFX "%s: cannot register net device\n",
3286 pci_name(pdev));
3287 goto err_out_free_netdev;
3288 }
3289
3290 skge_show_addr(dev);
3291
3292 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3293 if (register_netdev(dev1) == 0)
3294 skge_show_addr(dev1);
3295 else {
3296 /* Failure to register second port need not be fatal */
3297 printk(KERN_WARNING PFX "register of second port failed\n");
3298 hw->dev[1] = NULL;
3299 free_netdev(dev1);
3300 }
3301 }
3302
3303 return 0;
3304
3305 err_out_free_netdev:
3306 free_netdev(dev);
3307 err_out_led_off:
3308 skge_write16(hw, B0_LED, LED_STAT_OFF);
3309 err_out_free_irq:
3310 free_irq(pdev->irq, hw);
3311 err_out_iounmap:
3312 iounmap(hw->regs);
3313 err_out_free_hw:
3314 kfree(hw);
3315 err_out_free_regions:
3316 pci_release_regions(pdev);
3317 err_out_disable_pdev:
3318 pci_disable_device(pdev);
3319 pci_set_drvdata(pdev, NULL);
3320 err_out:
3321 return err;
3322 }
3323
3324 static void __devexit skge_remove(struct pci_dev *pdev)
3325 {
3326 struct skge_hw *hw = pci_get_drvdata(pdev);
3327 struct net_device *dev0, *dev1;
3328
3329 if (!hw)
3330 return;
3331
3332 if ((dev1 = hw->dev[1]))
3333 unregister_netdev(dev1);
3334 dev0 = hw->dev[0];
3335 unregister_netdev(dev0);
3336
3337 skge_write32(hw, B0_IMSK, 0);
3338 skge_write16(hw, B0_LED, LED_STAT_OFF);
3339 skge_pci_clear(hw);
3340 skge_write8(hw, B0_CTST, CS_RST_SET);
3341
3342 tasklet_kill(&hw->ext_tasklet);
3343
3344 free_irq(pdev->irq, hw);
3345 pci_release_regions(pdev);
3346 pci_disable_device(pdev);
3347 if (dev1)
3348 free_netdev(dev1);
3349 free_netdev(dev0);
3350
3351 iounmap(hw->regs);
3352 kfree(hw);
3353 pci_set_drvdata(pdev, NULL);
3354 }
3355
3356 #ifdef CONFIG_PM
3357 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3358 {
3359 struct skge_hw *hw = pci_get_drvdata(pdev);
3360 int i, wol = 0;
3361
3362 for (i = 0; i < 2; i++) {
3363 struct net_device *dev = hw->dev[i];
3364
3365 if (dev) {
3366 struct skge_port *skge = netdev_priv(dev);
3367 if (netif_running(dev)) {
3368 netif_carrier_off(dev);
3369 if (skge->wol)
3370 netif_stop_queue(dev);
3371 else
3372 skge_down(dev);
3373 }
3374 netif_device_detach(dev);
3375 wol |= skge->wol;
3376 }
3377 }
3378
3379 pci_save_state(pdev);
3380 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3381 pci_disable_device(pdev);
3382 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3383
3384 return 0;
3385 }
3386
3387 static int skge_resume(struct pci_dev *pdev)
3388 {
3389 struct skge_hw *hw = pci_get_drvdata(pdev);
3390 int i;
3391
3392 pci_set_power_state(pdev, PCI_D0);
3393 pci_restore_state(pdev);
3394 pci_enable_wake(pdev, PCI_D0, 0);
3395
3396 skge_reset(hw);
3397
3398 for (i = 0; i < 2; i++) {
3399 struct net_device *dev = hw->dev[i];
3400 if (dev) {
3401 netif_device_attach(dev);
3402 if (netif_running(dev))
3403 skge_up(dev);
3404 }
3405 }
3406 return 0;
3407 }
3408 #endif
3409
3410 static struct pci_driver skge_driver = {
3411 .name = DRV_NAME,
3412 .id_table = skge_id_table,
3413 .probe = skge_probe,
3414 .remove = __devexit_p(skge_remove),
3415 #ifdef CONFIG_PM
3416 .suspend = skge_suspend,
3417 .resume = skge_resume,
3418 #endif
3419 };
3420
3421 static int __init skge_init_module(void)
3422 {
3423 return pci_module_init(&skge_driver);
3424 }
3425
3426 static void __exit skge_cleanup_module(void)
3427 {
3428 pci_unregister_driver(&skge_driver);
3429 }
3430
3431 module_init(skge_init_module);
3432 module_exit(skge_cleanup_module);
kernel-based virtual machine