1 /*******************************************************************************
3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the adapter
36 /* Local function prototypes */
38 static uint32_t ixgb_hash_mc_addr(struct ixgb_hw
*hw
, uint8_t * mc_addr
);
40 static void ixgb_mta_set(struct ixgb_hw
*hw
, uint32_t hash_value
);
42 static void ixgb_get_bus_info(struct ixgb_hw
*hw
);
44 static boolean_t
ixgb_link_reset(struct ixgb_hw
*hw
);
46 static void ixgb_optics_reset(struct ixgb_hw
*hw
);
48 static ixgb_phy_type
ixgb_identify_phy(struct ixgb_hw
*hw
);
50 static void ixgb_clear_hw_cntrs(struct ixgb_hw
*hw
);
52 static void ixgb_clear_vfta(struct ixgb_hw
*hw
);
54 static void ixgb_init_rx_addrs(struct ixgb_hw
*hw
);
56 static uint16_t ixgb_read_phy_reg(struct ixgb_hw
*hw
,
59 uint32_t device_type
);
61 static boolean_t
ixgb_setup_fc(struct ixgb_hw
*hw
);
63 static boolean_t
mac_addr_valid(uint8_t *mac_addr
);
65 static uint32_t ixgb_mac_reset(struct ixgb_hw
*hw
)
69 ctrl_reg
= IXGB_CTRL0_RST
|
70 IXGB_CTRL0_SDP3_DIR
| /* All pins are Output=1 */
74 IXGB_CTRL0_SDP3
| /* Initial value 1101 */
79 /* Workaround for 82597EX reset errata */
80 IXGB_WRITE_REG_IO(hw
, CTRL0
, ctrl_reg
);
82 IXGB_WRITE_REG(hw
, CTRL0
, ctrl_reg
);
85 /* Delay a few ms just to allow the reset to complete */
86 msleep(IXGB_DELAY_AFTER_RESET
);
87 ctrl_reg
= IXGB_READ_REG(hw
, CTRL0
);
89 /* Make sure the self-clearing global reset bit did self clear */
90 ASSERT(!(ctrl_reg
& IXGB_CTRL0_RST
));
93 if (hw
->phy_type
== ixgb_phy_type_txn17401
) {
94 ixgb_optics_reset(hw
);
100 /******************************************************************************
101 * Reset the transmit and receive units; mask and clear all interrupts.
103 * hw - Struct containing variables accessed by shared code
104 *****************************************************************************/
106 ixgb_adapter_stop(struct ixgb_hw
*hw
)
111 DEBUGFUNC("ixgb_adapter_stop");
113 /* If we are stopped or resetting exit gracefully and wait to be
114 * started again before accessing the hardware.
116 if(hw
->adapter_stopped
) {
117 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
121 /* Set the Adapter Stopped flag so other driver functions stop
122 * touching the Hardware.
124 hw
->adapter_stopped
= TRUE
;
126 /* Clear interrupt mask to stop board from generating interrupts */
127 DEBUGOUT("Masking off all interrupts\n");
128 IXGB_WRITE_REG(hw
, IMC
, 0xFFFFFFFF);
130 /* Disable the Transmit and Receive units. Then delay to allow
131 * any pending transactions to complete before we hit the MAC with
134 IXGB_WRITE_REG(hw
, RCTL
, IXGB_READ_REG(hw
, RCTL
) & ~IXGB_RCTL_RXEN
);
135 IXGB_WRITE_REG(hw
, TCTL
, IXGB_READ_REG(hw
, TCTL
) & ~IXGB_TCTL_TXEN
);
136 msleep(IXGB_DELAY_BEFORE_RESET
);
138 /* Issue a global reset to the MAC. This will reset the chip's
139 * transmit, receive, DMA, and link units. It will not effect
140 * the current PCI configuration. The global reset bit is self-
141 * clearing, and should clear within a microsecond.
143 DEBUGOUT("Issuing a global reset to MAC\n");
145 ctrl_reg
= ixgb_mac_reset(hw
);
147 /* Clear interrupt mask to stop board from generating interrupts */
148 DEBUGOUT("Masking off all interrupts\n");
149 IXGB_WRITE_REG(hw
, IMC
, 0xffffffff);
151 /* Clear any pending interrupt events. */
152 icr_reg
= IXGB_READ_REG(hw
, ICR
);
154 return (ctrl_reg
& IXGB_CTRL0_RST
);
158 /******************************************************************************
159 * Identifies the vendor of the optics module on the adapter. The SR adapters
160 * support two different types of XPAK optics, so it is necessary to determine
161 * which optics are present before applying any optics-specific workarounds.
163 * hw - Struct containing variables accessed by shared code.
165 * Returns: the vendor of the XPAK optics module.
166 *****************************************************************************/
167 static ixgb_xpak_vendor
168 ixgb_identify_xpak_vendor(struct ixgb_hw
*hw
)
171 uint16_t vendor_name
[5];
172 ixgb_xpak_vendor xpak_vendor
;
174 DEBUGFUNC("ixgb_identify_xpak_vendor");
176 /* Read the first few bytes of the vendor string from the XPAK NVR
177 * registers. These are standard XENPAK/XPAK registers, so all XPAK
178 * devices should implement them. */
179 for (i
= 0; i
< 5; i
++) {
180 vendor_name
[i
] = ixgb_read_phy_reg(hw
,
181 MDIO_PMA_PMD_XPAK_VENDOR_NAME
182 + i
, IXGB_PHY_ADDRESS
,
186 /* Determine the actual vendor */
187 if (vendor_name
[0] == 'I' &&
188 vendor_name
[1] == 'N' &&
189 vendor_name
[2] == 'T' &&
190 vendor_name
[3] == 'E' && vendor_name
[4] == 'L') {
191 xpak_vendor
= ixgb_xpak_vendor_intel
;
193 xpak_vendor
= ixgb_xpak_vendor_infineon
;
196 return (xpak_vendor
);
199 /******************************************************************************
200 * Determine the physical layer module on the adapter.
202 * hw - Struct containing variables accessed by shared code. The device_id
203 * field must be (correctly) populated before calling this routine.
205 * Returns: the phy type of the adapter.
206 *****************************************************************************/
208 ixgb_identify_phy(struct ixgb_hw
*hw
)
210 ixgb_phy_type phy_type
;
211 ixgb_xpak_vendor xpak_vendor
;
213 DEBUGFUNC("ixgb_identify_phy");
215 /* Infer the transceiver/phy type from the device id */
216 switch (hw
->device_id
) {
217 case IXGB_DEVICE_ID_82597EX
:
218 DEBUGOUT("Identified TXN17401 optics\n");
219 phy_type
= ixgb_phy_type_txn17401
;
222 case IXGB_DEVICE_ID_82597EX_SR
:
223 /* The SR adapters carry two different types of XPAK optics
224 * modules; read the vendor identifier to determine the exact
226 xpak_vendor
= ixgb_identify_xpak_vendor(hw
);
227 if (xpak_vendor
== ixgb_xpak_vendor_intel
) {
228 DEBUGOUT("Identified TXN17201 optics\n");
229 phy_type
= ixgb_phy_type_txn17201
;
231 DEBUGOUT("Identified G6005 optics\n");
232 phy_type
= ixgb_phy_type_g6005
;
235 case IXGB_DEVICE_ID_82597EX_LR
:
236 DEBUGOUT("Identified G6104 optics\n");
237 phy_type
= ixgb_phy_type_g6104
;
239 case IXGB_DEVICE_ID_82597EX_CX4
:
240 DEBUGOUT("Identified CX4\n");
241 xpak_vendor
= ixgb_identify_xpak_vendor(hw
);
242 if (xpak_vendor
== ixgb_xpak_vendor_intel
) {
243 DEBUGOUT("Identified TXN17201 optics\n");
244 phy_type
= ixgb_phy_type_txn17201
;
246 DEBUGOUT("Identified G6005 optics\n");
247 phy_type
= ixgb_phy_type_g6005
;
251 DEBUGOUT("Unknown physical layer module\n");
252 phy_type
= ixgb_phy_type_unknown
;
259 /******************************************************************************
260 * Performs basic configuration of the adapter.
262 * hw - Struct containing variables accessed by shared code
264 * Resets the controller.
265 * Reads and validates the EEPROM.
266 * Initializes the receive address registers.
267 * Initializes the multicast table.
268 * Clears all on-chip counters.
269 * Calls routine to setup flow control settings.
270 * Leaves the transmit and receive units disabled and uninitialized.
273 * TRUE if successful,
274 * FALSE if unrecoverable problems were encountered.
275 *****************************************************************************/
277 ixgb_init_hw(struct ixgb_hw
*hw
)
283 DEBUGFUNC("ixgb_init_hw");
285 /* Issue a global reset to the MAC. This will reset the chip's
286 * transmit, receive, DMA, and link units. It will not effect
287 * the current PCI configuration. The global reset bit is self-
288 * clearing, and should clear within a microsecond.
290 DEBUGOUT("Issuing a global reset to MAC\n");
292 ctrl_reg
= ixgb_mac_reset(hw
);
294 DEBUGOUT("Issuing an EE reset to MAC\n");
296 /* Workaround for 82597EX reset errata */
297 IXGB_WRITE_REG_IO(hw
, CTRL1
, IXGB_CTRL1_EE_RST
);
299 IXGB_WRITE_REG(hw
, CTRL1
, IXGB_CTRL1_EE_RST
);
302 /* Delay a few ms just to allow the reset to complete */
303 msleep(IXGB_DELAY_AFTER_EE_RESET
);
305 if (ixgb_get_eeprom_data(hw
) == FALSE
) {
309 /* Use the device id to determine the type of phy/transceiver. */
310 hw
->device_id
= ixgb_get_ee_device_id(hw
);
311 hw
->phy_type
= ixgb_identify_phy(hw
);
313 /* Setup the receive addresses.
314 * Receive Address Registers (RARs 0 - 15).
316 ixgb_init_rx_addrs(hw
);
319 * Check that a valid MAC address has been set.
320 * If it is not valid, we fail hardware init.
322 if (!mac_addr_valid(hw
->curr_mac_addr
)) {
323 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
327 /* tell the routines in this file they can access hardware again */
328 hw
->adapter_stopped
= FALSE
;
330 /* Fill in the bus_info structure */
331 ixgb_get_bus_info(hw
);
333 /* Zero out the Multicast HASH table */
334 DEBUGOUT("Zeroing the MTA\n");
335 for(i
= 0; i
< IXGB_MC_TBL_SIZE
; i
++)
336 IXGB_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
338 /* Zero out the VLAN Filter Table Array */
341 /* Zero all of the hardware counters */
342 ixgb_clear_hw_cntrs(hw
);
344 /* Call a subroutine to setup flow control. */
345 status
= ixgb_setup_fc(hw
);
347 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
348 ixgb_check_for_link(hw
);
353 /******************************************************************************
354 * Initializes receive address filters.
356 * hw - Struct containing variables accessed by shared code
358 * Places the MAC address in receive address register 0 and clears the rest
359 * of the receive addresss registers. Clears the multicast table. Assumes
360 * the receiver is in reset when the routine is called.
361 *****************************************************************************/
363 ixgb_init_rx_addrs(struct ixgb_hw
*hw
)
367 DEBUGFUNC("ixgb_init_rx_addrs");
370 * If the current mac address is valid, assume it is a software override
371 * to the permanent address.
372 * Otherwise, use the permanent address from the eeprom.
374 if (!mac_addr_valid(hw
->curr_mac_addr
)) {
376 /* Get the MAC address from the eeprom for later reference */
377 ixgb_get_ee_mac_addr(hw
, hw
->curr_mac_addr
);
379 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
380 hw
->curr_mac_addr
[0],
381 hw
->curr_mac_addr
[1], hw
->curr_mac_addr
[2]);
382 DEBUGOUT3("%.2X %.2X %.2X\n",
383 hw
->curr_mac_addr
[3],
384 hw
->curr_mac_addr
[4], hw
->curr_mac_addr
[5]);
387 /* Setup the receive address. */
388 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
389 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
390 hw
->curr_mac_addr
[0],
391 hw
->curr_mac_addr
[1], hw
->curr_mac_addr
[2]);
392 DEBUGOUT3("%.2X %.2X %.2X\n",
393 hw
->curr_mac_addr
[3],
394 hw
->curr_mac_addr
[4], hw
->curr_mac_addr
[5]);
396 ixgb_rar_set(hw
, hw
->curr_mac_addr
, 0);
399 /* Zero out the other 15 receive addresses. */
400 DEBUGOUT("Clearing RAR[1-15]\n");
401 for(i
= 1; i
< IXGB_RAR_ENTRIES
; i
++) {
402 IXGB_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
403 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
409 /******************************************************************************
410 * Updates the MAC's list of multicast addresses.
412 * hw - Struct containing variables accessed by shared code
413 * mc_addr_list - the list of new multicast addresses
414 * mc_addr_count - number of addresses
415 * pad - number of bytes between addresses in the list
417 * The given list replaces any existing list. Clears the last 15 receive
418 * address registers and the multicast table. Uses receive address registers
419 * for the first 15 multicast addresses, and hashes the rest into the
421 *****************************************************************************/
423 ixgb_mc_addr_list_update(struct ixgb_hw
*hw
,
424 uint8_t *mc_addr_list
,
425 uint32_t mc_addr_count
,
430 uint32_t rar_used_count
= 1; /* RAR[0] is used for our MAC address */
432 DEBUGFUNC("ixgb_mc_addr_list_update");
434 /* Set the new number of MC addresses that we are being requested to use. */
435 hw
->num_mc_addrs
= mc_addr_count
;
437 /* Clear RAR[1-15] */
438 DEBUGOUT(" Clearing RAR[1-15]\n");
439 for(i
= rar_used_count
; i
< IXGB_RAR_ENTRIES
; i
++) {
440 IXGB_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
441 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
445 DEBUGOUT(" Clearing MTA\n");
446 for(i
= 0; i
< IXGB_MC_TBL_SIZE
; i
++) {
447 IXGB_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
450 /* Add the new addresses */
451 for(i
= 0; i
< mc_addr_count
; i
++) {
452 DEBUGOUT(" Adding the multicast addresses:\n");
453 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i
,
454 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
)],
455 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
457 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
459 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
461 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
463 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
466 /* Place this multicast address in the RAR if there is room, *
467 * else put it in the MTA
469 if(rar_used_count
< IXGB_RAR_ENTRIES
) {
472 (i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
)),
474 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i
);
477 hash_value
= ixgb_hash_mc_addr(hw
,
480 (IXGB_ETH_LENGTH_OF_ADDRESS
483 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value
);
485 ixgb_mta_set(hw
, hash_value
);
489 DEBUGOUT("MC Update Complete\n");
493 /******************************************************************************
494 * Hashes an address to determine its location in the multicast table
496 * hw - Struct containing variables accessed by shared code
497 * mc_addr - the multicast address to hash
501 *****************************************************************************/
503 ixgb_hash_mc_addr(struct ixgb_hw
*hw
,
506 uint32_t hash_value
= 0;
508 DEBUGFUNC("ixgb_hash_mc_addr");
510 /* The portion of the address that is used for the hash table is
511 * determined by the mc_filter_type setting.
513 switch (hw
->mc_filter_type
) {
514 /* [0] [1] [2] [3] [4] [5]
516 * LSB MSB - According to H/W docs */
518 /* [47:36] i.e. 0x563 for above example address */
520 ((mc_addr
[4] >> 4) | (((uint16_t) mc_addr
[5]) << 4));
522 case 1: /* [46:35] i.e. 0xAC6 for above example address */
524 ((mc_addr
[4] >> 3) | (((uint16_t) mc_addr
[5]) << 5));
526 case 2: /* [45:34] i.e. 0x5D8 for above example address */
528 ((mc_addr
[4] >> 2) | (((uint16_t) mc_addr
[5]) << 6));
530 case 3: /* [43:32] i.e. 0x634 for above example address */
531 hash_value
= ((mc_addr
[4]) | (((uint16_t) mc_addr
[5]) << 8));
534 /* Invalid mc_filter_type, what should we do? */
535 DEBUGOUT("MC filter type param set incorrectly\n");
544 /******************************************************************************
545 * Sets the bit in the multicast table corresponding to the hash value.
547 * hw - Struct containing variables accessed by shared code
548 * hash_value - Multicast address hash value
549 *****************************************************************************/
551 ixgb_mta_set(struct ixgb_hw
*hw
,
554 uint32_t hash_bit
, hash_reg
;
557 /* The MTA is a register array of 128 32-bit registers.
558 * It is treated like an array of 4096 bits. We want to set
559 * bit BitArray[hash_value]. So we figure out what register
560 * the bit is in, read it, OR in the new bit, then write
561 * back the new value. The register is determined by the
562 * upper 7 bits of the hash value and the bit within that
563 * register are determined by the lower 5 bits of the value.
565 hash_reg
= (hash_value
>> 5) & 0x7F;
566 hash_bit
= hash_value
& 0x1F;
568 mta_reg
= IXGB_READ_REG_ARRAY(hw
, MTA
, hash_reg
);
570 mta_reg
|= (1 << hash_bit
);
572 IXGB_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta_reg
);
577 /******************************************************************************
578 * Puts an ethernet address into a receive address register.
580 * hw - Struct containing variables accessed by shared code
581 * addr - Address to put into receive address register
582 * index - Receive address register to write
583 *****************************************************************************/
585 ixgb_rar_set(struct ixgb_hw
*hw
,
589 uint32_t rar_low
, rar_high
;
591 DEBUGFUNC("ixgb_rar_set");
593 /* HW expects these in little endian so we reverse the byte order
594 * from network order (big endian) to little endian
596 rar_low
= ((uint32_t) addr
[0] |
597 ((uint32_t)addr
[1] << 8) |
598 ((uint32_t)addr
[2] << 16) |
599 ((uint32_t)addr
[3] << 24));
601 rar_high
= ((uint32_t) addr
[4] |
602 ((uint32_t)addr
[5] << 8) |
605 IXGB_WRITE_REG_ARRAY(hw
, RA
, (index
<< 1), rar_low
);
606 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((index
<< 1) + 1), rar_high
);
610 /******************************************************************************
611 * Writes a value to the specified offset in the VLAN filter table.
613 * hw - Struct containing variables accessed by shared code
614 * offset - Offset in VLAN filer table to write
615 * value - Value to write into VLAN filter table
616 *****************************************************************************/
618 ixgb_write_vfta(struct ixgb_hw
*hw
,
622 IXGB_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
626 /******************************************************************************
627 * Clears the VLAN filer table
629 * hw - Struct containing variables accessed by shared code
630 *****************************************************************************/
632 ixgb_clear_vfta(struct ixgb_hw
*hw
)
636 for(offset
= 0; offset
< IXGB_VLAN_FILTER_TBL_SIZE
; offset
++)
637 IXGB_WRITE_REG_ARRAY(hw
, VFTA
, offset
, 0);
641 /******************************************************************************
642 * Configures the flow control settings based on SW configuration.
644 * hw - Struct containing variables accessed by shared code
645 *****************************************************************************/
648 ixgb_setup_fc(struct ixgb_hw
*hw
)
651 uint32_t pap_reg
= 0; /* by default, assume no pause time */
652 boolean_t status
= TRUE
;
654 DEBUGFUNC("ixgb_setup_fc");
656 /* Get the current control reg 0 settings */
657 ctrl_reg
= IXGB_READ_REG(hw
, CTRL0
);
659 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
660 ctrl_reg
&= ~(IXGB_CTRL0_RPE
| IXGB_CTRL0_TPE
);
662 /* The possible values of the "flow_control" parameter are:
663 * 0: Flow control is completely disabled
664 * 1: Rx flow control is enabled (we can receive pause frames
665 * but not send pause frames).
666 * 2: Tx flow control is enabled (we can send pause frames
667 * but we do not support receiving pause frames).
668 * 3: Both Rx and TX flow control (symmetric) are enabled.
671 switch (hw
->fc
.type
) {
672 case ixgb_fc_none
: /* 0 */
673 /* Set CMDC bit to disable Rx Flow control */
674 ctrl_reg
|= (IXGB_CTRL0_CMDC
);
676 case ixgb_fc_rx_pause
: /* 1 */
677 /* RX Flow control is enabled, and TX Flow control is
680 ctrl_reg
|= (IXGB_CTRL0_RPE
);
682 case ixgb_fc_tx_pause
: /* 2 */
683 /* TX Flow control is enabled, and RX Flow control is
684 * disabled, by a software over-ride.
686 ctrl_reg
|= (IXGB_CTRL0_TPE
);
687 pap_reg
= hw
->fc
.pause_time
;
689 case ixgb_fc_full
: /* 3 */
690 /* Flow control (both RX and TX) is enabled by a software
693 ctrl_reg
|= (IXGB_CTRL0_RPE
| IXGB_CTRL0_TPE
);
694 pap_reg
= hw
->fc
.pause_time
;
697 /* We should never get here. The value should be 0-3. */
698 DEBUGOUT("Flow control param set incorrectly\n");
703 /* Write the new settings */
704 IXGB_WRITE_REG(hw
, CTRL0
, ctrl_reg
);
707 IXGB_WRITE_REG(hw
, PAP
, pap_reg
);
710 /* Set the flow control receive threshold registers. Normally,
711 * these registers will be set to a default threshold that may be
712 * adjusted later by the driver's runtime code. However, if the
713 * ability to transmit pause frames in not enabled, then these
714 * registers will be set to 0.
716 if(!(hw
->fc
.type
& ixgb_fc_tx_pause
)) {
717 IXGB_WRITE_REG(hw
, FCRTL
, 0);
718 IXGB_WRITE_REG(hw
, FCRTH
, 0);
720 /* We need to set up the Receive Threshold high and low water
721 * marks as well as (optionally) enabling the transmission of XON
723 if(hw
->fc
.send_xon
) {
724 IXGB_WRITE_REG(hw
, FCRTL
,
725 (hw
->fc
.low_water
| IXGB_FCRTL_XONE
));
727 IXGB_WRITE_REG(hw
, FCRTL
, hw
->fc
.low_water
);
729 IXGB_WRITE_REG(hw
, FCRTH
, hw
->fc
.high_water
);
734 /******************************************************************************
735 * Reads a word from a device over the Management Data Interface (MDI) bus.
736 * This interface is used to manage Physical layer devices.
738 * hw - Struct containing variables accessed by hw code
739 * reg_address - Offset of device register being read.
740 * phy_address - Address of device on MDI.
742 * Returns: Data word (16 bits) from MDI device.
744 * The 82597EX has support for several MDI access methods. This routine
745 * uses the new protocol MDI Single Command and Address Operation.
746 * This requires that first an address cycle command is sent, followed by a
748 *****************************************************************************/
750 ixgb_read_phy_reg(struct ixgb_hw
*hw
,
751 uint32_t reg_address
,
752 uint32_t phy_address
,
753 uint32_t device_type
)
757 uint32_t command
= 0;
759 ASSERT(reg_address
<= IXGB_MAX_PHY_REG_ADDRESS
);
760 ASSERT(phy_address
<= IXGB_MAX_PHY_ADDRESS
);
761 ASSERT(device_type
<= IXGB_MAX_PHY_DEV_TYPE
);
763 /* Setup and write the address cycle command */
764 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
765 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
766 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
767 (IXGB_MSCA_ADDR_CYCLE
| IXGB_MSCA_MDI_COMMAND
));
769 IXGB_WRITE_REG(hw
, MSCA
, command
);
771 /**************************************************************
772 ** Check every 10 usec to see if the address cycle completed
773 ** The COMMAND bit will clear when the operation is complete.
774 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
775 ** from the CPU Write to the Ready bit assertion.
776 **************************************************************/
778 for(i
= 0; i
< 10; i
++)
782 command
= IXGB_READ_REG(hw
, MSCA
);
784 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
788 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
790 /* Address cycle complete, setup and write the read command */
791 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
792 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
793 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
794 (IXGB_MSCA_READ
| IXGB_MSCA_MDI_COMMAND
));
796 IXGB_WRITE_REG(hw
, MSCA
, command
);
798 /**************************************************************
799 ** Check every 10 usec to see if the read command completed
800 ** The COMMAND bit will clear when the operation is complete.
801 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
802 ** from the CPU Write to the Ready bit assertion.
803 **************************************************************/
805 for(i
= 0; i
< 10; i
++)
809 command
= IXGB_READ_REG(hw
, MSCA
);
811 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
815 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
817 /* Operation is complete, get the data from the MDIO Read/Write Data
818 * register and return.
820 data
= IXGB_READ_REG(hw
, MSRWD
);
821 data
>>= IXGB_MSRWD_READ_DATA_SHIFT
;
822 return((uint16_t) data
);
825 /******************************************************************************
826 * Writes a word to a device over the Management Data Interface (MDI) bus.
827 * This interface is used to manage Physical layer devices.
829 * hw - Struct containing variables accessed by hw code
830 * reg_address - Offset of device register being read.
831 * phy_address - Address of device on MDI.
832 * device_type - Also known as the Device ID or DID.
833 * data - 16-bit value to be written
837 * The 82597EX has support for several MDI access methods. This routine
838 * uses the new protocol MDI Single Command and Address Operation.
839 * This requires that first an address cycle command is sent, followed by a
841 *****************************************************************************/
843 ixgb_write_phy_reg(struct ixgb_hw
*hw
,
844 uint32_t reg_address
,
845 uint32_t phy_address
,
846 uint32_t device_type
,
850 uint32_t command
= 0;
852 ASSERT(reg_address
<= IXGB_MAX_PHY_REG_ADDRESS
);
853 ASSERT(phy_address
<= IXGB_MAX_PHY_ADDRESS
);
854 ASSERT(device_type
<= IXGB_MAX_PHY_DEV_TYPE
);
856 /* Put the data in the MDIO Read/Write Data register */
857 IXGB_WRITE_REG(hw
, MSRWD
, (uint32_t)data
);
859 /* Setup and write the address cycle command */
860 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
861 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
862 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
863 (IXGB_MSCA_ADDR_CYCLE
| IXGB_MSCA_MDI_COMMAND
));
865 IXGB_WRITE_REG(hw
, MSCA
, command
);
867 /**************************************************************
868 ** Check every 10 usec to see if the address cycle completed
869 ** The COMMAND bit will clear when the operation is complete.
870 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
871 ** from the CPU Write to the Ready bit assertion.
872 **************************************************************/
874 for(i
= 0; i
< 10; i
++)
878 command
= IXGB_READ_REG(hw
, MSCA
);
880 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
884 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
886 /* Address cycle complete, setup and write the write command */
887 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
888 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
889 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
890 (IXGB_MSCA_WRITE
| IXGB_MSCA_MDI_COMMAND
));
892 IXGB_WRITE_REG(hw
, MSCA
, command
);
894 /**************************************************************
895 ** Check every 10 usec to see if the read command completed
896 ** The COMMAND bit will clear when the operation is complete.
897 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
898 ** from the CPU Write to the Ready bit assertion.
899 **************************************************************/
901 for(i
= 0; i
< 10; i
++)
905 command
= IXGB_READ_REG(hw
, MSCA
);
907 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
911 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
913 /* Operation is complete, return. */
916 /******************************************************************************
917 * Checks to see if the link status of the hardware has changed.
919 * hw - Struct containing variables accessed by hw code
921 * Called by any function that needs to check the link status of the adapter.
922 *****************************************************************************/
924 ixgb_check_for_link(struct ixgb_hw
*hw
)
929 DEBUGFUNC("ixgb_check_for_link");
931 xpcss_reg
= IXGB_READ_REG(hw
, XPCSS
);
932 status_reg
= IXGB_READ_REG(hw
, STATUS
);
934 if ((xpcss_reg
& IXGB_XPCSS_ALIGN_STATUS
) &&
935 (status_reg
& IXGB_STATUS_LU
)) {
937 } else if (!(xpcss_reg
& IXGB_XPCSS_ALIGN_STATUS
) &&
938 (status_reg
& IXGB_STATUS_LU
)) {
939 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
940 hw
->link_up
= ixgb_link_reset(hw
);
943 * 82597EX errata. Since the lane deskew problem may prevent
944 * link, reset the link before reporting link down.
946 hw
->link_up
= ixgb_link_reset(hw
);
948 /* Anything else for 10 Gig?? */
951 /******************************************************************************
952 * Check for a bad link condition that may have occured.
953 * The indication is that the RFC / LFC registers may be incrementing
954 * continually. A full adapter reset is required to recover.
956 * hw - Struct containing variables accessed by hw code
958 * Called by any function that needs to check the link status of the adapter.
959 *****************************************************************************/
960 boolean_t
ixgb_check_for_bad_link(struct ixgb_hw
*hw
)
962 uint32_t newLFC
, newRFC
;
963 boolean_t bad_link_returncode
= FALSE
;
965 if (hw
->phy_type
== ixgb_phy_type_txn17401
) {
966 newLFC
= IXGB_READ_REG(hw
, LFC
);
967 newRFC
= IXGB_READ_REG(hw
, RFC
);
968 if ((hw
->lastLFC
+ 250 < newLFC
)
969 || (hw
->lastRFC
+ 250 < newRFC
)) {
971 ("BAD LINK! too many LFC/RFC since last check\n");
972 bad_link_returncode
= TRUE
;
974 hw
->lastLFC
= newLFC
;
975 hw
->lastRFC
= newRFC
;
978 return bad_link_returncode
;
981 /******************************************************************************
982 * Clears all hardware statistics counters.
984 * hw - Struct containing variables accessed by shared code
985 *****************************************************************************/
987 ixgb_clear_hw_cntrs(struct ixgb_hw
*hw
)
989 volatile uint32_t temp_reg
;
991 DEBUGFUNC("ixgb_clear_hw_cntrs");
993 /* if we are stopped or resetting exit gracefully */
994 if(hw
->adapter_stopped
) {
995 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
999 temp_reg
= IXGB_READ_REG(hw
, TPRL
);
1000 temp_reg
= IXGB_READ_REG(hw
, TPRH
);
1001 temp_reg
= IXGB_READ_REG(hw
, GPRCL
);
1002 temp_reg
= IXGB_READ_REG(hw
, GPRCH
);
1003 temp_reg
= IXGB_READ_REG(hw
, BPRCL
);
1004 temp_reg
= IXGB_READ_REG(hw
, BPRCH
);
1005 temp_reg
= IXGB_READ_REG(hw
, MPRCL
);
1006 temp_reg
= IXGB_READ_REG(hw
, MPRCH
);
1007 temp_reg
= IXGB_READ_REG(hw
, UPRCL
);
1008 temp_reg
= IXGB_READ_REG(hw
, UPRCH
);
1009 temp_reg
= IXGB_READ_REG(hw
, VPRCL
);
1010 temp_reg
= IXGB_READ_REG(hw
, VPRCH
);
1011 temp_reg
= IXGB_READ_REG(hw
, JPRCL
);
1012 temp_reg
= IXGB_READ_REG(hw
, JPRCH
);
1013 temp_reg
= IXGB_READ_REG(hw
, GORCL
);
1014 temp_reg
= IXGB_READ_REG(hw
, GORCH
);
1015 temp_reg
= IXGB_READ_REG(hw
, TORL
);
1016 temp_reg
= IXGB_READ_REG(hw
, TORH
);
1017 temp_reg
= IXGB_READ_REG(hw
, RNBC
);
1018 temp_reg
= IXGB_READ_REG(hw
, RUC
);
1019 temp_reg
= IXGB_READ_REG(hw
, ROC
);
1020 temp_reg
= IXGB_READ_REG(hw
, RLEC
);
1021 temp_reg
= IXGB_READ_REG(hw
, CRCERRS
);
1022 temp_reg
= IXGB_READ_REG(hw
, ICBC
);
1023 temp_reg
= IXGB_READ_REG(hw
, ECBC
);
1024 temp_reg
= IXGB_READ_REG(hw
, MPC
);
1025 temp_reg
= IXGB_READ_REG(hw
, TPTL
);
1026 temp_reg
= IXGB_READ_REG(hw
, TPTH
);
1027 temp_reg
= IXGB_READ_REG(hw
, GPTCL
);
1028 temp_reg
= IXGB_READ_REG(hw
, GPTCH
);
1029 temp_reg
= IXGB_READ_REG(hw
, BPTCL
);
1030 temp_reg
= IXGB_READ_REG(hw
, BPTCH
);
1031 temp_reg
= IXGB_READ_REG(hw
, MPTCL
);
1032 temp_reg
= IXGB_READ_REG(hw
, MPTCH
);
1033 temp_reg
= IXGB_READ_REG(hw
, UPTCL
);
1034 temp_reg
= IXGB_READ_REG(hw
, UPTCH
);
1035 temp_reg
= IXGB_READ_REG(hw
, VPTCL
);
1036 temp_reg
= IXGB_READ_REG(hw
, VPTCH
);
1037 temp_reg
= IXGB_READ_REG(hw
, JPTCL
);
1038 temp_reg
= IXGB_READ_REG(hw
, JPTCH
);
1039 temp_reg
= IXGB_READ_REG(hw
, GOTCL
);
1040 temp_reg
= IXGB_READ_REG(hw
, GOTCH
);
1041 temp_reg
= IXGB_READ_REG(hw
, TOTL
);
1042 temp_reg
= IXGB_READ_REG(hw
, TOTH
);
1043 temp_reg
= IXGB_READ_REG(hw
, DC
);
1044 temp_reg
= IXGB_READ_REG(hw
, PLT64C
);
1045 temp_reg
= IXGB_READ_REG(hw
, TSCTC
);
1046 temp_reg
= IXGB_READ_REG(hw
, TSCTFC
);
1047 temp_reg
= IXGB_READ_REG(hw
, IBIC
);
1048 temp_reg
= IXGB_READ_REG(hw
, RFC
);
1049 temp_reg
= IXGB_READ_REG(hw
, LFC
);
1050 temp_reg
= IXGB_READ_REG(hw
, PFRC
);
1051 temp_reg
= IXGB_READ_REG(hw
, PFTC
);
1052 temp_reg
= IXGB_READ_REG(hw
, MCFRC
);
1053 temp_reg
= IXGB_READ_REG(hw
, MCFTC
);
1054 temp_reg
= IXGB_READ_REG(hw
, XONRXC
);
1055 temp_reg
= IXGB_READ_REG(hw
, XONTXC
);
1056 temp_reg
= IXGB_READ_REG(hw
, XOFFRXC
);
1057 temp_reg
= IXGB_READ_REG(hw
, XOFFTXC
);
1058 temp_reg
= IXGB_READ_REG(hw
, RJC
);
1062 /******************************************************************************
1063 * Turns on the software controllable LED
1065 * hw - Struct containing variables accessed by shared code
1066 *****************************************************************************/
1068 ixgb_led_on(struct ixgb_hw
*hw
)
1070 uint32_t ctrl0_reg
= IXGB_READ_REG(hw
, CTRL0
);
1072 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1073 ctrl0_reg
&= ~IXGB_CTRL0_SDP0
;
1074 IXGB_WRITE_REG(hw
, CTRL0
, ctrl0_reg
);
1078 /******************************************************************************
1079 * Turns off the software controllable LED
1081 * hw - Struct containing variables accessed by shared code
1082 *****************************************************************************/
1084 ixgb_led_off(struct ixgb_hw
*hw
)
1086 uint32_t ctrl0_reg
= IXGB_READ_REG(hw
, CTRL0
);
1088 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1089 ctrl0_reg
|= IXGB_CTRL0_SDP0
;
1090 IXGB_WRITE_REG(hw
, CTRL0
, ctrl0_reg
);
1094 /******************************************************************************
1095 * Gets the current PCI bus type, speed, and width of the hardware
1097 * hw - Struct containing variables accessed by shared code
1098 *****************************************************************************/
1100 ixgb_get_bus_info(struct ixgb_hw
*hw
)
1102 uint32_t status_reg
;
1104 status_reg
= IXGB_READ_REG(hw
, STATUS
);
1106 hw
->bus
.type
= (status_reg
& IXGB_STATUS_PCIX_MODE
) ?
1107 ixgb_bus_type_pcix
: ixgb_bus_type_pci
;
1109 if (hw
->bus
.type
== ixgb_bus_type_pci
) {
1110 hw
->bus
.speed
= (status_reg
& IXGB_STATUS_PCI_SPD
) ?
1111 ixgb_bus_speed_66
: ixgb_bus_speed_33
;
1113 switch (status_reg
& IXGB_STATUS_PCIX_SPD_MASK
) {
1114 case IXGB_STATUS_PCIX_SPD_66
:
1115 hw
->bus
.speed
= ixgb_bus_speed_66
;
1117 case IXGB_STATUS_PCIX_SPD_100
:
1118 hw
->bus
.speed
= ixgb_bus_speed_100
;
1120 case IXGB_STATUS_PCIX_SPD_133
:
1121 hw
->bus
.speed
= ixgb_bus_speed_133
;
1124 hw
->bus
.speed
= ixgb_bus_speed_reserved
;
1129 hw
->bus
.width
= (status_reg
& IXGB_STATUS_BUS64
) ?
1130 ixgb_bus_width_64
: ixgb_bus_width_32
;
1135 /******************************************************************************
1136 * Tests a MAC address to ensure it is a valid Individual Address
1138 * mac_addr - pointer to MAC address.
1140 *****************************************************************************/
1142 mac_addr_valid(uint8_t *mac_addr
)
1144 boolean_t is_valid
= TRUE
;
1145 DEBUGFUNC("mac_addr_valid");
1147 /* Make sure it is not a multicast address */
1148 if (IS_MULTICAST(mac_addr
)) {
1149 DEBUGOUT("MAC address is multicast\n");
1152 /* Not a broadcast address */
1153 else if (IS_BROADCAST(mac_addr
)) {
1154 DEBUGOUT("MAC address is broadcast\n");
1157 /* Reject the zero address */
1158 else if (mac_addr
[0] == 0 &&
1164 DEBUGOUT("MAC address is all zeros\n");
1170 /******************************************************************************
1171 * Resets the 10GbE link. Waits the settle time and returns the state of
1174 * hw - Struct containing variables accessed by shared code
1175 *****************************************************************************/
1177 ixgb_link_reset(struct ixgb_hw
*hw
)
1179 boolean_t link_status
= FALSE
;
1180 uint8_t wait_retries
= MAX_RESET_ITERATIONS
;
1181 uint8_t lrst_retries
= MAX_RESET_ITERATIONS
;
1184 /* Reset the link */
1185 IXGB_WRITE_REG(hw
, CTRL0
,
1186 IXGB_READ_REG(hw
, CTRL0
) | IXGB_CTRL0_LRST
);
1188 /* Wait for link-up and lane re-alignment */
1190 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET
);
1192 ((IXGB_READ_REG(hw
, STATUS
) & IXGB_STATUS_LU
)
1193 && (IXGB_READ_REG(hw
, XPCSS
) &
1194 IXGB_XPCSS_ALIGN_STATUS
)) ? TRUE
: FALSE
;
1195 } while (!link_status
&& --wait_retries
);
1197 } while (!link_status
&& --lrst_retries
);
1202 /******************************************************************************
1203 * Resets the 10GbE optics module.
1205 * hw - Struct containing variables accessed by shared code
1206 *****************************************************************************/
1208 ixgb_optics_reset(struct ixgb_hw
*hw
)
1210 if (hw
->phy_type
== ixgb_phy_type_txn17401
) {
1213 ixgb_write_phy_reg(hw
,
1217 MDIO_PMA_PMD_CR1_RESET
);
1219 mdio_reg
= ixgb_read_phy_reg( hw
,