arch/arm/mach-ixp2000/core.c

   1 /*
   2  * arch/arm/mach-ixp2000/common.c
   3  *
   4  * Common routines used by all IXP2400/2800 based platforms.
   5  *
   6  * Author: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2004 (C) MontaVista Software, Inc.
   9  *
  10  * Based on work Copyright (C) 2002-2003 Intel Corporation
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2. This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/sched.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/serial.h>
  24 #include <linux/tty.h>
  25 #include <linux/bitops.h>
  26 #include <linux/serial_8250.h>
  27 #include <linux/mm.h>
  28
  29 #include <asm/types.h>
  30 #include <asm/setup.h>
  31 #include <asm/memory.h>
  32 #include <asm/hardware.h>
  33 #include <asm/mach-types.h>
  34 #include <asm/irq.h>
  35 #include <asm/system.h>
  36 #include <asm/tlbflush.h>
  37 #include <asm/pgtable.h>
  38
  39 #include <asm/mach/map.h>
  40 #include <asm/mach/time.h>
  41 #include <asm/mach/irq.h>
  42
  43 #include <asm/arch/gpio.h>
  44
  45 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
  46 static unsigned long ixp2000_slowport_irq_flags;
  47
  48 /*************************************************************************
  49  * Slowport access routines
  50  *************************************************************************/
  51 void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
  52 {
  53
  54         spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
  55
  56         old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
  57         old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
  58         old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
  59         old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
  60         old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
  61
  62         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
  63         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
  64         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
  65         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
  66         ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
  67 }
  68
  69 void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
  70 {
  71         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
  72         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
  73         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
  74         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
  75         ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
  76
  77         spin_unlock_irqrestore(&ixp2000_slowport_lock,
  78                                         ixp2000_slowport_irq_flags);
  79 }
  80
  81 /*************************************************************************
  82  * Chip specific mappings shared by all IXP2000 systems
  83  *************************************************************************/
  84 static struct map_desc ixp2000_io_desc[] __initdata = {
  85         {
  86                 .virtual        = IXP2000_CAP_VIRT_BASE,
  87                 .physical       = IXP2000_CAP_PHYS_BASE,
  88                 .length         = IXP2000_CAP_SIZE,
  89                 .type           = MT_DEVICE
  90         }, {
  91                 .virtual        = IXP2000_INTCTL_VIRT_BASE,
  92                 .physical       = IXP2000_INTCTL_PHYS_BASE,
  93                 .length         = IXP2000_INTCTL_SIZE,
  94                 .type           = MT_DEVICE
  95         }, {
  96                 .virtual        = IXP2000_PCI_CREG_VIRT_BASE,
  97                 .physical       = IXP2000_PCI_CREG_PHYS_BASE,
  98                 .length         = IXP2000_PCI_CREG_SIZE,
  99                 .type           = MT_DEVICE
 100         }, {
 101                 .virtual        = IXP2000_PCI_CSR_VIRT_BASE,
 102                 .physical       = IXP2000_PCI_CSR_PHYS_BASE,
 103                 .length         = IXP2000_PCI_CSR_SIZE,
 104                 .type           = MT_DEVICE
 105         }, {
 106                 .virtual        = IXP2000_MSF_VIRT_BASE,
 107                 .physical       = IXP2000_MSF_PHYS_BASE,
 108                 .length         = IXP2000_MSF_SIZE,
 109                 .type           = MT_DEVICE
 110         }, {
 111                 .virtual        = IXP2000_PCI_IO_VIRT_BASE,
 112                 .physical       = IXP2000_PCI_IO_PHYS_BASE,
 113                 .length         = IXP2000_PCI_IO_SIZE,
 114                 .type           = MT_DEVICE
 115         }, {
 116                 .virtual        = IXP2000_PCI_CFG0_VIRT_BASE,
 117                 .physical       = IXP2000_PCI_CFG0_PHYS_BASE,
 118                 .length         = IXP2000_PCI_CFG0_SIZE,
 119                 .type           = MT_DEVICE
 120         }, {
 121                 .virtual        = IXP2000_PCI_CFG1_VIRT_BASE,
 122                 .physical       = IXP2000_PCI_CFG1_PHYS_BASE,
 123                 .length         = IXP2000_PCI_CFG1_SIZE,
 124                 .type           = MT_DEVICE
 125         }
 126 };
 127
 128 void __init ixp2000_map_io(void)
 129 {
 130         extern unsigned int processor_id;
 131
 132         /*
 133          * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE for
 134          * tweaking the PMDs so XCB=101. On IXP2800s we use the normal
 135          * PMD flags.
 136          */
 137         if ((processor_id & 0xfffffff0) == 0x69054190) {
 138                 int i;
 139
 140                 printk(KERN_INFO "Enabling IXP2400 erratum #66 workaround\n");
 141
 142                 for(i=0;i<ARRAY_SIZE(ixp2000_io_desc);i++)
 143                         ixp2000_io_desc[i].type = MT_IXP2000_DEVICE;
 144         }
 145
 146         iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
 147
 148         /* Set slowport to 8-bit mode.  */
 149         ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1);
 150 }
 151
 152
 153 /*************************************************************************
 154  * Serial port support for IXP2000
 155  *************************************************************************/
 156 static struct plat_serial8250_port ixp2000_serial_port[] = {
 157         {
 158                 .mapbase        = IXP2000_UART_PHYS_BASE,
 159                 .membase        = (char *)(IXP2000_UART_VIRT_BASE + 3),
 160                 .irq            = IRQ_IXP2000_UART,
 161                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 162                 .iotype         = UPIO_MEM,
 163                 .regshift       = 2,
 164                 .uartclk        = 50000000,
 165         },
 166         { },
 167 };
 168
 169 static struct resource ixp2000_uart_resource = {
 170         .start          = IXP2000_UART_PHYS_BASE,
 171         .end            = IXP2000_UART_PHYS_BASE + 0xffff,
 172         .flags          = IORESOURCE_MEM,
 173 };
 174
 175 static struct platform_device ixp2000_serial_device = {
 176         .name           = "serial8250",
 177         .id             = 0,
 178         .dev            = {
 179                 .platform_data          = ixp2000_serial_port,
 180         },
 181         .num_resources  = 1,
 182         .resource       = &ixp2000_uart_resource,
 183 };
 184
 185 void __init ixp2000_uart_init(void)
 186 {
 187         platform_device_register(&ixp2000_serial_device);
 188 }
 189
 190
 191 /*************************************************************************
 192  * Timer-tick functions for IXP2000
 193  *************************************************************************/
 194 static unsigned ticks_per_jiffy;
 195 static unsigned ticks_per_usec;
 196 static unsigned next_jiffy_time;
 197 static volatile unsigned long *missing_jiffy_timer_csr;
 198
 199 unsigned long ixp2000_gettimeoffset (void)
 200 {
 201         unsigned long offset;
 202
 203         offset = next_jiffy_time - *missing_jiffy_timer_csr;
 204
 205         return offset / ticks_per_usec;
 206 }
 207
 208 static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 209 {
 210         write_seqlock(&xtime_lock);
 211
 212         /* clear timer 1 */
 213         ixp2000_reg_write(IXP2000_T1_CLR, 1);
 214
 215         while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
 216                 timer_tick(regs);
 217                 next_jiffy_time -= ticks_per_jiffy;
 218         }
 219
 220         write_sequnlock(&xtime_lock);
 221
 222         return IRQ_HANDLED;
 223 }
 224
 225 static struct irqaction ixp2000_timer_irq = {
 226         .name           = "IXP2000 Timer Tick",
 227         .flags          = SA_INTERRUPT | SA_TIMER,
 228         .handler        = ixp2000_timer_interrupt,
 229 };
 230
 231 void __init ixp2000_init_time(unsigned long tick_rate)
 232 {
 233         ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
 234         ticks_per_usec = tick_rate / 1000000;
 235
 236         /*
 237          * We use timer 1 as our timer interrupt.
 238          */
 239         ixp2000_reg_write(IXP2000_T1_CLR, 0);
 240         ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
 241         ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
 242
 243         /*
 244          * We use a second timer as a monotonic counter for tracking
 245          * missed jiffies.  The IXP2000 has four timers, but if we're
 246          * on an A-step IXP2800, timer 2 and 3 don't work, so on those
 247          * chips we use timer 4.  Timer 4 is the only timer that can
 248          * be used for the watchdog, so we use timer 2 if we're on a
 249          * non-buggy chip.
 250          */
 251         if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
 252                 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
 253
 254                 ixp2000_reg_write(IXP2000_T4_CLR, 0);
 255                 ixp2000_reg_write(IXP2000_T4_CLD, -1);
 256                 ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));
 257                 missing_jiffy_timer_csr = IXP2000_T4_CSR;
 258         } else {
 259                 ixp2000_reg_write(IXP2000_T2_CLR, 0);
 260                 ixp2000_reg_write(IXP2000_T2_CLD, -1);
 261                 ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7));
 262                 missing_jiffy_timer_csr = IXP2000_T2_CSR;
 263         }
 264         next_jiffy_time = 0xffffffff;
 265
 266         /* register for interrupt */
 267         setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
 268 }
 269
 270 /*************************************************************************
 271  * GPIO helpers
 272  *************************************************************************/
 273 static unsigned long GPIO_IRQ_falling_edge;
 274 static unsigned long GPIO_IRQ_rising_edge;
 275 static unsigned long GPIO_IRQ_level_low;
 276 static unsigned long GPIO_IRQ_level_high;
 277
 278 static void update_gpio_int_csrs(void)
 279 {
 280         ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
 281         ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
 282         ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
 283         ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
 284 }
 285
 286 void gpio_line_config(int line, int direction)
 287 {
 288         unsigned long flags;
 289
 290         local_irq_save(flags);
 291         if (direction == GPIO_OUT) {
 292                 irq_desc[line + IRQ_IXP2000_GPIO0].valid = 0;
 293
 294                 /* if it's an output, it ain't an interrupt anymore */
 295                 GPIO_IRQ_falling_edge &= ~(1 << line);
 296                 GPIO_IRQ_rising_edge &= ~(1 << line);
 297                 GPIO_IRQ_level_low &= ~(1 << line);
 298                 GPIO_IRQ_level_high &= ~(1 << line);
 299                 update_gpio_int_csrs();
 300
 301                 ixp2000_reg_write(IXP2000_GPIO_PDSR, 1 << line);
 302         } else if (direction == GPIO_IN) {
 303                 ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
 304         }
 305         local_irq_restore(flags);
 306 }
 307
 308
 309 /*************************************************************************
 310  * IRQ handling IXP2000
 311  *************************************************************************/
 312 static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 313 {
 314         int i;
 315         unsigned long status = *IXP2000_GPIO_INST;
 316
 317         for (i = 0; i <= 7; i++) {
 318                 if (status & (1<<i)) {
 319                         desc = irq_desc + i + IRQ_IXP2000_GPIO0;
 320                         desc->handle(i + IRQ_IXP2000_GPIO0, desc, regs);
 321                 }
 322         }
 323 }
 324
 325 static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
 326 {
 327         int line = irq - IRQ_IXP2000_GPIO0;
 328
 329         /*
 330          * First, configure this GPIO line as an input.
 331          */
 332         ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
 333
 334         /*
 335          * Then, set the proper trigger type.
 336          */
 337         if (type & IRQT_FALLING)
 338                 GPIO_IRQ_falling_edge |= 1 << line;
 339         else
 340                 GPIO_IRQ_falling_edge &= ~(1 << line);
 341         if (type & IRQT_RISING)
 342                 GPIO_IRQ_rising_edge |= 1 << line;
 343         else
 344                 GPIO_IRQ_rising_edge &= ~(1 << line);
 345         if (type & IRQT_LOW)
 346                 GPIO_IRQ_level_low |= 1 << line;
 347         else
 348                 GPIO_IRQ_level_low &= ~(1 << line);
 349         if (type & IRQT_HIGH)
 350                 GPIO_IRQ_level_high |= 1 << line;
 351         else
 352                 GPIO_IRQ_level_high &= ~(1 << line);
 353         update_gpio_int_csrs();
 354
 355         /*
 356          * Finally, mark the corresponding IRQ as valid.
 357          */
 358         irq_desc[irq].valid = 1;
 359
 360         return 0;
 361 }
 362
 363 static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
 364 {
 365         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 366
 367         ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 368         ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 369         ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
 370 }
 371
 372 static void ixp2000_GPIO_irq_mask(unsigned int irq)
 373 {
 374         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 375 }
 376
 377 static void ixp2000_GPIO_irq_unmask(unsigned int irq)
 378 {
 379         ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 380 }
 381
 382 static struct irqchip ixp2000_GPIO_irq_chip = {
 383         .type   = ixp2000_GPIO_irq_type,
 384         .ack    = ixp2000_GPIO_irq_mask_ack,
 385         .mask   = ixp2000_GPIO_irq_mask,
 386         .unmask = ixp2000_GPIO_irq_unmask
 387 };
 388
 389 static void ixp2000_pci_irq_mask(unsigned int irq)
 390 {
 391         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
 392         if (irq == IRQ_IXP2000_PCIA)
 393                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
 394         else if (irq == IRQ_IXP2000_PCIB)
 395                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
 396 }
 397
 398 static void ixp2000_pci_irq_unmask(unsigned int irq)
 399 {
 400         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
 401         if (irq == IRQ_IXP2000_PCIA)
 402                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
 403         else if (irq == IRQ_IXP2000_PCIB)
 404                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
 405 }
 406
 407 static struct irqchip ixp2000_pci_irq_chip = {
 408         .ack    = ixp2000_pci_irq_mask,
 409         .mask   = ixp2000_pci_irq_mask,
 410         .unmask = ixp2000_pci_irq_unmask
 411 };
 412
 413 static void ixp2000_irq_mask(unsigned int irq)
 414 {
 415         ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
 416 }
 417
 418 static void ixp2000_irq_unmask(unsigned int irq)
 419 {
 420         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
 421 }
 422
 423 static struct irqchip ixp2000_irq_chip = {
 424         .ack    = ixp2000_irq_mask,
 425         .mask   = ixp2000_irq_mask,
 426         .unmask = ixp2000_irq_unmask
 427 };
 428
 429 void __init ixp2000_init_irq(void)
 430 {
 431         int irq;
 432
 433         /*
 434          * Mask all sources
 435          */
 436         ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
 437         ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
 438
 439         /* clear all GPIO edge/level detects */
 440         ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
 441         ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
 442         ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
 443         ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
 444         ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
 445
 446         /* clear PCI interrupt sources */
 447         ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
 448
 449         /*
 450          * Certain bits in the IRQ status register of the
 451          * IXP2000 are reserved. Instead of trying to map
 452          * things non 1:1 from bit position to IRQ number,
 453          * we mark the reserved IRQs as invalid. This makes
 454          * our mask/unmask code much simpler.
 455          */
 456         for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
 457                 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
 458                         set_irq_chip(irq, &ixp2000_irq_chip);
 459                         set_irq_handler(irq, do_level_IRQ);
 460                         set_irq_flags(irq, IRQF_VALID);
 461                 } else set_irq_flags(irq, 0);
 462         }
 463
 464         /*
 465          * GPIO IRQs are invalid until someone sets the interrupt mode
 466          * by calling set_irq_type().
 467          */
 468         for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
 469                 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
 470                 set_irq_handler(irq, do_level_IRQ);
 471                 set_irq_flags(irq, 0);
 472         }
 473         set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
 474
 475         /*
 476          * Enable PCI irqs.  The actual PCI[AB] decoding is done in
 477          * entry-macro.S, so we don't need a chained handler for the
 478          * PCI interrupt source.
 479          */
 480         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
 481         for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
 482                 set_irq_chip(irq, &ixp2000_pci_irq_chip);
 483                 set_irq_handler(irq, do_level_IRQ);
 484                 set_irq_flags(irq, IRQF_VALID);
 485         }
 486 }
 487