2 * linux/drivers/ide/pci/siimage.c Version 1.11 Jan 27, 2007
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
6 * Copyright (C) 2007 MontaVista Software, Inc.
8 * May be copied or modified under the terms of the GNU General Public License
10 * Documentation for CMD680:
11 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
13 * Documentation for SiI 3112:
14 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
16 * Errata and other documentation only available under NDA.
20 * If you are using Marvell SATA-IDE adapters with Maxtor drives
21 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
23 * If you are using WD drives with SATA bridges you must set the
24 * drive to "Single". "Master" will hang
26 * If you have strange problems with nVidia chipset systems please
27 * see the SI support documentation and update your system BIOS
31 #include <linux/types.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
35 #include <linux/hdreg.h>
36 #include <linux/ide.h>
37 #include <linux/init.h>
42 * pdev_is_sata - check if device is SATA
43 * @pdev: PCI device to check
45 * Returns true if this is a SATA controller
48 static int pdev_is_sata(struct pci_dev
*pdev
)
52 case PCI_DEVICE_ID_SII_3112
:
53 case PCI_DEVICE_ID_SII_1210SA
:
55 case PCI_DEVICE_ID_SII_680
:
63 * is_sata - check if hwif is SATA
64 * @hwif: interface to check
66 * Returns true if this is a SATA controller
69 static inline int is_sata(ide_hwif_t
*hwif
)
71 return pdev_is_sata(hwif
->pci_dev
);
75 * siimage_selreg - return register base
79 * Turn a config register offset into the right address in either
80 * PCI space or MMIO space to access the control register in question
81 * Thankfully this is a configuration operation so isnt performance
85 static unsigned long siimage_selreg(ide_hwif_t
*hwif
, int r
)
87 unsigned long base
= (unsigned long)hwif
->hwif_data
;
90 base
+= (hwif
->channel
<< 6);
92 base
+= (hwif
->channel
<< 4);
97 * siimage_seldev - return register base
101 * Turn a config register offset into the right address in either
102 * PCI space or MMIO space to access the control register in question
103 * including accounting for the unit shift.
106 static inline unsigned long siimage_seldev(ide_drive_t
*drive
, int r
)
108 ide_hwif_t
*hwif
= HWIF(drive
);
109 unsigned long base
= (unsigned long)hwif
->hwif_data
;
112 base
+= (hwif
->channel
<< 6);
114 base
+= (hwif
->channel
<< 4);
115 base
|= drive
->select
.b
.unit
<< drive
->select
.b
.unit
;
120 * siimage_ratemask - Compute available modes
123 * Compute the available speeds for the devices on the interface.
124 * For the CMD680 this depends on the clocking mode (scsc), for the
125 * SI3312 SATA controller life is a bit simpler. Enforce UDMA33
126 * as a limit if there is no 80pin cable present.
129 static byte
siimage_ratemask (ide_drive_t
*drive
)
131 ide_hwif_t
*hwif
= HWIF(drive
);
132 u8 mode
= 0, scsc
= 0;
133 unsigned long base
= (unsigned long) hwif
->hwif_data
;
136 scsc
= hwif
->INB(base
+ 0x4A);
138 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
142 if(strstr(drive
->id
->model
, "Maxtor"))
147 if ((scsc
& 0x30) == 0x10) /* 133 */
149 else if ((scsc
& 0x30) == 0x20) /* 2xPCI */
151 else if ((scsc
& 0x30) == 0x00) /* 100 */
153 else /* Disabled ? */
156 if (!eighty_ninty_three(drive
))
157 mode
= min(mode
, (u8
)1);
162 * siimage_taskfile_timing - turn timing data to a mode
163 * @hwif: interface to query
165 * Read the timing data for the interface and return the
166 * mode that is being used.
169 static byte
siimage_taskfile_timing (ide_hwif_t
*hwif
)
172 unsigned long addr
= siimage_selreg(hwif
, 2);
175 timing
= hwif
->INW(addr
);
177 pci_read_config_word(hwif
->pci_dev
, addr
, &timing
);
180 case 0x10c1: return 4;
181 case 0x10c3: return 3;
183 case 0x1281: return 2;
184 case 0x2283: return 1;
191 * simmage_tuneproc - tune a drive
192 * @drive: drive to tune
193 * @mode_wanted: the target operating mode
195 * Load the timing settings for this device mode into the
196 * controller. If we are in PIO mode 3 or 4 turn on IORDY
197 * monitoring (bit 9). The TF timing is bits 31:16
200 static void siimage_tuneproc (ide_drive_t
*drive
, byte mode_wanted
)
202 ide_hwif_t
*hwif
= HWIF(drive
);
205 unsigned long addr
= siimage_seldev(drive
, 0x04);
206 unsigned long tfaddr
= siimage_selreg(hwif
, 0x02);
208 /* cheat for now and use the docs */
209 switch (mode_wanted
) {
234 hwif
->OUTW(speedp
, addr
);
235 hwif
->OUTW(speedt
, tfaddr
);
236 /* Now set up IORDY */
237 if(mode_wanted
== 3 || mode_wanted
== 4)
238 hwif
->OUTW(hwif
->INW(tfaddr
-2)|0x200, tfaddr
-2);
240 hwif
->OUTW(hwif
->INW(tfaddr
-2)&~0x200, tfaddr
-2);
242 pci_write_config_word(hwif
->pci_dev
, addr
, speedp
);
243 pci_write_config_word(hwif
->pci_dev
, tfaddr
, speedt
);
244 pci_read_config_word(hwif
->pci_dev
, tfaddr
-2, &speedp
);
246 /* Set IORDY for mode 3 or 4 */
247 if(mode_wanted
== 3 || mode_wanted
== 4)
249 pci_write_config_word(hwif
->pci_dev
, tfaddr
-2, speedp
);
254 * config_siimage_chipset_for_pio - set drive timings
255 * @drive: drive to tune
258 * Compute the best pio mode we can for a given device. Also honour
259 * the timings for the driver when dealing with mixed devices. Some
260 * of this is ugly but its all wrapped up here
262 * The SI680 can also do VDMA - we need to start using that
264 * FIXME: we use the BIOS channel timings to avoid driving the task
265 * files too fast at the disk. We need to compute the master/slave
266 * drive PIO mode properly so that we can up the speed on a hotplug
270 static void config_siimage_chipset_for_pio (ide_drive_t
*drive
, byte set_speed
)
272 u8 channel_timings
= siimage_taskfile_timing(HWIF(drive
));
273 u8 speed
= 0, set_pio
= ide_get_best_pio_mode(drive
, 4, 5, NULL
);
275 /* WARNING PIO timing mess is going to happen b/w devices, argh */
276 if ((channel_timings
!= set_pio
) && (set_pio
> channel_timings
))
277 set_pio
= channel_timings
;
279 siimage_tuneproc(drive
, set_pio
);
280 speed
= XFER_PIO_0
+ set_pio
;
282 (void) ide_config_drive_speed(drive
, speed
);
285 static void config_chipset_for_pio (ide_drive_t
*drive
, byte set_speed
)
287 config_siimage_chipset_for_pio(drive
, set_speed
);
291 * siimage_tune_chipset - set controller timings
292 * @drive: Drive to set up
293 * @xferspeed: speed we want to achieve
295 * Tune the SII chipset for the desired mode. If we can't achieve
296 * the desired mode then tune for a lower one, but ultimately
297 * make the thing work.
300 static int siimage_tune_chipset (ide_drive_t
*drive
, byte xferspeed
)
302 u8 ultra6
[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
303 u8 ultra5
[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
304 u16 dma
[] = { 0x2208, 0x10C2, 0x10C1 };
306 ide_hwif_t
*hwif
= HWIF(drive
);
307 u16 ultra
= 0, multi
= 0;
308 u8 mode
= 0, unit
= drive
->select
.b
.unit
;
309 u8 speed
= ide_rate_filter(siimage_ratemask(drive
), xferspeed
);
310 unsigned long base
= (unsigned long)hwif
->hwif_data
;
311 u8 scsc
= 0, addr_mask
= ((hwif
->channel
) ?
312 ((hwif
->mmio
) ? 0xF4 : 0x84) :
313 ((hwif
->mmio
) ? 0xB4 : 0x80));
315 unsigned long ma
= siimage_seldev(drive
, 0x08);
316 unsigned long ua
= siimage_seldev(drive
, 0x0C);
319 scsc
= hwif
->INB(base
+ 0x4A);
320 mode
= hwif
->INB(base
+ addr_mask
);
321 multi
= hwif
->INW(ma
);
322 ultra
= hwif
->INW(ua
);
324 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
325 pci_read_config_byte(hwif
->pci_dev
, addr_mask
, &mode
);
326 pci_read_config_word(hwif
->pci_dev
, ma
, &multi
);
327 pci_read_config_word(hwif
->pci_dev
, ua
, &ultra
);
330 mode
&= ~((unit
) ? 0x30 : 0x03);
332 scsc
= ((scsc
& 0x30) == 0x00) ? 0 : 1;
334 scsc
= is_sata(hwif
) ? 1 : scsc
;
342 siimage_tuneproc(drive
, (speed
- XFER_PIO_0
));
343 mode
|= ((unit
) ? 0x10 : 0x01);
348 multi
= dma
[speed
- XFER_MW_DMA_0
];
349 mode
|= ((unit
) ? 0x20 : 0x02);
350 config_siimage_chipset_for_pio(drive
, 0);
360 ultra
|= ((scsc
) ? (ultra6
[speed
- XFER_UDMA_0
]) :
361 (ultra5
[speed
- XFER_UDMA_0
]));
362 mode
|= ((unit
) ? 0x30 : 0x03);
363 config_siimage_chipset_for_pio(drive
, 0);
370 hwif
->OUTB(mode
, base
+ addr_mask
);
371 hwif
->OUTW(multi
, ma
);
372 hwif
->OUTW(ultra
, ua
);
374 pci_write_config_byte(hwif
->pci_dev
, addr_mask
, mode
);
375 pci_write_config_word(hwif
->pci_dev
, ma
, multi
);
376 pci_write_config_word(hwif
->pci_dev
, ua
, ultra
);
378 return (ide_config_drive_speed(drive
, speed
));
382 * config_chipset_for_dma - configure for DMA
383 * @drive: drive to configure
385 * Called by the IDE layer when it wants the timings set up.
386 * For the CMD680 we also need to set up the PIO timings and
390 static int config_chipset_for_dma (ide_drive_t
*drive
)
392 u8 speed
= ide_dma_speed(drive
, siimage_ratemask(drive
));
394 config_chipset_for_pio(drive
, !speed
);
399 if (siimage_tune_chipset(drive
, speed
))
402 return ide_dma_enable(drive
);
406 * siimage_configure_drive_for_dma - set up for DMA transfers
407 * @drive: drive we are going to set up
409 * Set up the drive for DMA, tune the controller and drive as
410 * required. If the drive isn't suitable for DMA or we hit
411 * other problems then we will drop down to PIO and set up
415 static int siimage_config_drive_for_dma (ide_drive_t
*drive
)
417 ide_hwif_t
*hwif
= HWIF(drive
);
419 if (ide_use_dma(drive
) && config_chipset_for_dma(drive
))
420 return hwif
->ide_dma_on(drive
);
422 if (ide_use_fast_pio(drive
)) {
423 config_chipset_for_pio(drive
, 1);
424 return hwif
->ide_dma_off_quietly(drive
);
426 /* IORDY not supported */
430 /* returns 1 if dma irq issued, 0 otherwise */
431 static int siimage_io_ide_dma_test_irq (ide_drive_t
*drive
)
433 ide_hwif_t
*hwif
= HWIF(drive
);
435 unsigned long addr
= siimage_selreg(hwif
, 1);
437 /* return 1 if INTR asserted */
438 if ((hwif
->INB(hwif
->dma_status
) & 4) == 4)
441 /* return 1 if Device INTR asserted */
442 pci_read_config_byte(hwif
->pci_dev
, addr
, &dma_altstat
);
444 return 0; //return 1;
449 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
450 * @drive: drive we are testing
452 * Check if we caused an IDE DMA interrupt. We may also have caused
453 * SATA status interrupts, if so we clean them up and continue.
456 static int siimage_mmio_ide_dma_test_irq (ide_drive_t
*drive
)
458 ide_hwif_t
*hwif
= HWIF(drive
);
459 unsigned long base
= (unsigned long)hwif
->hwif_data
;
460 unsigned long addr
= siimage_selreg(hwif
, 0x1);
462 if (SATA_ERROR_REG
) {
463 u32 ext_stat
= readl((void __iomem
*)(base
+ 0x10));
465 if (ext_stat
& ((hwif
->channel
) ? 0x40 : 0x10)) {
466 u32 sata_error
= readl((void __iomem
*)SATA_ERROR_REG
);
467 writel(sata_error
, (void __iomem
*)SATA_ERROR_REG
);
468 watchdog
= (sata_error
& 0x00680000) ? 1 : 0;
469 printk(KERN_WARNING
"%s: sata_error = 0x%08x, "
470 "watchdog = %d, %s\n",
471 drive
->name
, sata_error
, watchdog
,
475 watchdog
= (ext_stat
& 0x8000) ? 1 : 0;
479 if (!(ext_stat
& 0x0404) && !watchdog
)
483 /* return 1 if INTR asserted */
484 if ((readb((void __iomem
*)hwif
->dma_status
) & 0x04) == 0x04)
487 /* return 1 if Device INTR asserted */
488 if ((readb((void __iomem
*)addr
) & 8) == 8)
489 return 0; //return 1;
495 * siimage_busproc - bus isolation ioctl
496 * @drive: drive to isolate/restore
497 * @state: bus state to set
499 * Used by the SII3112 to handle bus isolation. As this is a
500 * SATA controller the work required is quite limited, we
501 * just have to clean up the statistics
504 static int siimage_busproc (ide_drive_t
* drive
, int state
)
506 ide_hwif_t
*hwif
= HWIF(drive
);
508 unsigned long addr
= siimage_selreg(hwif
, 0);
511 stat_config
= readl((void __iomem
*)addr
);
513 pci_read_config_dword(hwif
->pci_dev
, addr
, &stat_config
);
517 hwif
->drives
[0].failures
= 0;
518 hwif
->drives
[1].failures
= 0;
521 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
522 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
524 case BUSSTATE_TRISTATE
:
525 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
526 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
531 hwif
->bus_state
= state
;
536 * siimage_reset_poll - wait for sata reset
537 * @drive: drive we are resetting
539 * Poll the SATA phy and see whether it has come back from the dead
543 static int siimage_reset_poll (ide_drive_t
*drive
)
545 if (SATA_STATUS_REG
) {
546 ide_hwif_t
*hwif
= HWIF(drive
);
548 /* SATA_STATUS_REG is valid only when in MMIO mode */
549 if ((readl((void __iomem
*)SATA_STATUS_REG
) & 0x03) != 0x03) {
550 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
551 hwif
->name
, readl((void __iomem
*)SATA_STATUS_REG
));
552 HWGROUP(drive
)->polling
= 0;
562 * siimage_pre_reset - reset hook
563 * @drive: IDE device being reset
565 * For the SATA devices we need to handle recalibration/geometry
569 static void siimage_pre_reset (ide_drive_t
*drive
)
571 if (drive
->media
!= ide_disk
)
574 if (is_sata(HWIF(drive
)))
576 drive
->special
.b
.set_geometry
= 0;
577 drive
->special
.b
.recalibrate
= 0;
582 * siimage_reset - reset a device on an siimage controller
583 * @drive: drive to reset
585 * Perform a controller level reset fo the device. For
586 * SATA we must also check the PHY.
589 static void siimage_reset (ide_drive_t
*drive
)
591 ide_hwif_t
*hwif
= HWIF(drive
);
593 unsigned long addr
= siimage_selreg(hwif
, 0);
596 reset
= hwif
->INB(addr
);
597 hwif
->OUTB((reset
|0x03), addr
);
600 hwif
->OUTB(reset
, addr
);
601 (void) hwif
->INB(addr
);
603 pci_read_config_byte(hwif
->pci_dev
, addr
, &reset
);
604 pci_write_config_byte(hwif
->pci_dev
, addr
, reset
|0x03);
606 pci_write_config_byte(hwif
->pci_dev
, addr
, reset
);
607 pci_read_config_byte(hwif
->pci_dev
, addr
, &reset
);
610 if (SATA_STATUS_REG
) {
611 /* SATA_STATUS_REG is valid only when in MMIO mode */
612 u32 sata_stat
= readl((void __iomem
*)SATA_STATUS_REG
);
613 printk(KERN_WARNING
"%s: reset phy, status=0x%08x, %s\n",
614 hwif
->name
, sata_stat
, __FUNCTION__
);
616 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
617 hwif
->name
, sata_stat
);
625 * proc_reports_siimage - add siimage controller to proc
627 * @clocking: SCSC value
628 * @name: controller name
630 * Report the clocking mode of the controller and add it to
631 * the /proc interface layer
634 static void proc_reports_siimage (struct pci_dev
*dev
, u8 clocking
, const char *name
)
636 if (!pdev_is_sata(dev
)) {
637 printk(KERN_INFO
"%s: BASE CLOCK ", name
);
640 case 0x03: printk("DISABLED!\n"); break;
641 case 0x02: printk("== 2X PCI\n"); break;
642 case 0x01: printk("== 133\n"); break;
643 case 0x00: printk("== 100\n"); break;
649 * setup_mmio_siimage - switch an SI controller into MMIO
650 * @dev: PCI device we are configuring
653 * Attempt to put the device into mmio mode. There are some slight
654 * complications here with certain systems where the mmio bar isnt
655 * mapped so we have to be sure we can fall back to I/O.
658 static unsigned int setup_mmio_siimage (struct pci_dev
*dev
, const char *name
)
660 unsigned long bar5
= pci_resource_start(dev
, 5);
661 unsigned long barsize
= pci_resource_len(dev
, 5);
663 void __iomem
*ioaddr
;
667 * Drop back to PIO if we can't map the mmio. Some
668 * systems seem to get terminally confused in the PCI
672 if(!request_mem_region(bar5
, barsize
, name
))
674 printk(KERN_WARNING
"siimage: IDE controller MMIO ports not available.\n");
678 ioaddr
= ioremap(bar5
, barsize
);
682 release_mem_region(bar5
, barsize
);
687 pci_set_drvdata(dev
, (void *) ioaddr
);
689 if (pdev_is_sata(dev
)) {
690 /* make sure IDE0/1 interrupts are not masked */
691 irq_mask
= (1 << 22) | (1 << 23);
692 tmp
= readl(ioaddr
+ 0x48);
693 if (tmp
& irq_mask
) {
695 writel(tmp
, ioaddr
+ 0x48);
696 readl(ioaddr
+ 0x48); /* flush */
698 writel(0, ioaddr
+ 0x148);
699 writel(0, ioaddr
+ 0x1C8);
702 writeb(0, ioaddr
+ 0xB4);
703 writeb(0, ioaddr
+ 0xF4);
704 tmpbyte
= readb(ioaddr
+ 0x4A);
706 switch(tmpbyte
& 0x30) {
708 /* In 100 MHz clocking, try and switch to 133 */
709 writeb(tmpbyte
|0x10, ioaddr
+ 0x4A);
712 /* On 133Mhz clocking */
715 /* On PCIx2 clocking */
718 /* Clocking is disabled */
719 /* 133 clock attempt to force it on */
720 writeb(tmpbyte
& ~0x20, ioaddr
+ 0x4A);
724 writeb( 0x72, ioaddr
+ 0xA1);
725 writew( 0x328A, ioaddr
+ 0xA2);
726 writel(0x62DD62DD, ioaddr
+ 0xA4);
727 writel(0x43924392, ioaddr
+ 0xA8);
728 writel(0x40094009, ioaddr
+ 0xAC);
729 writeb( 0x72, ioaddr
+ 0xE1);
730 writew( 0x328A, ioaddr
+ 0xE2);
731 writel(0x62DD62DD, ioaddr
+ 0xE4);
732 writel(0x43924392, ioaddr
+ 0xE8);
733 writel(0x40094009, ioaddr
+ 0xEC);
735 if (pdev_is_sata(dev
)) {
736 writel(0xFFFF0000, ioaddr
+ 0x108);
737 writel(0xFFFF0000, ioaddr
+ 0x188);
738 writel(0x00680000, ioaddr
+ 0x148);
739 writel(0x00680000, ioaddr
+ 0x1C8);
742 tmpbyte
= readb(ioaddr
+ 0x4A);
744 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
749 * init_chipset_siimage - set up an SI device
753 * Perform the initial PCI set up for this device. Attempt to switch
754 * to 133MHz clocking if the system isn't already set up to do it.
757 static unsigned int __devinit
init_chipset_siimage(struct pci_dev
*dev
, const char *name
)
763 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
765 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (class_rev
) ? 1 : 255);
767 pci_read_config_byte(dev
, 0x8A, &BA5_EN
);
768 if ((BA5_EN
& 0x01) || (pci_resource_start(dev
, 5))) {
769 if (setup_mmio_siimage(dev
, name
)) {
774 pci_write_config_byte(dev
, 0x80, 0x00);
775 pci_write_config_byte(dev
, 0x84, 0x00);
776 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
777 switch(tmpbyte
& 0x30) {
779 /* 133 clock attempt to force it on */
780 pci_write_config_byte(dev
, 0x8A, tmpbyte
|0x10);
782 /* if clocking is disabled */
783 /* 133 clock attempt to force it on */
784 pci_write_config_byte(dev
, 0x8A, tmpbyte
& ~0x20);
789 /* BIOS set PCI x2 clocking */
793 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
795 pci_write_config_byte(dev
, 0xA1, 0x72);
796 pci_write_config_word(dev
, 0xA2, 0x328A);
797 pci_write_config_dword(dev
, 0xA4, 0x62DD62DD);
798 pci_write_config_dword(dev
, 0xA8, 0x43924392);
799 pci_write_config_dword(dev
, 0xAC, 0x40094009);
800 pci_write_config_byte(dev
, 0xB1, 0x72);
801 pci_write_config_word(dev
, 0xB2, 0x328A);
802 pci_write_config_dword(dev
, 0xB4, 0x62DD62DD);
803 pci_write_config_dword(dev
, 0xB8, 0x43924392);
804 pci_write_config_dword(dev
, 0xBC, 0x40094009);
806 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
811 * init_mmio_iops_siimage - set up the iops for MMIO
812 * @hwif: interface to set up
814 * The basic setup here is fairly simple, we can use standard MMIO
815 * operations. However we do have to set the taskfile register offsets
816 * by hand as there isnt a standard defined layout for them this
819 * The hardware supports buffered taskfiles and also some rather nice
820 * extended PRD tables. For better SI3112 support use the libata driver
823 static void __devinit
init_mmio_iops_siimage(ide_hwif_t
*hwif
)
825 struct pci_dev
*dev
= hwif
->pci_dev
;
826 void *addr
= pci_get_drvdata(dev
);
827 u8 ch
= hwif
->channel
;
832 * Fill in the basic HWIF bits
835 default_hwif_mmiops(hwif
);
836 hwif
->hwif_data
= addr
;
839 * Now set up the hw. We have to do this ourselves as
840 * the MMIO layout isnt the same as the the standard port
844 memset(&hw
, 0, sizeof(hw_regs_t
));
846 base
= (unsigned long)addr
;
853 * The buffered task file doesn't have status/control
854 * so we can't currently use it sanely since we want to
857 hw
.io_ports
[IDE_DATA_OFFSET
] = base
;
858 hw
.io_ports
[IDE_ERROR_OFFSET
] = base
+ 1;
859 hw
.io_ports
[IDE_NSECTOR_OFFSET
] = base
+ 2;
860 hw
.io_ports
[IDE_SECTOR_OFFSET
] = base
+ 3;
861 hw
.io_ports
[IDE_LCYL_OFFSET
] = base
+ 4;
862 hw
.io_ports
[IDE_HCYL_OFFSET
] = base
+ 5;
863 hw
.io_ports
[IDE_SELECT_OFFSET
] = base
+ 6;
864 hw
.io_ports
[IDE_STATUS_OFFSET
] = base
+ 7;
865 hw
.io_ports
[IDE_CONTROL_OFFSET
] = base
+ 10;
867 hw
.io_ports
[IDE_IRQ_OFFSET
] = 0;
869 if (pdev_is_sata(dev
)) {
870 base
= (unsigned long)addr
;
873 hwif
->sata_scr
[SATA_STATUS_OFFSET
] = base
+ 0x104;
874 hwif
->sata_scr
[SATA_ERROR_OFFSET
] = base
+ 0x108;
875 hwif
->sata_scr
[SATA_CONTROL_OFFSET
] = base
+ 0x100;
876 hwif
->sata_misc
[SATA_MISC_OFFSET
] = base
+ 0x140;
877 hwif
->sata_misc
[SATA_PHY_OFFSET
] = base
+ 0x144;
878 hwif
->sata_misc
[SATA_IEN_OFFSET
] = base
+ 0x148;
881 hw
.irq
= hwif
->pci_dev
->irq
;
883 memcpy(&hwif
->hw
, &hw
, sizeof(hw
));
884 memcpy(hwif
->io_ports
, hwif
->hw
.io_ports
, sizeof(hwif
->hw
.io_ports
));
888 base
= (unsigned long) addr
;
890 hwif
->dma_base
= base
+ (ch
? 0x08 : 0x00);
894 static int is_dev_seagate_sata(ide_drive_t
*drive
)
896 const char *s
= &drive
->id
->model
[0];
902 len
= strnlen(s
, sizeof(drive
->id
->model
));
904 if ((len
> 4) && (!memcmp(s
, "ST", 2))) {
905 if ((!memcmp(s
+ len
- 2, "AS", 2)) ||
906 (!memcmp(s
+ len
- 3, "ASL", 3))) {
907 printk(KERN_INFO
"%s: applying pessimistic Seagate "
908 "errata fix\n", drive
->name
);
916 * siimage_fixup - post probe fixups
917 * @hwif: interface to fix up
919 * Called after drive probe we use this to decide whether the
920 * Seagate fixup must be applied. This used to be in init_iops but
921 * that can occur before we know what drives are present.
924 static void __devinit
siimage_fixup(ide_hwif_t
*hwif
)
926 /* Try and raise the rqsize */
927 if (!is_sata(hwif
) || !is_dev_seagate_sata(&hwif
->drives
[0]))
932 * init_iops_siimage - set up iops
933 * @hwif: interface to set up
935 * Do the basic setup for the SIIMAGE hardware interface
936 * and then do the MMIO setup if we can. This is the first
937 * look in we get for setting up the hwif so that we
938 * can get the iops right before using them.
941 static void __devinit
init_iops_siimage(ide_hwif_t
*hwif
)
943 struct pci_dev
*dev
= hwif
->pci_dev
;
946 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
949 hwif
->hwif_data
= NULL
;
951 /* Pessimal until we finish probing */
954 if (pci_get_drvdata(dev
) == NULL
)
956 init_mmio_iops_siimage(hwif
);
960 * ata66_siimage - check for 80 pin cable
961 * @hwif: interface to check
963 * Check for the presence of an ATA66 capable cable on the
967 static unsigned int __devinit
ata66_siimage(ide_hwif_t
*hwif
)
969 unsigned long addr
= siimage_selreg(hwif
, 0);
970 if (pci_get_drvdata(hwif
->pci_dev
) == NULL
) {
972 pci_read_config_byte(hwif
->pci_dev
, addr
, &ata66
);
973 return (ata66
& 0x01) ? 1 : 0;
976 return (hwif
->INB(addr
) & 0x01) ? 1 : 0;
980 * init_hwif_siimage - set up hwif structs
981 * @hwif: interface to set up
983 * We do the basic set up of the interface structure. The SIIMAGE
984 * requires several custom handlers so we override the default
985 * ide DMA handlers appropriately
988 static void __devinit
init_hwif_siimage(ide_hwif_t
*hwif
)
992 hwif
->resetproc
= &siimage_reset
;
993 hwif
->speedproc
= &siimage_tune_chipset
;
994 hwif
->tuneproc
= &siimage_tuneproc
;
995 hwif
->reset_poll
= &siimage_reset_poll
;
996 hwif
->pre_reset
= &siimage_pre_reset
;
999 static int first
= 1;
1001 hwif
->busproc
= &siimage_busproc
;
1004 printk(KERN_INFO
"siimage: For full SATA support you should use the libata sata_sil module.\n");
1008 if (!hwif
->dma_base
) {
1009 hwif
->drives
[0].autotune
= 1;
1010 hwif
->drives
[1].autotune
= 1;
1014 hwif
->ultra_mask
= 0x7f;
1015 hwif
->mwdma_mask
= 0x07;
1016 hwif
->swdma_mask
= 0x07;
1019 hwif
->atapi_dma
= 1;
1021 hwif
->ide_dma_check
= &siimage_config_drive_for_dma
;
1022 if (!(hwif
->udma_four
))
1023 hwif
->udma_four
= ata66_siimage(hwif
);
1026 hwif
->ide_dma_test_irq
= &siimage_mmio_ide_dma_test_irq
;
1028 hwif
->ide_dma_test_irq
= & siimage_io_ide_dma_test_irq
;
1032 * The BIOS often doesn't set up DMA on this controller
1033 * so we always do it.
1037 hwif
->drives
[0].autodma
= hwif
->autodma
;
1038 hwif
->drives
[1].autodma
= hwif
->autodma
;
1041 #define DECLARE_SII_DEV(name_str) \
1044 .init_chipset = init_chipset_siimage, \
1045 .init_iops = init_iops_siimage, \
1046 .init_hwif = init_hwif_siimage, \
1047 .fixup = siimage_fixup, \
1049 .autodma = AUTODMA, \
1050 .bootable = ON_BOARD, \
1053 static ide_pci_device_t siimage_chipsets
[] __devinitdata
= {
1054 /* 0 */ DECLARE_SII_DEV("SiI680"),
1055 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1056 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
1060 * siimage_init_one - pci layer discovery entry
1062 * @id: ident table entry
1064 * Called by the PCI code when it finds an SI680 or SI3112 controller.
1065 * We then use the IDE PCI generic helper to do most of the work.
1068 static int __devinit
siimage_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1070 return ide_setup_pci_device(dev
, &siimage_chipsets
[id
->driver_data
]);
1073 static struct pci_device_id siimage_pci_tbl
[] = {
1074 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_680
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1075 #ifdef CONFIG_BLK_DEV_IDE_SATA
1076 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_3112
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
1077 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_1210SA
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
1081 MODULE_DEVICE_TABLE(pci
, siimage_pci_tbl
);
1083 static struct pci_driver driver
= {
1085 .id_table
= siimage_pci_tbl
,
1086 .probe
= siimage_init_one
,
1089 static int __init
siimage_ide_init(void)
1091 return ide_pci_register_driver(&driver
);
1094 module_init(siimage_ide_init
);
1096 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1097 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1098 MODULE_LICENSE("GPL");