arch/mips/kernel/smp-mt.c

   1 /*
   2  *  This program is free software; you can distribute it and/or modify it
   3  *  under the terms of the GNU General Public License (Version 2) as
   4  *  published by the Free Software Foundation.
   5  *
   6  *  This program is distributed in the hope it will be useful, but WITHOUT
   7  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   8  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   9  *  for more details.
  10  *
  11  *  You should have received a copy of the GNU General Public License along
  12  *  with this program; if not, write to the Free Software Foundation, Inc.,
  13  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  14  *
  15  * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
  16  *    Elizabeth Clarke (beth@mips.com)
  17  *    Ralf Baechle (ralf@linux-mips.org)
  18  * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/sched.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/compiler.h>
  25 #include <linux/smp.h>
  26
  27 #include <asm/atomic.h>
  28 #include <asm/cacheflush.h>
  29 #include <asm/cpu.h>
  30 #include <asm/processor.h>
  31 #include <asm/system.h>
  32 #include <asm/hardirq.h>
  33 #include <asm/mmu_context.h>
  34 #include <asm/time.h>
  35 #include <asm/mipsregs.h>
  36 #include <asm/mipsmtregs.h>
  37 #include <asm/mips_mt.h>
  38
  39 #define MIPS_CPU_IPI_RESCHED_IRQ 0
  40 #define MIPS_CPU_IPI_CALL_IRQ 1
  41
  42 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
  43
  44 #if 0
  45 static void dump_mtregisters(int vpe, int tc)
  46 {
  47         printk("vpe %d tc %d\n", vpe, tc);
  48
  49         settc(tc);
  50
  51         printk("  c0 status  0x%lx\n", read_vpe_c0_status());
  52         printk("  vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol());
  53         printk("  vpeconf0    0x%lx\n", read_vpe_c0_vpeconf0());
  54         printk("  tcstatus 0x%lx\n", read_tc_c0_tcstatus());
  55         printk("  tcrestart 0x%lx\n", read_tc_c0_tcrestart());
  56         printk("  tcbind 0x%lx\n", read_tc_c0_tcbind());
  57         printk("  tchalt 0x%lx\n", read_tc_c0_tchalt());
  58 }
  59 #endif
  60
  61 static void ipi_resched_dispatch(void)
  62 {
  63         do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
  64 }
  65
  66 static void ipi_call_dispatch(void)
  67 {
  68         do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
  69 }
  70
  71 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
  72 {
  73         return IRQ_HANDLED;
  74 }
  75
  76 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
  77 {
  78         smp_call_function_interrupt();
  79
  80         return IRQ_HANDLED;
  81 }
  82
  83 static struct irqaction irq_resched = {
  84         .handler        = ipi_resched_interrupt,
  85         .flags          = IRQF_DISABLED|IRQF_PERCPU,
  86         .name           = "IPI_resched"
  87 };
  88
  89 static struct irqaction irq_call = {
  90         .handler        = ipi_call_interrupt,
  91         .flags          = IRQF_DISABLED|IRQF_PERCPU,
  92         .name           = "IPI_call"
  93 };
  94
  95 static void __init smp_copy_vpe_config(void)
  96 {
  97         write_vpe_c0_status(
  98                 (read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
  99
 100         /* set config to be the same as vpe0, particularly kseg0 coherency alg */
 101         write_vpe_c0_config( read_c0_config());
 102
 103         /* make sure there are no software interrupts pending */
 104         write_vpe_c0_cause(0);
 105
 106         /* Propagate Config7 */
 107         write_vpe_c0_config7(read_c0_config7());
 108
 109         write_vpe_c0_count(read_c0_count());
 110 }
 111
 112 static unsigned int __init smp_vpe_init(unsigned int tc, unsigned int mvpconf0,
 113         unsigned int ncpu)
 114 {
 115         if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
 116                 return ncpu;
 117
 118         /* Deactivate all but VPE 0 */
 119         if (tc != 0) {
 120                 unsigned long tmp = read_vpe_c0_vpeconf0();
 121
 122                 tmp &= ~VPECONF0_VPA;
 123
 124                 /* master VPE */
 125                 tmp |= VPECONF0_MVP;
 126                 write_vpe_c0_vpeconf0(tmp);
 127
 128                 /* Record this as available CPU */
 129                 cpu_set(tc, phys_cpu_present_map);
 130                 __cpu_number_map[tc]    = ++ncpu;
 131                 __cpu_logical_map[ncpu] = tc;
 132         }
 133
 134         /* Disable multi-threading with TC's */
 135         write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
 136
 137         if (tc != 0)
 138                 smp_copy_vpe_config();
 139
 140         return ncpu;
 141 }
 142
 143 static void __init smp_tc_init(unsigned int tc, unsigned int mvpconf0)
 144 {
 145         unsigned long tmp;
 146
 147         if (!tc)
 148                 return;
 149
 150         /* bind a TC to each VPE, May as well put all excess TC's
 151            on the last VPE */
 152         if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
 153                 write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
 154         else {
 155                 write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);
 156
 157                 /* and set XTC */
 158                 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
 159         }
 160
 161         tmp = read_tc_c0_tcstatus();
 162
 163         /* mark not allocated and not dynamically allocatable */
 164         tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
 165         tmp |= TCSTATUS_IXMT;           /* interrupt exempt */
 166         write_tc_c0_tcstatus(tmp);
 167
 168         write_tc_c0_tchalt(TCHALT_H);
 169 }
 170
 171 static void vsmp_send_ipi_single(int cpu, unsigned int action)
 172 {
 173         int i;
 174         unsigned long flags;
 175         int vpflags;
 176
 177         local_irq_save(flags);
 178
 179         vpflags = dvpe();       /* cant access the other CPU's registers whilst MVPE enabled */
 180
 181         switch (action) {
 182         case SMP_CALL_FUNCTION:
 183                 i = C_SW1;
 184                 break;
 185
 186         case SMP_RESCHEDULE_YOURSELF:
 187         default:
 188                 i = C_SW0;
 189                 break;
 190         }
 191
 192         /* 1:1 mapping of vpe and tc... */
 193         settc(cpu);
 194         write_vpe_c0_cause(read_vpe_c0_cause() | i);
 195         evpe(vpflags);
 196
 197         local_irq_restore(flags);
 198 }
 199
 200 static void vsmp_send_ipi_mask(cpumask_t mask, unsigned int action)
 201 {
 202         unsigned int i;
 203
 204         for_each_cpu_mask(i, mask)
 205                 vsmp_send_ipi_single(i, action);
 206 }
 207
 208 static void __cpuinit vsmp_init_secondary(void)
 209 {
 210         /* Enable per-cpu interrupts */
 211
 212         /* This is Malta specific: IPI,performance and timer inetrrupts */
 213         write_c0_status((read_c0_status() & ~ST0_IM ) |
 214                         (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7));
 215 }
 216
 217 static void __cpuinit vsmp_smp_finish(void)
 218 {
 219         write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
 220
 221 #ifdef CONFIG_MIPS_MT_FPAFF
 222         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 223         if (cpu_has_fpu)
 224                 cpu_set(smp_processor_id(), mt_fpu_cpumask);
 225 #endif /* CONFIG_MIPS_MT_FPAFF */
 226
 227         local_irq_enable();
 228 }
 229
 230 static void vsmp_cpus_done(void)
 231 {
 232 }
 233
 234 /*
 235  * Setup the PC, SP, and GP of a secondary processor and start it
 236  * running!
 237  * smp_bootstrap is the place to resume from
 238  * __KSTK_TOS(idle) is apparently the stack pointer
 239  * (unsigned long)idle->thread_info the gp
 240  * assumes a 1:1 mapping of TC => VPE
 241  */
 242 static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle)
 243 {
 244         struct thread_info *gp = task_thread_info(idle);
 245         dvpe();
 246         set_c0_mvpcontrol(MVPCONTROL_VPC);
 247
 248         settc(cpu);
 249
 250         /* restart */
 251         write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
 252
 253         /* enable the tc this vpe/cpu will be running */
 254         write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);
 255
 256         write_tc_c0_tchalt(0);
 257
 258         /* enable the VPE */
 259         write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
 260
 261         /* stack pointer */
 262         write_tc_gpr_sp( __KSTK_TOS(idle));
 263
 264         /* global pointer */
 265         write_tc_gpr_gp((unsigned long)gp);
 266
 267         flush_icache_range((unsigned long)gp,
 268                            (unsigned long)(gp + sizeof(struct thread_info)));
 269
 270         /* finally out of configuration and into chaos */
 271         clear_c0_mvpcontrol(MVPCONTROL_VPC);
 272
 273         evpe(EVPE_ENABLE);
 274 }
 275
 276 /*
 277  * Common setup before any secondaries are started
 278  * Make sure all CPU's are in a sensible state before we boot any of the
 279  * secondarys
 280  */
 281 static void __init vsmp_smp_setup(void)
 282 {
 283         unsigned int mvpconf0, ntc, tc, ncpu = 0;
 284         unsigned int nvpe;
 285
 286 #ifdef CONFIG_MIPS_MT_FPAFF
 287         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 288         if (cpu_has_fpu)
 289                 cpu_set(0, mt_fpu_cpumask);
 290 #endif /* CONFIG_MIPS_MT_FPAFF */
 291         if (!cpu_has_mipsmt)
 292                 return;
 293
 294         /* disable MT so we can configure */
 295         dvpe();
 296         dmt();
 297
 298         /* Put MVPE's into 'configuration state' */
 299         set_c0_mvpcontrol(MVPCONTROL_VPC);
 300
 301         mvpconf0 = read_c0_mvpconf0();
 302         ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
 303
 304         nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
 305         smp_num_siblings = nvpe;
 306
 307         /* we'll always have more TC's than VPE's, so loop setting everything
 308            to a sensible state */
 309         for (tc = 0; tc <= ntc; tc++) {
 310                 settc(tc);
 311
 312                 smp_tc_init(tc, mvpconf0);
 313                 ncpu = smp_vpe_init(tc, mvpconf0, ncpu);
 314         }
 315
 316         /* Release config state */
 317         clear_c0_mvpcontrol(MVPCONTROL_VPC);
 318
 319         /* We'll wait until starting the secondaries before starting MVPE */
 320
 321         printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
 322 }
 323
 324 static void __init vsmp_prepare_cpus(unsigned int max_cpus)
 325 {
 326         mips_mt_set_cpuoptions();
 327
 328         /* set up ipi interrupts */
 329         if (cpu_has_vint) {
 330                 set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
 331                 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
 332         }
 333
 334         cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
 335         cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
 336
 337         setup_irq(cpu_ipi_resched_irq, &irq_resched);
 338         setup_irq(cpu_ipi_call_irq, &irq_call);
 339
 340         set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
 341         set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
 342 }
 343
 344 struct plat_smp_ops vsmp_smp_ops = {
 345         .send_ipi_single        = vsmp_send_ipi_single,
 346         .send_ipi_mask          = vsmp_send_ipi_mask,
 347         .init_secondary         = vsmp_init_secondary,
 348         .smp_finish             = vsmp_smp_finish,
 349         .cpus_done              = vsmp_cpus_done,
 350         .boot_secondary         = vsmp_boot_secondary,
 351         .smp_setup              = vsmp_smp_setup,
 352         .prepare_cpus           = vsmp_prepare_cpus,
 353 };