1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
26 #include <mach_apic.h>
29 #include <asm/pgtable.h>
30 #include <asm/processor.h>
32 #include <asm/atomic.h>
33 #include <asm/proto.h>
34 #include <asm/sections.h>
35 #include <asm/setup.h>
36 #include <asm/genapic.h>
40 /* We need valid kernel segments for data and code in long mode too
41 * IRET will check the segment types kkeil 2000/10/28
42 * Also sysret mandates a special GDT layout
44 /* The TLS descriptors are currently at a different place compared to i386.
45 Hopefully nobody expects them at a fixed place (Wine?) */
46 DEFINE_PER_CPU(struct gdt_page
, gdt_page
) = { .gdt
= {
47 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
48 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
49 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
50 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
51 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
52 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
54 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
56 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
58 /* Current gdt points %fs at the "master" per-cpu area: after this,
59 * it's on the real one. */
60 void switch_to_new_gdt(void)
62 struct desc_ptr gdt_descr
;
64 gdt_descr
.address
= (long)get_cpu_gdt_table(smp_processor_id());
65 gdt_descr
.size
= GDT_SIZE
- 1;
69 struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
71 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
76 static struct cpu_dev __cpuinitdata default_cpu
= {
77 .c_init
= default_init
,
78 .c_vendor
= "Unknown",
80 static struct cpu_dev
*this_cpu __cpuinitdata
= &default_cpu
;
82 int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
86 if (c
->extended_cpuid_level
< 0x80000004)
89 v
= (unsigned int *) c
->x86_model_id
;
90 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
91 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
92 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
93 c
->x86_model_id
[48] = 0;
98 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
100 unsigned int n
, dummy
, ebx
, ecx
, edx
;
102 n
= c
->extended_cpuid_level
;
104 if (n
>= 0x80000005) {
105 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
106 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), "
107 "D cache %dK (%d bytes/line)\n",
108 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
109 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
110 /* On K8 L1 TLB is inclusive, so don't count it */
114 if (n
>= 0x80000006) {
115 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
116 ecx
= cpuid_ecx(0x80000006);
117 c
->x86_cache_size
= ecx
>> 16;
118 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
120 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
121 c
->x86_cache_size
, ecx
& 0xFF);
125 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
128 u32 eax
, ebx
, ecx
, edx
;
129 int index_msb
, core_bits
;
131 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
134 if (!cpu_has(c
, X86_FEATURE_HT
))
136 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
139 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
141 if (smp_num_siblings
== 1) {
142 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
143 } else if (smp_num_siblings
> 1) {
145 if (smp_num_siblings
> NR_CPUS
) {
146 printk(KERN_WARNING
"CPU: Unsupported number of "
147 "siblings %d", smp_num_siblings
);
148 smp_num_siblings
= 1;
152 index_msb
= get_count_order(smp_num_siblings
);
153 c
->phys_proc_id
= phys_pkg_id(index_msb
);
155 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
157 index_msb
= get_count_order(smp_num_siblings
);
159 core_bits
= get_count_order(c
->x86_max_cores
);
161 c
->cpu_core_id
= phys_pkg_id(index_msb
) &
162 ((1 << core_bits
) - 1);
165 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
166 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
168 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
175 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
177 char *v
= c
->x86_vendor_id
;
181 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
183 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
184 (cpu_devs
[i
]->c_ident
[1] &&
185 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
187 this_cpu
= cpu_devs
[i
];
194 printk(KERN_ERR
"CPU: Vendor unknown, using generic init.\n");
195 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
197 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
200 static void __init
early_cpu_support_print(void)
203 struct cpu_dev
*cpu_devx
;
205 printk("KERNEL supported cpus:\n");
206 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
207 cpu_devx
= cpu_devs
[i
];
210 for (j
= 0; j
< 2; j
++) {
211 if (!cpu_devx
->c_ident
[j
])
213 printk(" %s %s\n", cpu_devx
->c_vendor
,
214 cpu_devx
->c_ident
[j
]);
220 * The NOPL instruction is supposed to exist on all CPUs with
221 * family >= 6, unfortunately, that's not true in practice because
222 * of early VIA chips and (more importantly) broken virtualizers that
223 * are not easy to detect. Hence, probe for it based on first
226 * Note: no 64-bit chip is known to lack these, but put the code here
227 * for consistency with 32 bits, and to make it utterly trivial to
228 * diagnose the problem should it ever surface.
230 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
232 const u32 nopl_signature
= 0x888c53b1; /* Random number */
233 u32 has_nopl
= nopl_signature
;
235 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
238 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
240 " .section .fixup,\"ax\"\n"
247 if (has_nopl
== nopl_signature
)
248 set_cpu_cap(c
, X86_FEATURE_NOPL
);
252 static void __cpuinit
early_identify_cpu(struct cpuinfo_x86
*c
);
254 void __init
early_cpu_init(void)
256 struct cpu_vendor_dev
*cvdev
;
258 for (cvdev
= __x86cpuvendor_start
;
259 cvdev
< __x86cpuvendor_end
;
261 cpu_devs
[cvdev
->vendor
] = cvdev
->cpu_dev
;
262 early_cpu_support_print();
263 early_identify_cpu(&boot_cpu_data
);
266 /* Do some early cpuid on the boot CPU to get some parameter that are
267 needed before check_bugs. Everything advanced is in identify_cpu
269 static void __cpuinit
early_identify_cpu(struct cpuinfo_x86
*c
)
273 c
->loops_per_jiffy
= loops_per_jiffy
;
274 c
->x86_cache_size
= -1;
275 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
276 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
277 c
->x86_vendor_id
[0] = '\0'; /* Unset */
278 c
->x86_model_id
[0] = '\0'; /* Unset */
279 c
->x86_clflush_size
= 64;
280 c
->x86_cache_alignment
= c
->x86_clflush_size
;
281 c
->x86_max_cores
= 1;
282 c
->x86_coreid_bits
= 0;
283 c
->extended_cpuid_level
= 0;
284 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
286 /* Get vendor name */
287 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
288 (unsigned int *)&c
->x86_vendor_id
[0],
289 (unsigned int *)&c
->x86_vendor_id
[8],
290 (unsigned int *)&c
->x86_vendor_id
[4]);
294 /* Initialize the standard set of capabilities */
295 /* Note that the vendor-specific code below might override */
297 /* Intel-defined flags: level 0x00000001 */
298 if (c
->cpuid_level
>= 0x00000001) {
300 cpuid(0x00000001, &tfms
, &misc
, &c
->x86_capability
[4],
301 &c
->x86_capability
[0]);
302 c
->x86
= (tfms
>> 8) & 0xf;
303 c
->x86_model
= (tfms
>> 4) & 0xf;
304 c
->x86_mask
= tfms
& 0xf;
306 c
->x86
+= (tfms
>> 20) & 0xff;
308 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
309 if (test_cpu_cap(c
, X86_FEATURE_CLFLSH
))
310 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
312 /* Have CPUID level 0 only - unheard of */
316 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xff;
318 c
->phys_proc_id
= c
->initial_apicid
;
320 /* AMD-defined flags: level 0x80000001 */
321 xlvl
= cpuid_eax(0x80000000);
322 c
->extended_cpuid_level
= xlvl
;
323 if ((xlvl
& 0xffff0000) == 0x80000000) {
324 if (xlvl
>= 0x80000001) {
325 c
->x86_capability
[1] = cpuid_edx(0x80000001);
326 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
328 if (xlvl
>= 0x80000004)
329 get_model_name(c
); /* Default name */
332 /* Transmeta-defined flags: level 0x80860001 */
333 xlvl
= cpuid_eax(0x80860000);
334 if ((xlvl
& 0xffff0000) == 0x80860000) {
335 /* Don't set x86_cpuid_level here for now to not confuse. */
336 if (xlvl
>= 0x80860001)
337 c
->x86_capability
[2] = cpuid_edx(0x80860001);
340 if (c
->extended_cpuid_level
>= 0x80000007)
341 c
->x86_power
= cpuid_edx(0x80000007);
343 if (c
->extended_cpuid_level
>= 0x80000008) {
344 u32 eax
= cpuid_eax(0x80000008);
346 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
347 c
->x86_phys_bits
= eax
& 0xff;
352 if (c
->x86_vendor
!= X86_VENDOR_UNKNOWN
&&
353 cpu_devs
[c
->x86_vendor
]->c_early_init
)
354 cpu_devs
[c
->x86_vendor
]->c_early_init(c
);
356 validate_pat_support(c
);
360 * This does the hard work of actually picking apart the CPU stuff...
362 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
366 early_identify_cpu(c
);
368 init_scattered_cpuid_features(c
);
370 c
->apicid
= phys_pkg_id(0);
373 * Vendor-specific initialization. In this section we
374 * canonicalize the feature flags, meaning if there are
375 * features a certain CPU supports which CPUID doesn't
376 * tell us, CPUID claiming incorrect flags, or other bugs,
377 * we handle them here.
379 * At the end of this section, c->x86_capability better
380 * indicate the features this CPU genuinely supports!
382 if (this_cpu
->c_init
)
388 * On SMP, boot_cpu_data holds the common feature set between
389 * all CPUs; so make sure that we indicate which features are
390 * common between the CPUs. The first time this routine gets
391 * executed, c == &boot_cpu_data.
393 if (c
!= &boot_cpu_data
) {
394 /* AND the already accumulated flags with these */
395 for (i
= 0; i
< NCAPINTS
; i
++)
396 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
399 /* Clear all flags overriden by options */
400 for (i
= 0; i
< NCAPINTS
; i
++)
401 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
403 #ifdef CONFIG_X86_MCE
406 select_idle_routine(c
);
409 numa_add_cpu(smp_processor_id());
414 void __cpuinit
identify_boot_cpu(void)
416 identify_cpu(&boot_cpu_data
);
419 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
421 BUG_ON(c
== &boot_cpu_data
);
426 static __init
int setup_noclflush(char *arg
)
428 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
431 __setup("noclflush", setup_noclflush
);
438 static struct msr_range msr_range_array
[] __cpuinitdata
= {
439 { 0x00000000, 0x00000418},
440 { 0xc0000000, 0xc000040b},
441 { 0xc0010000, 0xc0010142},
442 { 0xc0011000, 0xc001103b},
445 static void __cpuinit
print_cpu_msr(void)
450 unsigned index_min
, index_max
;
452 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
453 index_min
= msr_range_array
[i
].min
;
454 index_max
= msr_range_array
[i
].max
;
455 for (index
= index_min
; index
< index_max
; index
++) {
456 if (rdmsrl_amd_safe(index
, &val
))
458 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
463 static int show_msr __cpuinitdata
;
464 static __init
int setup_show_msr(char *arg
)
468 get_option(&arg
, &num
);
474 __setup("show_msr=", setup_show_msr
);
476 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
478 if (c
->x86_model_id
[0])
479 printk(KERN_CONT
"%s", c
->x86_model_id
);
481 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
482 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
484 printk(KERN_CONT
"\n");
487 if (c
->cpu_index
< show_msr
)
495 static __init
int setup_disablecpuid(char *arg
)
498 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
499 setup_clear_cpu_cap(bit
);
504 __setup("clearcpuid=", setup_disablecpuid
);
506 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
508 struct x8664_pda
**_cpu_pda __read_mostly
;
509 EXPORT_SYMBOL(_cpu_pda
);
511 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
513 char boot_cpu_stack
[IRQSTACKSIZE
] __page_aligned_bss
;
515 unsigned long __supported_pte_mask __read_mostly
= ~0UL;
516 EXPORT_SYMBOL_GPL(__supported_pte_mask
);
518 static int do_not_nx __cpuinitdata
;
521 Control non executable mappings for 64bit processes.
526 static int __init
nonx_setup(char *str
)
530 if (!strncmp(str
, "on", 2)) {
531 __supported_pte_mask
|= _PAGE_NX
;
533 } else if (!strncmp(str
, "off", 3)) {
535 __supported_pte_mask
&= ~_PAGE_NX
;
539 early_param("noexec", nonx_setup
);
541 int force_personality32
;
544 Control non executable heap for 32bit processes.
545 To control the stack too use noexec=off
547 on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
548 off PROT_READ implies PROT_EXEC
550 static int __init
nonx32_setup(char *str
)
552 if (!strcmp(str
, "on"))
553 force_personality32
&= ~READ_IMPLIES_EXEC
;
554 else if (!strcmp(str
, "off"))
555 force_personality32
|= READ_IMPLIES_EXEC
;
558 __setup("noexec32=", nonx32_setup
);
560 void pda_init(int cpu
)
562 struct x8664_pda
*pda
= cpu_pda(cpu
);
564 /* Setup up data that may be needed in __get_free_pages early */
567 /* Memory clobbers used to order PDA accessed */
569 wrmsrl(MSR_GS_BASE
, pda
);
572 pda
->cpunumber
= cpu
;
574 pda
->kernelstack
= (unsigned long)stack_thread_info() -
575 PDA_STACKOFFSET
+ THREAD_SIZE
;
576 pda
->active_mm
= &init_mm
;
580 /* others are initialized in smpboot.c */
581 pda
->pcurrent
= &init_task
;
582 pda
->irqstackptr
= boot_cpu_stack
;
583 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
585 if (!pda
->irqstackptr
) {
586 pda
->irqstackptr
= (char *)
587 __get_free_pages(GFP_ATOMIC
, IRQSTACK_ORDER
);
588 if (!pda
->irqstackptr
)
589 panic("cannot allocate irqstack for cpu %d",
591 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
594 if (pda
->nodenumber
== 0 && cpu_to_node(cpu
) != NUMA_NO_NODE
)
595 pda
->nodenumber
= cpu_to_node(cpu
);
599 char boot_exception_stacks
[(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+
600 DEBUG_STKSZ
] __page_aligned_bss
;
602 extern asmlinkage
void ignore_sysret(void);
604 /* May not be marked __init: used by software suspend */
605 void syscall_init(void)
608 * LSTAR and STAR live in a bit strange symbiosis.
609 * They both write to the same internal register. STAR allows to
610 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
612 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
613 wrmsrl(MSR_LSTAR
, system_call
);
614 wrmsrl(MSR_CSTAR
, ignore_sysret
);
616 #ifdef CONFIG_IA32_EMULATION
617 syscall32_cpu_init();
620 /* Flags to clear on syscall */
621 wrmsrl(MSR_SYSCALL_MASK
,
622 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
625 void __cpuinit
check_efer(void)
629 rdmsrl(MSR_EFER
, efer
);
630 if (!(efer
& EFER_NX
) || do_not_nx
)
631 __supported_pte_mask
&= ~_PAGE_NX
;
634 unsigned long kernel_eflags
;
637 * Copies of the original ist values from the tss are only accessed during
638 * debugging, no special alignment required.
640 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
643 * cpu_init() initializes state that is per-CPU. Some data is already
644 * initialized (naturally) in the bootstrap process, such as the GDT
645 * and IDT. We reload them nevertheless, this function acts as a
646 * 'CPU state barrier', nothing should get across.
647 * A lot of state is already set up in PDA init.
649 void __cpuinit
cpu_init(void)
651 int cpu
= stack_smp_processor_id();
652 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
653 struct orig_ist
*orig_ist
= &per_cpu(orig_ist
, cpu
);
655 char *estacks
= NULL
;
656 struct task_struct
*me
;
659 /* CPU 0 is initialised in head64.c */
663 estacks
= boot_exception_stacks
;
667 if (cpu_test_and_set(cpu
, cpu_initialized
))
668 panic("CPU#%d already initialized!\n", cpu
);
670 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
672 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
675 * Initialize the per-CPU GDT with the boot GDT,
676 * and set up the GDT descriptor:
680 load_idt((const struct desc_ptr
*)&idt_descr
);
682 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
685 wrmsrl(MSR_FS_BASE
, 0);
686 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
692 * set up and load the per-CPU TSS
694 if (!orig_ist
->ist
[0]) {
695 static const unsigned int order
[N_EXCEPTION_STACKS
] = {
696 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STACK_ORDER
,
697 [DEBUG_STACK
- 1] = DEBUG_STACK_ORDER
699 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
701 estacks
= (char *)__get_free_pages(GFP_ATOMIC
, order
[v
]);
703 panic("Cannot allocate exception "
704 "stack %ld %d\n", v
, cpu
);
706 estacks
+= PAGE_SIZE
<< order
[v
];
707 orig_ist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
708 (unsigned long)estacks
;
712 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
714 * <= is required because the CPU will access up to
715 * 8 bits beyond the end of the IO permission bitmap.
717 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
718 t
->io_bitmap
[i
] = ~0UL;
720 atomic_inc(&init_mm
.mm_count
);
721 me
->active_mm
= &init_mm
;
724 enter_lazy_tlb(&init_mm
, me
);
726 load_sp0(t
, ¤t
->thread
);
727 set_tss_desc(cpu
, t
);
729 load_LDT(&init_mm
.context
);
733 * If the kgdb is connected no debug regs should be altered. This
734 * is only applicable when KGDB and a KGDB I/O module are built
735 * into the kernel and you are using early debugging with
736 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
738 if (kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
)
739 arch_kgdb_ops
.correct_hw_break();
743 * Clear all 6 debug registers:
746 set_debugreg(0UL, 0);
747 set_debugreg(0UL, 1);
748 set_debugreg(0UL, 2);
749 set_debugreg(0UL, 3);
750 set_debugreg(0UL, 6);
751 set_debugreg(0UL, 7);
753 /* If the kgdb is connected no debug regs should be altered. */
759 raw_local_save_flags(kernel_eflags
);