?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
R4600 has 32 FPRs.
[linux-2.6/kvm.git] / arch / mips / kernel / cpu-probe.c
blob5d71eca415759c1eb69910b07cfaeadfb09d725a
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 2003, 2004 Maciej W. Rozycki
6 * Copyright (C) 1994 - 2003 Ralf Baechle
7 * Copyright (C) 2001, 2004 MIPS Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/ptrace.h>
18 #include <linux/stddef.h>
19
20 #include <asm/cpu.h>
21 #include <asm/fpu.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
24
25 /*
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
27 * the implementation of the "wait" feature differs between CPU families. This
28 * points to the function that implements CPU specific wait.
29 * The wait instruction stops the pipeline and reduces the power consumption of
30 * the CPU very much.
31 */
32 void (*cpu_wait)(void) = NULL;
33
34 static void r3081_wait(void)
35 {
36 unsigned long cfg = read_c0_conf();
37 write_c0_conf(cfg | R30XX_CONF_HALT);
38 }
39
40 static void r39xx_wait(void)
41 {
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | TX39_CONF_HALT);
44 }
45
46 static void r4k_wait(void)
47 {
48 __asm__(".set\tmips3\n\t"
49 "wait\n\t"
50 ".set\tmips0");
51 }
52
53 /* The Au1xxx wait is available only if using 32khz counter or
54 * external timer source, but specifically not CP0 Counter. */
55 int allow_au1k_wait;
56
57 static void au1k_wait(void)
58 {
59 /* using the wait instruction makes CP0 counter unusable */
60 __asm__(".set mips3\n\t"
61 "cache 0x14, 0(%0)\n\t"
62 "cache 0x14, 32(%0)\n\t"
63 "sync\n\t"
64 "nop\n\t"
65 "wait\n\t"
66 "nop\n\t"
67 "nop\n\t"
68 "nop\n\t"
69 "nop\n\t"
70 ".set mips0\n\t"
71 : : "r" (au1k_wait));
72 }
73
74 static int __initdata nowait = 0;
75
76 int __init wait_disable(char *s)
77 {
78 nowait = 1;
79
80 return 1;
81 }
82
83 __setup("nowait", wait_disable);
84
85 static inline void check_wait(void)
86 {
87 struct cpuinfo_mips *c = &current_cpu_data;
88
89 printk("Checking for 'wait' instruction... ");
90 if (nowait) {
91 printk (" disabled.\n");
92 return;
93 }
94
95 switch (c->cputype) {
96 case CPU_R3081:
97 case CPU_R3081E:
98 cpu_wait = r3081_wait;
99 printk(" available.\n");
100 break;
101 case CPU_TX3927:
102 cpu_wait = r39xx_wait;
103 printk(" available.\n");
104 break;
105 case CPU_R4200:
106 /* case CPU_R4300: */
107 case CPU_R4600:
108 case CPU_R4640:
109 case CPU_R4650:
110 case CPU_R4700:
111 case CPU_R5000:
112 case CPU_NEVADA:
113 case CPU_RM7000:
114 case CPU_RM9000:
115 case CPU_TX49XX:
116 case CPU_4KC:
117 case CPU_4KEC:
118 case CPU_4KSC:
119 case CPU_5KC:
120 /* case CPU_20KC:*/
121 case CPU_24K:
122 case CPU_25KF:
123 case CPU_34K:
124 case CPU_PR4450:
125 cpu_wait = r4k_wait;
126 printk(" available.\n");
127 break;
128 case CPU_AU1000:
129 case CPU_AU1100:
130 case CPU_AU1500:
131 case CPU_AU1550:
132 case CPU_AU1200:
133 if (allow_au1k_wait) {
134 cpu_wait = au1k_wait;
135 printk(" available.\n");
136 } else
137 printk(" unavailable.\n");
138 break;
139 default:
140 printk(" unavailable.\n");
141 break;
142 }
143 }
144
145 void __init check_bugs32(void)
146 {
147 check_wait();
148 }
149
150 /*
151 * Probe whether cpu has config register by trying to play with
152 * alternate cache bit and see whether it matters.
153 * It's used by cpu_probe to distinguish between R3000A and R3081.
154 */
155 static inline int cpu_has_confreg(void)
156 {
157 #ifdef CONFIG_CPU_R3000
158 extern unsigned long r3k_cache_size(unsigned long);
159 unsigned long size1, size2;
160 unsigned long cfg = read_c0_conf();
161
162 size1 = r3k_cache_size(ST0_ISC);
163 write_c0_conf(cfg ^ R30XX_CONF_AC);
164 size2 = r3k_cache_size(ST0_ISC);
165 write_c0_conf(cfg);
166 return size1 != size2;
167 #else
168 return 0;
169 #endif
170 }
171
172 /*
173 * Get the FPU Implementation/Revision.
174 */
175 static inline unsigned long cpu_get_fpu_id(void)
176 {
177 unsigned long tmp, fpu_id;
178
179 tmp = read_c0_status();
180 __enable_fpu();
181 fpu_id = read_32bit_cp1_register(CP1_REVISION);
182 write_c0_status(tmp);
183 return fpu_id;
184 }
185
186 /*
187 * Check the CPU has an FPU the official way.
188 */
189 static inline int __cpu_has_fpu(void)
190 {
191 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
192 }
193
194 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
195 | MIPS_CPU_COUNTER)
196
197 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
198 {
199 switch (c->processor_id & 0xff00) {
200 case PRID_IMP_R2000:
201 c->cputype = CPU_R2000;
202 c->isa_level = MIPS_CPU_ISA_I;
203 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
204 if (__cpu_has_fpu())
205 c->options |= MIPS_CPU_FPU;
206 c->tlbsize = 64;
207 break;
208 case PRID_IMP_R3000:
209 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
210 if (cpu_has_confreg())
211 c->cputype = CPU_R3081E;
212 else
213 c->cputype = CPU_R3000A;
214 else
215 c->cputype = CPU_R3000;
216 c->isa_level = MIPS_CPU_ISA_I;
217 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
218 if (__cpu_has_fpu())
219 c->options |= MIPS_CPU_FPU;
220 c->tlbsize = 64;
221 break;
222 case PRID_IMP_R4000:
223 if (read_c0_config() & CONF_SC) {
224 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
225 c->cputype = CPU_R4400PC;
226 else
227 c->cputype = CPU_R4000PC;
228 } else {
229 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
230 c->cputype = CPU_R4400SC;
231 else
232 c->cputype = CPU_R4000SC;
233 }
234
235 c->isa_level = MIPS_CPU_ISA_III;
236 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
237 MIPS_CPU_WATCH | MIPS_CPU_VCE |
238 MIPS_CPU_LLSC;
239 c->tlbsize = 48;
240 break;
241 case PRID_IMP_VR41XX:
242 switch (c->processor_id & 0xf0) {
243 case PRID_REV_VR4111:
244 c->cputype = CPU_VR4111;
245 break;
246 case PRID_REV_VR4121:
247 c->cputype = CPU_VR4121;
248 break;
249 case PRID_REV_VR4122:
250 if ((c->processor_id & 0xf) < 0x3)
251 c->cputype = CPU_VR4122;
252 else
253 c->cputype = CPU_VR4181A;
254 break;
255 case PRID_REV_VR4130:
256 if ((c->processor_id & 0xf) < 0x4)
257 c->cputype = CPU_VR4131;
258 else
259 c->cputype = CPU_VR4133;
260 break;
261 default:
262 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
263 c->cputype = CPU_VR41XX;
264 break;
265 }
266 c->isa_level = MIPS_CPU_ISA_III;
267 c->options = R4K_OPTS;
268 c->tlbsize = 32;
269 break;
270 case PRID_IMP_R4300:
271 c->cputype = CPU_R4300;
272 c->isa_level = MIPS_CPU_ISA_III;
273 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
274 MIPS_CPU_LLSC;
275 c->tlbsize = 32;
276 break;
277 case PRID_IMP_R4600:
278 c->cputype = CPU_R4600;
279 c->isa_level = MIPS_CPU_ISA_III;
280 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
281 MIPS_CPU_LLSC;
282 c->tlbsize = 48;
283 break;
284 #if 0
285 case PRID_IMP_R4650:
286 /*
287 * This processor doesn't have an MMU, so it's not
288 * "real easy" to run Linux on it. It is left purely
289 * for documentation. Commented out because it shares
290 * it's c0_prid id number with the TX3900.
291 */
292 c->cputype = CPU_R4650;
293 c->isa_level = MIPS_CPU_ISA_III;
294 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
295 c->tlbsize = 48;
296 break;
297 #endif
298 case PRID_IMP_TX39:
299 c->isa_level = MIPS_CPU_ISA_I;
300 c->options = MIPS_CPU_TLB;
301
302 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
303 c->cputype = CPU_TX3927;
304 c->tlbsize = 64;
305 } else {
306 switch (c->processor_id & 0xff) {
307 case PRID_REV_TX3912:
308 c->cputype = CPU_TX3912;
309 c->tlbsize = 32;
310 break;
311 case PRID_REV_TX3922:
312 c->cputype = CPU_TX3922;
313 c->tlbsize = 64;
314 break;
315 default:
316 c->cputype = CPU_UNKNOWN;
317 break;
318 }
319 }
320 break;
321 case PRID_IMP_R4700:
322 c->cputype = CPU_R4700;
323 c->isa_level = MIPS_CPU_ISA_III;
324 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
325 MIPS_CPU_LLSC;
326 c->tlbsize = 48;
327 break;
328 case PRID_IMP_TX49:
329 c->cputype = CPU_TX49XX;
330 c->isa_level = MIPS_CPU_ISA_III;
331 c->options = R4K_OPTS | MIPS_CPU_LLSC;
332 if (!(c->processor_id & 0x08))
333 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
334 c->tlbsize = 48;
335 break;
336 case PRID_IMP_R5000:
337 c->cputype = CPU_R5000;
338 c->isa_level = MIPS_CPU_ISA_IV;
339 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
340 MIPS_CPU_LLSC;
341 c->tlbsize = 48;
342 break;
343 case PRID_IMP_R5432:
344 c->cputype = CPU_R5432;
345 c->isa_level = MIPS_CPU_ISA_IV;
346 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
347 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
348 c->tlbsize = 48;
349 break;
350 case PRID_IMP_R5500:
351 c->cputype = CPU_R5500;
352 c->isa_level = MIPS_CPU_ISA_IV;
353 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
354 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
355 c->tlbsize = 48;
356 break;
357 case PRID_IMP_NEVADA:
358 c->cputype = CPU_NEVADA;
359 c->isa_level = MIPS_CPU_ISA_IV;
360 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
361 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
362 c->tlbsize = 48;
363 break;
364 case PRID_IMP_R6000:
365 c->cputype = CPU_R6000;
366 c->isa_level = MIPS_CPU_ISA_II;
367 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
368 MIPS_CPU_LLSC;
369 c->tlbsize = 32;
370 break;
371 case PRID_IMP_R6000A:
372 c->cputype = CPU_R6000A;
373 c->isa_level = MIPS_CPU_ISA_II;
374 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
375 MIPS_CPU_LLSC;
376 c->tlbsize = 32;
377 break;
378 case PRID_IMP_RM7000:
379 c->cputype = CPU_RM7000;
380 c->isa_level = MIPS_CPU_ISA_IV;
381 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
382 MIPS_CPU_LLSC;
383 /*
384 * Undocumented RM7000: Bit 29 in the info register of
385 * the RM7000 v2.0 indicates if the TLB has 48 or 64
386 * entries.
387 *
388 * 29 1 => 64 entry JTLB
389 * 0 => 48 entry JTLB
390 */
391 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
392 break;
393 case PRID_IMP_RM9000:
394 c->cputype = CPU_RM9000;
395 c->isa_level = MIPS_CPU_ISA_IV;
396 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
397 MIPS_CPU_LLSC;
398 /*
399 * Bit 29 in the info register of the RM9000
400 * indicates if the TLB has 48 or 64 entries.
401 *
402 * 29 1 => 64 entry JTLB
403 * 0 => 48 entry JTLB
404 */
405 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
406 break;
407 case PRID_IMP_R8000:
408 c->cputype = CPU_R8000;
409 c->isa_level = MIPS_CPU_ISA_IV;
410 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
411 MIPS_CPU_FPU | MIPS_CPU_32FPR |
412 MIPS_CPU_LLSC;
413 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
414 break;
415 case PRID_IMP_R10000:
416 c->cputype = CPU_R10000;
417 c->isa_level = MIPS_CPU_ISA_IV;
418 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
419 MIPS_CPU_FPU | MIPS_CPU_32FPR |
420 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
421 MIPS_CPU_LLSC;
422 c->tlbsize = 64;
423 break;
424 case PRID_IMP_R12000:
425 c->cputype = CPU_R12000;
426 c->isa_level = MIPS_CPU_ISA_IV;
427 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
428 MIPS_CPU_FPU | MIPS_CPU_32FPR |
429 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
430 MIPS_CPU_LLSC;
431 c->tlbsize = 64;
432 break;
433 }
434 }
435
436 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
437 {
438 unsigned int config0;
439 int isa;
440
441 config0 = read_c0_config();
442
443 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
444 c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB;
445 isa = (config0 & MIPS_CONF_AT) >> 13;
446 switch (isa) {
447 case 0:
448 c->isa_level = MIPS_CPU_ISA_M32;
449 break;
450 case 2:
451 c->isa_level = MIPS_CPU_ISA_M64;
452 break;
453 default:
454 panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
455 }
456
457 return config0 & MIPS_CONF_M;
458 }
459
460 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
461 {
462 unsigned int config1;
463
464 config1 = read_c0_config1();
465
466 if (config1 & MIPS_CONF1_MD)
467 c->ases |= MIPS_ASE_MDMX;
468 if (config1 & MIPS_CONF1_WR)
469 c->options |= MIPS_CPU_WATCH;
470 if (config1 & MIPS_CONF1_CA)
471 c->ases |= MIPS_ASE_MIPS16;
472 if (config1 & MIPS_CONF1_EP)
473 c->options |= MIPS_CPU_EJTAG;
474 if (config1 & MIPS_CONF1_FP) {
475 c->options |= MIPS_CPU_FPU;
476 c->options |= MIPS_CPU_32FPR;
477 }
478 if (cpu_has_tlb)
479 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
480
481 return config1 & MIPS_CONF_M;
482 }
483
484 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
485 {
486 unsigned int config2;
487
488 config2 = read_c0_config2();
489
490 if (config2 & MIPS_CONF2_SL)
491 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
492
493 return config2 & MIPS_CONF_M;
494 }
495
496 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
497 {
498 unsigned int config3;
499
500 config3 = read_c0_config3();
501
502 if (config3 & MIPS_CONF3_SM)
503 c->ases |= MIPS_ASE_SMARTMIPS;
504 if (config3 & MIPS_CONF3_DSP)
505 c->ases |= MIPS_ASE_DSP;
506 if (config3 & MIPS_CONF3_VINT)
507 c->options |= MIPS_CPU_VINT;
508 if (config3 & MIPS_CONF3_VEIC)
509 c->options |= MIPS_CPU_VEIC;
510 if (config3 & MIPS_CONF3_MT)
511 c->ases |= MIPS_ASE_MIPSMT;
512
513 return config3 & MIPS_CONF_M;
514 }
515
516 static inline void decode_configs(struct cpuinfo_mips *c)
517 {
518 /* MIPS32 or MIPS64 compliant CPU. */
519 c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
520 MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
521
522 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
523
524 /* Read Config registers. */
525 if (!decode_config0(c))
526 return; /* actually worth a panic() */
527 if (!decode_config1(c))
528 return;
529 if (!decode_config2(c))
530 return;
531 if (!decode_config3(c))
532 return;
533 }
534
535 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
536 {
537 decode_configs(c);
538 switch (c->processor_id & 0xff00) {
539 case PRID_IMP_4KC:
540 c->cputype = CPU_4KC;
541 break;
542 case PRID_IMP_4KEC:
543 c->cputype = CPU_4KEC;
544 break;
545 case PRID_IMP_4KECR2:
546 c->cputype = CPU_4KEC;
547 break;
548 case PRID_IMP_4KSC:
549 c->cputype = CPU_4KSC;
550 break;
551 case PRID_IMP_5KC:
552 c->cputype = CPU_5KC;
553 break;
554 case PRID_IMP_20KC:
555 c->cputype = CPU_20KC;
556 break;
557 case PRID_IMP_24K:
558 case PRID_IMP_24KE:
559 c->cputype = CPU_24K;
560 break;
561 case PRID_IMP_25KF:
562 c->cputype = CPU_25KF;
563 /* Probe for L2 cache */
564 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
565 break;
566 case PRID_IMP_34K:
567 c->cputype = CPU_34K;
568 c->isa_level = MIPS_CPU_ISA_M32;
569 break;
570 }
571 }
572
573 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
574 {
575 decode_configs(c);
576 switch (c->processor_id & 0xff00) {
577 case PRID_IMP_AU1_REV1:
578 case PRID_IMP_AU1_REV2:
579 switch ((c->processor_id >> 24) & 0xff) {
580 case 0:
581 c->cputype = CPU_AU1000;
582 break;
583 case 1:
584 c->cputype = CPU_AU1500;
585 break;
586 case 2:
587 c->cputype = CPU_AU1100;
588 break;
589 case 3:
590 c->cputype = CPU_AU1550;
591 break;
592 case 4:
593 c->cputype = CPU_AU1200;
594 break;
595 default:
596 panic("Unknown Au Core!");
597 break;
598 }
599 break;
600 }
601 }
602
603 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
604 {
605 decode_configs(c);
606 switch (c->processor_id & 0xff00) {
607 case PRID_IMP_SB1:
608 c->cputype = CPU_SB1;
609 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
610 /* FPU in pass1 is known to have issues. */
611 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
612 #endif
613 break;
614 }
615 }
616
617 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
618 {
619 decode_configs(c);
620 switch (c->processor_id & 0xff00) {
621 case PRID_IMP_SR71000:
622 c->cputype = CPU_SR71000;
623 c->scache.ways = 8;
624 c->tlbsize = 64;
625 break;
626 }
627 }
628
629 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
630 {
631 decode_configs(c);
632 switch (c->processor_id & 0xff00) {
633 case PRID_IMP_PR4450:
634 c->cputype = CPU_PR4450;
635 c->isa_level = MIPS_CPU_ISA_M32;
636 break;
637 default:
638 panic("Unknown Philips Core!"); /* REVISIT: die? */
639 break;
640 }
641 }
642
643
644 __init void cpu_probe(void)
645 {
646 struct cpuinfo_mips *c = &current_cpu_data;
647
648 c->processor_id = PRID_IMP_UNKNOWN;
649 c->fpu_id = FPIR_IMP_NONE;
650 c->cputype = CPU_UNKNOWN;
651
652 c->processor_id = read_c0_prid();
653 switch (c->processor_id & 0xff0000) {
654 case PRID_COMP_LEGACY:
655 cpu_probe_legacy(c);
656 break;
657 case PRID_COMP_MIPS:
658 cpu_probe_mips(c);
659 break;
660 case PRID_COMP_ALCHEMY:
661 cpu_probe_alchemy(c);
662 break;
663 case PRID_COMP_SIBYTE:
664 cpu_probe_sibyte(c);
665 break;
666 case PRID_COMP_SANDCRAFT:
667 cpu_probe_sandcraft(c);
668 break;
669 case PRID_COMP_PHILIPS:
670 cpu_probe_philips(c);
671 break;
672 default:
673 c->cputype = CPU_UNKNOWN;
674 }
675 if (c->options & MIPS_CPU_FPU) {
676 c->fpu_id = cpu_get_fpu_id();
677
678 if (c->isa_level == MIPS_CPU_ISA_M32 ||
679 c->isa_level == MIPS_CPU_ISA_M64) {
680 if (c->fpu_id & MIPS_FPIR_3D)
681 c->ases |= MIPS_ASE_MIPS3D;
682 }
683 }
684 }
685
686 __init void cpu_report(void)
687 {
688 struct cpuinfo_mips *c = &current_cpu_data;
689
690 printk("CPU revision is: %08x\n", c->processor_id);
691 if (c->options & MIPS_CPU_FPU)
692 printk("FPU revision is: %08x\n", c->fpu_id);
693 }
kernel-based virtual machine