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[libata] remove ata_chk_err(), ->check_err() hook.
[linux-2.6/kvm.git] / drivers / scsi / ahci.c
blob03829aedfd391149359181dcd3c3709bf5181c24
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include "scsi.h"
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47 #include <asm/io.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "1.01"
51
52
53 enum {
54 AHCI_PCI_BAR = 5,
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
58 AHCI_CMD_SLOT_SZ = 32 * 32,
59 AHCI_RX_FIS_SZ = 256,
60 AHCI_CMD_TBL_HDR = 0x80,
61 AHCI_CMD_TBL_CDB = 0x40,
62 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
63 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
64 AHCI_RX_FIS_SZ,
65 AHCI_IRQ_ON_SG = (1 << 31),
66 AHCI_CMD_ATAPI = (1 << 5),
67 AHCI_CMD_WRITE = (1 << 6),
68
69 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
70
71 board_ahci = 0,
72
73 /* global controller registers */
74 HOST_CAP = 0x00, /* host capabilities */
75 HOST_CTL = 0x04, /* global host control */
76 HOST_IRQ_STAT = 0x08, /* interrupt status */
77 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
78 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
79
80 /* HOST_CTL bits */
81 HOST_RESET = (1 << 0), /* reset controller; self-clear */
82 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
83 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
84
85 /* HOST_CAP bits */
86 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
87
88 /* registers for each SATA port */
89 PORT_LST_ADDR = 0x00, /* command list DMA addr */
90 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
91 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
92 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
93 PORT_IRQ_STAT = 0x10, /* interrupt status */
94 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
95 PORT_CMD = 0x18, /* port command */
96 PORT_TFDATA = 0x20, /* taskfile data */
97 PORT_SIG = 0x24, /* device TF signature */
98 PORT_CMD_ISSUE = 0x38, /* command issue */
99 PORT_SCR = 0x28, /* SATA phy register block */
100 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
101 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
102 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
103 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
104
105 /* PORT_IRQ_{STAT,MASK} bits */
106 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
107 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
108 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
109 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
110 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
111 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
112 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
113 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
114
115 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
116 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
117 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
118 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
119 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
120 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
121 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
122 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
123 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
124
125 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
126 PORT_IRQ_HBUS_ERR |
127 PORT_IRQ_HBUS_DATA_ERR |
128 PORT_IRQ_IF_ERR,
129 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
130 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
131 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
132 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
133 PORT_IRQ_D2H_REG_FIS,
134
135 /* PORT_CMD bits */
136 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
137 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
138 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
139 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
140 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
141 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
142
143 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
144 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
145 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
146
147 /* hpriv->flags bits */
148 AHCI_FLAG_MSI = (1 << 0),
149 };
150
151 struct ahci_cmd_hdr {
152 u32 opts;
153 u32 status;
154 u32 tbl_addr;
155 u32 tbl_addr_hi;
156 u32 reserved[4];
157 };
158
159 struct ahci_sg {
160 u32 addr;
161 u32 addr_hi;
162 u32 reserved;
163 u32 flags_size;
164 };
165
166 struct ahci_host_priv {
167 unsigned long flags;
168 u32 cap; /* cache of HOST_CAP register */
169 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
170 };
171
172 struct ahci_port_priv {
173 struct ahci_cmd_hdr *cmd_slot;
174 dma_addr_t cmd_slot_dma;
175 void *cmd_tbl;
176 dma_addr_t cmd_tbl_dma;
177 struct ahci_sg *cmd_tbl_sg;
178 void *rx_fis;
179 dma_addr_t rx_fis_dma;
180 };
181
182 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
183 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
184 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
185 static int ahci_qc_issue(struct ata_queued_cmd *qc);
186 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
187 static void ahci_phy_reset(struct ata_port *ap);
188 static void ahci_irq_clear(struct ata_port *ap);
189 static void ahci_eng_timeout(struct ata_port *ap);
190 static int ahci_port_start(struct ata_port *ap);
191 static void ahci_port_stop(struct ata_port *ap);
192 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
193 static void ahci_qc_prep(struct ata_queued_cmd *qc);
194 static u8 ahci_check_status(struct ata_port *ap);
195 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
196 static void ahci_remove_one (struct pci_dev *pdev);
197
198 static Scsi_Host_Template ahci_sht = {
199 .module = THIS_MODULE,
200 .name = DRV_NAME,
201 .ioctl = ata_scsi_ioctl,
202 .queuecommand = ata_scsi_queuecmd,
203 .eh_strategy_handler = ata_scsi_error,
204 .can_queue = ATA_DEF_QUEUE,
205 .this_id = ATA_SHT_THIS_ID,
206 .sg_tablesize = AHCI_MAX_SG,
207 .max_sectors = ATA_MAX_SECTORS,
208 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
209 .emulated = ATA_SHT_EMULATED,
210 .use_clustering = AHCI_USE_CLUSTERING,
211 .proc_name = DRV_NAME,
212 .dma_boundary = AHCI_DMA_BOUNDARY,
213 .slave_configure = ata_scsi_slave_config,
214 .bios_param = ata_std_bios_param,
215 .ordered_flush = 1,
216 };
217
218 static const struct ata_port_operations ahci_ops = {
219 .port_disable = ata_port_disable,
220
221 .check_status = ahci_check_status,
222 .check_altstatus = ahci_check_status,
223 .dev_select = ata_noop_dev_select,
224
225 .tf_read = ahci_tf_read,
226
227 .phy_reset = ahci_phy_reset,
228
229 .qc_prep = ahci_qc_prep,
230 .qc_issue = ahci_qc_issue,
231
232 .eng_timeout = ahci_eng_timeout,
233
234 .irq_handler = ahci_interrupt,
235 .irq_clear = ahci_irq_clear,
236
237 .scr_read = ahci_scr_read,
238 .scr_write = ahci_scr_write,
239
240 .port_start = ahci_port_start,
241 .port_stop = ahci_port_stop,
242 };
243
244 static struct ata_port_info ahci_port_info[] = {
245 /* board_ahci */
246 {
247 .sht = &ahci_sht,
248 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
249 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
250 ATA_FLAG_PIO_DMA,
251 .pio_mask = 0x1f, /* pio0-4 */
252 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
253 .port_ops = &ahci_ops,
254 },
255 };
256
257 static struct pci_device_id ahci_pci_tbl[] = {
258 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
259 board_ahci }, /* ICH6 */
260 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_ahci }, /* ICH6M */
262 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH7 */
264 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH7M */
266 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH7R */
268 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ULi M5288 */
270 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ESB2 */
272 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ESB2 */
274 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ICH7-M DH */
278 { } /* terminate list */
279 };
280
281
282 static struct pci_driver ahci_pci_driver = {
283 .name = DRV_NAME,
284 .id_table = ahci_pci_tbl,
285 .probe = ahci_init_one,
286 .remove = ahci_remove_one,
287 };
288
289
290 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
291 {
292 return base + 0x100 + (port * 0x80);
293 }
294
295 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
296 {
297 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
298 }
299
300 static int ahci_port_start(struct ata_port *ap)
301 {
302 struct device *dev = ap->host_set->dev;
303 struct ahci_host_priv *hpriv = ap->host_set->private_data;
304 struct ahci_port_priv *pp;
305 void __iomem *mmio = ap->host_set->mmio_base;
306 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
307 void *mem;
308 dma_addr_t mem_dma;
309
310 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
311 if (!pp)
312 return -ENOMEM;
313 memset(pp, 0, sizeof(*pp));
314
315 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
316 if (!mem) {
317 kfree(pp);
318 return -ENOMEM;
319 }
320 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
321
322 /*
323 * First item in chunk of DMA memory: 32-slot command table,
324 * 32 bytes each in size
325 */
326 pp->cmd_slot = mem;
327 pp->cmd_slot_dma = mem_dma;
328
329 mem += AHCI_CMD_SLOT_SZ;
330 mem_dma += AHCI_CMD_SLOT_SZ;
331
332 /*
333 * Second item: Received-FIS area
334 */
335 pp->rx_fis = mem;
336 pp->rx_fis_dma = mem_dma;
337
338 mem += AHCI_RX_FIS_SZ;
339 mem_dma += AHCI_RX_FIS_SZ;
340
341 /*
342 * Third item: data area for storing a single command
343 * and its scatter-gather table
344 */
345 pp->cmd_tbl = mem;
346 pp->cmd_tbl_dma = mem_dma;
347
348 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
349
350 ap->private_data = pp;
351
352 if (hpriv->cap & HOST_CAP_64)
353 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
354 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
355 readl(port_mmio + PORT_LST_ADDR); /* flush */
356
357 if (hpriv->cap & HOST_CAP_64)
358 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
359 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
360 readl(port_mmio + PORT_FIS_ADDR); /* flush */
361
362 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
363 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
364 PORT_CMD_START, port_mmio + PORT_CMD);
365 readl(port_mmio + PORT_CMD); /* flush */
366
367 return 0;
368 }
369
370
371 static void ahci_port_stop(struct ata_port *ap)
372 {
373 struct device *dev = ap->host_set->dev;
374 struct ahci_port_priv *pp = ap->private_data;
375 void __iomem *mmio = ap->host_set->mmio_base;
376 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
377 u32 tmp;
378
379 tmp = readl(port_mmio + PORT_CMD);
380 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
381 writel(tmp, port_mmio + PORT_CMD);
382 readl(port_mmio + PORT_CMD); /* flush */
383
384 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
385 * this is slightly incorrect.
386 */
387 msleep(500);
388
389 ap->private_data = NULL;
390 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
391 pp->cmd_slot, pp->cmd_slot_dma);
392 kfree(pp);
393 }
394
395 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
396 {
397 unsigned int sc_reg;
398
399 switch (sc_reg_in) {
400 case SCR_STATUS: sc_reg = 0; break;
401 case SCR_CONTROL: sc_reg = 1; break;
402 case SCR_ERROR: sc_reg = 2; break;
403 case SCR_ACTIVE: sc_reg = 3; break;
404 default:
405 return 0xffffffffU;
406 }
407
408 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
409 }
410
411
412 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
413 u32 val)
414 {
415 unsigned int sc_reg;
416
417 switch (sc_reg_in) {
418 case SCR_STATUS: sc_reg = 0; break;
419 case SCR_CONTROL: sc_reg = 1; break;
420 case SCR_ERROR: sc_reg = 2; break;
421 case SCR_ACTIVE: sc_reg = 3; break;
422 default:
423 return;
424 }
425
426 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
427 }
428
429 static void ahci_phy_reset(struct ata_port *ap)
430 {
431 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
432 struct ata_taskfile tf;
433 struct ata_device *dev = &ap->device[0];
434 u32 tmp;
435
436 __sata_phy_reset(ap);
437
438 if (ap->flags & ATA_FLAG_PORT_DISABLED)
439 return;
440
441 tmp = readl(port_mmio + PORT_SIG);
442 tf.lbah = (tmp >> 24) & 0xff;
443 tf.lbam = (tmp >> 16) & 0xff;
444 tf.lbal = (tmp >> 8) & 0xff;
445 tf.nsect = (tmp) & 0xff;
446
447 dev->class = ata_dev_classify(&tf);
448 if (!ata_dev_present(dev))
449 ata_port_disable(ap);
450 }
451
452 static u8 ahci_check_status(struct ata_port *ap)
453 {
454 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
455
456 return readl(mmio + PORT_TFDATA) & 0xFF;
457 }
458
459 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
460 {
461 struct ahci_port_priv *pp = ap->private_data;
462 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
463
464 ata_tf_from_fis(d2h_fis, tf);
465 }
466
467 static void ahci_fill_sg(struct ata_queued_cmd *qc)
468 {
469 struct ahci_port_priv *pp = qc->ap->private_data;
470 unsigned int i;
471
472 VPRINTK("ENTER\n");
473
474 /*
475 * Next, the S/G list.
476 */
477 for (i = 0; i < qc->n_elem; i++) {
478 u32 sg_len;
479 dma_addr_t addr;
480
481 addr = sg_dma_address(&qc->sg[i]);
482 sg_len = sg_dma_len(&qc->sg[i]);
483
484 pp->cmd_tbl_sg[i].addr = cpu_to_le32(addr & 0xffffffff);
485 pp->cmd_tbl_sg[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
486 pp->cmd_tbl_sg[i].flags_size = cpu_to_le32(sg_len - 1);
487 }
488 }
489
490 static void ahci_qc_prep(struct ata_queued_cmd *qc)
491 {
492 struct ata_port *ap = qc->ap;
493 struct ahci_port_priv *pp = ap->private_data;
494 u32 opts;
495 const u32 cmd_fis_len = 5; /* five dwords */
496
497 /*
498 * Fill in command slot information (currently only one slot,
499 * slot 0, is currently since we don't do queueing)
500 */
501
502 opts = (qc->n_elem << 16) | cmd_fis_len;
503 if (qc->tf.flags & ATA_TFLAG_WRITE)
504 opts |= AHCI_CMD_WRITE;
505 if (is_atapi_taskfile(&qc->tf))
506 opts |= AHCI_CMD_ATAPI;
507
508 pp->cmd_slot[0].opts = cpu_to_le32(opts);
509 pp->cmd_slot[0].status = 0;
510 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
511 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
512
513 /*
514 * Fill in command table information. First, the header,
515 * a SATA Register - Host to Device command FIS.
516 */
517 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
518 if (opts & AHCI_CMD_ATAPI) {
519 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
520 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
521 }
522
523 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
524 return;
525
526 ahci_fill_sg(qc);
527 }
528
529 static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
530 {
531 void __iomem *mmio = ap->host_set->mmio_base;
532 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
533 u32 tmp;
534 int work;
535
536 /* stop DMA */
537 tmp = readl(port_mmio + PORT_CMD);
538 tmp &= ~PORT_CMD_START;
539 writel(tmp, port_mmio + PORT_CMD);
540
541 /* wait for engine to stop. TODO: this could be
542 * as long as 500 msec
543 */
544 work = 1000;
545 while (work-- > 0) {
546 tmp = readl(port_mmio + PORT_CMD);
547 if ((tmp & PORT_CMD_LIST_ON) == 0)
548 break;
549 udelay(10);
550 }
551
552 /* clear SATA phy error, if any */
553 tmp = readl(port_mmio + PORT_SCR_ERR);
554 writel(tmp, port_mmio + PORT_SCR_ERR);
555
556 /* if DRQ/BSY is set, device needs to be reset.
557 * if so, issue COMRESET
558 */
559 tmp = readl(port_mmio + PORT_TFDATA);
560 if (tmp & (ATA_BUSY | ATA_DRQ)) {
561 writel(0x301, port_mmio + PORT_SCR_CTL);
562 readl(port_mmio + PORT_SCR_CTL); /* flush */
563 udelay(10);
564 writel(0x300, port_mmio + PORT_SCR_CTL);
565 readl(port_mmio + PORT_SCR_CTL); /* flush */
566 }
567
568 /* re-start DMA */
569 tmp = readl(port_mmio + PORT_CMD);
570 tmp |= PORT_CMD_START;
571 writel(tmp, port_mmio + PORT_CMD);
572 readl(port_mmio + PORT_CMD); /* flush */
573
574 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
575 }
576
577 static void ahci_eng_timeout(struct ata_port *ap)
578 {
579 struct ata_host_set *host_set = ap->host_set;
580 void __iomem *mmio = host_set->mmio_base;
581 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
582 struct ata_queued_cmd *qc;
583 unsigned long flags;
584
585 DPRINTK("ENTER\n");
586
587 spin_lock_irqsave(&host_set->lock, flags);
588
589 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
590
591 qc = ata_qc_from_tag(ap, ap->active_tag);
592 if (!qc) {
593 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
594 ap->id);
595 } else {
596 /* hack alert! We cannot use the supplied completion
597 * function from inside the ->eh_strategy_handler() thread.
598 * libata is the only user of ->eh_strategy_handler() in
599 * any kernel, so the default scsi_done() assumes it is
600 * not being called from the SCSI EH.
601 */
602 qc->scsidone = scsi_finish_command;
603 ata_qc_complete(qc, ATA_ERR);
604 }
605
606 spin_unlock_irqrestore(&host_set->lock, flags);
607 }
608
609 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
610 {
611 void __iomem *mmio = ap->host_set->mmio_base;
612 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
613 u32 status, serr, ci;
614
615 serr = readl(port_mmio + PORT_SCR_ERR);
616 writel(serr, port_mmio + PORT_SCR_ERR);
617
618 status = readl(port_mmio + PORT_IRQ_STAT);
619 writel(status, port_mmio + PORT_IRQ_STAT);
620
621 ci = readl(port_mmio + PORT_CMD_ISSUE);
622 if (likely((ci & 0x1) == 0)) {
623 if (qc) {
624 ata_qc_complete(qc, 0);
625 qc = NULL;
626 }
627 }
628
629 if (status & PORT_IRQ_FATAL) {
630 ahci_intr_error(ap, status);
631 if (qc)
632 ata_qc_complete(qc, ATA_ERR);
633 }
634
635 return 1;
636 }
637
638 static void ahci_irq_clear(struct ata_port *ap)
639 {
640 /* TODO */
641 }
642
643 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
644 {
645 struct ata_host_set *host_set = dev_instance;
646 struct ahci_host_priv *hpriv;
647 unsigned int i, handled = 0;
648 void __iomem *mmio;
649 u32 irq_stat, irq_ack = 0;
650
651 VPRINTK("ENTER\n");
652
653 hpriv = host_set->private_data;
654 mmio = host_set->mmio_base;
655
656 /* sigh. 0xffffffff is a valid return from h/w */
657 irq_stat = readl(mmio + HOST_IRQ_STAT);
658 irq_stat &= hpriv->port_map;
659 if (!irq_stat)
660 return IRQ_NONE;
661
662 spin_lock(&host_set->lock);
663
664 for (i = 0; i < host_set->n_ports; i++) {
665 struct ata_port *ap;
666
667 if (!(irq_stat & (1 << i)))
668 continue;
669
670 ap = host_set->ports[i];
671 if (ap) {
672 struct ata_queued_cmd *qc;
673 qc = ata_qc_from_tag(ap, ap->active_tag);
674 if (!ahci_host_intr(ap, qc))
675 if (ata_ratelimit()) {
676 struct pci_dev *pdev =
677 to_pci_dev(ap->host_set->dev);
678 printk(KERN_WARNING
679 "ahci(%s): unhandled interrupt on port %u\n",
680 pci_name(pdev), i);
681 }
682
683 VPRINTK("port %u\n", i);
684 } else {
685 VPRINTK("port %u (no irq)\n", i);
686 if (ata_ratelimit()) {
687 struct pci_dev *pdev =
688 to_pci_dev(ap->host_set->dev);
689 printk(KERN_WARNING
690 "ahci(%s): interrupt on disabled port %u\n",
691 pci_name(pdev), i);
692 }
693 }
694
695 irq_ack |= (1 << i);
696 }
697
698 if (irq_ack) {
699 writel(irq_ack, mmio + HOST_IRQ_STAT);
700 handled = 1;
701 }
702
703 spin_unlock(&host_set->lock);
704
705 VPRINTK("EXIT\n");
706
707 return IRQ_RETVAL(handled);
708 }
709
710 static int ahci_qc_issue(struct ata_queued_cmd *qc)
711 {
712 struct ata_port *ap = qc->ap;
713 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
714
715 writel(1, port_mmio + PORT_CMD_ISSUE);
716 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
717
718 return 0;
719 }
720
721 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
722 unsigned int port_idx)
723 {
724 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
725 base = ahci_port_base_ul(base, port_idx);
726 VPRINTK("base now==0x%lx\n", base);
727
728 port->cmd_addr = base;
729 port->scr_addr = base + PORT_SCR;
730
731 VPRINTK("EXIT\n");
732 }
733
734 static int ahci_host_init(struct ata_probe_ent *probe_ent)
735 {
736 struct ahci_host_priv *hpriv = probe_ent->private_data;
737 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
738 void __iomem *mmio = probe_ent->mmio_base;
739 u32 tmp, cap_save;
740 u16 tmp16;
741 unsigned int i, j, using_dac;
742 int rc;
743 void __iomem *port_mmio;
744
745 cap_save = readl(mmio + HOST_CAP);
746 cap_save &= ( (1<<28) | (1<<17) );
747 cap_save |= (1 << 27);
748
749 /* global controller reset */
750 tmp = readl(mmio + HOST_CTL);
751 if ((tmp & HOST_RESET) == 0) {
752 writel(tmp | HOST_RESET, mmio + HOST_CTL);
753 readl(mmio + HOST_CTL); /* flush */
754 }
755
756 /* reset must complete within 1 second, or
757 * the hardware should be considered fried.
758 */
759 ssleep(1);
760
761 tmp = readl(mmio + HOST_CTL);
762 if (tmp & HOST_RESET) {
763 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
764 pci_name(pdev), tmp);
765 return -EIO;
766 }
767
768 writel(HOST_AHCI_EN, mmio + HOST_CTL);
769 (void) readl(mmio + HOST_CTL); /* flush */
770 writel(cap_save, mmio + HOST_CAP);
771 writel(0xf, mmio + HOST_PORTS_IMPL);
772 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
773
774 pci_read_config_word(pdev, 0x92, &tmp16);
775 tmp16 |= 0xf;
776 pci_write_config_word(pdev, 0x92, tmp16);
777
778 hpriv->cap = readl(mmio + HOST_CAP);
779 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
780 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
781
782 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
783 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
784
785 using_dac = hpriv->cap & HOST_CAP_64;
786 if (using_dac &&
787 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
788 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
789 if (rc) {
790 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
791 if (rc) {
792 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
793 pci_name(pdev));
794 return rc;
795 }
796 }
797 } else {
798 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
799 if (rc) {
800 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
801 pci_name(pdev));
802 return rc;
803 }
804 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
805 if (rc) {
806 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
807 pci_name(pdev));
808 return rc;
809 }
810 }
811
812 for (i = 0; i < probe_ent->n_ports; i++) {
813 #if 0 /* BIOSen initialize this incorrectly */
814 if (!(hpriv->port_map & (1 << i)))
815 continue;
816 #endif
817
818 port_mmio = ahci_port_base(mmio, i);
819 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
820
821 ahci_setup_port(&probe_ent->port[i],
822 (unsigned long) mmio, i);
823
824 /* make sure port is not active */
825 tmp = readl(port_mmio + PORT_CMD);
826 VPRINTK("PORT_CMD 0x%x\n", tmp);
827 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
828 PORT_CMD_FIS_RX | PORT_CMD_START)) {
829 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
830 PORT_CMD_FIS_RX | PORT_CMD_START);
831 writel(tmp, port_mmio + PORT_CMD);
832 readl(port_mmio + PORT_CMD); /* flush */
833
834 /* spec says 500 msecs for each bit, so
835 * this is slightly incorrect.
836 */
837 msleep(500);
838 }
839
840 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
841
842 j = 0;
843 while (j < 100) {
844 msleep(10);
845 tmp = readl(port_mmio + PORT_SCR_STAT);
846 if ((tmp & 0xf) == 0x3)
847 break;
848 j++;
849 }
850
851 tmp = readl(port_mmio + PORT_SCR_ERR);
852 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
853 writel(tmp, port_mmio + PORT_SCR_ERR);
854
855 /* ack any pending irq events for this port */
856 tmp = readl(port_mmio + PORT_IRQ_STAT);
857 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
858 if (tmp)
859 writel(tmp, port_mmio + PORT_IRQ_STAT);
860
861 writel(1 << i, mmio + HOST_IRQ_STAT);
862
863 /* set irq mask (enables interrupts) */
864 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
865 }
866
867 tmp = readl(mmio + HOST_CTL);
868 VPRINTK("HOST_CTL 0x%x\n", tmp);
869 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
870 tmp = readl(mmio + HOST_CTL);
871 VPRINTK("HOST_CTL 0x%x\n", tmp);
872
873 pci_set_master(pdev);
874
875 return 0;
876 }
877
878 static void ahci_print_info(struct ata_probe_ent *probe_ent)
879 {
880 struct ahci_host_priv *hpriv = probe_ent->private_data;
881 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
882 void __iomem *mmio = probe_ent->mmio_base;
883 u32 vers, cap, impl, speed;
884 const char *speed_s;
885 u16 cc;
886 const char *scc_s;
887
888 vers = readl(mmio + HOST_VERSION);
889 cap = hpriv->cap;
890 impl = hpriv->port_map;
891
892 speed = (cap >> 20) & 0xf;
893 if (speed == 1)
894 speed_s = "1.5";
895 else if (speed == 2)
896 speed_s = "3";
897 else
898 speed_s = "?";
899
900 pci_read_config_word(pdev, 0x0a, &cc);
901 if (cc == 0x0101)
902 scc_s = "IDE";
903 else if (cc == 0x0106)
904 scc_s = "SATA";
905 else if (cc == 0x0104)
906 scc_s = "RAID";
907 else
908 scc_s = "unknown";
909
910 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
911 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
912 ,
913 pci_name(pdev),
914
915 (vers >> 24) & 0xff,
916 (vers >> 16) & 0xff,
917 (vers >> 8) & 0xff,
918 vers & 0xff,
919
920 ((cap >> 8) & 0x1f) + 1,
921 (cap & 0x1f) + 1,
922 speed_s,
923 impl,
924 scc_s);
925
926 printk(KERN_INFO DRV_NAME "(%s) flags: "
927 "%s%s%s%s%s%s"
928 "%s%s%s%s%s%s%s\n"
929 ,
930 pci_name(pdev),
931
932 cap & (1 << 31) ? "64bit " : "",
933 cap & (1 << 30) ? "ncq " : "",
934 cap & (1 << 28) ? "ilck " : "",
935 cap & (1 << 27) ? "stag " : "",
936 cap & (1 << 26) ? "pm " : "",
937 cap & (1 << 25) ? "led " : "",
938
939 cap & (1 << 24) ? "clo " : "",
940 cap & (1 << 19) ? "nz " : "",
941 cap & (1 << 18) ? "only " : "",
942 cap & (1 << 17) ? "pmp " : "",
943 cap & (1 << 15) ? "pio " : "",
944 cap & (1 << 14) ? "slum " : "",
945 cap & (1 << 13) ? "part " : ""
946 );
947 }
948
949 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
950 {
951 static int printed_version;
952 struct ata_probe_ent *probe_ent = NULL;
953 struct ahci_host_priv *hpriv;
954 unsigned long base;
955 void __iomem *mmio_base;
956 unsigned int board_idx = (unsigned int) ent->driver_data;
957 int have_msi, pci_dev_busy = 0;
958 int rc;
959
960 VPRINTK("ENTER\n");
961
962 if (!printed_version++)
963 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
964
965 rc = pci_enable_device(pdev);
966 if (rc)
967 return rc;
968
969 rc = pci_request_regions(pdev, DRV_NAME);
970 if (rc) {
971 pci_dev_busy = 1;
972 goto err_out;
973 }
974
975 if (pci_enable_msi(pdev) == 0)
976 have_msi = 1;
977 else {
978 pci_intx(pdev, 1);
979 have_msi = 0;
980 }
981
982 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
983 if (probe_ent == NULL) {
984 rc = -ENOMEM;
985 goto err_out_msi;
986 }
987
988 memset(probe_ent, 0, sizeof(*probe_ent));
989 probe_ent->dev = pci_dev_to_dev(pdev);
990 INIT_LIST_HEAD(&probe_ent->node);
991
992 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
993 if (mmio_base == NULL) {
994 rc = -ENOMEM;
995 goto err_out_free_ent;
996 }
997 base = (unsigned long) mmio_base;
998
999 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1000 if (!hpriv) {
1001 rc = -ENOMEM;
1002 goto err_out_iounmap;
1003 }
1004 memset(hpriv, 0, sizeof(*hpriv));
1005
1006 probe_ent->sht = ahci_port_info[board_idx].sht;
1007 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1008 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1009 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1010 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1011
1012 probe_ent->irq = pdev->irq;
1013 probe_ent->irq_flags = SA_SHIRQ;
1014 probe_ent->mmio_base = mmio_base;
1015 probe_ent->private_data = hpriv;
1016
1017 if (have_msi)
1018 hpriv->flags |= AHCI_FLAG_MSI;
1019
1020 /* initialize adapter */
1021 rc = ahci_host_init(probe_ent);
1022 if (rc)
1023 goto err_out_hpriv;
1024
1025 ahci_print_info(probe_ent);
1026
1027 /* FIXME: check ata_device_add return value */
1028 ata_device_add(probe_ent);
1029 kfree(probe_ent);
1030
1031 return 0;
1032
1033 err_out_hpriv:
1034 kfree(hpriv);
1035 err_out_iounmap:
1036 pci_iounmap(pdev, mmio_base);
1037 err_out_free_ent:
1038 kfree(probe_ent);
1039 err_out_msi:
1040 if (have_msi)
1041 pci_disable_msi(pdev);
1042 else
1043 pci_intx(pdev, 0);
1044 pci_release_regions(pdev);
1045 err_out:
1046 if (!pci_dev_busy)
1047 pci_disable_device(pdev);
1048 return rc;
1049 }
1050
1051 static void ahci_remove_one (struct pci_dev *pdev)
1052 {
1053 struct device *dev = pci_dev_to_dev(pdev);
1054 struct ata_host_set *host_set = dev_get_drvdata(dev);
1055 struct ahci_host_priv *hpriv = host_set->private_data;
1056 struct ata_port *ap;
1057 unsigned int i;
1058 int have_msi;
1059
1060 for (i = 0; i < host_set->n_ports; i++) {
1061 ap = host_set->ports[i];
1062
1063 scsi_remove_host(ap->host);
1064 }
1065
1066 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1067 free_irq(host_set->irq, host_set);
1068
1069 for (i = 0; i < host_set->n_ports; i++) {
1070 ap = host_set->ports[i];
1071
1072 ata_scsi_release(ap->host);
1073 scsi_host_put(ap->host);
1074 }
1075
1076 kfree(hpriv);
1077 pci_iounmap(pdev, host_set->mmio_base);
1078 kfree(host_set);
1079
1080 if (have_msi)
1081 pci_disable_msi(pdev);
1082 else
1083 pci_intx(pdev, 0);
1084 pci_release_regions(pdev);
1085 pci_disable_device(pdev);
1086 dev_set_drvdata(dev, NULL);
1087 }
1088
1089 static int __init ahci_init(void)
1090 {
1091 return pci_module_init(&ahci_pci_driver);
1092 }
1093
1094 static void __exit ahci_exit(void)
1095 {
1096 pci_unregister_driver(&ahci_pci_driver);
1097 }
1098
1099
1100 MODULE_AUTHOR("Jeff Garzik");
1101 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1102 MODULE_LICENSE("GPL");
1103 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1104 MODULE_VERSION(DRV_VERSION);
1105
1106 module_init(ahci_init);
1107 module_exit(ahci_exit);
kernel-based virtual machine