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KVM: x86: Avoid issuing wbinvd twice
[linux-2.6/kvm-ia64.git] / arch / x86 / kvm / x86.c
blob34a1737f9f4cf5d61f51b29b6137209f0a193185
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
33 #include <linux/fs.h>
34 #include <linux/vmalloc.h>
35 #include <linux/module.h>
36 #include <linux/mman.h>
37 #include <linux/highmem.h>
38 #include <linux/iommu.h>
39 #include <linux/intel-iommu.h>
40 #include <linux/cpufreq.h>
41 #include <linux/user-return-notifier.h>
42 #include <linux/srcu.h>
43 #include <linux/slab.h>
44 #include <linux/perf_event.h>
45 #include <linux/uaccess.h>
46 #include <linux/hash.h>
47 #include <trace/events/kvm.h>
48
49 #define CREATE_TRACE_POINTS
50 #include "trace.h"
51
52 #include <asm/debugreg.h>
53 #include <asm/msr.h>
54 #include <asm/desc.h>
55 #include <asm/mtrr.h>
56 #include <asm/mce.h>
57 #include <asm/i387.h>
58 #include <asm/xcr.h>
59 #include <asm/pvclock.h>
60 #include <asm/div64.h>
61
62 #define MAX_IO_MSRS 256
63 #define CR0_RESERVED_BITS \
64 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
65 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
66 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
67 #define CR4_RESERVED_BITS \
68 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
69 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
70 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
71 | X86_CR4_OSXSAVE \
72 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
73
74 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
75
76 #define KVM_MAX_MCE_BANKS 32
77 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
78
79 /* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83 #ifdef CONFIG_X86_64
84 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
85 #else
86 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
87 #endif
88
89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
91
92 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
93 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
94 struct kvm_cpuid_entry2 __user *entries);
95
96 struct kvm_x86_ops *kvm_x86_ops;
97 EXPORT_SYMBOL_GPL(kvm_x86_ops);
98
99 int ignore_msrs = 0;
100 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
102 #define KVM_NR_SHARED_MSRS 16
103
104 struct kvm_shared_msrs_global {
105 int nr;
106 u32 msrs[KVM_NR_SHARED_MSRS];
107 };
108
109 struct kvm_shared_msrs {
110 struct user_return_notifier urn;
111 bool registered;
112 struct kvm_shared_msr_values {
113 u64 host;
114 u64 curr;
115 } values[KVM_NR_SHARED_MSRS];
116 };
117
118 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
119 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
120
121 struct kvm_stats_debugfs_item debugfs_entries[] = {
122 { "pf_fixed", VCPU_STAT(pf_fixed) },
123 { "pf_guest", VCPU_STAT(pf_guest) },
124 { "tlb_flush", VCPU_STAT(tlb_flush) },
125 { "invlpg", VCPU_STAT(invlpg) },
126 { "exits", VCPU_STAT(exits) },
127 { "io_exits", VCPU_STAT(io_exits) },
128 { "mmio_exits", VCPU_STAT(mmio_exits) },
129 { "signal_exits", VCPU_STAT(signal_exits) },
130 { "irq_window", VCPU_STAT(irq_window_exits) },
131 { "nmi_window", VCPU_STAT(nmi_window_exits) },
132 { "halt_exits", VCPU_STAT(halt_exits) },
133 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
134 { "hypercalls", VCPU_STAT(hypercalls) },
135 { "request_irq", VCPU_STAT(request_irq_exits) },
136 { "irq_exits", VCPU_STAT(irq_exits) },
137 { "host_state_reload", VCPU_STAT(host_state_reload) },
138 { "efer_reload", VCPU_STAT(efer_reload) },
139 { "fpu_reload", VCPU_STAT(fpu_reload) },
140 { "insn_emulation", VCPU_STAT(insn_emulation) },
141 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
142 { "irq_injections", VCPU_STAT(irq_injections) },
143 { "nmi_injections", VCPU_STAT(nmi_injections) },
144 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
145 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
146 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
147 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
148 { "mmu_flooded", VM_STAT(mmu_flooded) },
149 { "mmu_recycled", VM_STAT(mmu_recycled) },
150 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
151 { "mmu_unsync", VM_STAT(mmu_unsync) },
152 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
153 { "largepages", VM_STAT(lpages) },
154 { NULL }
155 };
156
157 u64 __read_mostly host_xcr0;
158
159 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
160 {
161 int i;
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
164 }
165
166 static inline u32 bit(int bitno)
167 {
168 return 1 << (bitno & 31);
169 }
170
171 static void kvm_on_user_return(struct user_return_notifier *urn)
172 {
173 unsigned slot;
174 struct kvm_shared_msrs *locals
175 = container_of(urn, struct kvm_shared_msrs, urn);
176 struct kvm_shared_msr_values *values;
177
178 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
179 values = &locals->values[slot];
180 if (values->host != values->curr) {
181 wrmsrl(shared_msrs_global.msrs[slot], values->host);
182 values->curr = values->host;
183 }
184 }
185 locals->registered = false;
186 user_return_notifier_unregister(urn);
187 }
188
189 static void shared_msr_update(unsigned slot, u32 msr)
190 {
191 struct kvm_shared_msrs *smsr;
192 u64 value;
193
194 smsr = &__get_cpu_var(shared_msrs);
195 /* only read, and nobody should modify it at this time,
196 * so don't need lock */
197 if (slot >= shared_msrs_global.nr) {
198 printk(KERN_ERR "kvm: invalid MSR slot!");
199 return;
200 }
201 rdmsrl_safe(msr, &value);
202 smsr->values[slot].host = value;
203 smsr->values[slot].curr = value;
204 }
205
206 void kvm_define_shared_msr(unsigned slot, u32 msr)
207 {
208 if (slot >= shared_msrs_global.nr)
209 shared_msrs_global.nr = slot + 1;
210 shared_msrs_global.msrs[slot] = msr;
211 /* we need ensured the shared_msr_global have been updated */
212 smp_wmb();
213 }
214 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
215
216 static void kvm_shared_msr_cpu_online(void)
217 {
218 unsigned i;
219
220 for (i = 0; i < shared_msrs_global.nr; ++i)
221 shared_msr_update(i, shared_msrs_global.msrs[i]);
222 }
223
224 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
225 {
226 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
227
228 if (((value ^ smsr->values[slot].curr) & mask) == 0)
229 return;
230 smsr->values[slot].curr = value;
231 wrmsrl(shared_msrs_global.msrs[slot], value);
232 if (!smsr->registered) {
233 smsr->urn.on_user_return = kvm_on_user_return;
234 user_return_notifier_register(&smsr->urn);
235 smsr->registered = true;
236 }
237 }
238 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
239
240 static void drop_user_return_notifiers(void *ignore)
241 {
242 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
243
244 if (smsr->registered)
245 kvm_on_user_return(&smsr->urn);
246 }
247
248 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
249 {
250 if (irqchip_in_kernel(vcpu->kvm))
251 return vcpu->arch.apic_base;
252 else
253 return vcpu->arch.apic_base;
254 }
255 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258 {
259 /* TODO: reserve bits check */
260 if (irqchip_in_kernel(vcpu->kvm))
261 kvm_lapic_set_base(vcpu, data);
262 else
263 vcpu->arch.apic_base = data;
264 }
265 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
266
267 #define EXCPT_BENIGN 0
268 #define EXCPT_CONTRIBUTORY 1
269 #define EXCPT_PF 2
270
271 static int exception_class(int vector)
272 {
273 switch (vector) {
274 case PF_VECTOR:
275 return EXCPT_PF;
276 case DE_VECTOR:
277 case TS_VECTOR:
278 case NP_VECTOR:
279 case SS_VECTOR:
280 case GP_VECTOR:
281 return EXCPT_CONTRIBUTORY;
282 default:
283 break;
284 }
285 return EXCPT_BENIGN;
286 }
287
288 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
289 unsigned nr, bool has_error, u32 error_code,
290 bool reinject)
291 {
292 u32 prev_nr;
293 int class1, class2;
294
295 kvm_make_request(KVM_REQ_EVENT, vcpu);
296
297 if (!vcpu->arch.exception.pending) {
298 queue:
299 vcpu->arch.exception.pending = true;
300 vcpu->arch.exception.has_error_code = has_error;
301 vcpu->arch.exception.nr = nr;
302 vcpu->arch.exception.error_code = error_code;
303 vcpu->arch.exception.reinject = reinject;
304 return;
305 }
306
307 /* to check exception */
308 prev_nr = vcpu->arch.exception.nr;
309 if (prev_nr == DF_VECTOR) {
310 /* triple fault -> shutdown */
311 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
312 return;
313 }
314 class1 = exception_class(prev_nr);
315 class2 = exception_class(nr);
316 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
317 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
318 /* generate double fault per SDM Table 5-5 */
319 vcpu->arch.exception.pending = true;
320 vcpu->arch.exception.has_error_code = true;
321 vcpu->arch.exception.nr = DF_VECTOR;
322 vcpu->arch.exception.error_code = 0;
323 } else
324 /* replace previous exception with a new one in a hope
325 that instruction re-execution will regenerate lost
326 exception */
327 goto queue;
328 }
329
330 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
331 {
332 kvm_multiple_exception(vcpu, nr, false, 0, false);
333 }
334 EXPORT_SYMBOL_GPL(kvm_queue_exception);
335
336 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
337 {
338 kvm_multiple_exception(vcpu, nr, false, 0, true);
339 }
340 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
341
342 void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
343 {
344 unsigned error_code = vcpu->arch.fault.error_code;
345
346 ++vcpu->stat.pf_guest;
347 vcpu->arch.cr2 = vcpu->arch.fault.address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
349 }
350
351 void kvm_propagate_fault(struct kvm_vcpu *vcpu)
352 {
353 if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
354 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
355 else
356 vcpu->arch.mmu.inject_page_fault(vcpu);
357
358 vcpu->arch.fault.nested = false;
359 }
360
361 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
362 {
363 kvm_make_request(KVM_REQ_EVENT, vcpu);
364 vcpu->arch.nmi_pending = 1;
365 }
366 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
367
368 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
369 {
370 kvm_multiple_exception(vcpu, nr, true, error_code, false);
371 }
372 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
373
374 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375 {
376 kvm_multiple_exception(vcpu, nr, true, error_code, true);
377 }
378 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
379
380 /*
381 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
382 * a #GP and return false.
383 */
384 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
385 {
386 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
387 return true;
388 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
389 return false;
390 }
391 EXPORT_SYMBOL_GPL(kvm_require_cpl);
392
393 /*
394 * This function will be used to read from the physical memory of the currently
395 * running guest. The difference to kvm_read_guest_page is that this function
396 * can read from guest physical or from the guest's guest physical memory.
397 */
398 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
399 gfn_t ngfn, void *data, int offset, int len,
400 u32 access)
401 {
402 gfn_t real_gfn;
403 gpa_t ngpa;
404
405 ngpa = gfn_to_gpa(ngfn);
406 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
407 if (real_gfn == UNMAPPED_GVA)
408 return -EFAULT;
409
410 real_gfn = gpa_to_gfn(real_gfn);
411
412 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
413 }
414 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
415
416 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
417 void *data, int offset, int len, u32 access)
418 {
419 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
420 data, offset, len, access);
421 }
422
423 /*
424 * Load the pae pdptrs. Return true is they are all valid.
425 */
426 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
427 {
428 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
429 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
430 int i;
431 int ret;
432 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
433
434 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
435 offset * sizeof(u64), sizeof(pdpte),
436 PFERR_USER_MASK|PFERR_WRITE_MASK);
437 if (ret < 0) {
438 ret = 0;
439 goto out;
440 }
441 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
442 if (is_present_gpte(pdpte[i]) &&
443 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
444 ret = 0;
445 goto out;
446 }
447 }
448 ret = 1;
449
450 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_avail);
453 __set_bit(VCPU_EXREG_PDPTR,
454 (unsigned long *)&vcpu->arch.regs_dirty);
455 out:
456
457 return ret;
458 }
459 EXPORT_SYMBOL_GPL(load_pdptrs);
460
461 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
462 {
463 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
464 bool changed = true;
465 int offset;
466 gfn_t gfn;
467 int r;
468
469 if (is_long_mode(vcpu) || !is_pae(vcpu))
470 return false;
471
472 if (!test_bit(VCPU_EXREG_PDPTR,
473 (unsigned long *)&vcpu->arch.regs_avail))
474 return true;
475
476 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
477 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
478 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
479 PFERR_USER_MASK | PFERR_WRITE_MASK);
480 if (r < 0)
481 goto out;
482 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
483 out:
484
485 return changed;
486 }
487
488 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
489 {
490 unsigned long old_cr0 = kvm_read_cr0(vcpu);
491 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
492 X86_CR0_CD | X86_CR0_NW;
493
494 cr0 |= X86_CR0_ET;
495
496 #ifdef CONFIG_X86_64
497 if (cr0 & 0xffffffff00000000UL)
498 return 1;
499 #endif
500
501 cr0 &= ~CR0_RESERVED_BITS;
502
503 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
504 return 1;
505
506 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
507 return 1;
508
509 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
510 #ifdef CONFIG_X86_64
511 if ((vcpu->arch.efer & EFER_LME)) {
512 int cs_db, cs_l;
513
514 if (!is_pae(vcpu))
515 return 1;
516 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
517 if (cs_l)
518 return 1;
519 } else
520 #endif
521 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
522 vcpu->arch.cr3))
523 return 1;
524 }
525
526 kvm_x86_ops->set_cr0(vcpu, cr0);
527
528 if ((cr0 ^ old_cr0) & update_bits)
529 kvm_mmu_reset_context(vcpu);
530 return 0;
531 }
532 EXPORT_SYMBOL_GPL(kvm_set_cr0);
533
534 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
535 {
536 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
537 }
538 EXPORT_SYMBOL_GPL(kvm_lmsw);
539
540 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
541 {
542 u64 xcr0;
543
544 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
545 if (index != XCR_XFEATURE_ENABLED_MASK)
546 return 1;
547 xcr0 = xcr;
548 if (kvm_x86_ops->get_cpl(vcpu) != 0)
549 return 1;
550 if (!(xcr0 & XSTATE_FP))
551 return 1;
552 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
553 return 1;
554 if (xcr0 & ~host_xcr0)
555 return 1;
556 vcpu->arch.xcr0 = xcr0;
557 vcpu->guest_xcr0_loaded = 0;
558 return 0;
559 }
560
561 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
562 {
563 if (__kvm_set_xcr(vcpu, index, xcr)) {
564 kvm_inject_gp(vcpu, 0);
565 return 1;
566 }
567 return 0;
568 }
569 EXPORT_SYMBOL_GPL(kvm_set_xcr);
570
571 static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
572 {
573 struct kvm_cpuid_entry2 *best;
574
575 best = kvm_find_cpuid_entry(vcpu, 1, 0);
576 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
577 }
578
579 static void update_cpuid(struct kvm_vcpu *vcpu)
580 {
581 struct kvm_cpuid_entry2 *best;
582
583 best = kvm_find_cpuid_entry(vcpu, 1, 0);
584 if (!best)
585 return;
586
587 /* Update OSXSAVE bit */
588 if (cpu_has_xsave && best->function == 0x1) {
589 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
590 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
591 best->ecx |= bit(X86_FEATURE_OSXSAVE);
592 }
593 }
594
595 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
596 {
597 unsigned long old_cr4 = kvm_read_cr4(vcpu);
598 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
599
600 if (cr4 & CR4_RESERVED_BITS)
601 return 1;
602
603 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
604 return 1;
605
606 if (is_long_mode(vcpu)) {
607 if (!(cr4 & X86_CR4_PAE))
608 return 1;
609 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
610 && ((cr4 ^ old_cr4) & pdptr_bits)
611 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
612 return 1;
613
614 if (cr4 & X86_CR4_VMXE)
615 return 1;
616
617 kvm_x86_ops->set_cr4(vcpu, cr4);
618
619 if ((cr4 ^ old_cr4) & pdptr_bits)
620 kvm_mmu_reset_context(vcpu);
621
622 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
623 update_cpuid(vcpu);
624
625 return 0;
626 }
627 EXPORT_SYMBOL_GPL(kvm_set_cr4);
628
629 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
630 {
631 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
632 kvm_mmu_sync_roots(vcpu);
633 kvm_mmu_flush_tlb(vcpu);
634 return 0;
635 }
636
637 if (is_long_mode(vcpu)) {
638 if (cr3 & CR3_L_MODE_RESERVED_BITS)
639 return 1;
640 } else {
641 if (is_pae(vcpu)) {
642 if (cr3 & CR3_PAE_RESERVED_BITS)
643 return 1;
644 if (is_paging(vcpu) &&
645 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
646 return 1;
647 }
648 /*
649 * We don't check reserved bits in nonpae mode, because
650 * this isn't enforced, and VMware depends on this.
651 */
652 }
653
654 /*
655 * Does the new cr3 value map to physical memory? (Note, we
656 * catch an invalid cr3 even in real-mode, because it would
657 * cause trouble later on when we turn on paging anyway.)
658 *
659 * A real CPU would silently accept an invalid cr3 and would
660 * attempt to use it - with largely undefined (and often hard
661 * to debug) behavior on the guest side.
662 */
663 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
664 return 1;
665 vcpu->arch.cr3 = cr3;
666 vcpu->arch.mmu.new_cr3(vcpu);
667 return 0;
668 }
669 EXPORT_SYMBOL_GPL(kvm_set_cr3);
670
671 int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
672 {
673 if (cr8 & CR8_RESERVED_BITS)
674 return 1;
675 if (irqchip_in_kernel(vcpu->kvm))
676 kvm_lapic_set_tpr(vcpu, cr8);
677 else
678 vcpu->arch.cr8 = cr8;
679 return 0;
680 }
681
682 void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
683 {
684 if (__kvm_set_cr8(vcpu, cr8))
685 kvm_inject_gp(vcpu, 0);
686 }
687 EXPORT_SYMBOL_GPL(kvm_set_cr8);
688
689 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
690 {
691 if (irqchip_in_kernel(vcpu->kvm))
692 return kvm_lapic_get_cr8(vcpu);
693 else
694 return vcpu->arch.cr8;
695 }
696 EXPORT_SYMBOL_GPL(kvm_get_cr8);
697
698 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
699 {
700 switch (dr) {
701 case 0 ... 3:
702 vcpu->arch.db[dr] = val;
703 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
704 vcpu->arch.eff_db[dr] = val;
705 break;
706 case 4:
707 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
708 return 1; /* #UD */
709 /* fall through */
710 case 6:
711 if (val & 0xffffffff00000000ULL)
712 return -1; /* #GP */
713 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
714 break;
715 case 5:
716 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
717 return 1; /* #UD */
718 /* fall through */
719 default: /* 7 */
720 if (val & 0xffffffff00000000ULL)
721 return -1; /* #GP */
722 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
723 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
724 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
725 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
726 }
727 break;
728 }
729
730 return 0;
731 }
732
733 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
734 {
735 int res;
736
737 res = __kvm_set_dr(vcpu, dr, val);
738 if (res > 0)
739 kvm_queue_exception(vcpu, UD_VECTOR);
740 else if (res < 0)
741 kvm_inject_gp(vcpu, 0);
742
743 return res;
744 }
745 EXPORT_SYMBOL_GPL(kvm_set_dr);
746
747 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
748 {
749 switch (dr) {
750 case 0 ... 3:
751 *val = vcpu->arch.db[dr];
752 break;
753 case 4:
754 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
755 return 1;
756 /* fall through */
757 case 6:
758 *val = vcpu->arch.dr6;
759 break;
760 case 5:
761 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
762 return 1;
763 /* fall through */
764 default: /* 7 */
765 *val = vcpu->arch.dr7;
766 break;
767 }
768
769 return 0;
770 }
771
772 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
773 {
774 if (_kvm_get_dr(vcpu, dr, val)) {
775 kvm_queue_exception(vcpu, UD_VECTOR);
776 return 1;
777 }
778 return 0;
779 }
780 EXPORT_SYMBOL_GPL(kvm_get_dr);
781
782 /*
783 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
784 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
785 *
786 * This list is modified at module load time to reflect the
787 * capabilities of the host cpu. This capabilities test skips MSRs that are
788 * kvm-specific. Those are put in the beginning of the list.
789 */
790
791 #define KVM_SAVE_MSRS_BEGIN 8
792 static u32 msrs_to_save[] = {
793 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
794 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
795 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
796 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
797 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
798 MSR_STAR,
799 #ifdef CONFIG_X86_64
800 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
801 #endif
802 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
803 };
804
805 static unsigned num_msrs_to_save;
806
807 static u32 emulated_msrs[] = {
808 MSR_IA32_MISC_ENABLE,
809 MSR_IA32_MCG_STATUS,
810 MSR_IA32_MCG_CTL,
811 };
812
813 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
814 {
815 u64 old_efer = vcpu->arch.efer;
816
817 if (efer & efer_reserved_bits)
818 return 1;
819
820 if (is_paging(vcpu)
821 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
822 return 1;
823
824 if (efer & EFER_FFXSR) {
825 struct kvm_cpuid_entry2 *feat;
826
827 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
828 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
829 return 1;
830 }
831
832 if (efer & EFER_SVME) {
833 struct kvm_cpuid_entry2 *feat;
834
835 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
836 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
837 return 1;
838 }
839
840 efer &= ~EFER_LMA;
841 efer |= vcpu->arch.efer & EFER_LMA;
842
843 kvm_x86_ops->set_efer(vcpu, efer);
844
845 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
846
847 /* Update reserved bits */
848 if ((efer ^ old_efer) & EFER_NX)
849 kvm_mmu_reset_context(vcpu);
850
851 return 0;
852 }
853
854 void kvm_enable_efer_bits(u64 mask)
855 {
856 efer_reserved_bits &= ~mask;
857 }
858 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
859
860
861 /*
862 * Writes msr value into into the appropriate "register".
863 * Returns 0 on success, non-0 otherwise.
864 * Assumes vcpu_load() was already called.
865 */
866 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
867 {
868 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
869 }
870
871 /*
872 * Adapt set_msr() to msr_io()'s calling convention
873 */
874 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
875 {
876 return kvm_set_msr(vcpu, index, *data);
877 }
878
879 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
880 {
881 int version;
882 int r;
883 struct pvclock_wall_clock wc;
884 struct timespec boot;
885
886 if (!wall_clock)
887 return;
888
889 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
890 if (r)
891 return;
892
893 if (version & 1)
894 ++version; /* first time write, random junk */
895
896 ++version;
897
898 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
899
900 /*
901 * The guest calculates current wall clock time by adding
902 * system time (updated by kvm_guest_time_update below) to the
903 * wall clock specified here. guest system time equals host
904 * system time for us, thus we must fill in host boot time here.
905 */
906 getboottime(&boot);
907
908 wc.sec = boot.tv_sec;
909 wc.nsec = boot.tv_nsec;
910 wc.version = version;
911
912 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
913
914 version++;
915 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
916 }
917
918 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
919 {
920 uint32_t quotient, remainder;
921
922 /* Don't try to replace with do_div(), this one calculates
923 * "(dividend << 32) / divisor" */
924 __asm__ ( "divl %4"
925 : "=a" (quotient), "=d" (remainder)
926 : "0" (0), "1" (dividend), "r" (divisor) );
927 return quotient;
928 }
929
930 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
931 s8 *pshift, u32 *pmultiplier)
932 {
933 uint64_t scaled64;
934 int32_t shift = 0;
935 uint64_t tps64;
936 uint32_t tps32;
937
938 tps64 = base_khz * 1000LL;
939 scaled64 = scaled_khz * 1000LL;
940 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
941 tps64 >>= 1;
942 shift--;
943 }
944
945 tps32 = (uint32_t)tps64;
946 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
947 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
948 scaled64 >>= 1;
949 else
950 tps32 <<= 1;
951 shift++;
952 }
953
954 *pshift = shift;
955 *pmultiplier = div_frac(scaled64, tps32);
956
957 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
958 __func__, base_khz, scaled_khz, shift, *pmultiplier);
959 }
960
961 static inline u64 get_kernel_ns(void)
962 {
963 struct timespec ts;
964
965 WARN_ON(preemptible());
966 ktime_get_ts(&ts);
967 monotonic_to_bootbased(&ts);
968 return timespec_to_ns(&ts);
969 }
970
971 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
972 unsigned long max_tsc_khz;
973
974 static inline int kvm_tsc_changes_freq(void)
975 {
976 int cpu = get_cpu();
977 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
978 cpufreq_quick_get(cpu) != 0;
979 put_cpu();
980 return ret;
981 }
982
983 static inline u64 nsec_to_cycles(u64 nsec)
984 {
985 u64 ret;
986
987 WARN_ON(preemptible());
988 if (kvm_tsc_changes_freq())
989 printk_once(KERN_WARNING
990 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
991 ret = nsec * __get_cpu_var(cpu_tsc_khz);
992 do_div(ret, USEC_PER_SEC);
993 return ret;
994 }
995
996 static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
997 {
998 /* Compute a scale to convert nanoseconds in TSC cycles */
999 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1000 &kvm->arch.virtual_tsc_shift,
1001 &kvm->arch.virtual_tsc_mult);
1002 kvm->arch.virtual_tsc_khz = this_tsc_khz;
1003 }
1004
1005 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1006 {
1007 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1008 vcpu->kvm->arch.virtual_tsc_mult,
1009 vcpu->kvm->arch.virtual_tsc_shift);
1010 tsc += vcpu->arch.last_tsc_write;
1011 return tsc;
1012 }
1013
1014 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1015 {
1016 struct kvm *kvm = vcpu->kvm;
1017 u64 offset, ns, elapsed;
1018 unsigned long flags;
1019 s64 sdiff;
1020
1021 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1022 offset = data - native_read_tsc();
1023 ns = get_kernel_ns();
1024 elapsed = ns - kvm->arch.last_tsc_nsec;
1025 sdiff = data - kvm->arch.last_tsc_write;
1026 if (sdiff < 0)
1027 sdiff = -sdiff;
1028
1029 /*
1030 * Special case: close write to TSC within 5 seconds of
1031 * another CPU is interpreted as an attempt to synchronize
1032 * The 5 seconds is to accomodate host load / swapping as
1033 * well as any reset of TSC during the boot process.
1034 *
1035 * In that case, for a reliable TSC, we can match TSC offsets,
1036 * or make a best guest using elapsed value.
1037 */
1038 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1039 elapsed < 5ULL * NSEC_PER_SEC) {
1040 if (!check_tsc_unstable()) {
1041 offset = kvm->arch.last_tsc_offset;
1042 pr_debug("kvm: matched tsc offset for %llu\n", data);
1043 } else {
1044 u64 delta = nsec_to_cycles(elapsed);
1045 offset += delta;
1046 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1047 }
1048 ns = kvm->arch.last_tsc_nsec;
1049 }
1050 kvm->arch.last_tsc_nsec = ns;
1051 kvm->arch.last_tsc_write = data;
1052 kvm->arch.last_tsc_offset = offset;
1053 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1054 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1055
1056 /* Reset of TSC must disable overshoot protection below */
1057 vcpu->arch.hv_clock.tsc_timestamp = 0;
1058 vcpu->arch.last_tsc_write = data;
1059 vcpu->arch.last_tsc_nsec = ns;
1060 }
1061 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1062
1063 static int kvm_guest_time_update(struct kvm_vcpu *v)
1064 {
1065 unsigned long flags;
1066 struct kvm_vcpu_arch *vcpu = &v->arch;
1067 void *shared_kaddr;
1068 unsigned long this_tsc_khz;
1069 s64 kernel_ns, max_kernel_ns;
1070 u64 tsc_timestamp;
1071
1072 /* Keep irq disabled to prevent changes to the clock */
1073 local_irq_save(flags);
1074 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
1075 kernel_ns = get_kernel_ns();
1076 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1077
1078 if (unlikely(this_tsc_khz == 0)) {
1079 local_irq_restore(flags);
1080 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1081 return 1;
1082 }
1083
1084 /*
1085 * We may have to catch up the TSC to match elapsed wall clock
1086 * time for two reasons, even if kvmclock is used.
1087 * 1) CPU could have been running below the maximum TSC rate
1088 * 2) Broken TSC compensation resets the base at each VCPU
1089 * entry to avoid unknown leaps of TSC even when running
1090 * again on the same CPU. This may cause apparent elapsed
1091 * time to disappear, and the guest to stand still or run
1092 * very slowly.
1093 */
1094 if (vcpu->tsc_catchup) {
1095 u64 tsc = compute_guest_tsc(v, kernel_ns);
1096 if (tsc > tsc_timestamp) {
1097 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1098 tsc_timestamp = tsc;
1099 }
1100 }
1101
1102 local_irq_restore(flags);
1103
1104 if (!vcpu->time_page)
1105 return 0;
1106
1107 /*
1108 * Time as measured by the TSC may go backwards when resetting the base
1109 * tsc_timestamp. The reason for this is that the TSC resolution is
1110 * higher than the resolution of the other clock scales. Thus, many
1111 * possible measurments of the TSC correspond to one measurement of any
1112 * other clock, and so a spread of values is possible. This is not a
1113 * problem for the computation of the nanosecond clock; with TSC rates
1114 * around 1GHZ, there can only be a few cycles which correspond to one
1115 * nanosecond value, and any path through this code will inevitably
1116 * take longer than that. However, with the kernel_ns value itself,
1117 * the precision may be much lower, down to HZ granularity. If the
1118 * first sampling of TSC against kernel_ns ends in the low part of the
1119 * range, and the second in the high end of the range, we can get:
1120 *
1121 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1122 *
1123 * As the sampling errors potentially range in the thousands of cycles,
1124 * it is possible such a time value has already been observed by the
1125 * guest. To protect against this, we must compute the system time as
1126 * observed by the guest and ensure the new system time is greater.
1127 */
1128 max_kernel_ns = 0;
1129 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1130 max_kernel_ns = vcpu->last_guest_tsc -
1131 vcpu->hv_clock.tsc_timestamp;
1132 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1133 vcpu->hv_clock.tsc_to_system_mul,
1134 vcpu->hv_clock.tsc_shift);
1135 max_kernel_ns += vcpu->last_kernel_ns;
1136 }
1137
1138 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1139 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1140 &vcpu->hv_clock.tsc_shift,
1141 &vcpu->hv_clock.tsc_to_system_mul);
1142 vcpu->hw_tsc_khz = this_tsc_khz;
1143 }
1144
1145 if (max_kernel_ns > kernel_ns)
1146 kernel_ns = max_kernel_ns;
1147
1148 /* With all the info we got, fill in the values */
1149 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1150 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1151 vcpu->last_kernel_ns = kernel_ns;
1152 vcpu->last_guest_tsc = tsc_timestamp;
1153 vcpu->hv_clock.flags = 0;
1154
1155 /*
1156 * The interface expects us to write an even number signaling that the
1157 * update is finished. Since the guest won't see the intermediate
1158 * state, we just increase by 2 at the end.
1159 */
1160 vcpu->hv_clock.version += 2;
1161
1162 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1163
1164 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1165 sizeof(vcpu->hv_clock));
1166
1167 kunmap_atomic(shared_kaddr, KM_USER0);
1168
1169 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1170 return 0;
1171 }
1172
1173 static bool msr_mtrr_valid(unsigned msr)
1174 {
1175 switch (msr) {
1176 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1177 case MSR_MTRRfix64K_00000:
1178 case MSR_MTRRfix16K_80000:
1179 case MSR_MTRRfix16K_A0000:
1180 case MSR_MTRRfix4K_C0000:
1181 case MSR_MTRRfix4K_C8000:
1182 case MSR_MTRRfix4K_D0000:
1183 case MSR_MTRRfix4K_D8000:
1184 case MSR_MTRRfix4K_E0000:
1185 case MSR_MTRRfix4K_E8000:
1186 case MSR_MTRRfix4K_F0000:
1187 case MSR_MTRRfix4K_F8000:
1188 case MSR_MTRRdefType:
1189 case MSR_IA32_CR_PAT:
1190 return true;
1191 case 0x2f8:
1192 return true;
1193 }
1194 return false;
1195 }
1196
1197 static bool valid_pat_type(unsigned t)
1198 {
1199 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1200 }
1201
1202 static bool valid_mtrr_type(unsigned t)
1203 {
1204 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1205 }
1206
1207 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1208 {
1209 int i;
1210
1211 if (!msr_mtrr_valid(msr))
1212 return false;
1213
1214 if (msr == MSR_IA32_CR_PAT) {
1215 for (i = 0; i < 8; i++)
1216 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1217 return false;
1218 return true;
1219 } else if (msr == MSR_MTRRdefType) {
1220 if (data & ~0xcff)
1221 return false;
1222 return valid_mtrr_type(data & 0xff);
1223 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1224 for (i = 0; i < 8 ; i++)
1225 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1226 return false;
1227 return true;
1228 }
1229
1230 /* variable MTRRs */
1231 return valid_mtrr_type(data & 0xff);
1232 }
1233
1234 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1235 {
1236 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1237
1238 if (!mtrr_valid(vcpu, msr, data))
1239 return 1;
1240
1241 if (msr == MSR_MTRRdefType) {
1242 vcpu->arch.mtrr_state.def_type = data;
1243 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1244 } else if (msr == MSR_MTRRfix64K_00000)
1245 p[0] = data;
1246 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1247 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1248 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1249 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1250 else if (msr == MSR_IA32_CR_PAT)
1251 vcpu->arch.pat = data;
1252 else { /* Variable MTRRs */
1253 int idx, is_mtrr_mask;
1254 u64 *pt;
1255
1256 idx = (msr - 0x200) / 2;
1257 is_mtrr_mask = msr - 0x200 - 2 * idx;
1258 if (!is_mtrr_mask)
1259 pt =
1260 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1261 else
1262 pt =
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1264 *pt = data;
1265 }
1266
1267 kvm_mmu_reset_context(vcpu);
1268 return 0;
1269 }
1270
1271 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1272 {
1273 u64 mcg_cap = vcpu->arch.mcg_cap;
1274 unsigned bank_num = mcg_cap & 0xff;
1275
1276 switch (msr) {
1277 case MSR_IA32_MCG_STATUS:
1278 vcpu->arch.mcg_status = data;
1279 break;
1280 case MSR_IA32_MCG_CTL:
1281 if (!(mcg_cap & MCG_CTL_P))
1282 return 1;
1283 if (data != 0 && data != ~(u64)0)
1284 return -1;
1285 vcpu->arch.mcg_ctl = data;
1286 break;
1287 default:
1288 if (msr >= MSR_IA32_MC0_CTL &&
1289 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1290 u32 offset = msr - MSR_IA32_MC0_CTL;
1291 /* only 0 or all 1s can be written to IA32_MCi_CTL
1292 * some Linux kernels though clear bit 10 in bank 4 to
1293 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1294 * this to avoid an uncatched #GP in the guest
1295 */
1296 if ((offset & 0x3) == 0 &&
1297 data != 0 && (data | (1 << 10)) != ~(u64)0)
1298 return -1;
1299 vcpu->arch.mce_banks[offset] = data;
1300 break;
1301 }
1302 return 1;
1303 }
1304 return 0;
1305 }
1306
1307 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1308 {
1309 struct kvm *kvm = vcpu->kvm;
1310 int lm = is_long_mode(vcpu);
1311 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1312 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1313 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1314 : kvm->arch.xen_hvm_config.blob_size_32;
1315 u32 page_num = data & ~PAGE_MASK;
1316 u64 page_addr = data & PAGE_MASK;
1317 u8 *page;
1318 int r;
1319
1320 r = -E2BIG;
1321 if (page_num >= blob_size)
1322 goto out;
1323 r = -ENOMEM;
1324 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1325 if (!page)
1326 goto out;
1327 r = -EFAULT;
1328 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1329 goto out_free;
1330 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1331 goto out_free;
1332 r = 0;
1333 out_free:
1334 kfree(page);
1335 out:
1336 return r;
1337 }
1338
1339 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1340 {
1341 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1342 }
1343
1344 static bool kvm_hv_msr_partition_wide(u32 msr)
1345 {
1346 bool r = false;
1347 switch (msr) {
1348 case HV_X64_MSR_GUEST_OS_ID:
1349 case HV_X64_MSR_HYPERCALL:
1350 r = true;
1351 break;
1352 }
1353
1354 return r;
1355 }
1356
1357 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1358 {
1359 struct kvm *kvm = vcpu->kvm;
1360
1361 switch (msr) {
1362 case HV_X64_MSR_GUEST_OS_ID:
1363 kvm->arch.hv_guest_os_id = data;
1364 /* setting guest os id to zero disables hypercall page */
1365 if (!kvm->arch.hv_guest_os_id)
1366 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1367 break;
1368 case HV_X64_MSR_HYPERCALL: {
1369 u64 gfn;
1370 unsigned long addr;
1371 u8 instructions[4];
1372
1373 /* if guest os id is not set hypercall should remain disabled */
1374 if (!kvm->arch.hv_guest_os_id)
1375 break;
1376 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1377 kvm->arch.hv_hypercall = data;
1378 break;
1379 }
1380 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1381 addr = gfn_to_hva(kvm, gfn);
1382 if (kvm_is_error_hva(addr))
1383 return 1;
1384 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1385 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1386 if (copy_to_user((void __user *)addr, instructions, 4))
1387 return 1;
1388 kvm->arch.hv_hypercall = data;
1389 break;
1390 }
1391 default:
1392 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1393 "data 0x%llx\n", msr, data);
1394 return 1;
1395 }
1396 return 0;
1397 }
1398
1399 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1400 {
1401 switch (msr) {
1402 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1403 unsigned long addr;
1404
1405 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1406 vcpu->arch.hv_vapic = data;
1407 break;
1408 }
1409 addr = gfn_to_hva(vcpu->kvm, data >>
1410 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1411 if (kvm_is_error_hva(addr))
1412 return 1;
1413 if (clear_user((void __user *)addr, PAGE_SIZE))
1414 return 1;
1415 vcpu->arch.hv_vapic = data;
1416 break;
1417 }
1418 case HV_X64_MSR_EOI:
1419 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1420 case HV_X64_MSR_ICR:
1421 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1422 case HV_X64_MSR_TPR:
1423 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1424 default:
1425 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1426 "data 0x%llx\n", msr, data);
1427 return 1;
1428 }
1429
1430 return 0;
1431 }
1432
1433 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1434 {
1435 gpa_t gpa = data & ~0x3f;
1436
1437 /* Bits 2:5 are resrved, Should be zero */
1438 if (data & 0x3c)
1439 return 1;
1440
1441 vcpu->arch.apf.msr_val = data;
1442
1443 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1444 kvm_clear_async_pf_completion_queue(vcpu);
1445 kvm_async_pf_hash_reset(vcpu);
1446 return 0;
1447 }
1448
1449 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1450 return 1;
1451
1452 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1453 kvm_async_pf_wakeup_all(vcpu);
1454 return 0;
1455 }
1456
1457 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1458 {
1459 switch (msr) {
1460 case MSR_EFER:
1461 return set_efer(vcpu, data);
1462 case MSR_K7_HWCR:
1463 data &= ~(u64)0x40; /* ignore flush filter disable */
1464 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1465 if (data != 0) {
1466 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1467 data);
1468 return 1;
1469 }
1470 break;
1471 case MSR_FAM10H_MMIO_CONF_BASE:
1472 if (data != 0) {
1473 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1474 "0x%llx\n", data);
1475 return 1;
1476 }
1477 break;
1478 case MSR_AMD64_NB_CFG:
1479 break;
1480 case MSR_IA32_DEBUGCTLMSR:
1481 if (!data) {
1482 /* We support the non-activated case already */
1483 break;
1484 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1485 /* Values other than LBR and BTF are vendor-specific,
1486 thus reserved and should throw a #GP */
1487 return 1;
1488 }
1489 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1490 __func__, data);
1491 break;
1492 case MSR_IA32_UCODE_REV:
1493 case MSR_IA32_UCODE_WRITE:
1494 case MSR_VM_HSAVE_PA:
1495 case MSR_AMD64_PATCH_LOADER:
1496 break;
1497 case 0x200 ... 0x2ff:
1498 return set_msr_mtrr(vcpu, msr, data);
1499 case MSR_IA32_APICBASE:
1500 kvm_set_apic_base(vcpu, data);
1501 break;
1502 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1503 return kvm_x2apic_msr_write(vcpu, msr, data);
1504 case MSR_IA32_MISC_ENABLE:
1505 vcpu->arch.ia32_misc_enable_msr = data;
1506 break;
1507 case MSR_KVM_WALL_CLOCK_NEW:
1508 case MSR_KVM_WALL_CLOCK:
1509 vcpu->kvm->arch.wall_clock = data;
1510 kvm_write_wall_clock(vcpu->kvm, data);
1511 break;
1512 case MSR_KVM_SYSTEM_TIME_NEW:
1513 case MSR_KVM_SYSTEM_TIME: {
1514 if (vcpu->arch.time_page) {
1515 kvm_release_page_dirty(vcpu->arch.time_page);
1516 vcpu->arch.time_page = NULL;
1517 }
1518
1519 vcpu->arch.time = data;
1520 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1521
1522 /* we verify if the enable bit is set... */
1523 if (!(data & 1))
1524 break;
1525
1526 /* ...but clean it before doing the actual write */
1527 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1528
1529 vcpu->arch.time_page =
1530 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1531
1532 if (is_error_page(vcpu->arch.time_page)) {
1533 kvm_release_page_clean(vcpu->arch.time_page);
1534 vcpu->arch.time_page = NULL;
1535 }
1536 break;
1537 }
1538 case MSR_KVM_ASYNC_PF_EN:
1539 if (kvm_pv_enable_async_pf(vcpu, data))
1540 return 1;
1541 break;
1542 case MSR_IA32_MCG_CTL:
1543 case MSR_IA32_MCG_STATUS:
1544 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1545 return set_msr_mce(vcpu, msr, data);
1546
1547 /* Performance counters are not protected by a CPUID bit,
1548 * so we should check all of them in the generic path for the sake of
1549 * cross vendor migration.
1550 * Writing a zero into the event select MSRs disables them,
1551 * which we perfectly emulate ;-). Any other value should be at least
1552 * reported, some guests depend on them.
1553 */
1554 case MSR_P6_EVNTSEL0:
1555 case MSR_P6_EVNTSEL1:
1556 case MSR_K7_EVNTSEL0:
1557 case MSR_K7_EVNTSEL1:
1558 case MSR_K7_EVNTSEL2:
1559 case MSR_K7_EVNTSEL3:
1560 if (data != 0)
1561 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1562 "0x%x data 0x%llx\n", msr, data);
1563 break;
1564 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1565 * so we ignore writes to make it happy.
1566 */
1567 case MSR_P6_PERFCTR0:
1568 case MSR_P6_PERFCTR1:
1569 case MSR_K7_PERFCTR0:
1570 case MSR_K7_PERFCTR1:
1571 case MSR_K7_PERFCTR2:
1572 case MSR_K7_PERFCTR3:
1573 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1574 "0x%x data 0x%llx\n", msr, data);
1575 break;
1576 case MSR_K7_CLK_CTL:
1577 /*
1578 * Ignore all writes to this no longer documented MSR.
1579 * Writes are only relevant for old K7 processors,
1580 * all pre-dating SVM, but a recommended workaround from
1581 * AMD for these chips. It is possible to speicify the
1582 * affected processor models on the command line, hence
1583 * the need to ignore the workaround.
1584 */
1585 break;
1586 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1587 if (kvm_hv_msr_partition_wide(msr)) {
1588 int r;
1589 mutex_lock(&vcpu->kvm->lock);
1590 r = set_msr_hyperv_pw(vcpu, msr, data);
1591 mutex_unlock(&vcpu->kvm->lock);
1592 return r;
1593 } else
1594 return set_msr_hyperv(vcpu, msr, data);
1595 break;
1596 default:
1597 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1598 return xen_hvm_config(vcpu, data);
1599 if (!ignore_msrs) {
1600 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1601 msr, data);
1602 return 1;
1603 } else {
1604 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1605 msr, data);
1606 break;
1607 }
1608 }
1609 return 0;
1610 }
1611 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1612
1613
1614 /*
1615 * Reads an msr value (of 'msr_index') into 'pdata'.
1616 * Returns 0 on success, non-0 otherwise.
1617 * Assumes vcpu_load() was already called.
1618 */
1619 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1620 {
1621 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1622 }
1623
1624 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1625 {
1626 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1627
1628 if (!msr_mtrr_valid(msr))
1629 return 1;
1630
1631 if (msr == MSR_MTRRdefType)
1632 *pdata = vcpu->arch.mtrr_state.def_type +
1633 (vcpu->arch.mtrr_state.enabled << 10);
1634 else if (msr == MSR_MTRRfix64K_00000)
1635 *pdata = p[0];
1636 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1637 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1638 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1639 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1640 else if (msr == MSR_IA32_CR_PAT)
1641 *pdata = vcpu->arch.pat;
1642 else { /* Variable MTRRs */
1643 int idx, is_mtrr_mask;
1644 u64 *pt;
1645
1646 idx = (msr - 0x200) / 2;
1647 is_mtrr_mask = msr - 0x200 - 2 * idx;
1648 if (!is_mtrr_mask)
1649 pt =
1650 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1651 else
1652 pt =
1653 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1654 *pdata = *pt;
1655 }
1656
1657 return 0;
1658 }
1659
1660 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1661 {
1662 u64 data;
1663 u64 mcg_cap = vcpu->arch.mcg_cap;
1664 unsigned bank_num = mcg_cap & 0xff;
1665
1666 switch (msr) {
1667 case MSR_IA32_P5_MC_ADDR:
1668 case MSR_IA32_P5_MC_TYPE:
1669 data = 0;
1670 break;
1671 case MSR_IA32_MCG_CAP:
1672 data = vcpu->arch.mcg_cap;
1673 break;
1674 case MSR_IA32_MCG_CTL:
1675 if (!(mcg_cap & MCG_CTL_P))
1676 return 1;
1677 data = vcpu->arch.mcg_ctl;
1678 break;
1679 case MSR_IA32_MCG_STATUS:
1680 data = vcpu->arch.mcg_status;
1681 break;
1682 default:
1683 if (msr >= MSR_IA32_MC0_CTL &&
1684 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1685 u32 offset = msr - MSR_IA32_MC0_CTL;
1686 data = vcpu->arch.mce_banks[offset];
1687 break;
1688 }
1689 return 1;
1690 }
1691 *pdata = data;
1692 return 0;
1693 }
1694
1695 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1696 {
1697 u64 data = 0;
1698 struct kvm *kvm = vcpu->kvm;
1699
1700 switch (msr) {
1701 case HV_X64_MSR_GUEST_OS_ID:
1702 data = kvm->arch.hv_guest_os_id;
1703 break;
1704 case HV_X64_MSR_HYPERCALL:
1705 data = kvm->arch.hv_hypercall;
1706 break;
1707 default:
1708 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1709 return 1;
1710 }
1711
1712 *pdata = data;
1713 return 0;
1714 }
1715
1716 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1717 {
1718 u64 data = 0;
1719
1720 switch (msr) {
1721 case HV_X64_MSR_VP_INDEX: {
1722 int r;
1723 struct kvm_vcpu *v;
1724 kvm_for_each_vcpu(r, v, vcpu->kvm)
1725 if (v == vcpu)
1726 data = r;
1727 break;
1728 }
1729 case HV_X64_MSR_EOI:
1730 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1731 case HV_X64_MSR_ICR:
1732 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1733 case HV_X64_MSR_TPR:
1734 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1735 default:
1736 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1737 return 1;
1738 }
1739 *pdata = data;
1740 return 0;
1741 }
1742
1743 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1744 {
1745 u64 data;
1746
1747 switch (msr) {
1748 case MSR_IA32_PLATFORM_ID:
1749 case MSR_IA32_UCODE_REV:
1750 case MSR_IA32_EBL_CR_POWERON:
1751 case MSR_IA32_DEBUGCTLMSR:
1752 case MSR_IA32_LASTBRANCHFROMIP:
1753 case MSR_IA32_LASTBRANCHTOIP:
1754 case MSR_IA32_LASTINTFROMIP:
1755 case MSR_IA32_LASTINTTOIP:
1756 case MSR_K8_SYSCFG:
1757 case MSR_K7_HWCR:
1758 case MSR_VM_HSAVE_PA:
1759 case MSR_P6_PERFCTR0:
1760 case MSR_P6_PERFCTR1:
1761 case MSR_P6_EVNTSEL0:
1762 case MSR_P6_EVNTSEL1:
1763 case MSR_K7_EVNTSEL0:
1764 case MSR_K7_PERFCTR0:
1765 case MSR_K8_INT_PENDING_MSG:
1766 case MSR_AMD64_NB_CFG:
1767 case MSR_FAM10H_MMIO_CONF_BASE:
1768 data = 0;
1769 break;
1770 case MSR_MTRRcap:
1771 data = 0x500 | KVM_NR_VAR_MTRR;
1772 break;
1773 case 0x200 ... 0x2ff:
1774 return get_msr_mtrr(vcpu, msr, pdata);
1775 case 0xcd: /* fsb frequency */
1776 data = 3;
1777 break;
1778 /*
1779 * MSR_EBC_FREQUENCY_ID
1780 * Conservative value valid for even the basic CPU models.
1781 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1782 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1783 * and 266MHz for model 3, or 4. Set Core Clock
1784 * Frequency to System Bus Frequency Ratio to 1 (bits
1785 * 31:24) even though these are only valid for CPU
1786 * models > 2, however guests may end up dividing or
1787 * multiplying by zero otherwise.
1788 */
1789 case MSR_EBC_FREQUENCY_ID:
1790 data = 1 << 24;
1791 break;
1792 case MSR_IA32_APICBASE:
1793 data = kvm_get_apic_base(vcpu);
1794 break;
1795 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1796 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1797 break;
1798 case MSR_IA32_MISC_ENABLE:
1799 data = vcpu->arch.ia32_misc_enable_msr;
1800 break;
1801 case MSR_IA32_PERF_STATUS:
1802 /* TSC increment by tick */
1803 data = 1000ULL;
1804 /* CPU multiplier */
1805 data |= (((uint64_t)4ULL) << 40);
1806 break;
1807 case MSR_EFER:
1808 data = vcpu->arch.efer;
1809 break;
1810 case MSR_KVM_WALL_CLOCK:
1811 case MSR_KVM_WALL_CLOCK_NEW:
1812 data = vcpu->kvm->arch.wall_clock;
1813 break;
1814 case MSR_KVM_SYSTEM_TIME:
1815 case MSR_KVM_SYSTEM_TIME_NEW:
1816 data = vcpu->arch.time;
1817 break;
1818 case MSR_KVM_ASYNC_PF_EN:
1819 data = vcpu->arch.apf.msr_val;
1820 break;
1821 case MSR_IA32_P5_MC_ADDR:
1822 case MSR_IA32_P5_MC_TYPE:
1823 case MSR_IA32_MCG_CAP:
1824 case MSR_IA32_MCG_CTL:
1825 case MSR_IA32_MCG_STATUS:
1826 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1827 return get_msr_mce(vcpu, msr, pdata);
1828 case MSR_K7_CLK_CTL:
1829 /*
1830 * Provide expected ramp-up count for K7. All other
1831 * are set to zero, indicating minimum divisors for
1832 * every field.
1833 *
1834 * This prevents guest kernels on AMD host with CPU
1835 * type 6, model 8 and higher from exploding due to
1836 * the rdmsr failing.
1837 */
1838 data = 0x20000000;
1839 break;
1840 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1841 if (kvm_hv_msr_partition_wide(msr)) {
1842 int r;
1843 mutex_lock(&vcpu->kvm->lock);
1844 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1845 mutex_unlock(&vcpu->kvm->lock);
1846 return r;
1847 } else
1848 return get_msr_hyperv(vcpu, msr, pdata);
1849 break;
1850 default:
1851 if (!ignore_msrs) {
1852 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1853 return 1;
1854 } else {
1855 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1856 data = 0;
1857 }
1858 break;
1859 }
1860 *pdata = data;
1861 return 0;
1862 }
1863 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1864
1865 /*
1866 * Read or write a bunch of msrs. All parameters are kernel addresses.
1867 *
1868 * @return number of msrs set successfully.
1869 */
1870 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1871 struct kvm_msr_entry *entries,
1872 int (*do_msr)(struct kvm_vcpu *vcpu,
1873 unsigned index, u64 *data))
1874 {
1875 int i, idx;
1876
1877 idx = srcu_read_lock(&vcpu->kvm->srcu);
1878 for (i = 0; i < msrs->nmsrs; ++i)
1879 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1880 break;
1881 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1882
1883 return i;
1884 }
1885
1886 /*
1887 * Read or write a bunch of msrs. Parameters are user addresses.
1888 *
1889 * @return number of msrs set successfully.
1890 */
1891 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1892 int (*do_msr)(struct kvm_vcpu *vcpu,
1893 unsigned index, u64 *data),
1894 int writeback)
1895 {
1896 struct kvm_msrs msrs;
1897 struct kvm_msr_entry *entries;
1898 int r, n;
1899 unsigned size;
1900
1901 r = -EFAULT;
1902 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1903 goto out;
1904
1905 r = -E2BIG;
1906 if (msrs.nmsrs >= MAX_IO_MSRS)
1907 goto out;
1908
1909 r = -ENOMEM;
1910 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1911 entries = kmalloc(size, GFP_KERNEL);
1912 if (!entries)
1913 goto out;
1914
1915 r = -EFAULT;
1916 if (copy_from_user(entries, user_msrs->entries, size))
1917 goto out_free;
1918
1919 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1920 if (r < 0)
1921 goto out_free;
1922
1923 r = -EFAULT;
1924 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1925 goto out_free;
1926
1927 r = n;
1928
1929 out_free:
1930 kfree(entries);
1931 out:
1932 return r;
1933 }
1934
1935 int kvm_dev_ioctl_check_extension(long ext)
1936 {
1937 int r;
1938
1939 switch (ext) {
1940 case KVM_CAP_IRQCHIP:
1941 case KVM_CAP_HLT:
1942 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1943 case KVM_CAP_SET_TSS_ADDR:
1944 case KVM_CAP_EXT_CPUID:
1945 case KVM_CAP_CLOCKSOURCE:
1946 case KVM_CAP_PIT:
1947 case KVM_CAP_NOP_IO_DELAY:
1948 case KVM_CAP_MP_STATE:
1949 case KVM_CAP_SYNC_MMU:
1950 case KVM_CAP_REINJECT_CONTROL:
1951 case KVM_CAP_IRQ_INJECT_STATUS:
1952 case KVM_CAP_ASSIGN_DEV_IRQ:
1953 case KVM_CAP_IRQFD:
1954 case KVM_CAP_IOEVENTFD:
1955 case KVM_CAP_PIT2:
1956 case KVM_CAP_PIT_STATE2:
1957 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
1958 case KVM_CAP_XEN_HVM:
1959 case KVM_CAP_ADJUST_CLOCK:
1960 case KVM_CAP_VCPU_EVENTS:
1961 case KVM_CAP_HYPERV:
1962 case KVM_CAP_HYPERV_VAPIC:
1963 case KVM_CAP_HYPERV_SPIN:
1964 case KVM_CAP_PCI_SEGMENT:
1965 case KVM_CAP_DEBUGREGS:
1966 case KVM_CAP_X86_ROBUST_SINGLESTEP:
1967 case KVM_CAP_XSAVE:
1968 case KVM_CAP_ASYNC_PF:
1969 r = 1;
1970 break;
1971 case KVM_CAP_COALESCED_MMIO:
1972 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1973 break;
1974 case KVM_CAP_VAPIC:
1975 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1976 break;
1977 case KVM_CAP_NR_VCPUS:
1978 r = KVM_MAX_VCPUS;
1979 break;
1980 case KVM_CAP_NR_MEMSLOTS:
1981 r = KVM_MEMORY_SLOTS;
1982 break;
1983 case KVM_CAP_PV_MMU: /* obsolete */
1984 r = 0;
1985 break;
1986 case KVM_CAP_IOMMU:
1987 r = iommu_found();
1988 break;
1989 case KVM_CAP_MCE:
1990 r = KVM_MAX_MCE_BANKS;
1991 break;
1992 case KVM_CAP_XCRS:
1993 r = cpu_has_xsave;
1994 break;
1995 default:
1996 r = 0;
1997 break;
1998 }
1999 return r;
2000
2001 }
2002
2003 long kvm_arch_dev_ioctl(struct file *filp,
2004 unsigned int ioctl, unsigned long arg)
2005 {
2006 void __user *argp = (void __user *)arg;
2007 long r;
2008
2009 switch (ioctl) {
2010 case KVM_GET_MSR_INDEX_LIST: {
2011 struct kvm_msr_list __user *user_msr_list = argp;
2012 struct kvm_msr_list msr_list;
2013 unsigned n;
2014
2015 r = -EFAULT;
2016 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2017 goto out;
2018 n = msr_list.nmsrs;
2019 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2020 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2021 goto out;
2022 r = -E2BIG;
2023 if (n < msr_list.nmsrs)
2024 goto out;
2025 r = -EFAULT;
2026 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2027 num_msrs_to_save * sizeof(u32)))
2028 goto out;
2029 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2030 &emulated_msrs,
2031 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2032 goto out;
2033 r = 0;
2034 break;
2035 }
2036 case KVM_GET_SUPPORTED_CPUID: {
2037 struct kvm_cpuid2 __user *cpuid_arg = argp;
2038 struct kvm_cpuid2 cpuid;
2039
2040 r = -EFAULT;
2041 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2042 goto out;
2043 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2044 cpuid_arg->entries);
2045 if (r)
2046 goto out;
2047
2048 r = -EFAULT;
2049 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2050 goto out;
2051 r = 0;
2052 break;
2053 }
2054 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2055 u64 mce_cap;
2056
2057 mce_cap = KVM_MCE_CAP_SUPPORTED;
2058 r = -EFAULT;
2059 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2060 goto out;
2061 r = 0;
2062 break;
2063 }
2064 default:
2065 r = -EINVAL;
2066 }
2067 out:
2068 return r;
2069 }
2070
2071 static void wbinvd_ipi(void *garbage)
2072 {
2073 wbinvd();
2074 }
2075
2076 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2077 {
2078 return vcpu->kvm->arch.iommu_domain &&
2079 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2080 }
2081
2082 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2083 {
2084 /* Address WBINVD may be executed by guest */
2085 if (need_emulate_wbinvd(vcpu)) {
2086 if (kvm_x86_ops->has_wbinvd_exit())
2087 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2088 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2089 smp_call_function_single(vcpu->cpu,
2090 wbinvd_ipi, NULL, 1);
2091 }
2092
2093 kvm_x86_ops->vcpu_load(vcpu, cpu);
2094 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2095 /* Make sure TSC doesn't go backwards */
2096 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2097 native_read_tsc() - vcpu->arch.last_host_tsc;
2098 if (tsc_delta < 0)
2099 mark_tsc_unstable("KVM discovered backwards TSC");
2100 if (check_tsc_unstable()) {
2101 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2102 vcpu->arch.tsc_catchup = 1;
2103 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2104 }
2105 if (vcpu->cpu != cpu)
2106 kvm_migrate_timers(vcpu);
2107 vcpu->cpu = cpu;
2108 }
2109 }
2110
2111 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2112 {
2113 kvm_x86_ops->vcpu_put(vcpu);
2114 kvm_put_guest_fpu(vcpu);
2115 vcpu->arch.last_host_tsc = native_read_tsc();
2116 }
2117
2118 static int is_efer_nx(void)
2119 {
2120 unsigned long long efer = 0;
2121
2122 rdmsrl_safe(MSR_EFER, &efer);
2123 return efer & EFER_NX;
2124 }
2125
2126 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2127 {
2128 int i;
2129 struct kvm_cpuid_entry2 *e, *entry;
2130
2131 entry = NULL;
2132 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2133 e = &vcpu->arch.cpuid_entries[i];
2134 if (e->function == 0x80000001) {
2135 entry = e;
2136 break;
2137 }
2138 }
2139 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
2140 entry->edx &= ~(1 << 20);
2141 printk(KERN_INFO "kvm: guest NX capability removed\n");
2142 }
2143 }
2144
2145 /* when an old userspace process fills a new kernel module */
2146 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2147 struct kvm_cpuid *cpuid,
2148 struct kvm_cpuid_entry __user *entries)
2149 {
2150 int r, i;
2151 struct kvm_cpuid_entry *cpuid_entries;
2152
2153 r = -E2BIG;
2154 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2155 goto out;
2156 r = -ENOMEM;
2157 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2158 if (!cpuid_entries)
2159 goto out;
2160 r = -EFAULT;
2161 if (copy_from_user(cpuid_entries, entries,
2162 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2163 goto out_free;
2164 for (i = 0; i < cpuid->nent; i++) {
2165 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2166 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2167 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2168 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2169 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2170 vcpu->arch.cpuid_entries[i].index = 0;
2171 vcpu->arch.cpuid_entries[i].flags = 0;
2172 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2173 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2174 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2175 }
2176 vcpu->arch.cpuid_nent = cpuid->nent;
2177 cpuid_fix_nx_cap(vcpu);
2178 r = 0;
2179 kvm_apic_set_version(vcpu);
2180 kvm_x86_ops->cpuid_update(vcpu);
2181 update_cpuid(vcpu);
2182
2183 out_free:
2184 vfree(cpuid_entries);
2185 out:
2186 return r;
2187 }
2188
2189 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
2190 struct kvm_cpuid2 *cpuid,
2191 struct kvm_cpuid_entry2 __user *entries)
2192 {
2193 int r;
2194
2195 r = -E2BIG;
2196 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2197 goto out;
2198 r = -EFAULT;
2199 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
2200 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
2201 goto out;
2202 vcpu->arch.cpuid_nent = cpuid->nent;
2203 kvm_apic_set_version(vcpu);
2204 kvm_x86_ops->cpuid_update(vcpu);
2205 update_cpuid(vcpu);
2206 return 0;
2207
2208 out:
2209 return r;
2210 }
2211
2212 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
2213 struct kvm_cpuid2 *cpuid,
2214 struct kvm_cpuid_entry2 __user *entries)
2215 {
2216 int r;
2217
2218 r = -E2BIG;
2219 if (cpuid->nent < vcpu->arch.cpuid_nent)
2220 goto out;
2221 r = -EFAULT;
2222 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
2223 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
2224 goto out;
2225 return 0;
2226
2227 out:
2228 cpuid->nent = vcpu->arch.cpuid_nent;
2229 return r;
2230 }
2231
2232 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2233 u32 index)
2234 {
2235 entry->function = function;
2236 entry->index = index;
2237 cpuid_count(entry->function, entry->index,
2238 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
2239 entry->flags = 0;
2240 }
2241
2242 #define F(x) bit(X86_FEATURE_##x)
2243
2244 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2245 u32 index, int *nent, int maxnent)
2246 {
2247 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
2248 #ifdef CONFIG_X86_64
2249 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2250 ? F(GBPAGES) : 0;
2251 unsigned f_lm = F(LM);
2252 #else
2253 unsigned f_gbpages = 0;
2254 unsigned f_lm = 0;
2255 #endif
2256 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
2257
2258 /* cpuid 1.edx */
2259 const u32 kvm_supported_word0_x86_features =
2260 F(FPU) | F(VME) | F(DE) | F(PSE) |
2261 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2262 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2263 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2264 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2265 0 /* Reserved, DS, ACPI */ | F(MMX) |
2266 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2267 0 /* HTT, TM, Reserved, PBE */;
2268 /* cpuid 0x80000001.edx */
2269 const u32 kvm_supported_word1_x86_features =
2270 F(FPU) | F(VME) | F(DE) | F(PSE) |
2271 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2272 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2273 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2274 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2275 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
2276 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
2277 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2278 /* cpuid 1.ecx */
2279 const u32 kvm_supported_word4_x86_features =
2280 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
2281 0 /* DS-CPL, VMX, SMX, EST */ |
2282 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2283 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2284 0 /* Reserved, DCA */ | F(XMM4_1) |
2285 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
2286 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2287 F(F16C);
2288 /* cpuid 0x80000001.ecx */
2289 const u32 kvm_supported_word6_x86_features =
2290 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
2291 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2292 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
2293 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
2294
2295 /* all calls to cpuid_count() should be made on the same cpu */
2296 get_cpu();
2297 do_cpuid_1_ent(entry, function, index);
2298 ++*nent;
2299
2300 switch (function) {
2301 case 0:
2302 entry->eax = min(entry->eax, (u32)0xd);
2303 break;
2304 case 1:
2305 entry->edx &= kvm_supported_word0_x86_features;
2306 entry->ecx &= kvm_supported_word4_x86_features;
2307 /* we support x2apic emulation even if host does not support
2308 * it since we emulate x2apic in software */
2309 entry->ecx |= F(X2APIC);
2310 break;
2311 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2312 * may return different values. This forces us to get_cpu() before
2313 * issuing the first command, and also to emulate this annoying behavior
2314 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2315 case 2: {
2316 int t, times = entry->eax & 0xff;
2317
2318 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2319 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2320 for (t = 1; t < times && *nent < maxnent; ++t) {
2321 do_cpuid_1_ent(&entry[t], function, 0);
2322 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2323 ++*nent;
2324 }
2325 break;
2326 }
2327 /* function 4 and 0xb have additional index. */
2328 case 4: {
2329 int i, cache_type;
2330
2331 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2332 /* read more entries until cache_type is zero */
2333 for (i = 1; *nent < maxnent; ++i) {
2334 cache_type = entry[i - 1].eax & 0x1f;
2335 if (!cache_type)
2336 break;
2337 do_cpuid_1_ent(&entry[i], function, i);
2338 entry[i].flags |=
2339 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2340 ++*nent;
2341 }
2342 break;
2343 }
2344 case 0xb: {
2345 int i, level_type;
2346
2347 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2348 /* read more entries until level_type is zero */
2349 for (i = 1; *nent < maxnent; ++i) {
2350 level_type = entry[i - 1].ecx & 0xff00;
2351 if (!level_type)
2352 break;
2353 do_cpuid_1_ent(&entry[i], function, i);
2354 entry[i].flags |=
2355 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2356 ++*nent;
2357 }
2358 break;
2359 }
2360 case 0xd: {
2361 int i;
2362
2363 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2364 for (i = 1; *nent < maxnent; ++i) {
2365 if (entry[i - 1].eax == 0 && i != 2)
2366 break;
2367 do_cpuid_1_ent(&entry[i], function, i);
2368 entry[i].flags |=
2369 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2370 ++*nent;
2371 }
2372 break;
2373 }
2374 case KVM_CPUID_SIGNATURE: {
2375 char signature[12] = "KVMKVMKVM\0\0";
2376 u32 *sigptr = (u32 *)signature;
2377 entry->eax = 0;
2378 entry->ebx = sigptr[0];
2379 entry->ecx = sigptr[1];
2380 entry->edx = sigptr[2];
2381 break;
2382 }
2383 case KVM_CPUID_FEATURES:
2384 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2385 (1 << KVM_FEATURE_NOP_IO_DELAY) |
2386 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2387 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
2388 entry->ebx = 0;
2389 entry->ecx = 0;
2390 entry->edx = 0;
2391 break;
2392 case 0x80000000:
2393 entry->eax = min(entry->eax, 0x8000001a);
2394 break;
2395 case 0x80000001:
2396 entry->edx &= kvm_supported_word1_x86_features;
2397 entry->ecx &= kvm_supported_word6_x86_features;
2398 break;
2399 }
2400
2401 kvm_x86_ops->set_supported_cpuid(function, entry);
2402
2403 put_cpu();
2404 }
2405
2406 #undef F
2407
2408 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
2409 struct kvm_cpuid_entry2 __user *entries)
2410 {
2411 struct kvm_cpuid_entry2 *cpuid_entries;
2412 int limit, nent = 0, r = -E2BIG;
2413 u32 func;
2414
2415 if (cpuid->nent < 1)
2416 goto out;
2417 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2418 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
2419 r = -ENOMEM;
2420 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2421 if (!cpuid_entries)
2422 goto out;
2423
2424 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2425 limit = cpuid_entries[0].eax;
2426 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2427 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2428 &nent, cpuid->nent);
2429 r = -E2BIG;
2430 if (nent >= cpuid->nent)
2431 goto out_free;
2432
2433 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2434 limit = cpuid_entries[nent - 1].eax;
2435 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2436 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2437 &nent, cpuid->nent);
2438
2439
2440
2441 r = -E2BIG;
2442 if (nent >= cpuid->nent)
2443 goto out_free;
2444
2445 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2446 cpuid->nent);
2447
2448 r = -E2BIG;
2449 if (nent >= cpuid->nent)
2450 goto out_free;
2451
2452 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2453 cpuid->nent);
2454
2455 r = -E2BIG;
2456 if (nent >= cpuid->nent)
2457 goto out_free;
2458
2459 r = -EFAULT;
2460 if (copy_to_user(entries, cpuid_entries,
2461 nent * sizeof(struct kvm_cpuid_entry2)))
2462 goto out_free;
2463 cpuid->nent = nent;
2464 r = 0;
2465
2466 out_free:
2467 vfree(cpuid_entries);
2468 out:
2469 return r;
2470 }
2471
2472 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2473 struct kvm_lapic_state *s)
2474 {
2475 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2476
2477 return 0;
2478 }
2479
2480 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2481 struct kvm_lapic_state *s)
2482 {
2483 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2484 kvm_apic_post_state_restore(vcpu);
2485 update_cr8_intercept(vcpu);
2486
2487 return 0;
2488 }
2489
2490 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2491 struct kvm_interrupt *irq)
2492 {
2493 if (irq->irq < 0 || irq->irq >= 256)
2494 return -EINVAL;
2495 if (irqchip_in_kernel(vcpu->kvm))
2496 return -ENXIO;
2497
2498 kvm_queue_interrupt(vcpu, irq->irq, false);
2499 kvm_make_request(KVM_REQ_EVENT, vcpu);
2500
2501 return 0;
2502 }
2503
2504 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2505 {
2506 kvm_inject_nmi(vcpu);
2507
2508 return 0;
2509 }
2510
2511 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2512 struct kvm_tpr_access_ctl *tac)
2513 {
2514 if (tac->flags)
2515 return -EINVAL;
2516 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2517 return 0;
2518 }
2519
2520 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2521 u64 mcg_cap)
2522 {
2523 int r;
2524 unsigned bank_num = mcg_cap & 0xff, bank;
2525
2526 r = -EINVAL;
2527 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2528 goto out;
2529 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2530 goto out;
2531 r = 0;
2532 vcpu->arch.mcg_cap = mcg_cap;
2533 /* Init IA32_MCG_CTL to all 1s */
2534 if (mcg_cap & MCG_CTL_P)
2535 vcpu->arch.mcg_ctl = ~(u64)0;
2536 /* Init IA32_MCi_CTL to all 1s */
2537 for (bank = 0; bank < bank_num; bank++)
2538 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2539 out:
2540 return r;
2541 }
2542
2543 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2544 struct kvm_x86_mce *mce)
2545 {
2546 u64 mcg_cap = vcpu->arch.mcg_cap;
2547 unsigned bank_num = mcg_cap & 0xff;
2548 u64 *banks = vcpu->arch.mce_banks;
2549
2550 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2551 return -EINVAL;
2552 /*
2553 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2554 * reporting is disabled
2555 */
2556 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2557 vcpu->arch.mcg_ctl != ~(u64)0)
2558 return 0;
2559 banks += 4 * mce->bank;
2560 /*
2561 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2562 * reporting is disabled for the bank
2563 */
2564 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2565 return 0;
2566 if (mce->status & MCI_STATUS_UC) {
2567 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2568 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2569 printk(KERN_DEBUG "kvm: set_mce: "
2570 "injects mce exception while "
2571 "previous one is in progress!\n");
2572 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2573 return 0;
2574 }
2575 if (banks[1] & MCI_STATUS_VAL)
2576 mce->status |= MCI_STATUS_OVER;
2577 banks[2] = mce->addr;
2578 banks[3] = mce->misc;
2579 vcpu->arch.mcg_status = mce->mcg_status;
2580 banks[1] = mce->status;
2581 kvm_queue_exception(vcpu, MC_VECTOR);
2582 } else if (!(banks[1] & MCI_STATUS_VAL)
2583 || !(banks[1] & MCI_STATUS_UC)) {
2584 if (banks[1] & MCI_STATUS_VAL)
2585 mce->status |= MCI_STATUS_OVER;
2586 banks[2] = mce->addr;
2587 banks[3] = mce->misc;
2588 banks[1] = mce->status;
2589 } else
2590 banks[1] |= MCI_STATUS_OVER;
2591 return 0;
2592 }
2593
2594 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2595 struct kvm_vcpu_events *events)
2596 {
2597 events->exception.injected =
2598 vcpu->arch.exception.pending &&
2599 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2600 events->exception.nr = vcpu->arch.exception.nr;
2601 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2602 events->exception.pad = 0;
2603 events->exception.error_code = vcpu->arch.exception.error_code;
2604
2605 events->interrupt.injected =
2606 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2607 events->interrupt.nr = vcpu->arch.interrupt.nr;
2608 events->interrupt.soft = 0;
2609 events->interrupt.shadow =
2610 kvm_x86_ops->get_interrupt_shadow(vcpu,
2611 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2612
2613 events->nmi.injected = vcpu->arch.nmi_injected;
2614 events->nmi.pending = vcpu->arch.nmi_pending;
2615 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2616 events->nmi.pad = 0;
2617
2618 events->sipi_vector = vcpu->arch.sipi_vector;
2619
2620 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2621 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2622 | KVM_VCPUEVENT_VALID_SHADOW);
2623 memset(&events->reserved, 0, sizeof(events->reserved));
2624 }
2625
2626 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2627 struct kvm_vcpu_events *events)
2628 {
2629 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2630 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2631 | KVM_VCPUEVENT_VALID_SHADOW))
2632 return -EINVAL;
2633
2634 vcpu->arch.exception.pending = events->exception.injected;
2635 vcpu->arch.exception.nr = events->exception.nr;
2636 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2637 vcpu->arch.exception.error_code = events->exception.error_code;
2638
2639 vcpu->arch.interrupt.pending = events->interrupt.injected;
2640 vcpu->arch.interrupt.nr = events->interrupt.nr;
2641 vcpu->arch.interrupt.soft = events->interrupt.soft;
2642 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2643 kvm_pic_clear_isr_ack(vcpu->kvm);
2644 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2645 kvm_x86_ops->set_interrupt_shadow(vcpu,
2646 events->interrupt.shadow);
2647
2648 vcpu->arch.nmi_injected = events->nmi.injected;
2649 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2650 vcpu->arch.nmi_pending = events->nmi.pending;
2651 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2652
2653 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2654 vcpu->arch.sipi_vector = events->sipi_vector;
2655
2656 kvm_make_request(KVM_REQ_EVENT, vcpu);
2657
2658 return 0;
2659 }
2660
2661 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2662 struct kvm_debugregs *dbgregs)
2663 {
2664 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2665 dbgregs->dr6 = vcpu->arch.dr6;
2666 dbgregs->dr7 = vcpu->arch.dr7;
2667 dbgregs->flags = 0;
2668 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2669 }
2670
2671 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2672 struct kvm_debugregs *dbgregs)
2673 {
2674 if (dbgregs->flags)
2675 return -EINVAL;
2676
2677 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2678 vcpu->arch.dr6 = dbgregs->dr6;
2679 vcpu->arch.dr7 = dbgregs->dr7;
2680
2681 return 0;
2682 }
2683
2684 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2685 struct kvm_xsave *guest_xsave)
2686 {
2687 if (cpu_has_xsave)
2688 memcpy(guest_xsave->region,
2689 &vcpu->arch.guest_fpu.state->xsave,
2690 xstate_size);
2691 else {
2692 memcpy(guest_xsave->region,
2693 &vcpu->arch.guest_fpu.state->fxsave,
2694 sizeof(struct i387_fxsave_struct));
2695 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2696 XSTATE_FPSSE;
2697 }
2698 }
2699
2700 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2701 struct kvm_xsave *guest_xsave)
2702 {
2703 u64 xstate_bv =
2704 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2705
2706 if (cpu_has_xsave)
2707 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2708 guest_xsave->region, xstate_size);
2709 else {
2710 if (xstate_bv & ~XSTATE_FPSSE)
2711 return -EINVAL;
2712 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2713 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2714 }
2715 return 0;
2716 }
2717
2718 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2719 struct kvm_xcrs *guest_xcrs)
2720 {
2721 if (!cpu_has_xsave) {
2722 guest_xcrs->nr_xcrs = 0;
2723 return;
2724 }
2725
2726 guest_xcrs->nr_xcrs = 1;
2727 guest_xcrs->flags = 0;
2728 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2729 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2730 }
2731
2732 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2733 struct kvm_xcrs *guest_xcrs)
2734 {
2735 int i, r = 0;
2736
2737 if (!cpu_has_xsave)
2738 return -EINVAL;
2739
2740 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2741 return -EINVAL;
2742
2743 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2744 /* Only support XCR0 currently */
2745 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2746 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2747 guest_xcrs->xcrs[0].value);
2748 break;
2749 }
2750 if (r)
2751 r = -EINVAL;
2752 return r;
2753 }
2754
2755 long kvm_arch_vcpu_ioctl(struct file *filp,
2756 unsigned int ioctl, unsigned long arg)
2757 {
2758 struct kvm_vcpu *vcpu = filp->private_data;
2759 void __user *argp = (void __user *)arg;
2760 int r;
2761 union {
2762 struct kvm_lapic_state *lapic;
2763 struct kvm_xsave *xsave;
2764 struct kvm_xcrs *xcrs;
2765 void *buffer;
2766 } u;
2767
2768 u.buffer = NULL;
2769 switch (ioctl) {
2770 case KVM_GET_LAPIC: {
2771 r = -EINVAL;
2772 if (!vcpu->arch.apic)
2773 goto out;
2774 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2775
2776 r = -ENOMEM;
2777 if (!u.lapic)
2778 goto out;
2779 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2780 if (r)
2781 goto out;
2782 r = -EFAULT;
2783 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2784 goto out;
2785 r = 0;
2786 break;
2787 }
2788 case KVM_SET_LAPIC: {
2789 r = -EINVAL;
2790 if (!vcpu->arch.apic)
2791 goto out;
2792 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2793 r = -ENOMEM;
2794 if (!u.lapic)
2795 goto out;
2796 r = -EFAULT;
2797 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
2798 goto out;
2799 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2800 if (r)
2801 goto out;
2802 r = 0;
2803 break;
2804 }
2805 case KVM_INTERRUPT: {
2806 struct kvm_interrupt irq;
2807
2808 r = -EFAULT;
2809 if (copy_from_user(&irq, argp, sizeof irq))
2810 goto out;
2811 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2812 if (r)
2813 goto out;
2814 r = 0;
2815 break;
2816 }
2817 case KVM_NMI: {
2818 r = kvm_vcpu_ioctl_nmi(vcpu);
2819 if (r)
2820 goto out;
2821 r = 0;
2822 break;
2823 }
2824 case KVM_SET_CPUID: {
2825 struct kvm_cpuid __user *cpuid_arg = argp;
2826 struct kvm_cpuid cpuid;
2827
2828 r = -EFAULT;
2829 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2830 goto out;
2831 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2832 if (r)
2833 goto out;
2834 break;
2835 }
2836 case KVM_SET_CPUID2: {
2837 struct kvm_cpuid2 __user *cpuid_arg = argp;
2838 struct kvm_cpuid2 cpuid;
2839
2840 r = -EFAULT;
2841 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2842 goto out;
2843 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2844 cpuid_arg->entries);
2845 if (r)
2846 goto out;
2847 break;
2848 }
2849 case KVM_GET_CPUID2: {
2850 struct kvm_cpuid2 __user *cpuid_arg = argp;
2851 struct kvm_cpuid2 cpuid;
2852
2853 r = -EFAULT;
2854 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2855 goto out;
2856 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2857 cpuid_arg->entries);
2858 if (r)
2859 goto out;
2860 r = -EFAULT;
2861 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2862 goto out;
2863 r = 0;
2864 break;
2865 }
2866 case KVM_GET_MSRS:
2867 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2868 break;
2869 case KVM_SET_MSRS:
2870 r = msr_io(vcpu, argp, do_set_msr, 0);
2871 break;
2872 case KVM_TPR_ACCESS_REPORTING: {
2873 struct kvm_tpr_access_ctl tac;
2874
2875 r = -EFAULT;
2876 if (copy_from_user(&tac, argp, sizeof tac))
2877 goto out;
2878 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2879 if (r)
2880 goto out;
2881 r = -EFAULT;
2882 if (copy_to_user(argp, &tac, sizeof tac))
2883 goto out;
2884 r = 0;
2885 break;
2886 };
2887 case KVM_SET_VAPIC_ADDR: {
2888 struct kvm_vapic_addr va;
2889
2890 r = -EINVAL;
2891 if (!irqchip_in_kernel(vcpu->kvm))
2892 goto out;
2893 r = -EFAULT;
2894 if (copy_from_user(&va, argp, sizeof va))
2895 goto out;
2896 r = 0;
2897 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2898 break;
2899 }
2900 case KVM_X86_SETUP_MCE: {
2901 u64 mcg_cap;
2902
2903 r = -EFAULT;
2904 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2905 goto out;
2906 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2907 break;
2908 }
2909 case KVM_X86_SET_MCE: {
2910 struct kvm_x86_mce mce;
2911
2912 r = -EFAULT;
2913 if (copy_from_user(&mce, argp, sizeof mce))
2914 goto out;
2915 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2916 break;
2917 }
2918 case KVM_GET_VCPU_EVENTS: {
2919 struct kvm_vcpu_events events;
2920
2921 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2922
2923 r = -EFAULT;
2924 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2925 break;
2926 r = 0;
2927 break;
2928 }
2929 case KVM_SET_VCPU_EVENTS: {
2930 struct kvm_vcpu_events events;
2931
2932 r = -EFAULT;
2933 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2934 break;
2935
2936 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2937 break;
2938 }
2939 case KVM_GET_DEBUGREGS: {
2940 struct kvm_debugregs dbgregs;
2941
2942 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2943
2944 r = -EFAULT;
2945 if (copy_to_user(argp, &dbgregs,
2946 sizeof(struct kvm_debugregs)))
2947 break;
2948 r = 0;
2949 break;
2950 }
2951 case KVM_SET_DEBUGREGS: {
2952 struct kvm_debugregs dbgregs;
2953
2954 r = -EFAULT;
2955 if (copy_from_user(&dbgregs, argp,
2956 sizeof(struct kvm_debugregs)))
2957 break;
2958
2959 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2960 break;
2961 }
2962 case KVM_GET_XSAVE: {
2963 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2964 r = -ENOMEM;
2965 if (!u.xsave)
2966 break;
2967
2968 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2969
2970 r = -EFAULT;
2971 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2972 break;
2973 r = 0;
2974 break;
2975 }
2976 case KVM_SET_XSAVE: {
2977 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2978 r = -ENOMEM;
2979 if (!u.xsave)
2980 break;
2981
2982 r = -EFAULT;
2983 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2984 break;
2985
2986 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2987 break;
2988 }
2989 case KVM_GET_XCRS: {
2990 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2991 r = -ENOMEM;
2992 if (!u.xcrs)
2993 break;
2994
2995 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2996
2997 r = -EFAULT;
2998 if (copy_to_user(argp, u.xcrs,
2999 sizeof(struct kvm_xcrs)))
3000 break;
3001 r = 0;
3002 break;
3003 }
3004 case KVM_SET_XCRS: {
3005 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3006 r = -ENOMEM;
3007 if (!u.xcrs)
3008 break;
3009
3010 r = -EFAULT;
3011 if (copy_from_user(u.xcrs, argp,
3012 sizeof(struct kvm_xcrs)))
3013 break;
3014
3015 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3016 break;
3017 }
3018 default:
3019 r = -EINVAL;
3020 }
3021 out:
3022 kfree(u.buffer);
3023 return r;
3024 }
3025
3026 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3027 {
3028 int ret;
3029
3030 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3031 return -1;
3032 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3033 return ret;
3034 }
3035
3036 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3037 u64 ident_addr)
3038 {
3039 kvm->arch.ept_identity_map_addr = ident_addr;
3040 return 0;
3041 }
3042
3043 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3044 u32 kvm_nr_mmu_pages)
3045 {
3046 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3047 return -EINVAL;
3048
3049 mutex_lock(&kvm->slots_lock);
3050 spin_lock(&kvm->mmu_lock);
3051
3052 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3053 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3054
3055 spin_unlock(&kvm->mmu_lock);
3056 mutex_unlock(&kvm->slots_lock);
3057 return 0;
3058 }
3059
3060 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3061 {
3062 return kvm->arch.n_max_mmu_pages;
3063 }
3064
3065 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3066 {
3067 int r;
3068
3069 r = 0;
3070 switch (chip->chip_id) {
3071 case KVM_IRQCHIP_PIC_MASTER:
3072 memcpy(&chip->chip.pic,
3073 &pic_irqchip(kvm)->pics[0],
3074 sizeof(struct kvm_pic_state));
3075 break;
3076 case KVM_IRQCHIP_PIC_SLAVE:
3077 memcpy(&chip->chip.pic,
3078 &pic_irqchip(kvm)->pics[1],
3079 sizeof(struct kvm_pic_state));
3080 break;
3081 case KVM_IRQCHIP_IOAPIC:
3082 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3083 break;
3084 default:
3085 r = -EINVAL;
3086 break;
3087 }
3088 return r;
3089 }
3090
3091 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3092 {
3093 int r;
3094
3095 r = 0;
3096 switch (chip->chip_id) {
3097 case KVM_IRQCHIP_PIC_MASTER:
3098 spin_lock(&pic_irqchip(kvm)->lock);
3099 memcpy(&pic_irqchip(kvm)->pics[0],
3100 &chip->chip.pic,
3101 sizeof(struct kvm_pic_state));
3102 spin_unlock(&pic_irqchip(kvm)->lock);
3103 break;
3104 case KVM_IRQCHIP_PIC_SLAVE:
3105 spin_lock(&pic_irqchip(kvm)->lock);
3106 memcpy(&pic_irqchip(kvm)->pics[1],
3107 &chip->chip.pic,
3108 sizeof(struct kvm_pic_state));
3109 spin_unlock(&pic_irqchip(kvm)->lock);
3110 break;
3111 case KVM_IRQCHIP_IOAPIC:
3112 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3113 break;
3114 default:
3115 r = -EINVAL;
3116 break;
3117 }
3118 kvm_pic_update_irq(pic_irqchip(kvm));
3119 return r;
3120 }
3121
3122 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3123 {
3124 int r = 0;
3125
3126 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3127 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3128 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3129 return r;
3130 }
3131
3132 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3133 {
3134 int r = 0;
3135
3136 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3137 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3138 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3139 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3140 return r;
3141 }
3142
3143 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3144 {
3145 int r = 0;
3146
3147 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3148 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3149 sizeof(ps->channels));
3150 ps->flags = kvm->arch.vpit->pit_state.flags;
3151 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3152 memset(&ps->reserved, 0, sizeof(ps->reserved));
3153 return r;
3154 }
3155
3156 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3157 {
3158 int r = 0, start = 0;
3159 u32 prev_legacy, cur_legacy;
3160 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3161 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3162 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3163 if (!prev_legacy && cur_legacy)
3164 start = 1;
3165 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3166 sizeof(kvm->arch.vpit->pit_state.channels));
3167 kvm->arch.vpit->pit_state.flags = ps->flags;
3168 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3169 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3170 return r;
3171 }
3172
3173 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3174 struct kvm_reinject_control *control)
3175 {
3176 if (!kvm->arch.vpit)
3177 return -ENXIO;
3178 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3179 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3180 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3181 return 0;
3182 }
3183
3184 /*
3185 * Get (and clear) the dirty memory log for a memory slot.
3186 */
3187 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3188 struct kvm_dirty_log *log)
3189 {
3190 int r, i;
3191 struct kvm_memory_slot *memslot;
3192 unsigned long n;
3193 unsigned long is_dirty = 0;
3194
3195 mutex_lock(&kvm->slots_lock);
3196
3197 r = -EINVAL;
3198 if (log->slot >= KVM_MEMORY_SLOTS)
3199 goto out;
3200
3201 memslot = &kvm->memslots->memslots[log->slot];
3202 r = -ENOENT;
3203 if (!memslot->dirty_bitmap)
3204 goto out;
3205
3206 n = kvm_dirty_bitmap_bytes(memslot);
3207
3208 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3209 is_dirty = memslot->dirty_bitmap[i];
3210
3211 /* If nothing is dirty, don't bother messing with page tables. */
3212 if (is_dirty) {
3213 struct kvm_memslots *slots, *old_slots;
3214 unsigned long *dirty_bitmap;
3215
3216 dirty_bitmap = memslot->dirty_bitmap_head;
3217 if (memslot->dirty_bitmap == dirty_bitmap)
3218 dirty_bitmap += n / sizeof(long);
3219 memset(dirty_bitmap, 0, n);
3220
3221 r = -ENOMEM;
3222 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3223 if (!slots)
3224 goto out;
3225 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3226 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3227 slots->generation++;
3228
3229 old_slots = kvm->memslots;
3230 rcu_assign_pointer(kvm->memslots, slots);
3231 synchronize_srcu_expedited(&kvm->srcu);
3232 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3233 kfree(old_slots);
3234
3235 spin_lock(&kvm->mmu_lock);
3236 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3237 spin_unlock(&kvm->mmu_lock);
3238
3239 r = -EFAULT;
3240 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
3241 goto out;
3242 } else {
3243 r = -EFAULT;
3244 if (clear_user(log->dirty_bitmap, n))
3245 goto out;
3246 }
3247
3248 r = 0;
3249 out:
3250 mutex_unlock(&kvm->slots_lock);
3251 return r;
3252 }
3253
3254 long kvm_arch_vm_ioctl(struct file *filp,
3255 unsigned int ioctl, unsigned long arg)
3256 {
3257 struct kvm *kvm = filp->private_data;
3258 void __user *argp = (void __user *)arg;
3259 int r = -ENOTTY;
3260 /*
3261 * This union makes it completely explicit to gcc-3.x
3262 * that these two variables' stack usage should be
3263 * combined, not added together.
3264 */
3265 union {
3266 struct kvm_pit_state ps;
3267 struct kvm_pit_state2 ps2;
3268 struct kvm_pit_config pit_config;
3269 } u;
3270
3271 switch (ioctl) {
3272 case KVM_SET_TSS_ADDR:
3273 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3274 if (r < 0)
3275 goto out;
3276 break;
3277 case KVM_SET_IDENTITY_MAP_ADDR: {
3278 u64 ident_addr;
3279
3280 r = -EFAULT;
3281 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3282 goto out;
3283 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3284 if (r < 0)
3285 goto out;
3286 break;
3287 }
3288 case KVM_SET_NR_MMU_PAGES:
3289 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3290 if (r)
3291 goto out;
3292 break;
3293 case KVM_GET_NR_MMU_PAGES:
3294 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3295 break;
3296 case KVM_CREATE_IRQCHIP: {
3297 struct kvm_pic *vpic;
3298
3299 mutex_lock(&kvm->lock);
3300 r = -EEXIST;
3301 if (kvm->arch.vpic)
3302 goto create_irqchip_unlock;
3303 r = -ENOMEM;
3304 vpic = kvm_create_pic(kvm);
3305 if (vpic) {
3306 r = kvm_ioapic_init(kvm);
3307 if (r) {
3308 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3309 &vpic->dev);
3310 kfree(vpic);
3311 goto create_irqchip_unlock;
3312 }
3313 } else
3314 goto create_irqchip_unlock;
3315 smp_wmb();
3316 kvm->arch.vpic = vpic;
3317 smp_wmb();
3318 r = kvm_setup_default_irq_routing(kvm);
3319 if (r) {
3320 mutex_lock(&kvm->irq_lock);
3321 kvm_ioapic_destroy(kvm);
3322 kvm_destroy_pic(kvm);
3323 mutex_unlock(&kvm->irq_lock);
3324 }
3325 create_irqchip_unlock:
3326 mutex_unlock(&kvm->lock);
3327 break;
3328 }
3329 case KVM_CREATE_PIT:
3330 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3331 goto create_pit;
3332 case KVM_CREATE_PIT2:
3333 r = -EFAULT;
3334 if (copy_from_user(&u.pit_config, argp,
3335 sizeof(struct kvm_pit_config)))
3336 goto out;
3337 create_pit:
3338 mutex_lock(&kvm->slots_lock);
3339 r = -EEXIST;
3340 if (kvm->arch.vpit)
3341 goto create_pit_unlock;
3342 r = -ENOMEM;
3343 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3344 if (kvm->arch.vpit)
3345 r = 0;
3346 create_pit_unlock:
3347 mutex_unlock(&kvm->slots_lock);
3348 break;
3349 case KVM_IRQ_LINE_STATUS:
3350 case KVM_IRQ_LINE: {
3351 struct kvm_irq_level irq_event;
3352
3353 r = -EFAULT;
3354 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3355 goto out;
3356 r = -ENXIO;
3357 if (irqchip_in_kernel(kvm)) {
3358 __s32 status;
3359 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3360 irq_event.irq, irq_event.level);
3361 if (ioctl == KVM_IRQ_LINE_STATUS) {
3362 r = -EFAULT;
3363 irq_event.status = status;
3364 if (copy_to_user(argp, &irq_event,
3365 sizeof irq_event))
3366 goto out;
3367 }
3368 r = 0;
3369 }
3370 break;
3371 }
3372 case KVM_GET_IRQCHIP: {
3373 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3374 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3375
3376 r = -ENOMEM;
3377 if (!chip)
3378 goto out;
3379 r = -EFAULT;
3380 if (copy_from_user(chip, argp, sizeof *chip))
3381 goto get_irqchip_out;
3382 r = -ENXIO;
3383 if (!irqchip_in_kernel(kvm))
3384 goto get_irqchip_out;
3385 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3386 if (r)
3387 goto get_irqchip_out;
3388 r = -EFAULT;
3389 if (copy_to_user(argp, chip, sizeof *chip))
3390 goto get_irqchip_out;
3391 r = 0;
3392 get_irqchip_out:
3393 kfree(chip);
3394 if (r)
3395 goto out;
3396 break;
3397 }
3398 case KVM_SET_IRQCHIP: {
3399 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3400 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3401
3402 r = -ENOMEM;
3403 if (!chip)
3404 goto out;
3405 r = -EFAULT;
3406 if (copy_from_user(chip, argp, sizeof *chip))
3407 goto set_irqchip_out;
3408 r = -ENXIO;
3409 if (!irqchip_in_kernel(kvm))
3410 goto set_irqchip_out;
3411 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3412 if (r)
3413 goto set_irqchip_out;
3414 r = 0;
3415 set_irqchip_out:
3416 kfree(chip);
3417 if (r)
3418 goto out;
3419 break;
3420 }
3421 case KVM_GET_PIT: {
3422 r = -EFAULT;
3423 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3424 goto out;
3425 r = -ENXIO;
3426 if (!kvm->arch.vpit)
3427 goto out;
3428 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3429 if (r)
3430 goto out;
3431 r = -EFAULT;
3432 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3433 goto out;
3434 r = 0;
3435 break;
3436 }
3437 case KVM_SET_PIT: {
3438 r = -EFAULT;
3439 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3440 goto out;
3441 r = -ENXIO;
3442 if (!kvm->arch.vpit)
3443 goto out;
3444 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3445 if (r)
3446 goto out;
3447 r = 0;
3448 break;
3449 }
3450 case KVM_GET_PIT2: {
3451 r = -ENXIO;
3452 if (!kvm->arch.vpit)
3453 goto out;
3454 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3455 if (r)
3456 goto out;
3457 r = -EFAULT;
3458 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3459 goto out;
3460 r = 0;
3461 break;
3462 }
3463 case KVM_SET_PIT2: {
3464 r = -EFAULT;
3465 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3466 goto out;
3467 r = -ENXIO;
3468 if (!kvm->arch.vpit)
3469 goto out;
3470 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3471 if (r)
3472 goto out;
3473 r = 0;
3474 break;
3475 }
3476 case KVM_REINJECT_CONTROL: {
3477 struct kvm_reinject_control control;
3478 r = -EFAULT;
3479 if (copy_from_user(&control, argp, sizeof(control)))
3480 goto out;
3481 r = kvm_vm_ioctl_reinject(kvm, &control);
3482 if (r)
3483 goto out;
3484 r = 0;
3485 break;
3486 }
3487 case KVM_XEN_HVM_CONFIG: {
3488 r = -EFAULT;
3489 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3490 sizeof(struct kvm_xen_hvm_config)))
3491 goto out;
3492 r = -EINVAL;
3493 if (kvm->arch.xen_hvm_config.flags)
3494 goto out;
3495 r = 0;
3496 break;
3497 }
3498 case KVM_SET_CLOCK: {
3499 struct kvm_clock_data user_ns;
3500 u64 now_ns;
3501 s64 delta;
3502
3503 r = -EFAULT;
3504 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3505 goto out;
3506
3507 r = -EINVAL;
3508 if (user_ns.flags)
3509 goto out;
3510
3511 r = 0;
3512 local_irq_disable();
3513 now_ns = get_kernel_ns();
3514 delta = user_ns.clock - now_ns;
3515 local_irq_enable();
3516 kvm->arch.kvmclock_offset = delta;
3517 break;
3518 }
3519 case KVM_GET_CLOCK: {
3520 struct kvm_clock_data user_ns;
3521 u64 now_ns;
3522
3523 local_irq_disable();
3524 now_ns = get_kernel_ns();
3525 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3526 local_irq_enable();
3527 user_ns.flags = 0;
3528 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3529
3530 r = -EFAULT;
3531 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3532 goto out;
3533 r = 0;
3534 break;
3535 }
3536
3537 default:
3538 ;
3539 }
3540 out:
3541 return r;
3542 }
3543
3544 static void kvm_init_msr_list(void)
3545 {
3546 u32 dummy[2];
3547 unsigned i, j;
3548
3549 /* skip the first msrs in the list. KVM-specific */
3550 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3551 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3552 continue;
3553 if (j < i)
3554 msrs_to_save[j] = msrs_to_save[i];
3555 j++;
3556 }
3557 num_msrs_to_save = j;
3558 }
3559
3560 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3561 const void *v)
3562 {
3563 if (vcpu->arch.apic &&
3564 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3565 return 0;
3566
3567 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
3568 }
3569
3570 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3571 {
3572 if (vcpu->arch.apic &&
3573 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3574 return 0;
3575
3576 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
3577 }
3578
3579 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3580 struct kvm_segment *var, int seg)
3581 {
3582 kvm_x86_ops->set_segment(vcpu, var, seg);
3583 }
3584
3585 void kvm_get_segment(struct kvm_vcpu *vcpu,
3586 struct kvm_segment *var, int seg)
3587 {
3588 kvm_x86_ops->get_segment(vcpu, var, seg);
3589 }
3590
3591 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3592 {
3593 return gpa;
3594 }
3595
3596 static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3597 {
3598 gpa_t t_gpa;
3599 u32 error;
3600
3601 BUG_ON(!mmu_is_nested(vcpu));
3602
3603 /* NPT walks are always user-walks */
3604 access |= PFERR_USER_MASK;
3605 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3606 if (t_gpa == UNMAPPED_GVA)
3607 vcpu->arch.fault.nested = true;
3608
3609 return t_gpa;
3610 }
3611
3612 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3613 {
3614 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3615 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
3616 }
3617
3618 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3619 {
3620 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3621 access |= PFERR_FETCH_MASK;
3622 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
3623 }
3624
3625 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3626 {
3627 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3628 access |= PFERR_WRITE_MASK;
3629 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
3630 }
3631
3632 /* uses this to access any guest's mapped memory without checking CPL */
3633 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3634 {
3635 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
3636 }
3637
3638 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3639 struct kvm_vcpu *vcpu, u32 access,
3640 u32 *error)
3641 {
3642 void *data = val;
3643 int r = X86EMUL_CONTINUE;
3644
3645 while (bytes) {
3646 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3647 error);
3648 unsigned offset = addr & (PAGE_SIZE-1);
3649 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3650 int ret;
3651
3652 if (gpa == UNMAPPED_GVA) {
3653 r = X86EMUL_PROPAGATE_FAULT;
3654 goto out;
3655 }
3656 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3657 if (ret < 0) {
3658 r = X86EMUL_IO_NEEDED;
3659 goto out;
3660 }
3661
3662 bytes -= toread;
3663 data += toread;
3664 addr += toread;
3665 }
3666 out:
3667 return r;
3668 }
3669
3670 /* used for instruction fetching */
3671 static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3672 struct kvm_vcpu *vcpu, u32 *error)
3673 {
3674 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3675 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3676 access | PFERR_FETCH_MASK, error);
3677 }
3678
3679 static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3680 struct kvm_vcpu *vcpu, u32 *error)
3681 {
3682 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3683 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3684 error);
3685 }
3686
3687 static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3688 struct kvm_vcpu *vcpu, u32 *error)
3689 {
3690 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3691 }
3692
3693 static int kvm_write_guest_virt_system(gva_t addr, void *val,
3694 unsigned int bytes,
3695 struct kvm_vcpu *vcpu,
3696 u32 *error)
3697 {
3698 void *data = val;
3699 int r = X86EMUL_CONTINUE;
3700
3701 while (bytes) {
3702 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3703 PFERR_WRITE_MASK,
3704 error);
3705 unsigned offset = addr & (PAGE_SIZE-1);
3706 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3707 int ret;
3708
3709 if (gpa == UNMAPPED_GVA) {
3710 r = X86EMUL_PROPAGATE_FAULT;
3711 goto out;
3712 }
3713 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3714 if (ret < 0) {
3715 r = X86EMUL_IO_NEEDED;
3716 goto out;
3717 }
3718
3719 bytes -= towrite;
3720 data += towrite;
3721 addr += towrite;
3722 }
3723 out:
3724 return r;
3725 }
3726
3727 static int emulator_read_emulated(unsigned long addr,
3728 void *val,
3729 unsigned int bytes,
3730 unsigned int *error_code,
3731 struct kvm_vcpu *vcpu)
3732 {
3733 gpa_t gpa;
3734
3735 if (vcpu->mmio_read_completed) {
3736 memcpy(val, vcpu->mmio_data, bytes);
3737 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3738 vcpu->mmio_phys_addr, *(u64 *)val);
3739 vcpu->mmio_read_completed = 0;
3740 return X86EMUL_CONTINUE;
3741 }
3742
3743 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
3744
3745 if (gpa == UNMAPPED_GVA)
3746 return X86EMUL_PROPAGATE_FAULT;
3747
3748 /* For APIC access vmexit */
3749 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3750 goto mmio;
3751
3752 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
3753 == X86EMUL_CONTINUE)
3754 return X86EMUL_CONTINUE;
3755
3756 mmio:
3757 /*
3758 * Is this MMIO handled locally?
3759 */
3760 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3761 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
3762 return X86EMUL_CONTINUE;
3763 }
3764
3765 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3766
3767 vcpu->mmio_needed = 1;
3768 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3769 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3770 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3771 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
3772
3773 return X86EMUL_IO_NEEDED;
3774 }
3775
3776 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3777 const void *val, int bytes)
3778 {
3779 int ret;
3780
3781 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3782 if (ret < 0)
3783 return 0;
3784 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
3785 return 1;
3786 }
3787
3788 static int emulator_write_emulated_onepage(unsigned long addr,
3789 const void *val,
3790 unsigned int bytes,
3791 unsigned int *error_code,
3792 struct kvm_vcpu *vcpu)
3793 {
3794 gpa_t gpa;
3795
3796 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
3797
3798 if (gpa == UNMAPPED_GVA)
3799 return X86EMUL_PROPAGATE_FAULT;
3800
3801 /* For APIC access vmexit */
3802 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3803 goto mmio;
3804
3805 if (emulator_write_phys(vcpu, gpa, val, bytes))
3806 return X86EMUL_CONTINUE;
3807
3808 mmio:
3809 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3810 /*
3811 * Is this MMIO handled locally?
3812 */
3813 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
3814 return X86EMUL_CONTINUE;
3815
3816 vcpu->mmio_needed = 1;
3817 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3818 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3819 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3820 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3821 memcpy(vcpu->run->mmio.data, val, bytes);
3822
3823 return X86EMUL_CONTINUE;
3824 }
3825
3826 int emulator_write_emulated(unsigned long addr,
3827 const void *val,
3828 unsigned int bytes,
3829 unsigned int *error_code,
3830 struct kvm_vcpu *vcpu)
3831 {
3832 /* Crossing a page boundary? */
3833 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3834 int rc, now;
3835
3836 now = -addr & ~PAGE_MASK;
3837 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3838 vcpu);
3839 if (rc != X86EMUL_CONTINUE)
3840 return rc;
3841 addr += now;
3842 val += now;
3843 bytes -= now;
3844 }
3845 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3846 vcpu);
3847 }
3848
3849 #define CMPXCHG_TYPE(t, ptr, old, new) \
3850 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3851
3852 #ifdef CONFIG_X86_64
3853 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3854 #else
3855 # define CMPXCHG64(ptr, old, new) \
3856 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3857 #endif
3858
3859 static int emulator_cmpxchg_emulated(unsigned long addr,
3860 const void *old,
3861 const void *new,
3862 unsigned int bytes,
3863 unsigned int *error_code,
3864 struct kvm_vcpu *vcpu)
3865 {
3866 gpa_t gpa;
3867 struct page *page;
3868 char *kaddr;
3869 bool exchanged;
3870
3871 /* guests cmpxchg8b have to be emulated atomically */
3872 if (bytes > 8 || (bytes & (bytes - 1)))
3873 goto emul_write;
3874
3875 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3876
3877 if (gpa == UNMAPPED_GVA ||
3878 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3879 goto emul_write;
3880
3881 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3882 goto emul_write;
3883
3884 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3885 if (is_error_page(page)) {
3886 kvm_release_page_clean(page);
3887 goto emul_write;
3888 }
3889
3890 kaddr = kmap_atomic(page, KM_USER0);
3891 kaddr += offset_in_page(gpa);
3892 switch (bytes) {
3893 case 1:
3894 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3895 break;
3896 case 2:
3897 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3898 break;
3899 case 4:
3900 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3901 break;
3902 case 8:
3903 exchanged = CMPXCHG64(kaddr, old, new);
3904 break;
3905 default:
3906 BUG();
3907 }
3908 kunmap_atomic(kaddr, KM_USER0);
3909 kvm_release_page_dirty(page);
3910
3911 if (!exchanged)
3912 return X86EMUL_CMPXCHG_FAILED;
3913
3914 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3915
3916 return X86EMUL_CONTINUE;
3917
3918 emul_write:
3919 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3920
3921 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
3922 }
3923
3924 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3925 {
3926 /* TODO: String I/O for in kernel device */
3927 int r;
3928
3929 if (vcpu->arch.pio.in)
3930 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3931 vcpu->arch.pio.size, pd);
3932 else
3933 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3934 vcpu->arch.pio.port, vcpu->arch.pio.size,
3935 pd);
3936 return r;
3937 }
3938
3939
3940 static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3941 unsigned int count, struct kvm_vcpu *vcpu)
3942 {
3943 if (vcpu->arch.pio.count)
3944 goto data_avail;
3945
3946 trace_kvm_pio(0, port, size, 1);
3947
3948 vcpu->arch.pio.port = port;
3949 vcpu->arch.pio.in = 1;
3950 vcpu->arch.pio.count = count;
3951 vcpu->arch.pio.size = size;
3952
3953 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3954 data_avail:
3955 memcpy(val, vcpu->arch.pio_data, size * count);
3956 vcpu->arch.pio.count = 0;
3957 return 1;
3958 }
3959
3960 vcpu->run->exit_reason = KVM_EXIT_IO;
3961 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3962 vcpu->run->io.size = size;
3963 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3964 vcpu->run->io.count = count;
3965 vcpu->run->io.port = port;
3966
3967 return 0;
3968 }
3969
3970 static int emulator_pio_out_emulated(int size, unsigned short port,
3971 const void *val, unsigned int count,
3972 struct kvm_vcpu *vcpu)
3973 {
3974 trace_kvm_pio(1, port, size, 1);
3975
3976 vcpu->arch.pio.port = port;
3977 vcpu->arch.pio.in = 0;
3978 vcpu->arch.pio.count = count;
3979 vcpu->arch.pio.size = size;
3980
3981 memcpy(vcpu->arch.pio_data, val, size * count);
3982
3983 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3984 vcpu->arch.pio.count = 0;
3985 return 1;
3986 }
3987
3988 vcpu->run->exit_reason = KVM_EXIT_IO;
3989 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3990 vcpu->run->io.size = size;
3991 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3992 vcpu->run->io.count = count;
3993 vcpu->run->io.port = port;
3994
3995 return 0;
3996 }
3997
3998 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3999 {
4000 return kvm_x86_ops->get_segment_base(vcpu, seg);
4001 }
4002
4003 int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4004 {
4005 kvm_mmu_invlpg(vcpu, address);
4006 return X86EMUL_CONTINUE;
4007 }
4008
4009 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4010 {
4011 if (!need_emulate_wbinvd(vcpu))
4012 return X86EMUL_CONTINUE;
4013
4014 if (kvm_x86_ops->has_wbinvd_exit()) {
4015 int cpu = get_cpu();
4016
4017 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4018 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4019 wbinvd_ipi, NULL, 1);
4020 put_cpu();
4021 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4022 } else
4023 wbinvd();
4024 return X86EMUL_CONTINUE;
4025 }
4026 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4027
4028 int emulate_clts(struct kvm_vcpu *vcpu)
4029 {
4030 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4031 kvm_x86_ops->fpu_activate(vcpu);
4032 return X86EMUL_CONTINUE;
4033 }
4034
4035 int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
4036 {
4037 return _kvm_get_dr(vcpu, dr, dest);
4038 }
4039
4040 int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
4041 {
4042
4043 return __kvm_set_dr(vcpu, dr, value);
4044 }
4045
4046 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4047 {
4048 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4049 }
4050
4051 static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
4052 {
4053 unsigned long value;
4054
4055 switch (cr) {
4056 case 0:
4057 value = kvm_read_cr0(vcpu);
4058 break;
4059 case 2:
4060 value = vcpu->arch.cr2;
4061 break;
4062 case 3:
4063 value = vcpu->arch.cr3;
4064 break;
4065 case 4:
4066 value = kvm_read_cr4(vcpu);
4067 break;
4068 case 8:
4069 value = kvm_get_cr8(vcpu);
4070 break;
4071 default:
4072 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4073 return 0;
4074 }
4075
4076 return value;
4077 }
4078
4079 static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
4080 {
4081 int res = 0;
4082
4083 switch (cr) {
4084 case 0:
4085 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4086 break;
4087 case 2:
4088 vcpu->arch.cr2 = val;
4089 break;
4090 case 3:
4091 res = kvm_set_cr3(vcpu, val);
4092 break;
4093 case 4:
4094 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4095 break;
4096 case 8:
4097 res = __kvm_set_cr8(vcpu, val & 0xfUL);
4098 break;
4099 default:
4100 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4101 res = -1;
4102 }
4103
4104 return res;
4105 }
4106
4107 static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4108 {
4109 return kvm_x86_ops->get_cpl(vcpu);
4110 }
4111
4112 static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4113 {
4114 kvm_x86_ops->get_gdt(vcpu, dt);
4115 }
4116
4117 static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4118 {
4119 kvm_x86_ops->get_idt(vcpu, dt);
4120 }
4121
4122 static unsigned long emulator_get_cached_segment_base(int seg,
4123 struct kvm_vcpu *vcpu)
4124 {
4125 return get_segment_base(vcpu, seg);
4126 }
4127
4128 static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4129 struct kvm_vcpu *vcpu)
4130 {
4131 struct kvm_segment var;
4132
4133 kvm_get_segment(vcpu, &var, seg);
4134
4135 if (var.unusable)
4136 return false;
4137
4138 if (var.g)
4139 var.limit >>= 12;
4140 set_desc_limit(desc, var.limit);
4141 set_desc_base(desc, (unsigned long)var.base);
4142 desc->type = var.type;
4143 desc->s = var.s;
4144 desc->dpl = var.dpl;
4145 desc->p = var.present;
4146 desc->avl = var.avl;
4147 desc->l = var.l;
4148 desc->d = var.db;
4149 desc->g = var.g;
4150
4151 return true;
4152 }
4153
4154 static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4155 struct kvm_vcpu *vcpu)
4156 {
4157 struct kvm_segment var;
4158
4159 /* needed to preserve selector */
4160 kvm_get_segment(vcpu, &var, seg);
4161
4162 var.base = get_desc_base(desc);
4163 var.limit = get_desc_limit(desc);
4164 if (desc->g)
4165 var.limit = (var.limit << 12) | 0xfff;
4166 var.type = desc->type;
4167 var.present = desc->p;
4168 var.dpl = desc->dpl;
4169 var.db = desc->d;
4170 var.s = desc->s;
4171 var.l = desc->l;
4172 var.g = desc->g;
4173 var.avl = desc->avl;
4174 var.present = desc->p;
4175 var.unusable = !var.present;
4176 var.padding = 0;
4177
4178 kvm_set_segment(vcpu, &var, seg);
4179 return;
4180 }
4181
4182 static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4183 {
4184 struct kvm_segment kvm_seg;
4185
4186 kvm_get_segment(vcpu, &kvm_seg, seg);
4187 return kvm_seg.selector;
4188 }
4189
4190 static void emulator_set_segment_selector(u16 sel, int seg,
4191 struct kvm_vcpu *vcpu)
4192 {
4193 struct kvm_segment kvm_seg;
4194
4195 kvm_get_segment(vcpu, &kvm_seg, seg);
4196 kvm_seg.selector = sel;
4197 kvm_set_segment(vcpu, &kvm_seg, seg);
4198 }
4199
4200 static struct x86_emulate_ops emulate_ops = {
4201 .read_std = kvm_read_guest_virt_system,
4202 .write_std = kvm_write_guest_virt_system,
4203 .fetch = kvm_fetch_guest_virt,
4204 .read_emulated = emulator_read_emulated,
4205 .write_emulated = emulator_write_emulated,
4206 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4207 .pio_in_emulated = emulator_pio_in_emulated,
4208 .pio_out_emulated = emulator_pio_out_emulated,
4209 .get_cached_descriptor = emulator_get_cached_descriptor,
4210 .set_cached_descriptor = emulator_set_cached_descriptor,
4211 .get_segment_selector = emulator_get_segment_selector,
4212 .set_segment_selector = emulator_set_segment_selector,
4213 .get_cached_segment_base = emulator_get_cached_segment_base,
4214 .get_gdt = emulator_get_gdt,
4215 .get_idt = emulator_get_idt,
4216 .get_cr = emulator_get_cr,
4217 .set_cr = emulator_set_cr,
4218 .cpl = emulator_get_cpl,
4219 .get_dr = emulator_get_dr,
4220 .set_dr = emulator_set_dr,
4221 .set_msr = kvm_set_msr,
4222 .get_msr = kvm_get_msr,
4223 };
4224
4225 static void cache_all_regs(struct kvm_vcpu *vcpu)
4226 {
4227 kvm_register_read(vcpu, VCPU_REGS_RAX);
4228 kvm_register_read(vcpu, VCPU_REGS_RSP);
4229 kvm_register_read(vcpu, VCPU_REGS_RIP);
4230 vcpu->arch.regs_dirty = ~0;
4231 }
4232
4233 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4234 {
4235 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4236 /*
4237 * an sti; sti; sequence only disable interrupts for the first
4238 * instruction. So, if the last instruction, be it emulated or
4239 * not, left the system with the INT_STI flag enabled, it
4240 * means that the last instruction is an sti. We should not
4241 * leave the flag on in this case. The same goes for mov ss
4242 */
4243 if (!(int_shadow & mask))
4244 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4245 }
4246
4247 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4248 {
4249 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4250 if (ctxt->exception == PF_VECTOR)
4251 kvm_propagate_fault(vcpu);
4252 else if (ctxt->error_code_valid)
4253 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4254 else
4255 kvm_queue_exception(vcpu, ctxt->exception);
4256 }
4257
4258 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4259 {
4260 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4261 int cs_db, cs_l;
4262
4263 cache_all_regs(vcpu);
4264
4265 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4266
4267 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4268 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4269 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4270 vcpu->arch.emulate_ctxt.mode =
4271 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4272 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4273 ? X86EMUL_MODE_VM86 : cs_l
4274 ? X86EMUL_MODE_PROT64 : cs_db
4275 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4276 memset(c, 0, sizeof(struct decode_cache));
4277 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4278 }
4279
4280 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4281 {
4282 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4283 int ret;
4284
4285 init_emulate_ctxt(vcpu);
4286
4287 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4288 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4289 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4290 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4291
4292 if (ret != X86EMUL_CONTINUE)
4293 return EMULATE_FAIL;
4294
4295 vcpu->arch.emulate_ctxt.eip = c->eip;
4296 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4297 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4298 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4299
4300 if (irq == NMI_VECTOR)
4301 vcpu->arch.nmi_pending = false;
4302 else
4303 vcpu->arch.interrupt.pending = false;
4304
4305 return EMULATE_DONE;
4306 }
4307 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4308
4309 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4310 {
4311 ++vcpu->stat.insn_emulation_fail;
4312 trace_kvm_emulate_insn_failed(vcpu);
4313 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4314 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4315 vcpu->run->internal.ndata = 0;
4316 kvm_queue_exception(vcpu, UD_VECTOR);
4317 return EMULATE_FAIL;
4318 }
4319
4320 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4321 {
4322 gpa_t gpa;
4323
4324 if (tdp_enabled)
4325 return false;
4326
4327 /*
4328 * if emulation was due to access to shadowed page table
4329 * and it failed try to unshadow page and re-entetr the
4330 * guest to let CPU execute the instruction.
4331 */
4332 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4333 return true;
4334
4335 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4336
4337 if (gpa == UNMAPPED_GVA)
4338 return true; /* let cpu generate fault */
4339
4340 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4341 return true;
4342
4343 return false;
4344 }
4345
4346 int emulate_instruction(struct kvm_vcpu *vcpu,
4347 unsigned long cr2,
4348 u16 error_code,
4349 int emulation_type)
4350 {
4351 int r;
4352 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4353
4354 kvm_clear_exception_queue(vcpu);
4355 vcpu->arch.mmio_fault_cr2 = cr2;
4356 /*
4357 * TODO: fix emulate.c to use guest_read/write_register
4358 * instead of direct ->regs accesses, can save hundred cycles
4359 * on Intel for instructions that don't read/change RSP, for
4360 * for example.
4361 */
4362 cache_all_regs(vcpu);
4363
4364 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4365 init_emulate_ctxt(vcpu);
4366 vcpu->arch.emulate_ctxt.interruptibility = 0;
4367 vcpu->arch.emulate_ctxt.exception = -1;
4368 vcpu->arch.emulate_ctxt.perm_ok = false;
4369
4370 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
4371 if (r == X86EMUL_PROPAGATE_FAULT)
4372 goto done;
4373
4374 trace_kvm_emulate_insn_start(vcpu);
4375
4376 /* Only allow emulation of specific instructions on #UD
4377 * (namely VMMCALL, sysenter, sysexit, syscall)*/
4378 if (emulation_type & EMULTYPE_TRAP_UD) {
4379 if (!c->twobyte)
4380 return EMULATE_FAIL;
4381 switch (c->b) {
4382 case 0x01: /* VMMCALL */
4383 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4384 return EMULATE_FAIL;
4385 break;
4386 case 0x34: /* sysenter */
4387 case 0x35: /* sysexit */
4388 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4389 return EMULATE_FAIL;
4390 break;
4391 case 0x05: /* syscall */
4392 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4393 return EMULATE_FAIL;
4394 break;
4395 default:
4396 return EMULATE_FAIL;
4397 }
4398
4399 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4400 return EMULATE_FAIL;
4401 }
4402
4403 ++vcpu->stat.insn_emulation;
4404 if (r) {
4405 if (reexecute_instruction(vcpu, cr2))
4406 return EMULATE_DONE;
4407 if (emulation_type & EMULTYPE_SKIP)
4408 return EMULATE_FAIL;
4409 return handle_emulation_failure(vcpu);
4410 }
4411 }
4412
4413 if (emulation_type & EMULTYPE_SKIP) {
4414 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4415 return EMULATE_DONE;
4416 }
4417
4418 /* this is needed for vmware backdor interface to work since it
4419 changes registers values during IO operation */
4420 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4421
4422 restart:
4423 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
4424
4425 if (r == EMULATION_FAILED) {
4426 if (reexecute_instruction(vcpu, cr2))
4427 return EMULATE_DONE;
4428
4429 return handle_emulation_failure(vcpu);
4430 }
4431
4432 done:
4433 if (vcpu->arch.emulate_ctxt.exception >= 0) {
4434 inject_emulated_exception(vcpu);
4435 r = EMULATE_DONE;
4436 } else if (vcpu->arch.pio.count) {
4437 if (!vcpu->arch.pio.in)
4438 vcpu->arch.pio.count = 0;
4439 r = EMULATE_DO_MMIO;
4440 } else if (vcpu->mmio_needed) {
4441 if (vcpu->mmio_is_write)
4442 vcpu->mmio_needed = 0;
4443 r = EMULATE_DO_MMIO;
4444 } else if (r == EMULATION_RESTART)
4445 goto restart;
4446 else
4447 r = EMULATE_DONE;
4448
4449 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4450 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4451 kvm_make_request(KVM_REQ_EVENT, vcpu);
4452 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4453 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4454
4455 return r;
4456 }
4457 EXPORT_SYMBOL_GPL(emulate_instruction);
4458
4459 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4460 {
4461 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4462 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4463 /* do not return to emulator after return from userspace */
4464 vcpu->arch.pio.count = 0;
4465 return ret;
4466 }
4467 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4468
4469 static void tsc_bad(void *info)
4470 {
4471 __get_cpu_var(cpu_tsc_khz) = 0;
4472 }
4473
4474 static void tsc_khz_changed(void *data)
4475 {
4476 struct cpufreq_freqs *freq = data;
4477 unsigned long khz = 0;
4478
4479 if (data)
4480 khz = freq->new;
4481 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4482 khz = cpufreq_quick_get(raw_smp_processor_id());
4483 if (!khz)
4484 khz = tsc_khz;
4485 __get_cpu_var(cpu_tsc_khz) = khz;
4486 }
4487
4488 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4489 void *data)
4490 {
4491 struct cpufreq_freqs *freq = data;
4492 struct kvm *kvm;
4493 struct kvm_vcpu *vcpu;
4494 int i, send_ipi = 0;
4495
4496 /*
4497 * We allow guests to temporarily run on slowing clocks,
4498 * provided we notify them after, or to run on accelerating
4499 * clocks, provided we notify them before. Thus time never
4500 * goes backwards.
4501 *
4502 * However, we have a problem. We can't atomically update
4503 * the frequency of a given CPU from this function; it is
4504 * merely a notifier, which can be called from any CPU.
4505 * Changing the TSC frequency at arbitrary points in time
4506 * requires a recomputation of local variables related to
4507 * the TSC for each VCPU. We must flag these local variables
4508 * to be updated and be sure the update takes place with the
4509 * new frequency before any guests proceed.
4510 *
4511 * Unfortunately, the combination of hotplug CPU and frequency
4512 * change creates an intractable locking scenario; the order
4513 * of when these callouts happen is undefined with respect to
4514 * CPU hotplug, and they can race with each other. As such,
4515 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4516 * undefined; you can actually have a CPU frequency change take
4517 * place in between the computation of X and the setting of the
4518 * variable. To protect against this problem, all updates of
4519 * the per_cpu tsc_khz variable are done in an interrupt
4520 * protected IPI, and all callers wishing to update the value
4521 * must wait for a synchronous IPI to complete (which is trivial
4522 * if the caller is on the CPU already). This establishes the
4523 * necessary total order on variable updates.
4524 *
4525 * Note that because a guest time update may take place
4526 * anytime after the setting of the VCPU's request bit, the
4527 * correct TSC value must be set before the request. However,
4528 * to ensure the update actually makes it to any guest which
4529 * starts running in hardware virtualization between the set
4530 * and the acquisition of the spinlock, we must also ping the
4531 * CPU after setting the request bit.
4532 *
4533 */
4534
4535 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4536 return 0;
4537 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4538 return 0;
4539
4540 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4541
4542 spin_lock(&kvm_lock);
4543 list_for_each_entry(kvm, &vm_list, vm_list) {
4544 kvm_for_each_vcpu(i, vcpu, kvm) {
4545 if (vcpu->cpu != freq->cpu)
4546 continue;
4547 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4548 if (vcpu->cpu != smp_processor_id())
4549 send_ipi = 1;
4550 }
4551 }
4552 spin_unlock(&kvm_lock);
4553
4554 if (freq->old < freq->new && send_ipi) {
4555 /*
4556 * We upscale the frequency. Must make the guest
4557 * doesn't see old kvmclock values while running with
4558 * the new frequency, otherwise we risk the guest sees
4559 * time go backwards.
4560 *
4561 * In case we update the frequency for another cpu
4562 * (which might be in guest context) send an interrupt
4563 * to kick the cpu out of guest context. Next time
4564 * guest context is entered kvmclock will be updated,
4565 * so the guest will not see stale values.
4566 */
4567 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4568 }
4569 return 0;
4570 }
4571
4572 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4573 .notifier_call = kvmclock_cpufreq_notifier
4574 };
4575
4576 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4577 unsigned long action, void *hcpu)
4578 {
4579 unsigned int cpu = (unsigned long)hcpu;
4580
4581 switch (action) {
4582 case CPU_ONLINE:
4583 case CPU_DOWN_FAILED:
4584 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4585 break;
4586 case CPU_DOWN_PREPARE:
4587 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4588 break;
4589 }
4590 return NOTIFY_OK;
4591 }
4592
4593 static struct notifier_block kvmclock_cpu_notifier_block = {
4594 .notifier_call = kvmclock_cpu_notifier,
4595 .priority = -INT_MAX
4596 };
4597
4598 static void kvm_timer_init(void)
4599 {
4600 int cpu;
4601
4602 max_tsc_khz = tsc_khz;
4603 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4604 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4605 #ifdef CONFIG_CPU_FREQ
4606 struct cpufreq_policy policy;
4607 memset(&policy, 0, sizeof(policy));
4608 cpufreq_get_policy(&policy, get_cpu());
4609 if (policy.cpuinfo.max_freq)
4610 max_tsc_khz = policy.cpuinfo.max_freq;
4611 #endif
4612 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4613 CPUFREQ_TRANSITION_NOTIFIER);
4614 }
4615 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4616 for_each_online_cpu(cpu)
4617 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4618 }
4619
4620 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4621
4622 static int kvm_is_in_guest(void)
4623 {
4624 return percpu_read(current_vcpu) != NULL;
4625 }
4626
4627 static int kvm_is_user_mode(void)
4628 {
4629 int user_mode = 3;
4630
4631 if (percpu_read(current_vcpu))
4632 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
4633
4634 return user_mode != 0;
4635 }
4636
4637 static unsigned long kvm_get_guest_ip(void)
4638 {
4639 unsigned long ip = 0;
4640
4641 if (percpu_read(current_vcpu))
4642 ip = kvm_rip_read(percpu_read(current_vcpu));
4643
4644 return ip;
4645 }
4646
4647 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4648 .is_in_guest = kvm_is_in_guest,
4649 .is_user_mode = kvm_is_user_mode,
4650 .get_guest_ip = kvm_get_guest_ip,
4651 };
4652
4653 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4654 {
4655 percpu_write(current_vcpu, vcpu);
4656 }
4657 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4658
4659 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4660 {
4661 percpu_write(current_vcpu, NULL);
4662 }
4663 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4664
4665 int kvm_arch_init(void *opaque)
4666 {
4667 int r;
4668 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4669
4670 if (kvm_x86_ops) {
4671 printk(KERN_ERR "kvm: already loaded the other module\n");
4672 r = -EEXIST;
4673 goto out;
4674 }
4675
4676 if (!ops->cpu_has_kvm_support()) {
4677 printk(KERN_ERR "kvm: no hardware support\n");
4678 r = -EOPNOTSUPP;
4679 goto out;
4680 }
4681 if (ops->disabled_by_bios()) {
4682 printk(KERN_ERR "kvm: disabled by bios\n");
4683 r = -EOPNOTSUPP;
4684 goto out;
4685 }
4686
4687 r = kvm_mmu_module_init();
4688 if (r)
4689 goto out;
4690
4691 kvm_init_msr_list();
4692
4693 kvm_x86_ops = ops;
4694 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
4695 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4696 PT_DIRTY_MASK, PT64_NX_MASK, 0);
4697
4698 kvm_timer_init();
4699
4700 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4701
4702 if (cpu_has_xsave)
4703 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4704
4705 return 0;
4706
4707 out:
4708 return r;
4709 }
4710
4711 void kvm_arch_exit(void)
4712 {
4713 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4714
4715 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4716 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4717 CPUFREQ_TRANSITION_NOTIFIER);
4718 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4719 kvm_x86_ops = NULL;
4720 kvm_mmu_module_exit();
4721 }
4722
4723 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4724 {
4725 ++vcpu->stat.halt_exits;
4726 if (irqchip_in_kernel(vcpu->kvm)) {
4727 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4728 return 1;
4729 } else {
4730 vcpu->run->exit_reason = KVM_EXIT_HLT;
4731 return 0;
4732 }
4733 }
4734 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4735
4736 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4737 unsigned long a1)
4738 {
4739 if (is_long_mode(vcpu))
4740 return a0;
4741 else
4742 return a0 | ((gpa_t)a1 << 32);
4743 }
4744
4745 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4746 {
4747 u64 param, ingpa, outgpa, ret;
4748 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4749 bool fast, longmode;
4750 int cs_db, cs_l;
4751
4752 /*
4753 * hypercall generates UD from non zero cpl and real mode
4754 * per HYPER-V spec
4755 */
4756 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4757 kvm_queue_exception(vcpu, UD_VECTOR);
4758 return 0;
4759 }
4760
4761 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4762 longmode = is_long_mode(vcpu) && cs_l == 1;
4763
4764 if (!longmode) {
4765 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4766 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4767 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4768 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4769 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4770 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4771 }
4772 #ifdef CONFIG_X86_64
4773 else {
4774 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4775 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4776 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4777 }
4778 #endif
4779
4780 code = param & 0xffff;
4781 fast = (param >> 16) & 0x1;
4782 rep_cnt = (param >> 32) & 0xfff;
4783 rep_idx = (param >> 48) & 0xfff;
4784
4785 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4786
4787 switch (code) {
4788 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4789 kvm_vcpu_on_spin(vcpu);
4790 break;
4791 default:
4792 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4793 break;
4794 }
4795
4796 ret = res | (((u64)rep_done & 0xfff) << 32);
4797 if (longmode) {
4798 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4799 } else {
4800 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4801 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4802 }
4803
4804 return 1;
4805 }
4806
4807 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4808 {
4809 unsigned long nr, a0, a1, a2, a3, ret;
4810 int r = 1;
4811
4812 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4813 return kvm_hv_hypercall(vcpu);
4814
4815 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4816 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4817 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4818 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4819 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
4820
4821 trace_kvm_hypercall(nr, a0, a1, a2, a3);
4822
4823 if (!is_long_mode(vcpu)) {
4824 nr &= 0xFFFFFFFF;
4825 a0 &= 0xFFFFFFFF;
4826 a1 &= 0xFFFFFFFF;
4827 a2 &= 0xFFFFFFFF;
4828 a3 &= 0xFFFFFFFF;
4829 }
4830
4831 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4832 ret = -KVM_EPERM;
4833 goto out;
4834 }
4835
4836 switch (nr) {
4837 case KVM_HC_VAPIC_POLL_IRQ:
4838 ret = 0;
4839 break;
4840 case KVM_HC_MMU_OP:
4841 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4842 break;
4843 default:
4844 ret = -KVM_ENOSYS;
4845 break;
4846 }
4847 out:
4848 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4849 ++vcpu->stat.hypercalls;
4850 return r;
4851 }
4852 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4853
4854 int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4855 {
4856 char instruction[3];
4857 unsigned long rip = kvm_rip_read(vcpu);
4858
4859 /*
4860 * Blow out the MMU to ensure that no other VCPU has an active mapping
4861 * to ensure that the updated hypercall appears atomically across all
4862 * VCPUs.
4863 */
4864 kvm_mmu_zap_all(vcpu->kvm);
4865
4866 kvm_x86_ops->patch_hypercall(vcpu, instruction);
4867
4868 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
4869 }
4870
4871 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4872 {
4873 struct desc_ptr dt = { limit, base };
4874
4875 kvm_x86_ops->set_gdt(vcpu, &dt);
4876 }
4877
4878 void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4879 {
4880 struct desc_ptr dt = { limit, base };
4881
4882 kvm_x86_ops->set_idt(vcpu, &dt);
4883 }
4884
4885 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4886 {
4887 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4888 int j, nent = vcpu->arch.cpuid_nent;
4889
4890 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4891 /* when no next entry is found, the current entry[i] is reselected */
4892 for (j = i + 1; ; j = (j + 1) % nent) {
4893 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
4894 if (ej->function == e->function) {
4895 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4896 return j;
4897 }
4898 }
4899 return 0; /* silence gcc, even though control never reaches here */
4900 }
4901
4902 /* find an entry with matching function, matching index (if needed), and that
4903 * should be read next (if it's stateful) */
4904 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4905 u32 function, u32 index)
4906 {
4907 if (e->function != function)
4908 return 0;
4909 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4910 return 0;
4911 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
4912 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
4913 return 0;
4914 return 1;
4915 }
4916
4917 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4918 u32 function, u32 index)
4919 {
4920 int i;
4921 struct kvm_cpuid_entry2 *best = NULL;
4922
4923 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
4924 struct kvm_cpuid_entry2 *e;
4925
4926 e = &vcpu->arch.cpuid_entries[i];
4927 if (is_matching_cpuid_entry(e, function, index)) {
4928 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4929 move_to_next_stateful_cpuid_entry(vcpu, i);
4930 best = e;
4931 break;
4932 }
4933 /*
4934 * Both basic or both extended?
4935 */
4936 if (((e->function ^ function) & 0x80000000) == 0)
4937 if (!best || e->function > best->function)
4938 best = e;
4939 }
4940 return best;
4941 }
4942 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
4943
4944 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4945 {
4946 struct kvm_cpuid_entry2 *best;
4947
4948 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4949 if (!best || best->eax < 0x80000008)
4950 goto not_found;
4951 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4952 if (best)
4953 return best->eax & 0xff;
4954 not_found:
4955 return 36;
4956 }
4957
4958 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4959 {
4960 u32 function, index;
4961 struct kvm_cpuid_entry2 *best;
4962
4963 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4964 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4965 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4966 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4967 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4968 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4969 best = kvm_find_cpuid_entry(vcpu, function, index);
4970 if (best) {
4971 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4972 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4973 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4974 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
4975 }
4976 kvm_x86_ops->skip_emulated_instruction(vcpu);
4977 trace_kvm_cpuid(function,
4978 kvm_register_read(vcpu, VCPU_REGS_RAX),
4979 kvm_register_read(vcpu, VCPU_REGS_RBX),
4980 kvm_register_read(vcpu, VCPU_REGS_RCX),
4981 kvm_register_read(vcpu, VCPU_REGS_RDX));
4982 }
4983 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
4984
4985 /*
4986 * Check if userspace requested an interrupt window, and that the
4987 * interrupt window is open.
4988 *
4989 * No need to exit to userspace if we already have an interrupt queued.
4990 */
4991 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
4992 {
4993 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
4994 vcpu->run->request_interrupt_window &&
4995 kvm_arch_interrupt_allowed(vcpu));
4996 }
4997
4998 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
4999 {
5000 struct kvm_run *kvm_run = vcpu->run;
5001
5002 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5003 kvm_run->cr8 = kvm_get_cr8(vcpu);
5004 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5005 if (irqchip_in_kernel(vcpu->kvm))
5006 kvm_run->ready_for_interrupt_injection = 1;
5007 else
5008 kvm_run->ready_for_interrupt_injection =
5009 kvm_arch_interrupt_allowed(vcpu) &&
5010 !kvm_cpu_has_interrupt(vcpu) &&
5011 !kvm_event_needs_reinjection(vcpu);
5012 }
5013
5014 static void vapic_enter(struct kvm_vcpu *vcpu)
5015 {
5016 struct kvm_lapic *apic = vcpu->arch.apic;
5017 struct page *page;
5018
5019 if (!apic || !apic->vapic_addr)
5020 return;
5021
5022 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5023
5024 vcpu->arch.apic->vapic_page = page;
5025 }
5026
5027 static void vapic_exit(struct kvm_vcpu *vcpu)
5028 {
5029 struct kvm_lapic *apic = vcpu->arch.apic;
5030 int idx;
5031
5032 if (!apic || !apic->vapic_addr)
5033 return;
5034
5035 idx = srcu_read_lock(&vcpu->kvm->srcu);
5036 kvm_release_page_dirty(apic->vapic_page);
5037 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5038 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5039 }
5040
5041 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5042 {
5043 int max_irr, tpr;
5044
5045 if (!kvm_x86_ops->update_cr8_intercept)
5046 return;
5047
5048 if (!vcpu->arch.apic)
5049 return;
5050
5051 if (!vcpu->arch.apic->vapic_addr)
5052 max_irr = kvm_lapic_find_highest_irr(vcpu);
5053 else
5054 max_irr = -1;
5055
5056 if (max_irr != -1)
5057 max_irr >>= 4;
5058
5059 tpr = kvm_lapic_get_cr8(vcpu);
5060
5061 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5062 }
5063
5064 static void inject_pending_event(struct kvm_vcpu *vcpu)
5065 {
5066 /* try to reinject previous events if any */
5067 if (vcpu->arch.exception.pending) {
5068 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5069 vcpu->arch.exception.has_error_code,
5070 vcpu->arch.exception.error_code);
5071 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5072 vcpu->arch.exception.has_error_code,
5073 vcpu->arch.exception.error_code,
5074 vcpu->arch.exception.reinject);
5075 return;
5076 }
5077
5078 if (vcpu->arch.nmi_injected) {
5079 kvm_x86_ops->set_nmi(vcpu);
5080 return;
5081 }
5082
5083 if (vcpu->arch.interrupt.pending) {
5084 kvm_x86_ops->set_irq(vcpu);
5085 return;
5086 }
5087
5088 /* try to inject new event if pending */
5089 if (vcpu->arch.nmi_pending) {
5090 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5091 vcpu->arch.nmi_pending = false;
5092 vcpu->arch.nmi_injected = true;
5093 kvm_x86_ops->set_nmi(vcpu);
5094 }
5095 } else if (kvm_cpu_has_interrupt(vcpu)) {
5096 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5097 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5098 false);
5099 kvm_x86_ops->set_irq(vcpu);
5100 }
5101 }
5102 }
5103
5104 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5105 {
5106 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5107 !vcpu->guest_xcr0_loaded) {
5108 /* kvm_set_xcr() also depends on this */
5109 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5110 vcpu->guest_xcr0_loaded = 1;
5111 }
5112 }
5113
5114 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5115 {
5116 if (vcpu->guest_xcr0_loaded) {
5117 if (vcpu->arch.xcr0 != host_xcr0)
5118 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5119 vcpu->guest_xcr0_loaded = 0;
5120 }
5121 }
5122
5123 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5124 {
5125 int r;
5126 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5127 vcpu->run->request_interrupt_window;
5128
5129 if (vcpu->requests) {
5130 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5131 kvm_mmu_unload(vcpu);
5132 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5133 __kvm_migrate_timers(vcpu);
5134 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5135 r = kvm_guest_time_update(vcpu);
5136 if (unlikely(r))
5137 goto out;
5138 }
5139 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5140 kvm_mmu_sync_roots(vcpu);
5141 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5142 kvm_x86_ops->tlb_flush(vcpu);
5143 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5144 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5145 r = 0;
5146 goto out;
5147 }
5148 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5149 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5150 r = 0;
5151 goto out;
5152 }
5153 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5154 vcpu->fpu_active = 0;
5155 kvm_x86_ops->fpu_deactivate(vcpu);
5156 }
5157 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5158 /* Page is swapped out. Do synthetic halt */
5159 vcpu->arch.apf.halted = true;
5160 r = 1;
5161 goto out;
5162 }
5163 }
5164
5165 r = kvm_mmu_reload(vcpu);
5166 if (unlikely(r))
5167 goto out;
5168
5169 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5170 inject_pending_event(vcpu);
5171
5172 /* enable NMI/IRQ window open exits if needed */
5173 if (vcpu->arch.nmi_pending)
5174 kvm_x86_ops->enable_nmi_window(vcpu);
5175 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5176 kvm_x86_ops->enable_irq_window(vcpu);
5177
5178 if (kvm_lapic_enabled(vcpu)) {
5179 update_cr8_intercept(vcpu);
5180 kvm_lapic_sync_to_vapic(vcpu);
5181 }
5182 }
5183
5184 preempt_disable();
5185
5186 kvm_x86_ops->prepare_guest_switch(vcpu);
5187 if (vcpu->fpu_active)
5188 kvm_load_guest_fpu(vcpu);
5189 kvm_load_guest_xcr0(vcpu);
5190
5191 atomic_set(&vcpu->guest_mode, 1);
5192 smp_wmb();
5193
5194 local_irq_disable();
5195
5196 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5197 || need_resched() || signal_pending(current)) {
5198 atomic_set(&vcpu->guest_mode, 0);
5199 smp_wmb();
5200 local_irq_enable();
5201 preempt_enable();
5202 kvm_x86_ops->cancel_injection(vcpu);
5203 r = 1;
5204 goto out;
5205 }
5206
5207 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5208
5209 kvm_guest_enter();
5210
5211 if (unlikely(vcpu->arch.switch_db_regs)) {
5212 set_debugreg(0, 7);
5213 set_debugreg(vcpu->arch.eff_db[0], 0);
5214 set_debugreg(vcpu->arch.eff_db[1], 1);
5215 set_debugreg(vcpu->arch.eff_db[2], 2);
5216 set_debugreg(vcpu->arch.eff_db[3], 3);
5217 }
5218
5219 trace_kvm_entry(vcpu->vcpu_id);
5220 kvm_x86_ops->run(vcpu);
5221
5222 /*
5223 * If the guest has used debug registers, at least dr7
5224 * will be disabled while returning to the host.
5225 * If we don't have active breakpoints in the host, we don't
5226 * care about the messed up debug address registers. But if
5227 * we have some of them active, restore the old state.
5228 */
5229 if (hw_breakpoint_active())
5230 hw_breakpoint_restore();
5231
5232 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5233
5234 atomic_set(&vcpu->guest_mode, 0);
5235 smp_wmb();
5236 local_irq_enable();
5237
5238 ++vcpu->stat.exits;
5239
5240 /*
5241 * We must have an instruction between local_irq_enable() and
5242 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5243 * the interrupt shadow. The stat.exits increment will do nicely.
5244 * But we need to prevent reordering, hence this barrier():
5245 */
5246 barrier();
5247
5248 kvm_guest_exit();
5249
5250 preempt_enable();
5251
5252 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5253
5254 /*
5255 * Profile KVM exit RIPs:
5256 */
5257 if (unlikely(prof_on == KVM_PROFILING)) {
5258 unsigned long rip = kvm_rip_read(vcpu);
5259 profile_hit(KVM_PROFILING, (void *)rip);
5260 }
5261
5262
5263 kvm_lapic_sync_from_vapic(vcpu);
5264
5265 r = kvm_x86_ops->handle_exit(vcpu);
5266 out:
5267 return r;
5268 }
5269
5270
5271 static int __vcpu_run(struct kvm_vcpu *vcpu)
5272 {
5273 int r;
5274 struct kvm *kvm = vcpu->kvm;
5275
5276 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5277 pr_debug("vcpu %d received sipi with vector # %x\n",
5278 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5279 kvm_lapic_reset(vcpu);
5280 r = kvm_arch_vcpu_reset(vcpu);
5281 if (r)
5282 return r;
5283 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5284 }
5285
5286 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5287 vapic_enter(vcpu);
5288
5289 r = 1;
5290 while (r > 0) {
5291 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5292 !vcpu->arch.apf.halted)
5293 r = vcpu_enter_guest(vcpu);
5294 else {
5295 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5296 kvm_vcpu_block(vcpu);
5297 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5298 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5299 {
5300 switch(vcpu->arch.mp_state) {
5301 case KVM_MP_STATE_HALTED:
5302 vcpu->arch.mp_state =
5303 KVM_MP_STATE_RUNNABLE;
5304 case KVM_MP_STATE_RUNNABLE:
5305 vcpu->arch.apf.halted = false;
5306 break;
5307 case KVM_MP_STATE_SIPI_RECEIVED:
5308 default:
5309 r = -EINTR;
5310 break;
5311 }
5312 }
5313 }
5314
5315 if (r <= 0)
5316 break;
5317
5318 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5319 if (kvm_cpu_has_pending_timer(vcpu))
5320 kvm_inject_pending_timer_irqs(vcpu);
5321
5322 if (dm_request_for_irq_injection(vcpu)) {
5323 r = -EINTR;
5324 vcpu->run->exit_reason = KVM_EXIT_INTR;
5325 ++vcpu->stat.request_irq_exits;
5326 }
5327
5328 kvm_check_async_pf_completion(vcpu);
5329
5330 if (signal_pending(current)) {
5331 r = -EINTR;
5332 vcpu->run->exit_reason = KVM_EXIT_INTR;
5333 ++vcpu->stat.signal_exits;
5334 }
5335 if (need_resched()) {
5336 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5337 kvm_resched(vcpu);
5338 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5339 }
5340 }
5341
5342 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5343
5344 vapic_exit(vcpu);
5345
5346 return r;
5347 }
5348
5349 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5350 {
5351 int r;
5352 sigset_t sigsaved;
5353
5354 if (vcpu->sigset_active)
5355 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5356
5357 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5358 kvm_vcpu_block(vcpu);
5359 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5360 r = -EAGAIN;
5361 goto out;
5362 }
5363
5364 /* re-sync apic's tpr */
5365 if (!irqchip_in_kernel(vcpu->kvm))
5366 kvm_set_cr8(vcpu, kvm_run->cr8);
5367
5368 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
5369 if (vcpu->mmio_needed) {
5370 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5371 vcpu->mmio_read_completed = 1;
5372 vcpu->mmio_needed = 0;
5373 }
5374 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5375 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
5376 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5377 if (r != EMULATE_DONE) {
5378 r = 0;
5379 goto out;
5380 }
5381 }
5382 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5383 kvm_register_write(vcpu, VCPU_REGS_RAX,
5384 kvm_run->hypercall.ret);
5385
5386 r = __vcpu_run(vcpu);
5387
5388 out:
5389 post_kvm_run_save(vcpu);
5390 if (vcpu->sigset_active)
5391 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5392
5393 return r;
5394 }
5395
5396 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5397 {
5398 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5399 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5400 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5401 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5402 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5403 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5404 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5405 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5406 #ifdef CONFIG_X86_64
5407 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5408 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5409 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5410 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5411 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5412 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5413 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5414 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5415 #endif
5416
5417 regs->rip = kvm_rip_read(vcpu);
5418 regs->rflags = kvm_get_rflags(vcpu);
5419
5420 return 0;
5421 }
5422
5423 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5424 {
5425 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5426 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5427 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5428 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5429 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5430 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5431 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5432 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5433 #ifdef CONFIG_X86_64
5434 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5435 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5436 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5437 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5438 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5439 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5440 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5441 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5442 #endif
5443
5444 kvm_rip_write(vcpu, regs->rip);
5445 kvm_set_rflags(vcpu, regs->rflags);
5446
5447 vcpu->arch.exception.pending = false;
5448
5449 kvm_make_request(KVM_REQ_EVENT, vcpu);
5450
5451 return 0;
5452 }
5453
5454 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5455 {
5456 struct kvm_segment cs;
5457
5458 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5459 *db = cs.db;
5460 *l = cs.l;
5461 }
5462 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5463
5464 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5465 struct kvm_sregs *sregs)
5466 {
5467 struct desc_ptr dt;
5468
5469 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5470 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5471 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5472 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5473 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5474 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5475
5476 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5477 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5478
5479 kvm_x86_ops->get_idt(vcpu, &dt);
5480 sregs->idt.limit = dt.size;
5481 sregs->idt.base = dt.address;
5482 kvm_x86_ops->get_gdt(vcpu, &dt);
5483 sregs->gdt.limit = dt.size;
5484 sregs->gdt.base = dt.address;
5485
5486 sregs->cr0 = kvm_read_cr0(vcpu);
5487 sregs->cr2 = vcpu->arch.cr2;
5488 sregs->cr3 = vcpu->arch.cr3;
5489 sregs->cr4 = kvm_read_cr4(vcpu);
5490 sregs->cr8 = kvm_get_cr8(vcpu);
5491 sregs->efer = vcpu->arch.efer;
5492 sregs->apic_base = kvm_get_apic_base(vcpu);
5493
5494 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5495
5496 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5497 set_bit(vcpu->arch.interrupt.nr,
5498 (unsigned long *)sregs->interrupt_bitmap);
5499
5500 return 0;
5501 }
5502
5503 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5504 struct kvm_mp_state *mp_state)
5505 {
5506 mp_state->mp_state = vcpu->arch.mp_state;
5507 return 0;
5508 }
5509
5510 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5511 struct kvm_mp_state *mp_state)
5512 {
5513 vcpu->arch.mp_state = mp_state->mp_state;
5514 kvm_make_request(KVM_REQ_EVENT, vcpu);
5515 return 0;
5516 }
5517
5518 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5519 bool has_error_code, u32 error_code)
5520 {
5521 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
5522 int ret;
5523
5524 init_emulate_ctxt(vcpu);
5525
5526 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
5527 tss_selector, reason, has_error_code,
5528 error_code);
5529
5530 if (ret)
5531 return EMULATE_FAIL;
5532
5533 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
5534 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
5535 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5536 kvm_make_request(KVM_REQ_EVENT, vcpu);
5537 return EMULATE_DONE;
5538 }
5539 EXPORT_SYMBOL_GPL(kvm_task_switch);
5540
5541 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5542 struct kvm_sregs *sregs)
5543 {
5544 int mmu_reset_needed = 0;
5545 int pending_vec, max_bits;
5546 struct desc_ptr dt;
5547
5548 dt.size = sregs->idt.limit;
5549 dt.address = sregs->idt.base;
5550 kvm_x86_ops->set_idt(vcpu, &dt);
5551 dt.size = sregs->gdt.limit;
5552 dt.address = sregs->gdt.base;
5553 kvm_x86_ops->set_gdt(vcpu, &dt);
5554
5555 vcpu->arch.cr2 = sregs->cr2;
5556 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
5557 vcpu->arch.cr3 = sregs->cr3;
5558
5559 kvm_set_cr8(vcpu, sregs->cr8);
5560
5561 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5562 kvm_x86_ops->set_efer(vcpu, sregs->efer);
5563 kvm_set_apic_base(vcpu, sregs->apic_base);
5564
5565 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5566 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5567 vcpu->arch.cr0 = sregs->cr0;
5568
5569 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5570 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5571 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5572 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
5573 mmu_reset_needed = 1;
5574 }
5575
5576 if (mmu_reset_needed)
5577 kvm_mmu_reset_context(vcpu);
5578
5579 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5580 pending_vec = find_first_bit(
5581 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5582 if (pending_vec < max_bits) {
5583 kvm_queue_interrupt(vcpu, pending_vec, false);
5584 pr_debug("Set back pending irq %d\n", pending_vec);
5585 if (irqchip_in_kernel(vcpu->kvm))
5586 kvm_pic_clear_isr_ack(vcpu->kvm);
5587 }
5588
5589 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5590 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5591 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5592 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5593 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5594 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5595
5596 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5597 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5598
5599 update_cr8_intercept(vcpu);
5600
5601 /* Older userspace won't unhalt the vcpu on reset. */
5602 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5603 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5604 !is_protmode(vcpu))
5605 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5606
5607 kvm_make_request(KVM_REQ_EVENT, vcpu);
5608
5609 return 0;
5610 }
5611
5612 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5613 struct kvm_guest_debug *dbg)
5614 {
5615 unsigned long rflags;
5616 int i, r;
5617
5618 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5619 r = -EBUSY;
5620 if (vcpu->arch.exception.pending)
5621 goto out;
5622 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5623 kvm_queue_exception(vcpu, DB_VECTOR);
5624 else
5625 kvm_queue_exception(vcpu, BP_VECTOR);
5626 }
5627
5628 /*
5629 * Read rflags as long as potentially injected trace flags are still
5630 * filtered out.
5631 */
5632 rflags = kvm_get_rflags(vcpu);
5633
5634 vcpu->guest_debug = dbg->control;
5635 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5636 vcpu->guest_debug = 0;
5637
5638 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5639 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5640 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5641 vcpu->arch.switch_db_regs =
5642 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5643 } else {
5644 for (i = 0; i < KVM_NR_DB_REGS; i++)
5645 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5646 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5647 }
5648
5649 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5650 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5651 get_segment_base(vcpu, VCPU_SREG_CS);
5652
5653 /*
5654 * Trigger an rflags update that will inject or remove the trace
5655 * flags.
5656 */
5657 kvm_set_rflags(vcpu, rflags);
5658
5659 kvm_x86_ops->set_guest_debug(vcpu, dbg);
5660
5661 r = 0;
5662
5663 out:
5664
5665 return r;
5666 }
5667
5668 /*
5669 * Translate a guest virtual address to a guest physical address.
5670 */
5671 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5672 struct kvm_translation *tr)
5673 {
5674 unsigned long vaddr = tr->linear_address;
5675 gpa_t gpa;
5676 int idx;
5677
5678 idx = srcu_read_lock(&vcpu->kvm->srcu);
5679 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5680 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5681 tr->physical_address = gpa;
5682 tr->valid = gpa != UNMAPPED_GVA;
5683 tr->writeable = 1;
5684 tr->usermode = 0;
5685
5686 return 0;
5687 }
5688
5689 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5690 {
5691 struct i387_fxsave_struct *fxsave =
5692 &vcpu->arch.guest_fpu.state->fxsave;
5693
5694 memcpy(fpu->fpr, fxsave->st_space, 128);
5695 fpu->fcw = fxsave->cwd;
5696 fpu->fsw = fxsave->swd;
5697 fpu->ftwx = fxsave->twd;
5698 fpu->last_opcode = fxsave->fop;
5699 fpu->last_ip = fxsave->rip;
5700 fpu->last_dp = fxsave->rdp;
5701 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5702
5703 return 0;
5704 }
5705
5706 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5707 {
5708 struct i387_fxsave_struct *fxsave =
5709 &vcpu->arch.guest_fpu.state->fxsave;
5710
5711 memcpy(fxsave->st_space, fpu->fpr, 128);
5712 fxsave->cwd = fpu->fcw;
5713 fxsave->swd = fpu->fsw;
5714 fxsave->twd = fpu->ftwx;
5715 fxsave->fop = fpu->last_opcode;
5716 fxsave->rip = fpu->last_ip;
5717 fxsave->rdp = fpu->last_dp;
5718 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5719
5720 return 0;
5721 }
5722
5723 int fx_init(struct kvm_vcpu *vcpu)
5724 {
5725 int err;
5726
5727 err = fpu_alloc(&vcpu->arch.guest_fpu);
5728 if (err)
5729 return err;
5730
5731 fpu_finit(&vcpu->arch.guest_fpu);
5732
5733 /*
5734 * Ensure guest xcr0 is valid for loading
5735 */
5736 vcpu->arch.xcr0 = XSTATE_FP;
5737
5738 vcpu->arch.cr0 |= X86_CR0_ET;
5739
5740 return 0;
5741 }
5742 EXPORT_SYMBOL_GPL(fx_init);
5743
5744 static void fx_free(struct kvm_vcpu *vcpu)
5745 {
5746 fpu_free(&vcpu->arch.guest_fpu);
5747 }
5748
5749 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5750 {
5751 if (vcpu->guest_fpu_loaded)
5752 return;
5753
5754 /*
5755 * Restore all possible states in the guest,
5756 * and assume host would use all available bits.
5757 * Guest xcr0 would be loaded later.
5758 */
5759 kvm_put_guest_xcr0(vcpu);
5760 vcpu->guest_fpu_loaded = 1;
5761 unlazy_fpu(current);
5762 fpu_restore_checking(&vcpu->arch.guest_fpu);
5763 trace_kvm_fpu(1);
5764 }
5765
5766 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5767 {
5768 kvm_put_guest_xcr0(vcpu);
5769
5770 if (!vcpu->guest_fpu_loaded)
5771 return;
5772
5773 vcpu->guest_fpu_loaded = 0;
5774 fpu_save_init(&vcpu->arch.guest_fpu);
5775 ++vcpu->stat.fpu_reload;
5776 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5777 trace_kvm_fpu(0);
5778 }
5779
5780 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5781 {
5782 if (vcpu->arch.time_page) {
5783 kvm_release_page_dirty(vcpu->arch.time_page);
5784 vcpu->arch.time_page = NULL;
5785 }
5786
5787 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5788 fx_free(vcpu);
5789 kvm_x86_ops->vcpu_free(vcpu);
5790 }
5791
5792 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5793 unsigned int id)
5794 {
5795 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5796 printk_once(KERN_WARNING
5797 "kvm: SMP vm created on host with unstable TSC; "
5798 "guest TSC will not be reliable\n");
5799 return kvm_x86_ops->vcpu_create(kvm, id);
5800 }
5801
5802 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5803 {
5804 int r;
5805
5806 vcpu->arch.mtrr_state.have_fixed = 1;
5807 vcpu_load(vcpu);
5808 r = kvm_arch_vcpu_reset(vcpu);
5809 if (r == 0)
5810 r = kvm_mmu_setup(vcpu);
5811 vcpu_put(vcpu);
5812 if (r < 0)
5813 goto free_vcpu;
5814
5815 return 0;
5816 free_vcpu:
5817 kvm_x86_ops->vcpu_free(vcpu);
5818 return r;
5819 }
5820
5821 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
5822 {
5823 vcpu->arch.apf.msr_val = 0;
5824
5825 vcpu_load(vcpu);
5826 kvm_mmu_unload(vcpu);
5827 vcpu_put(vcpu);
5828
5829 fx_free(vcpu);
5830 kvm_x86_ops->vcpu_free(vcpu);
5831 }
5832
5833 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5834 {
5835 vcpu->arch.nmi_pending = false;
5836 vcpu->arch.nmi_injected = false;
5837
5838 vcpu->arch.switch_db_regs = 0;
5839 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5840 vcpu->arch.dr6 = DR6_FIXED_1;
5841 vcpu->arch.dr7 = DR7_FIXED_1;
5842
5843 kvm_make_request(KVM_REQ_EVENT, vcpu);
5844 vcpu->arch.apf.msr_val = 0;
5845
5846 kvm_clear_async_pf_completion_queue(vcpu);
5847 kvm_async_pf_hash_reset(vcpu);
5848 vcpu->arch.apf.halted = false;
5849
5850 return kvm_x86_ops->vcpu_reset(vcpu);
5851 }
5852
5853 int kvm_arch_hardware_enable(void *garbage)
5854 {
5855 struct kvm *kvm;
5856 struct kvm_vcpu *vcpu;
5857 int i;
5858
5859 kvm_shared_msr_cpu_online();
5860 list_for_each_entry(kvm, &vm_list, vm_list)
5861 kvm_for_each_vcpu(i, vcpu, kvm)
5862 if (vcpu->cpu == smp_processor_id())
5863 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5864 return kvm_x86_ops->hardware_enable(garbage);
5865 }
5866
5867 void kvm_arch_hardware_disable(void *garbage)
5868 {
5869 kvm_x86_ops->hardware_disable(garbage);
5870 drop_user_return_notifiers(garbage);
5871 }
5872
5873 int kvm_arch_hardware_setup(void)
5874 {
5875 return kvm_x86_ops->hardware_setup();
5876 }
5877
5878 void kvm_arch_hardware_unsetup(void)
5879 {
5880 kvm_x86_ops->hardware_unsetup();
5881 }
5882
5883 void kvm_arch_check_processor_compat(void *rtn)
5884 {
5885 kvm_x86_ops->check_processor_compatibility(rtn);
5886 }
5887
5888 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5889 {
5890 struct page *page;
5891 struct kvm *kvm;
5892 int r;
5893
5894 BUG_ON(vcpu->kvm == NULL);
5895 kvm = vcpu->kvm;
5896
5897 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
5898 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
5899 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
5900 vcpu->arch.mmu.translate_gpa = translate_gpa;
5901 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5902 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
5903 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5904 else
5905 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
5906
5907 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5908 if (!page) {
5909 r = -ENOMEM;
5910 goto fail;
5911 }
5912 vcpu->arch.pio_data = page_address(page);
5913
5914 if (!kvm->arch.virtual_tsc_khz)
5915 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5916
5917 r = kvm_mmu_create(vcpu);
5918 if (r < 0)
5919 goto fail_free_pio_data;
5920
5921 if (irqchip_in_kernel(kvm)) {
5922 r = kvm_create_lapic(vcpu);
5923 if (r < 0)
5924 goto fail_mmu_destroy;
5925 }
5926
5927 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5928 GFP_KERNEL);
5929 if (!vcpu->arch.mce_banks) {
5930 r = -ENOMEM;
5931 goto fail_free_lapic;
5932 }
5933 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5934
5935 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5936 goto fail_free_mce_banks;
5937
5938 kvm_async_pf_hash_reset(vcpu);
5939
5940 return 0;
5941 fail_free_mce_banks:
5942 kfree(vcpu->arch.mce_banks);
5943 fail_free_lapic:
5944 kvm_free_lapic(vcpu);
5945 fail_mmu_destroy:
5946 kvm_mmu_destroy(vcpu);
5947 fail_free_pio_data:
5948 free_page((unsigned long)vcpu->arch.pio_data);
5949 fail:
5950 return r;
5951 }
5952
5953 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5954 {
5955 int idx;
5956
5957 kfree(vcpu->arch.mce_banks);
5958 kvm_free_lapic(vcpu);
5959 idx = srcu_read_lock(&vcpu->kvm->srcu);
5960 kvm_mmu_destroy(vcpu);
5961 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5962 free_page((unsigned long)vcpu->arch.pio_data);
5963 }
5964
5965 struct kvm *kvm_arch_create_vm(void)
5966 {
5967 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5968
5969 if (!kvm)
5970 return ERR_PTR(-ENOMEM);
5971
5972 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
5973 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
5974
5975 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5976 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5977
5978 spin_lock_init(&kvm->arch.tsc_write_lock);
5979
5980 return kvm;
5981 }
5982
5983 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5984 {
5985 vcpu_load(vcpu);
5986 kvm_mmu_unload(vcpu);
5987 vcpu_put(vcpu);
5988 }
5989
5990 static void kvm_free_vcpus(struct kvm *kvm)
5991 {
5992 unsigned int i;
5993 struct kvm_vcpu *vcpu;
5994
5995 /*
5996 * Unpin any mmu pages first.
5997 */
5998 kvm_for_each_vcpu(i, vcpu, kvm) {
5999 kvm_clear_async_pf_completion_queue(vcpu);
6000 kvm_unload_vcpu_mmu(vcpu);
6001 }
6002 kvm_for_each_vcpu(i, vcpu, kvm)
6003 kvm_arch_vcpu_free(vcpu);
6004
6005 mutex_lock(&kvm->lock);
6006 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6007 kvm->vcpus[i] = NULL;
6008
6009 atomic_set(&kvm->online_vcpus, 0);
6010 mutex_unlock(&kvm->lock);
6011 }
6012
6013 void kvm_arch_sync_events(struct kvm *kvm)
6014 {
6015 kvm_free_all_assigned_devices(kvm);
6016 kvm_free_pit(kvm);
6017 }
6018
6019 void kvm_arch_destroy_vm(struct kvm *kvm)
6020 {
6021 kvm_iommu_unmap_guest(kvm);
6022 kfree(kvm->arch.vpic);
6023 kfree(kvm->arch.vioapic);
6024 kvm_free_vcpus(kvm);
6025 kvm_free_physmem(kvm);
6026 if (kvm->arch.apic_access_page)
6027 put_page(kvm->arch.apic_access_page);
6028 if (kvm->arch.ept_identity_pagetable)
6029 put_page(kvm->arch.ept_identity_pagetable);
6030 cleanup_srcu_struct(&kvm->srcu);
6031 kfree(kvm);
6032 }
6033
6034 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6035 struct kvm_memory_slot *memslot,
6036 struct kvm_memory_slot old,
6037 struct kvm_userspace_memory_region *mem,
6038 int user_alloc)
6039 {
6040 int npages = memslot->npages;
6041 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6042
6043 /* Prevent internal slot pages from being moved by fork()/COW. */
6044 if (memslot->id >= KVM_MEMORY_SLOTS)
6045 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6046
6047 /*To keep backward compatibility with older userspace,
6048 *x86 needs to hanlde !user_alloc case.
6049 */
6050 if (!user_alloc) {
6051 if (npages && !old.rmap) {
6052 unsigned long userspace_addr;
6053
6054 down_write(&current->mm->mmap_sem);
6055 userspace_addr = do_mmap(NULL, 0,
6056 npages * PAGE_SIZE,
6057 PROT_READ | PROT_WRITE,
6058 map_flags,
6059 0);
6060 up_write(&current->mm->mmap_sem);
6061
6062 if (IS_ERR((void *)userspace_addr))
6063 return PTR_ERR((void *)userspace_addr);
6064
6065 memslot->userspace_addr = userspace_addr;
6066 }
6067 }
6068
6069
6070 return 0;
6071 }
6072
6073 void kvm_arch_commit_memory_region(struct kvm *kvm,
6074 struct kvm_userspace_memory_region *mem,
6075 struct kvm_memory_slot old,
6076 int user_alloc)
6077 {
6078
6079 int npages = mem->memory_size >> PAGE_SHIFT;
6080
6081 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6082 int ret;
6083
6084 down_write(&current->mm->mmap_sem);
6085 ret = do_munmap(current->mm, old.userspace_addr,
6086 old.npages * PAGE_SIZE);
6087 up_write(&current->mm->mmap_sem);
6088 if (ret < 0)
6089 printk(KERN_WARNING
6090 "kvm_vm_ioctl_set_memory_region: "
6091 "failed to munmap memory\n");
6092 }
6093
6094 spin_lock(&kvm->mmu_lock);
6095 if (!kvm->arch.n_requested_mmu_pages) {
6096 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6097 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6098 }
6099
6100 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6101 spin_unlock(&kvm->mmu_lock);
6102 }
6103
6104 void kvm_arch_flush_shadow(struct kvm *kvm)
6105 {
6106 kvm_mmu_zap_all(kvm);
6107 kvm_reload_remote_mmus(kvm);
6108 }
6109
6110 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6111 {
6112 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6113 !vcpu->arch.apf.halted)
6114 || !list_empty_careful(&vcpu->async_pf.done)
6115 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6116 || vcpu->arch.nmi_pending ||
6117 (kvm_arch_interrupt_allowed(vcpu) &&
6118 kvm_cpu_has_interrupt(vcpu));
6119 }
6120
6121 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6122 {
6123 int me;
6124 int cpu = vcpu->cpu;
6125
6126 if (waitqueue_active(&vcpu->wq)) {
6127 wake_up_interruptible(&vcpu->wq);
6128 ++vcpu->stat.halt_wakeup;
6129 }
6130
6131 me = get_cpu();
6132 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6133 if (atomic_xchg(&vcpu->guest_mode, 0))
6134 smp_send_reschedule(cpu);
6135 put_cpu();
6136 }
6137
6138 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6139 {
6140 return kvm_x86_ops->interrupt_allowed(vcpu);
6141 }
6142
6143 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6144 {
6145 unsigned long current_rip = kvm_rip_read(vcpu) +
6146 get_segment_base(vcpu, VCPU_SREG_CS);
6147
6148 return current_rip == linear_rip;
6149 }
6150 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6151
6152 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6153 {
6154 unsigned long rflags;
6155
6156 rflags = kvm_x86_ops->get_rflags(vcpu);
6157 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6158 rflags &= ~X86_EFLAGS_TF;
6159 return rflags;
6160 }
6161 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6162
6163 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6164 {
6165 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6166 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6167 rflags |= X86_EFLAGS_TF;
6168 kvm_x86_ops->set_rflags(vcpu, rflags);
6169 kvm_make_request(KVM_REQ_EVENT, vcpu);
6170 }
6171 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6172
6173 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6174 {
6175 int r;
6176
6177 if (!vcpu->arch.mmu.direct_map || is_error_page(work->page))
6178 return;
6179
6180 r = kvm_mmu_reload(vcpu);
6181 if (unlikely(r))
6182 return;
6183
6184 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6185 }
6186
6187 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6188 {
6189 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6190 }
6191
6192 static inline u32 kvm_async_pf_next_probe(u32 key)
6193 {
6194 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6195 }
6196
6197 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6198 {
6199 u32 key = kvm_async_pf_hash_fn(gfn);
6200
6201 while (vcpu->arch.apf.gfns[key] != ~0)
6202 key = kvm_async_pf_next_probe(key);
6203
6204 vcpu->arch.apf.gfns[key] = gfn;
6205 }
6206
6207 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6208 {
6209 int i;
6210 u32 key = kvm_async_pf_hash_fn(gfn);
6211
6212 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6213 (vcpu->arch.apf.gfns[key] != gfn ||
6214 vcpu->arch.apf.gfns[key] == ~0); i++)
6215 key = kvm_async_pf_next_probe(key);
6216
6217 return key;
6218 }
6219
6220 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6221 {
6222 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6223 }
6224
6225 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6226 {
6227 u32 i, j, k;
6228
6229 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6230 while (true) {
6231 vcpu->arch.apf.gfns[i] = ~0;
6232 do {
6233 j = kvm_async_pf_next_probe(j);
6234 if (vcpu->arch.apf.gfns[j] == ~0)
6235 return;
6236 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6237 /*
6238 * k lies cyclically in ]i,j]
6239 * | i.k.j |
6240 * |....j i.k.| or |.k..j i...|
6241 */
6242 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6243 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6244 i = j;
6245 }
6246 }
6247
6248 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6249 {
6250
6251 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6252 sizeof(val));
6253 }
6254
6255 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6256 struct kvm_async_pf *work)
6257 {
6258 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
6259 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6260
6261 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
6262 (vcpu->arch.apf.send_user_only &&
6263 kvm_x86_ops->get_cpl(vcpu) == 0))
6264 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6265 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6266 vcpu->arch.fault.error_code = 0;
6267 vcpu->arch.fault.address = work->arch.token;
6268 kvm_inject_page_fault(vcpu);
6269 }
6270 }
6271
6272 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6273 struct kvm_async_pf *work)
6274 {
6275 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6276 if (is_error_page(work->page))
6277 work->arch.token = ~0; /* broadcast wakeup */
6278 else
6279 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6280
6281 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6282 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6283 vcpu->arch.fault.error_code = 0;
6284 vcpu->arch.fault.address = work->arch.token;
6285 kvm_inject_page_fault(vcpu);
6286 }
6287 }
6288
6289 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6290 {
6291 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6292 return true;
6293 else
6294 return !kvm_event_needs_reinjection(vcpu) &&
6295 kvm_x86_ops->interrupt_allowed(vcpu);
6296 }
6297
6298 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6299 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6300 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6301 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6302 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6303 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6304 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6305 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6306 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6307 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6308 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6309 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kvm source repo for ia64