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[PATCH] bcm43xx: check for valid MAC address in SPROM
[linux-2.6/kmemtrace.git] / drivers / net / wireless / bcm43xx / bcm43xx_main.c
blob4be2d9b5749ba44d7f3206ef033b02cf37c39e44
1 /*
2
3 Broadcom BCM43xx wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <net/iw_handler.h>
43
44 #include "bcm43xx.h"
45 #include "bcm43xx_main.h"
46 #include "bcm43xx_debugfs.h"
47 #include "bcm43xx_radio.h"
48 #include "bcm43xx_phy.h"
49 #include "bcm43xx_dma.h"
50 #include "bcm43xx_pio.h"
51 #include "bcm43xx_power.h"
52 #include "bcm43xx_wx.h"
53 #include "bcm43xx_ethtool.h"
54 #include "bcm43xx_xmit.h"
55 #include "bcm43xx_sysfs.h"
56
57
58 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
59 MODULE_AUTHOR("Martin Langer");
60 MODULE_AUTHOR("Stefano Brivio");
61 MODULE_AUTHOR("Michael Buesch");
62 MODULE_LICENSE("GPL");
63
64 #ifdef CONFIG_BCM947XX
65 extern char *nvram_get(char *name);
66 #endif
67
68 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
69 static int modparam_pio;
70 module_param_named(pio, modparam_pio, int, 0444);
71 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
72 #elif defined(CONFIG_BCM43XX_DMA)
73 # define modparam_pio 0
74 #elif defined(CONFIG_BCM43XX_PIO)
75 # define modparam_pio 1
76 #endif
77
78 static int modparam_bad_frames_preempt;
79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
81
82 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
83 module_param_named(short_retry, modparam_short_retry, int, 0444);
84 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
85
86 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
87 module_param_named(long_retry, modparam_long_retry, int, 0444);
88 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
89
90 static int modparam_locale = -1;
91 module_param_named(locale, modparam_locale, int, 0444);
92 MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
93
94 static int modparam_noleds;
95 module_param_named(noleds, modparam_noleds, int, 0444);
96 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
97
98 #ifdef CONFIG_BCM43XX_DEBUG
99 static char modparam_fwpostfix[64];
100 module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
101 MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
102 #else
103 # define modparam_fwpostfix ""
104 #endif /* CONFIG_BCM43XX_DEBUG*/
105
106
107 /* If you want to debug with just a single device, enable this,
108 * where the string is the pci device ID (as given by the kernel's
109 * pci_name function) of the device to be used.
110 */
111 //#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
112
113 /* If you want to enable printing of each MMIO access, enable this. */
114 //#define DEBUG_ENABLE_MMIO_PRINT
115
116 /* If you want to enable printing of MMIO access within
117 * ucode/pcm upload, initvals write, enable this.
118 */
119 //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
120
121 /* If you want to enable printing of PCI Config Space access, enable this */
122 //#define DEBUG_ENABLE_PCILOG
123
124
125 /* Detailed list maintained at:
126 * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
127 */
128 static struct pci_device_id bcm43xx_pci_tbl[] = {
129 /* Broadcom 4303 802.11b */
130 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 /* Broadcom 4307 802.11b */
132 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 /* Broadcom 4318 802.11b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4306 802.11b/g */
136 { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 /* Broadcom 4306 802.11a */
138 // { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 /* Broadcom 4309 802.11a/b/g */
140 { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 /* Broadcom 43XG 802.11b/g */
142 { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 #ifdef CONFIG_BCM947XX
144 /* SB bus on BCM947xx */
145 { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
146 #endif
147 { 0 },
148 };
149 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
150
151 static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
152 {
153 u32 status;
154
155 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
156 if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
157 val = swab32(val);
158
159 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
160 mmiowb();
161 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
162 }
163
164 static inline
165 void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
166 u16 routing, u16 offset)
167 {
168 u32 control;
169
170 /* "offset" is the WORD offset. */
171
172 control = routing;
173 control <<= 16;
174 control |= offset;
175 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
176 }
177
178 u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
179 u16 routing, u16 offset)
180 {
181 u32 ret;
182
183 if (routing == BCM43xx_SHM_SHARED) {
184 if (offset & 0x0003) {
185 /* Unaligned access */
186 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
187 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
188 ret <<= 16;
189 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
190 ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
191
192 return ret;
193 }
194 offset >>= 2;
195 }
196 bcm43xx_shm_control_word(bcm, routing, offset);
197 ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
198
199 return ret;
200 }
201
202 u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
203 u16 routing, u16 offset)
204 {
205 u16 ret;
206
207 if (routing == BCM43xx_SHM_SHARED) {
208 if (offset & 0x0003) {
209 /* Unaligned access */
210 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
211 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
212
213 return ret;
214 }
215 offset >>= 2;
216 }
217 bcm43xx_shm_control_word(bcm, routing, offset);
218 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
219
220 return ret;
221 }
222
223 void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
224 u16 routing, u16 offset,
225 u32 value)
226 {
227 if (routing == BCM43xx_SHM_SHARED) {
228 if (offset & 0x0003) {
229 /* Unaligned access */
230 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
231 mmiowb();
232 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
233 (value >> 16) & 0xffff);
234 mmiowb();
235 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
236 mmiowb();
237 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
238 value & 0xffff);
239 return;
240 }
241 offset >>= 2;
242 }
243 bcm43xx_shm_control_word(bcm, routing, offset);
244 mmiowb();
245 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
246 }
247
248 void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
249 u16 routing, u16 offset,
250 u16 value)
251 {
252 if (routing == BCM43xx_SHM_SHARED) {
253 if (offset & 0x0003) {
254 /* Unaligned access */
255 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
256 mmiowb();
257 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
258 value);
259 return;
260 }
261 offset >>= 2;
262 }
263 bcm43xx_shm_control_word(bcm, routing, offset);
264 mmiowb();
265 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
266 }
267
268 void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
269 {
270 /* We need to be careful. As we read the TSF from multiple
271 * registers, we should take care of register overflows.
272 * In theory, the whole tsf read process should be atomic.
273 * We try to be atomic here, by restaring the read process,
274 * if any of the high registers changed (overflew).
275 */
276 if (bcm->current_core->rev >= 3) {
277 u32 low, high, high2;
278
279 do {
280 high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
281 low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
282 high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
283 } while (unlikely(high != high2));
284
285 *tsf = high;
286 *tsf <<= 32;
287 *tsf |= low;
288 } else {
289 u64 tmp;
290 u16 v0, v1, v2, v3;
291 u16 test1, test2, test3;
292
293 do {
294 v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
295 v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
296 v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
297 v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
298
299 test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
300 test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
301 test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
302 } while (v3 != test3 || v2 != test2 || v1 != test1);
303
304 *tsf = v3;
305 *tsf <<= 48;
306 tmp = v2;
307 tmp <<= 32;
308 *tsf |= tmp;
309 tmp = v1;
310 tmp <<= 16;
311 *tsf |= tmp;
312 *tsf |= v0;
313 }
314 }
315
316 void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
317 {
318 u32 status;
319
320 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
321 status |= BCM43xx_SBF_TIME_UPDATE;
322 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
323 mmiowb();
324
325 /* Be careful with the in-progress timer.
326 * First zero out the low register, so we have a full
327 * register-overflow duration to complete the operation.
328 */
329 if (bcm->current_core->rev >= 3) {
330 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
331 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
332
333 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
334 mmiowb();
335 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
336 mmiowb();
337 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
338 } else {
339 u16 v0 = (tsf & 0x000000000000FFFFULL);
340 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
341 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
342 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
343
344 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
345 mmiowb();
346 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
347 mmiowb();
348 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
349 mmiowb();
350 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
351 mmiowb();
352 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
353 }
354
355 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
356 status &= ~BCM43xx_SBF_TIME_UPDATE;
357 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
358 }
359
360 static
361 void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
362 u16 offset,
363 const u8 *mac)
364 {
365 u16 data;
366
367 offset |= 0x0020;
368 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
369
370 data = mac[0];
371 data |= mac[1] << 8;
372 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
373 data = mac[2];
374 data |= mac[3] << 8;
375 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
376 data = mac[4];
377 data |= mac[5] << 8;
378 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
379 }
380
381 static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
382 u16 offset)
383 {
384 const u8 zero_addr[ETH_ALEN] = { 0 };
385
386 bcm43xx_macfilter_set(bcm, offset, zero_addr);
387 }
388
389 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
390 {
391 const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
392 const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
393 u8 mac_bssid[ETH_ALEN * 2];
394 int i;
395
396 memcpy(mac_bssid, mac, ETH_ALEN);
397 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
398
399 /* Write our MAC address and BSSID to template ram */
400 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
401 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
402 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
403 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
404 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
405 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
406 }
407
408 //FIXME: Well, we should probably call them from somewhere.
409 #if 0
410 static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
411 {
412 /* slot_time is in usec. */
413 if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
414 return;
415 bcm43xx_write16(bcm, 0x684, 510 + slot_time);
416 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
417 }
418
419 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
420 {
421 bcm43xx_set_slot_time(bcm, 9);
422 }
423
424 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
425 {
426 bcm43xx_set_slot_time(bcm, 20);
427 }
428 #endif
429
430 /* FIXME: To get the MAC-filter working, we need to implement the
431 * following functions (and rename them :)
432 */
433 #if 0
434 static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
435 {
436 bcm43xx_mac_suspend(bcm);
437 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
438
439 bcm43xx_ram_write(bcm, 0x0026, 0x0000);
440 bcm43xx_ram_write(bcm, 0x0028, 0x0000);
441 bcm43xx_ram_write(bcm, 0x007E, 0x0000);
442 bcm43xx_ram_write(bcm, 0x0080, 0x0000);
443 bcm43xx_ram_write(bcm, 0x047E, 0x0000);
444 bcm43xx_ram_write(bcm, 0x0480, 0x0000);
445
446 if (bcm->current_core->rev < 3) {
447 bcm43xx_write16(bcm, 0x0610, 0x8000);
448 bcm43xx_write16(bcm, 0x060E, 0x0000);
449 } else
450 bcm43xx_write32(bcm, 0x0188, 0x80000000);
451
452 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
453
454 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
455 ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
456 bcm43xx_short_slot_timing_enable(bcm);
457
458 bcm43xx_mac_enable(bcm);
459 }
460
461 static void bcm43xx_associate(struct bcm43xx_private *bcm,
462 const u8 *mac)
463 {
464 memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
465
466 bcm43xx_mac_suspend(bcm);
467 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
468 bcm43xx_write_mac_bssid_templates(bcm);
469 bcm43xx_mac_enable(bcm);
470 }
471 #endif
472
473 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
474 * Returns the _previously_ enabled IRQ mask.
475 */
476 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
477 {
478 u32 old_mask;
479
480 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
481 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
482
483 return old_mask;
484 }
485
486 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
487 * Returns the _previously_ enabled IRQ mask.
488 */
489 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
490 {
491 u32 old_mask;
492
493 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
494 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
495
496 return old_mask;
497 }
498
499 /* Make sure we don't receive more data from the device. */
500 static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm, u32 *oldstate)
501 {
502 u32 old;
503 unsigned long flags;
504
505 bcm43xx_lock_mmio(bcm, flags);
506 if (bcm43xx_is_initializing(bcm) || bcm->shutting_down) {
507 bcm43xx_unlock_mmio(bcm, flags);
508 return -EBUSY;
509 }
510 old = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
511 tasklet_disable(&bcm->isr_tasklet);
512 bcm43xx_unlock_mmio(bcm, flags);
513 if (oldstate)
514 *oldstate = old;
515
516 return 0;
517 }
518
519 static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
520 {
521 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
522 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
523 u32 radio_id;
524 u16 manufact;
525 u16 version;
526 u8 revision;
527 s8 i;
528
529 if (bcm->chip_id == 0x4317) {
530 if (bcm->chip_rev == 0x00)
531 radio_id = 0x3205017F;
532 else if (bcm->chip_rev == 0x01)
533 radio_id = 0x4205017F;
534 else
535 radio_id = 0x5205017F;
536 } else {
537 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
538 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
539 radio_id <<= 16;
540 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
541 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
542 }
543
544 manufact = (radio_id & 0x00000FFF);
545 version = (radio_id & 0x0FFFF000) >> 12;
546 revision = (radio_id & 0xF0000000) >> 28;
547
548 dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
549 radio_id, manufact, version, revision);
550
551 switch (phy->type) {
552 case BCM43xx_PHYTYPE_A:
553 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
554 goto err_unsupported_radio;
555 break;
556 case BCM43xx_PHYTYPE_B:
557 if ((version & 0xFFF0) != 0x2050)
558 goto err_unsupported_radio;
559 break;
560 case BCM43xx_PHYTYPE_G:
561 if (version != 0x2050)
562 goto err_unsupported_radio;
563 break;
564 }
565
566 radio->manufact = manufact;
567 radio->version = version;
568 radio->revision = revision;
569
570 /* Set default attenuation values. */
571 radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
572 radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
573 radio->txctl1 = bcm43xx_default_txctl1(bcm);
574 radio->txctl2 = 0xFFFF;
575 if (phy->type == BCM43xx_PHYTYPE_A)
576 radio->txpower_desired = bcm->sprom.maxpower_aphy;
577 else
578 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
579
580 /* Initialize the in-memory nrssi Lookup Table. */
581 for (i = 0; i < 64; i++)
582 radio->nrssi_lt[i] = i;
583
584 return 0;
585
586 err_unsupported_radio:
587 printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
588 return -ENODEV;
589 }
590
591 static const char * bcm43xx_locale_iso(u8 locale)
592 {
593 /* ISO 3166-1 country codes.
594 * Note that there aren't ISO 3166-1 codes for
595 * all or locales. (Not all locales are countries)
596 */
597 switch (locale) {
598 case BCM43xx_LOCALE_WORLD:
599 case BCM43xx_LOCALE_ALL:
600 return "XX";
601 case BCM43xx_LOCALE_THAILAND:
602 return "TH";
603 case BCM43xx_LOCALE_ISRAEL:
604 return "IL";
605 case BCM43xx_LOCALE_JORDAN:
606 return "JO";
607 case BCM43xx_LOCALE_CHINA:
608 return "CN";
609 case BCM43xx_LOCALE_JAPAN:
610 case BCM43xx_LOCALE_JAPAN_HIGH:
611 return "JP";
612 case BCM43xx_LOCALE_USA_CANADA_ANZ:
613 case BCM43xx_LOCALE_USA_LOW:
614 return "US";
615 case BCM43xx_LOCALE_EUROPE:
616 return "EU";
617 case BCM43xx_LOCALE_NONE:
618 return " ";
619 }
620 assert(0);
621 return " ";
622 }
623
624 static const char * bcm43xx_locale_string(u8 locale)
625 {
626 switch (locale) {
627 case BCM43xx_LOCALE_WORLD:
628 return "World";
629 case BCM43xx_LOCALE_THAILAND:
630 return "Thailand";
631 case BCM43xx_LOCALE_ISRAEL:
632 return "Israel";
633 case BCM43xx_LOCALE_JORDAN:
634 return "Jordan";
635 case BCM43xx_LOCALE_CHINA:
636 return "China";
637 case BCM43xx_LOCALE_JAPAN:
638 return "Japan";
639 case BCM43xx_LOCALE_USA_CANADA_ANZ:
640 return "USA/Canada/ANZ";
641 case BCM43xx_LOCALE_EUROPE:
642 return "Europe";
643 case BCM43xx_LOCALE_USA_LOW:
644 return "USAlow";
645 case BCM43xx_LOCALE_JAPAN_HIGH:
646 return "JapanHigh";
647 case BCM43xx_LOCALE_ALL:
648 return "All";
649 case BCM43xx_LOCALE_NONE:
650 return "None";
651 }
652 assert(0);
653 return "";
654 }
655
656 static inline u8 bcm43xx_crc8(u8 crc, u8 data)
657 {
658 static const u8 t[] = {
659 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
660 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
661 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
662 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
663 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
664 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
665 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
666 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
667 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
668 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
669 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
670 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
671 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
672 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
673 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
674 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
675 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
676 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
677 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
678 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
679 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
680 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
681 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
682 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
683 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
684 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
685 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
686 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
687 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
688 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
689 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
690 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
691 };
692 return t[crc ^ data];
693 }
694
695 static u8 bcm43xx_sprom_crc(const u16 *sprom)
696 {
697 int word;
698 u8 crc = 0xFF;
699
700 for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
701 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
702 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
703 }
704 crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
705 crc ^= 0xFF;
706
707 return crc;
708 }
709
710 int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
711 {
712 int i;
713 u8 crc, expected_crc;
714
715 for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
716 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
717 /* CRC-8 check. */
718 crc = bcm43xx_sprom_crc(sprom);
719 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
720 if (crc != expected_crc) {
721 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
722 "(0x%02X, expected: 0x%02X)\n",
723 crc, expected_crc);
724 return -EINVAL;
725 }
726
727 return 0;
728 }
729
730 int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
731 {
732 int i, err;
733 u8 crc, expected_crc;
734 u32 spromctl;
735
736 /* CRC-8 validation of the input data. */
737 crc = bcm43xx_sprom_crc(sprom);
738 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
739 if (crc != expected_crc) {
740 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
741 return -EINVAL;
742 }
743
744 printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
745 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
746 if (err)
747 goto err_ctlreg;
748 spromctl |= 0x10; /* SPROM WRITE enable. */
749 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
750 if (err)
751 goto err_ctlreg;
752 /* We must burn lots of CPU cycles here, but that does not
753 * really matter as one does not write the SPROM every other minute...
754 */
755 printk(KERN_INFO PFX "[ 0%%");
756 mdelay(500);
757 for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
758 if (i == 16)
759 printk("25%%");
760 else if (i == 32)
761 printk("50%%");
762 else if (i == 48)
763 printk("75%%");
764 else if (i % 2)
765 printk(".");
766 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
767 mmiowb();
768 mdelay(20);
769 }
770 spromctl &= ~0x10; /* SPROM WRITE enable. */
771 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
772 if (err)
773 goto err_ctlreg;
774 mdelay(500);
775 printk("100%% ]\n");
776 printk(KERN_INFO PFX "SPROM written.\n");
777 bcm43xx_controller_restart(bcm, "SPROM update");
778
779 return 0;
780 err_ctlreg:
781 printk(KERN_ERR PFX "Could not access SPROM control register.\n");
782 return -ENODEV;
783 }
784
785 static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
786 {
787 u16 value;
788 u16 *sprom;
789 #ifdef CONFIG_BCM947XX
790 char *c;
791 #endif
792
793 sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
794 GFP_KERNEL);
795 if (!sprom) {
796 printk(KERN_ERR PFX "sprom_extract OOM\n");
797 return -ENOMEM;
798 }
799 #ifdef CONFIG_BCM947XX
800 sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
801 sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
802
803 if ((c = nvram_get("il0macaddr")) != NULL)
804 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
805
806 if ((c = nvram_get("et1macaddr")) != NULL)
807 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
808
809 sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
810 sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
811 sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
812
813 sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
814 sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
815 sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
816
817 sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
818 #else
819 bcm43xx_sprom_read(bcm, sprom);
820 #endif
821
822 /* boardflags2 */
823 value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
824 bcm->sprom.boardflags2 = value;
825
826 /* il0macaddr */
827 value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
828 *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
829 value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
830 *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
831 value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
832 *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
833
834 /* et0macaddr */
835 value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
836 *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
837 value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
838 *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
839 value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
840 *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
841
842 /* et1macaddr */
843 value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
844 *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
845 value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
846 *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
847 value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
848 *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
849
850 /* ethernet phy settings */
851 value = sprom[BCM43xx_SPROM_ETHPHY];
852 bcm->sprom.et0phyaddr = (value & 0x001F);
853 bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
854 bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
855 bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
856
857 /* boardrev, antennas, locale */
858 value = sprom[BCM43xx_SPROM_BOARDREV];
859 bcm->sprom.boardrev = (value & 0x00FF);
860 bcm->sprom.locale = (value & 0x0F00) >> 8;
861 bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
862 bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
863 if (modparam_locale != -1) {
864 if (modparam_locale >= 0 && modparam_locale <= 11) {
865 bcm->sprom.locale = modparam_locale;
866 printk(KERN_WARNING PFX "Operating with modified "
867 "LocaleCode %u (%s)\n",
868 bcm->sprom.locale,
869 bcm43xx_locale_string(bcm->sprom.locale));
870 } else {
871 printk(KERN_WARNING PFX "Module parameter \"locale\" "
872 "invalid value. (0 - 11)\n");
873 }
874 }
875
876 /* pa0b* */
877 value = sprom[BCM43xx_SPROM_PA0B0];
878 bcm->sprom.pa0b0 = value;
879 value = sprom[BCM43xx_SPROM_PA0B1];
880 bcm->sprom.pa0b1 = value;
881 value = sprom[BCM43xx_SPROM_PA0B2];
882 bcm->sprom.pa0b2 = value;
883
884 /* wl0gpio* */
885 value = sprom[BCM43xx_SPROM_WL0GPIO0];
886 if (value == 0x0000)
887 value = 0xFFFF;
888 bcm->sprom.wl0gpio0 = value & 0x00FF;
889 bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
890 value = sprom[BCM43xx_SPROM_WL0GPIO2];
891 if (value == 0x0000)
892 value = 0xFFFF;
893 bcm->sprom.wl0gpio2 = value & 0x00FF;
894 bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
895
896 /* maxpower */
897 value = sprom[BCM43xx_SPROM_MAXPWR];
898 bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
899 bcm->sprom.maxpower_bgphy = value & 0x00FF;
900
901 /* pa1b* */
902 value = sprom[BCM43xx_SPROM_PA1B0];
903 bcm->sprom.pa1b0 = value;
904 value = sprom[BCM43xx_SPROM_PA1B1];
905 bcm->sprom.pa1b1 = value;
906 value = sprom[BCM43xx_SPROM_PA1B2];
907 bcm->sprom.pa1b2 = value;
908
909 /* idle tssi target */
910 value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
911 bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
912 bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
913
914 /* boardflags */
915 value = sprom[BCM43xx_SPROM_BOARDFLAGS];
916 if (value == 0xFFFF)
917 value = 0x0000;
918 bcm->sprom.boardflags = value;
919 /* boardflags workarounds */
920 if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
921 bcm->chip_id == 0x4301 &&
922 bcm->board_revision == 0x74)
923 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
924 if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
925 bcm->board_type == 0x4E &&
926 bcm->board_revision > 0x40)
927 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
928
929 /* antenna gain */
930 value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
931 if (value == 0x0000 || value == 0xFFFF)
932 value = 0x0202;
933 /* convert values to Q5.2 */
934 bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
935 bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
936
937 kfree(sprom);
938
939 return 0;
940 }
941
942 static void bcm43xx_geo_init(struct bcm43xx_private *bcm)
943 {
944 struct ieee80211_geo geo;
945 struct ieee80211_channel *chan;
946 int have_a = 0, have_bg = 0;
947 int i;
948 u8 channel;
949 struct bcm43xx_phyinfo *phy;
950 const char *iso_country;
951
952 memset(&geo, 0, sizeof(geo));
953 for (i = 0; i < bcm->nr_80211_available; i++) {
954 phy = &(bcm->core_80211_ext[i].phy);
955 switch (phy->type) {
956 case BCM43xx_PHYTYPE_B:
957 case BCM43xx_PHYTYPE_G:
958 have_bg = 1;
959 break;
960 case BCM43xx_PHYTYPE_A:
961 have_a = 1;
962 break;
963 default:
964 assert(0);
965 }
966 }
967 iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
968
969 if (have_a) {
970 for (i = 0, channel = 0; channel < 201; channel++) {
971 chan = &geo.a[i++];
972 chan->freq = bcm43xx_channel_to_freq_a(channel);
973 chan->channel = channel;
974 }
975 geo.a_channels = i;
976 }
977 if (have_bg) {
978 for (i = 0, channel = 1; channel < 15; channel++) {
979 chan = &geo.bg[i++];
980 chan->freq = bcm43xx_channel_to_freq_bg(channel);
981 chan->channel = channel;
982 }
983 geo.bg_channels = i;
984 }
985 memcpy(geo.name, iso_country, 2);
986 if (0 /*TODO: Outdoor use only */)
987 geo.name[2] = 'O';
988 else if (0 /*TODO: Indoor use only */)
989 geo.name[2] = 'I';
990 else
991 geo.name[2] = ' ';
992 geo.name[3] = '\0';
993
994 ieee80211_set_geo(bcm->ieee, &geo);
995 }
996
997 /* DummyTransmission function, as documented on
998 * http://bcm-specs.sipsolutions.net/DummyTransmission
999 */
1000 void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
1001 {
1002 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1003 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1004 unsigned int i, max_loop;
1005 u16 value = 0;
1006 u32 buffer[5] = {
1007 0x00000000,
1008 0x0000D400,
1009 0x00000000,
1010 0x00000001,
1011 0x00000000,
1012 };
1013
1014 switch (phy->type) {
1015 case BCM43xx_PHYTYPE_A:
1016 max_loop = 0x1E;
1017 buffer[0] = 0xCC010200;
1018 break;
1019 case BCM43xx_PHYTYPE_B:
1020 case BCM43xx_PHYTYPE_G:
1021 max_loop = 0xFA;
1022 buffer[0] = 0x6E840B00;
1023 break;
1024 default:
1025 assert(0);
1026 return;
1027 }
1028
1029 for (i = 0; i < 5; i++)
1030 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1031
1032 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1033
1034 bcm43xx_write16(bcm, 0x0568, 0x0000);
1035 bcm43xx_write16(bcm, 0x07C0, 0x0000);
1036 bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
1037 bcm43xx_write16(bcm, 0x0508, 0x0000);
1038 bcm43xx_write16(bcm, 0x050A, 0x0000);
1039 bcm43xx_write16(bcm, 0x054C, 0x0000);
1040 bcm43xx_write16(bcm, 0x056A, 0x0014);
1041 bcm43xx_write16(bcm, 0x0568, 0x0826);
1042 bcm43xx_write16(bcm, 0x0500, 0x0000);
1043 bcm43xx_write16(bcm, 0x0502, 0x0030);
1044
1045 if (radio->version == 0x2050 && radio->revision <= 0x5)
1046 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
1047 for (i = 0x00; i < max_loop; i++) {
1048 value = bcm43xx_read16(bcm, 0x050E);
1049 if (value & 0x0080)
1050 break;
1051 udelay(10);
1052 }
1053 for (i = 0x00; i < 0x0A; i++) {
1054 value = bcm43xx_read16(bcm, 0x050E);
1055 if (value & 0x0400)
1056 break;
1057 udelay(10);
1058 }
1059 for (i = 0x00; i < 0x0A; i++) {
1060 value = bcm43xx_read16(bcm, 0x0690);
1061 if (!(value & 0x0100))
1062 break;
1063 udelay(10);
1064 }
1065 if (radio->version == 0x2050 && radio->revision <= 0x5)
1066 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
1067 }
1068
1069 static void key_write(struct bcm43xx_private *bcm,
1070 u8 index, u8 algorithm, const u16 *key)
1071 {
1072 unsigned int i, basic_wep = 0;
1073 u32 offset;
1074 u16 value;
1075
1076 /* Write associated key information */
1077 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1078 ((index << 4) | (algorithm & 0x0F)));
1079
1080 /* The first 4 WEP keys need extra love */
1081 if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1082 (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1083 basic_wep = 1;
1084
1085 /* Write key payload, 8 little endian words */
1086 offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1087 for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1088 value = cpu_to_le16(key[i]);
1089 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1090 offset + (i * 2), value);
1091
1092 if (!basic_wep)
1093 continue;
1094
1095 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1096 offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1097 value);
1098 }
1099 }
1100
1101 static void keymac_write(struct bcm43xx_private *bcm,
1102 u8 index, const u32 *addr)
1103 {
1104 /* for keys 0-3 there is no associated mac address */
1105 if (index < 4)
1106 return;
1107
1108 index -= 4;
1109 if (bcm->current_core->rev >= 5) {
1110 bcm43xx_shm_write32(bcm,
1111 BCM43xx_SHM_HWMAC,
1112 index * 2,
1113 cpu_to_be32(*addr));
1114 bcm43xx_shm_write16(bcm,
1115 BCM43xx_SHM_HWMAC,
1116 (index * 2) + 1,
1117 cpu_to_be16(*((u16 *)(addr + 1))));
1118 } else {
1119 if (index < 8) {
1120 TODO(); /* Put them in the macaddress filter */
1121 } else {
1122 TODO();
1123 /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1124 Keep in mind to update the count of keymacs in 0x003E as well! */
1125 }
1126 }
1127 }
1128
1129 static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1130 u8 index, u8 algorithm,
1131 const u8 *_key, int key_len,
1132 const u8 *mac_addr)
1133 {
1134 u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1135
1136 if (index >= ARRAY_SIZE(bcm->key))
1137 return -EINVAL;
1138 if (key_len > ARRAY_SIZE(key))
1139 return -EINVAL;
1140 if (algorithm < 1 || algorithm > 5)
1141 return -EINVAL;
1142
1143 memcpy(key, _key, key_len);
1144 key_write(bcm, index, algorithm, (const u16 *)key);
1145 keymac_write(bcm, index, (const u32 *)mac_addr);
1146
1147 bcm->key[index].algorithm = algorithm;
1148
1149 return 0;
1150 }
1151
1152 static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1153 {
1154 static const u32 zero_mac[2] = { 0 };
1155 unsigned int i,j, nr_keys = 54;
1156 u16 offset;
1157
1158 if (bcm->current_core->rev < 5)
1159 nr_keys = 16;
1160 assert(nr_keys <= ARRAY_SIZE(bcm->key));
1161
1162 for (i = 0; i < nr_keys; i++) {
1163 bcm->key[i].enabled = 0;
1164 /* returns for i < 4 immediately */
1165 keymac_write(bcm, i, zero_mac);
1166 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1167 0x100 + (i * 2), 0x0000);
1168 for (j = 0; j < 8; j++) {
1169 offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1170 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1171 offset, 0x0000);
1172 }
1173 }
1174 dprintk(KERN_INFO PFX "Keys cleared\n");
1175 }
1176
1177 /* Lowlevel core-switch function. This is only to be used in
1178 * bcm43xx_switch_core() and bcm43xx_probe_cores()
1179 */
1180 static int _switch_core(struct bcm43xx_private *bcm, int core)
1181 {
1182 int err;
1183 int attempts = 0;
1184 u32 current_core;
1185
1186 assert(core >= 0);
1187 while (1) {
1188 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1189 (core * 0x1000) + 0x18000000);
1190 if (unlikely(err))
1191 goto error;
1192 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1193 &current_core);
1194 if (unlikely(err))
1195 goto error;
1196 current_core = (current_core - 0x18000000) / 0x1000;
1197 if (current_core == core)
1198 break;
1199
1200 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1201 goto error;
1202 udelay(10);
1203 }
1204 #ifdef CONFIG_BCM947XX
1205 if (bcm->pci_dev->bus->number == 0)
1206 bcm->current_core_offset = 0x1000 * core;
1207 else
1208 bcm->current_core_offset = 0;
1209 #endif
1210
1211 return 0;
1212 error:
1213 printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1214 return -ENODEV;
1215 }
1216
1217 int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1218 {
1219 int err;
1220
1221 if (unlikely(!new_core))
1222 return 0;
1223 if (!new_core->available)
1224 return -ENODEV;
1225 if (bcm->current_core == new_core)
1226 return 0;
1227 err = _switch_core(bcm, new_core->index);
1228 if (unlikely(err))
1229 goto out;
1230
1231 bcm->current_core = new_core;
1232 bcm->current_80211_core_idx = -1;
1233 if (new_core->id == BCM43xx_COREID_80211)
1234 bcm->current_80211_core_idx = (int)(new_core - &(bcm->core_80211[0]));
1235
1236 out:
1237 return err;
1238 }
1239
1240 static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
1241 {
1242 u32 value;
1243
1244 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1245 value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1246 | BCM43xx_SBTMSTATELOW_REJECT;
1247
1248 return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1249 }
1250
1251 /* disable current core */
1252 static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1253 {
1254 u32 sbtmstatelow;
1255 u32 sbtmstatehigh;
1256 int i;
1257
1258 /* fetch sbtmstatelow from core information registers */
1259 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1260
1261 /* core is already in reset */
1262 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1263 goto out;
1264
1265 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1266 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1267 BCM43xx_SBTMSTATELOW_REJECT;
1268 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1269
1270 for (i = 0; i < 1000; i++) {
1271 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1272 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1273 i = -1;
1274 break;
1275 }
1276 udelay(10);
1277 }
1278 if (i != -1) {
1279 printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1280 return -EBUSY;
1281 }
1282
1283 for (i = 0; i < 1000; i++) {
1284 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1285 if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1286 i = -1;
1287 break;
1288 }
1289 udelay(10);
1290 }
1291 if (i != -1) {
1292 printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1293 return -EBUSY;
1294 }
1295
1296 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1297 BCM43xx_SBTMSTATELOW_REJECT |
1298 BCM43xx_SBTMSTATELOW_RESET |
1299 BCM43xx_SBTMSTATELOW_CLOCK |
1300 core_flags;
1301 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1302 udelay(10);
1303 }
1304
1305 sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1306 BCM43xx_SBTMSTATELOW_REJECT |
1307 core_flags;
1308 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1309
1310 out:
1311 bcm->current_core->enabled = 0;
1312
1313 return 0;
1314 }
1315
1316 /* enable (reset) current core */
1317 static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1318 {
1319 u32 sbtmstatelow;
1320 u32 sbtmstatehigh;
1321 u32 sbimstate;
1322 int err;
1323
1324 err = bcm43xx_core_disable(bcm, core_flags);
1325 if (err)
1326 goto out;
1327
1328 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1329 BCM43xx_SBTMSTATELOW_RESET |
1330 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1331 core_flags;
1332 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1333 udelay(1);
1334
1335 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1336 if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1337 sbtmstatehigh = 0x00000000;
1338 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1339 }
1340
1341 sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1342 if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1343 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1344 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1345 }
1346
1347 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1348 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1349 core_flags;
1350 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1351 udelay(1);
1352
1353 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1354 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1355 udelay(1);
1356
1357 bcm->current_core->enabled = 1;
1358 assert(err == 0);
1359 out:
1360 return err;
1361 }
1362
1363 /* http://bcm-specs.sipsolutions.net/80211CoreReset */
1364 void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1365 {
1366 u32 flags = 0x00040000;
1367
1368 if ((bcm43xx_core_enabled(bcm)) &&
1369 !bcm43xx_using_pio(bcm)) {
1370 //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1371 #ifndef CONFIG_BCM947XX
1372 /* reset all used DMA controllers. */
1373 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1374 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1375 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1376 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1377 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1378 if (bcm->current_core->rev < 5)
1379 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1380 #endif
1381 }
1382 if (bcm->shutting_down) {
1383 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1384 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1385 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1386 } else {
1387 if (connect_phy)
1388 flags |= 0x20000000;
1389 bcm43xx_phy_connect(bcm, connect_phy);
1390 bcm43xx_core_enable(bcm, flags);
1391 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1392 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1393 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1394 | BCM43xx_SBF_400);
1395 }
1396 }
1397
1398 static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1399 {
1400 bcm43xx_radio_turn_off(bcm);
1401 bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1402 bcm43xx_core_disable(bcm, 0);
1403 }
1404
1405 /* Mark the current 80211 core inactive.
1406 * "active_80211_core" is the other 80211 core, which is used.
1407 */
1408 static int bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm,
1409 struct bcm43xx_coreinfo *active_80211_core)
1410 {
1411 u32 sbtmstatelow;
1412 struct bcm43xx_coreinfo *old_core;
1413 int err = 0;
1414
1415 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1416 bcm43xx_radio_turn_off(bcm);
1417 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1418 sbtmstatelow &= ~0x200a0000;
1419 sbtmstatelow |= 0xa0000;
1420 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1421 udelay(1);
1422 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1423 sbtmstatelow &= ~0xa0000;
1424 sbtmstatelow |= 0x80000;
1425 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1426 udelay(1);
1427
1428 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G) {
1429 old_core = bcm->current_core;
1430 err = bcm43xx_switch_core(bcm, active_80211_core);
1431 if (err)
1432 goto out;
1433 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1434 sbtmstatelow &= ~0x20000000;
1435 sbtmstatelow |= 0x20000000;
1436 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1437 err = bcm43xx_switch_core(bcm, old_core);
1438 }
1439
1440 out:
1441 return err;
1442 }
1443
1444 static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
1445 {
1446 u32 v0, v1;
1447 u16 tmp;
1448 struct bcm43xx_xmitstatus stat;
1449
1450 while (1) {
1451 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1452 if (!v0)
1453 break;
1454 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1455
1456 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1457 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1458 stat.flags = tmp & 0xFF;
1459 stat.cnt1 = (tmp & 0x0F00) >> 8;
1460 stat.cnt2 = (tmp & 0xF000) >> 12;
1461 stat.seq = (u16)(v1 & 0xFFFF);
1462 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1463
1464 bcm43xx_debugfs_log_txstat(bcm, &stat);
1465
1466 if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
1467 continue;
1468 if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
1469 //TODO: packet was not acked (was lost)
1470 }
1471 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1472
1473 if (bcm43xx_using_pio(bcm))
1474 bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1475 else
1476 bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1477 }
1478 }
1479
1480 static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
1481 {
1482 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1483 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1484 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1485 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1486 assert(bcm->noisecalc.core_at_start == bcm->current_core);
1487 assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
1488 }
1489
1490 static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1491 {
1492 /* Top half of Link Quality calculation. */
1493
1494 if (bcm->noisecalc.calculation_running)
1495 return;
1496 bcm->noisecalc.core_at_start = bcm->current_core;
1497 bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
1498 bcm->noisecalc.calculation_running = 1;
1499 bcm->noisecalc.nr_samples = 0;
1500
1501 bcm43xx_generate_noise_sample(bcm);
1502 }
1503
1504 static void handle_irq_noise(struct bcm43xx_private *bcm)
1505 {
1506 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1507 u16 tmp;
1508 u8 noise[4];
1509 u8 i, j;
1510 s32 average;
1511
1512 /* Bottom half of Link Quality calculation. */
1513
1514 assert(bcm->noisecalc.calculation_running);
1515 if (bcm->noisecalc.core_at_start != bcm->current_core ||
1516 bcm->noisecalc.channel_at_start != radio->channel)
1517 goto drop_calculation;
1518 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1519 noise[0] = (tmp & 0x00FF);
1520 noise[1] = (tmp & 0xFF00) >> 8;
1521 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1522 noise[2] = (tmp & 0x00FF);
1523 noise[3] = (tmp & 0xFF00) >> 8;
1524 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1525 noise[2] == 0x7F || noise[3] == 0x7F)
1526 goto generate_new;
1527
1528 /* Get the noise samples. */
1529 assert(bcm->noisecalc.nr_samples <= 8);
1530 i = bcm->noisecalc.nr_samples;
1531 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1532 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1533 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1534 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1535 bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1536 bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1537 bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1538 bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1539 bcm->noisecalc.nr_samples++;
1540 if (bcm->noisecalc.nr_samples == 8) {
1541 /* Calculate the Link Quality by the noise samples. */
1542 average = 0;
1543 for (i = 0; i < 8; i++) {
1544 for (j = 0; j < 4; j++)
1545 average += bcm->noisecalc.samples[i][j];
1546 }
1547 average /= (8 * 4);
1548 average *= 125;
1549 average += 64;
1550 average /= 128;
1551
1552 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1553 tmp = (tmp / 128) & 0x1F;
1554 if (tmp >= 8)
1555 average += 2;
1556 else
1557 average -= 25;
1558 if (tmp == 8)
1559 average -= 72;
1560 else
1561 average -= 48;
1562
1563 /* FIXME: This is wrong, but people want fancy stats. well... */
1564 bcm->stats.noise = average;
1565 if (average > -65)
1566 bcm->stats.link_quality = 0;
1567 else if (average > -75)
1568 bcm->stats.link_quality = 1;
1569 else if (average > -85)
1570 bcm->stats.link_quality = 2;
1571 else
1572 bcm->stats.link_quality = 3;
1573 // dprintk(KERN_INFO PFX "Link Quality: %u (avg was %d)\n", bcm->stats.link_quality, average);
1574 drop_calculation:
1575 bcm->noisecalc.calculation_running = 0;
1576 return;
1577 }
1578 generate_new:
1579 bcm43xx_generate_noise_sample(bcm);
1580 }
1581
1582 static void handle_irq_ps(struct bcm43xx_private *bcm)
1583 {
1584 if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1585 ///TODO: PS TBTT
1586 } else {
1587 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1588 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1589 }
1590 if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1591 bcm->reg124_set_0x4 = 1;
1592 //FIXME else set to false?
1593 }
1594
1595 static void handle_irq_reg124(struct bcm43xx_private *bcm)
1596 {
1597 if (!bcm->reg124_set_0x4)
1598 return;
1599 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1600 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1601 | 0x4);
1602 //FIXME: reset reg124_set_0x4 to false?
1603 }
1604
1605 static void handle_irq_pmq(struct bcm43xx_private *bcm)
1606 {
1607 u32 tmp;
1608
1609 //TODO: AP mode.
1610
1611 while (1) {
1612 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1613 if (!(tmp & 0x00000008))
1614 break;
1615 }
1616 /* 16bit write is odd, but correct. */
1617 bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1618 }
1619
1620 static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1621 u16 ram_offset, u16 shm_size_offset)
1622 {
1623 u32 value;
1624 u16 size = 0;
1625
1626 /* Timestamp. */
1627 //FIXME: assumption: The chip sets the timestamp
1628 value = 0;
1629 bcm43xx_ram_write(bcm, ram_offset++, value);
1630 bcm43xx_ram_write(bcm, ram_offset++, value);
1631 size += 8;
1632
1633 /* Beacon Interval / Capability Information */
1634 value = 0x0000;//FIXME: Which interval?
1635 value |= (1 << 0) << 16; /* ESS */
1636 value |= (1 << 2) << 16; /* CF Pollable */ //FIXME?
1637 value |= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
1638 if (!bcm->ieee->open_wep)
1639 value |= (1 << 4) << 16; /* Privacy */
1640 bcm43xx_ram_write(bcm, ram_offset++, value);
1641 size += 4;
1642
1643 /* SSID */
1644 //TODO
1645
1646 /* FH Parameter Set */
1647 //TODO
1648
1649 /* DS Parameter Set */
1650 //TODO
1651
1652 /* CF Parameter Set */
1653 //TODO
1654
1655 /* TIM */
1656 //TODO
1657
1658 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1659 }
1660
1661 static void handle_irq_beacon(struct bcm43xx_private *bcm)
1662 {
1663 u32 status;
1664
1665 bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1666 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1667
1668 if ((status & 0x1) && (status & 0x2)) {
1669 /* ACK beacon IRQ. */
1670 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1671 BCM43xx_IRQ_BEACON);
1672 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1673 return;
1674 }
1675 if (!(status & 0x1)) {
1676 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1677 status |= 0x1;
1678 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1679 }
1680 if (!(status & 0x2)) {
1681 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1682 status |= 0x2;
1683 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1684 }
1685 }
1686
1687 /* Interrupt handler bottom-half */
1688 static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1689 {
1690 u32 reason;
1691 u32 dma_reason[4];
1692 int activity = 0;
1693 unsigned long flags;
1694
1695 #ifdef CONFIG_BCM43XX_DEBUG
1696 u32 _handled = 0x00000000;
1697 # define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
1698 #else
1699 # define bcmirq_handled(irq) do { /* nothing */ } while (0)
1700 #endif /* CONFIG_BCM43XX_DEBUG*/
1701
1702 bcm43xx_lock_mmio(bcm, flags);
1703 reason = bcm->irq_reason;
1704 dma_reason[0] = bcm->dma_reason[0];
1705 dma_reason[1] = bcm->dma_reason[1];
1706 dma_reason[2] = bcm->dma_reason[2];
1707 dma_reason[3] = bcm->dma_reason[3];
1708
1709 if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1710 /* TX error. We get this when Template Ram is written in wrong endianess
1711 * in dummy_tx(). We also get this if something is wrong with the TX header
1712 * on DMA or PIO queues.
1713 * Maybe we get this in other error conditions, too.
1714 */
1715 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
1716 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1717 }
1718 if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_FATALMASK) |
1719 (dma_reason[1] & BCM43xx_DMAIRQ_FATALMASK) |
1720 (dma_reason[2] & BCM43xx_DMAIRQ_FATALMASK) |
1721 (dma_reason[3] & BCM43xx_DMAIRQ_FATALMASK))) {
1722 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1723 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1724 dma_reason[0], dma_reason[1],
1725 dma_reason[2], dma_reason[3]);
1726 bcm43xx_controller_restart(bcm, "DMA error");
1727 bcm43xx_unlock_mmio(bcm, flags);
1728 return;
1729 }
1730 if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_NONFATALMASK) |
1731 (dma_reason[1] & BCM43xx_DMAIRQ_NONFATALMASK) |
1732 (dma_reason[2] & BCM43xx_DMAIRQ_NONFATALMASK) |
1733 (dma_reason[3] & BCM43xx_DMAIRQ_NONFATALMASK))) {
1734 printkl(KERN_ERR PFX "DMA error: "
1735 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1736 dma_reason[0], dma_reason[1],
1737 dma_reason[2], dma_reason[3]);
1738 }
1739
1740 if (reason & BCM43xx_IRQ_PS) {
1741 handle_irq_ps(bcm);
1742 bcmirq_handled(BCM43xx_IRQ_PS);
1743 }
1744
1745 if (reason & BCM43xx_IRQ_REG124) {
1746 handle_irq_reg124(bcm);
1747 bcmirq_handled(BCM43xx_IRQ_REG124);
1748 }
1749
1750 if (reason & BCM43xx_IRQ_BEACON) {
1751 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1752 handle_irq_beacon(bcm);
1753 bcmirq_handled(BCM43xx_IRQ_BEACON);
1754 }
1755
1756 if (reason & BCM43xx_IRQ_PMQ) {
1757 handle_irq_pmq(bcm);
1758 bcmirq_handled(BCM43xx_IRQ_PMQ);
1759 }
1760
1761 if (reason & BCM43xx_IRQ_SCAN) {
1762 /*TODO*/
1763 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1764 }
1765
1766 if (reason & BCM43xx_IRQ_NOISE) {
1767 handle_irq_noise(bcm);
1768 bcmirq_handled(BCM43xx_IRQ_NOISE);
1769 }
1770
1771 /* Check the DMA reason registers for received data. */
1772 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1773 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1774 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1775 if (bcm43xx_using_pio(bcm))
1776 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
1777 else
1778 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
1779 /* We intentionally don't set "activity" to 1, here. */
1780 }
1781 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1782 if (bcm43xx_using_pio(bcm))
1783 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
1784 else
1785 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring1);
1786 activity = 1;
1787 }
1788 bcmirq_handled(BCM43xx_IRQ_RX);
1789
1790 if (reason & BCM43xx_IRQ_XMIT_STATUS) {
1791 handle_irq_transmit_status(bcm);
1792 activity = 1;
1793 //TODO: In AP mode, this also causes sending of powersave responses.
1794 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1795 }
1796
1797 /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1798 bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1799 #ifdef CONFIG_BCM43XX_DEBUG
1800 if (unlikely(reason & ~_handled)) {
1801 printkl(KERN_WARNING PFX
1802 "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
1803 "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1804 reason, (reason & ~_handled),
1805 dma_reason[0], dma_reason[1],
1806 dma_reason[2], dma_reason[3]);
1807 }
1808 #endif
1809 #undef bcmirq_handled
1810
1811 if (!modparam_noleds)
1812 bcm43xx_leds_update(bcm, activity);
1813 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
1814 bcm43xx_unlock_mmio(bcm, flags);
1815 }
1816
1817 static void pio_irq_workaround(struct bcm43xx_private *bcm,
1818 u16 base, int queueidx)
1819 {
1820 u16 rxctl;
1821
1822 rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
1823 if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1824 bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1825 else
1826 bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1827 }
1828
1829 static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
1830 {
1831 if (bcm43xx_using_pio(bcm) &&
1832 (bcm->current_core->rev < 3) &&
1833 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1834 /* Apply a PIO specific workaround to the dma_reasons */
1835 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
1836 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
1837 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
1838 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
1839 }
1840
1841 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
1842
1843 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
1844 bcm->dma_reason[0]);
1845 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
1846 bcm->dma_reason[1]);
1847 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
1848 bcm->dma_reason[2]);
1849 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1850 bcm->dma_reason[3]);
1851 }
1852
1853 /* Interrupt handler top-half */
1854 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
1855 {
1856 irqreturn_t ret = IRQ_HANDLED;
1857 struct bcm43xx_private *bcm = dev_id;
1858 u32 reason;
1859
1860 if (!bcm)
1861 return IRQ_NONE;
1862
1863 spin_lock(&bcm->_lock);
1864
1865 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1866 if (reason == 0xffffffff) {
1867 /* irq not for us (shared irq) */
1868 ret = IRQ_NONE;
1869 goto out;
1870 }
1871 reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1872 if (!reason)
1873 goto out;
1874
1875 bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1876 & 0x0001dc00;
1877 bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1878 & 0x0000dc00;
1879 bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1880 & 0x0000dc00;
1881 bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1882 & 0x0001dc00;
1883
1884 bcm43xx_interrupt_ack(bcm, reason);
1885
1886 /* Only accept IRQs, if we are initialized properly.
1887 * This avoids an RX race while initializing.
1888 * We should probably not enable IRQs before we are initialized
1889 * completely, but some careful work is needed to fix this. I think it
1890 * is best to stay with this cheap workaround for now... .
1891 */
1892 if (likely(bcm->initialized)) {
1893 /* disable all IRQs. They are enabled again in the bottom half. */
1894 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1895 /* save the reason code and call our bottom half. */
1896 bcm->irq_reason = reason;
1897 tasklet_schedule(&bcm->isr_tasklet);
1898 }
1899
1900 out:
1901 mmiowb();
1902 spin_unlock(&bcm->_lock);
1903
1904 return ret;
1905 }
1906
1907 static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
1908 {
1909 if (bcm->firmware_norelease && !force)
1910 return; /* Suspending or controller reset. */
1911 release_firmware(bcm->ucode);
1912 bcm->ucode = NULL;
1913 release_firmware(bcm->pcm);
1914 bcm->pcm = NULL;
1915 release_firmware(bcm->initvals0);
1916 bcm->initvals0 = NULL;
1917 release_firmware(bcm->initvals1);
1918 bcm->initvals1 = NULL;
1919 }
1920
1921 static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1922 {
1923 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1924 u8 rev = bcm->current_core->rev;
1925 int err = 0;
1926 int nr;
1927 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1928
1929 if (!bcm->ucode) {
1930 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1931 (rev >= 5 ? 5 : rev),
1932 modparam_fwpostfix);
1933 err = request_firmware(&bcm->ucode, buf, &bcm->pci_dev->dev);
1934 if (err) {
1935 printk(KERN_ERR PFX
1936 "Error: Microcode \"%s\" not available or load failed.\n",
1937 buf);
1938 goto error;
1939 }
1940 }
1941
1942 if (!bcm->pcm) {
1943 snprintf(buf, ARRAY_SIZE(buf),
1944 "bcm43xx_pcm%d%s.fw",
1945 (rev < 5 ? 4 : 5),
1946 modparam_fwpostfix);
1947 err = request_firmware(&bcm->pcm, buf, &bcm->pci_dev->dev);
1948 if (err) {
1949 printk(KERN_ERR PFX
1950 "Error: PCM \"%s\" not available or load failed.\n",
1951 buf);
1952 goto error;
1953 }
1954 }
1955
1956 if (!bcm->initvals0) {
1957 if (rev == 2 || rev == 4) {
1958 switch (phy->type) {
1959 case BCM43xx_PHYTYPE_A:
1960 nr = 3;
1961 break;
1962 case BCM43xx_PHYTYPE_B:
1963 case BCM43xx_PHYTYPE_G:
1964 nr = 1;
1965 break;
1966 default:
1967 goto err_noinitval;
1968 }
1969
1970 } else if (rev >= 5) {
1971 switch (phy->type) {
1972 case BCM43xx_PHYTYPE_A:
1973 nr = 7;
1974 break;
1975 case BCM43xx_PHYTYPE_B:
1976 case BCM43xx_PHYTYPE_G:
1977 nr = 5;
1978 break;
1979 default:
1980 goto err_noinitval;
1981 }
1982 } else
1983 goto err_noinitval;
1984 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1985 nr, modparam_fwpostfix);
1986
1987 err = request_firmware(&bcm->initvals0, buf, &bcm->pci_dev->dev);
1988 if (err) {
1989 printk(KERN_ERR PFX
1990 "Error: InitVals \"%s\" not available or load failed.\n",
1991 buf);
1992 goto error;
1993 }
1994 if (bcm->initvals0->size % sizeof(struct bcm43xx_initval)) {
1995 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1996 goto error;
1997 }
1998 }
1999
2000 if (!bcm->initvals1) {
2001 if (rev >= 5) {
2002 u32 sbtmstatehigh;
2003
2004 switch (phy->type) {
2005 case BCM43xx_PHYTYPE_A:
2006 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
2007 if (sbtmstatehigh & 0x00010000)
2008 nr = 9;
2009 else
2010 nr = 10;
2011 break;
2012 case BCM43xx_PHYTYPE_B:
2013 case BCM43xx_PHYTYPE_G:
2014 nr = 6;
2015 break;
2016 default:
2017 goto err_noinitval;
2018 }
2019 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2020 nr, modparam_fwpostfix);
2021
2022 err = request_firmware(&bcm->initvals1, buf, &bcm->pci_dev->dev);
2023 if (err) {
2024 printk(KERN_ERR PFX
2025 "Error: InitVals \"%s\" not available or load failed.\n",
2026 buf);
2027 goto error;
2028 }
2029 if (bcm->initvals1->size % sizeof(struct bcm43xx_initval)) {
2030 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2031 goto error;
2032 }
2033 }
2034 }
2035
2036 out:
2037 return err;
2038 error:
2039 bcm43xx_release_firmware(bcm, 1);
2040 goto out;
2041 err_noinitval:
2042 printk(KERN_ERR PFX "Error: No InitVals available!\n");
2043 err = -ENOENT;
2044 goto error;
2045 }
2046
2047 static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2048 {
2049 const u32 *data;
2050 unsigned int i, len;
2051
2052 /* Upload Microcode. */
2053 data = (u32 *)(bcm->ucode->data);
2054 len = bcm->ucode->size / sizeof(u32);
2055 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2056 for (i = 0; i < len; i++) {
2057 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2058 be32_to_cpu(data[i]));
2059 udelay(10);
2060 }
2061
2062 /* Upload PCM data. */
2063 data = (u32 *)(bcm->pcm->data);
2064 len = bcm->pcm->size / sizeof(u32);
2065 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2066 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2067 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2068 for (i = 0; i < len; i++) {
2069 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2070 be32_to_cpu(data[i]));
2071 udelay(10);
2072 }
2073 }
2074
2075 static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2076 const struct bcm43xx_initval *data,
2077 const unsigned int len)
2078 {
2079 u16 offset, size;
2080 u32 value;
2081 unsigned int i;
2082
2083 for (i = 0; i < len; i++) {
2084 offset = be16_to_cpu(data[i].offset);
2085 size = be16_to_cpu(data[i].size);
2086 value = be32_to_cpu(data[i].value);
2087
2088 if (unlikely(offset >= 0x1000))
2089 goto err_format;
2090 if (size == 2) {
2091 if (unlikely(value & 0xFFFF0000))
2092 goto err_format;
2093 bcm43xx_write16(bcm, offset, (u16)value);
2094 } else if (size == 4) {
2095 bcm43xx_write32(bcm, offset, value);
2096 } else
2097 goto err_format;
2098 }
2099
2100 return 0;
2101
2102 err_format:
2103 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2104 "Please fix your bcm43xx firmware files.\n");
2105 return -EPROTO;
2106 }
2107
2108 static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
2109 {
2110 int err;
2111
2112 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals0->data,
2113 bcm->initvals0->size / sizeof(struct bcm43xx_initval));
2114 if (err)
2115 goto out;
2116 if (bcm->initvals1) {
2117 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals1->data,
2118 bcm->initvals1->size / sizeof(struct bcm43xx_initval));
2119 if (err)
2120 goto out;
2121 }
2122 out:
2123 return err;
2124 }
2125
2126 static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2127 {
2128 int res;
2129 unsigned int i;
2130 u32 data;
2131
2132 bcm->irq = bcm->pci_dev->irq;
2133 #ifdef CONFIG_BCM947XX
2134 if (bcm->pci_dev->bus->number == 0) {
2135 struct pci_dev *d = NULL;
2136 /* FIXME: we will probably need more device IDs here... */
2137 d = pci_find_device(PCI_VENDOR_ID_BROADCOM, 0x4324, NULL);
2138 if (d != NULL) {
2139 bcm->irq = d->irq;
2140 }
2141 }
2142 #endif
2143 res = request_irq(bcm->irq, bcm43xx_interrupt_handler,
2144 SA_SHIRQ, KBUILD_MODNAME, bcm);
2145 if (res) {
2146 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
2147 return -ENODEV;
2148 }
2149 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xffffffff);
2150 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2151 i = 0;
2152 while (1) {
2153 data = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2154 if (data == BCM43xx_IRQ_READY)
2155 break;
2156 i++;
2157 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2158 printk(KERN_ERR PFX "Card IRQ register not responding. "
2159 "Giving up.\n");
2160 free_irq(bcm->irq, bcm);
2161 return -ENODEV;
2162 }
2163 udelay(10);
2164 }
2165 // dummy read
2166 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2167
2168 return 0;
2169 }
2170
2171 /* Switch to the core used to write the GPIO register.
2172 * This is either the ChipCommon, or the PCI core.
2173 */
2174 static int switch_to_gpio_core(struct bcm43xx_private *bcm)
2175 {
2176 int err;
2177
2178 /* Where to find the GPIO register depends on the chipset.
2179 * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2180 * control register. Otherwise the register at offset 0x6c in the
2181 * PCI core is the GPIO control register.
2182 */
2183 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2184 if (err == -ENODEV) {
2185 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2186 if (unlikely(err == -ENODEV)) {
2187 printk(KERN_ERR PFX "gpio error: "
2188 "Neither ChipCommon nor PCI core available!\n");
2189 }
2190 }
2191
2192 return err;
2193 }
2194
2195 /* Initialize the GPIOs
2196 * http://bcm-specs.sipsolutions.net/GPIO
2197 */
2198 static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2199 {
2200 struct bcm43xx_coreinfo *old_core;
2201 int err;
2202 u32 mask, set;
2203
2204 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2205 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2206 & 0xFFFF3FFF);
2207
2208 bcm43xx_leds_switch_all(bcm, 0);
2209 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2210 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2211
2212 mask = 0x0000001F;
2213 set = 0x0000000F;
2214 if (bcm->chip_id == 0x4301) {
2215 mask |= 0x0060;
2216 set |= 0x0060;
2217 }
2218 if (0 /* FIXME: conditional unknown */) {
2219 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2220 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2221 | 0x0100);
2222 mask |= 0x0180;
2223 set |= 0x0180;
2224 }
2225 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
2226 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2227 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2228 | 0x0200);
2229 mask |= 0x0200;
2230 set |= 0x0200;
2231 }
2232 if (bcm->current_core->rev >= 2)
2233 mask |= 0x0010; /* FIXME: This is redundant. */
2234
2235 old_core = bcm->current_core;
2236 err = switch_to_gpio_core(bcm);
2237 if (err)
2238 goto out;
2239 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
2240 (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
2241 err = bcm43xx_switch_core(bcm, old_core);
2242 out:
2243 return err;
2244 }
2245
2246 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2247 static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2248 {
2249 struct bcm43xx_coreinfo *old_core;
2250 int err;
2251
2252 old_core = bcm->current_core;
2253 err = switch_to_gpio_core(bcm);
2254 if (err)
2255 return err;
2256 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2257 err = bcm43xx_switch_core(bcm, old_core);
2258 assert(err == 0);
2259
2260 return 0;
2261 }
2262
2263 /* http://bcm-specs.sipsolutions.net/EnableMac */
2264 void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2265 {
2266 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2267 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2268 | BCM43xx_SBF_MAC_ENABLED);
2269 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2270 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2271 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2272 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2273 }
2274
2275 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2276 void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2277 {
2278 int i;
2279 u32 tmp;
2280
2281 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2282 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2283 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2284 & ~BCM43xx_SBF_MAC_ENABLED);
2285 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2286 for (i = 100000; i; i--) {
2287 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2288 if (tmp & BCM43xx_IRQ_READY)
2289 return;
2290 udelay(10);
2291 }
2292 printkl(KERN_ERR PFX "MAC suspend failed\n");
2293 }
2294
2295 void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2296 int iw_mode)
2297 {
2298 unsigned long flags;
2299 struct net_device *net_dev = bcm->net_dev;
2300 u32 status;
2301 u16 value;
2302
2303 spin_lock_irqsave(&bcm->ieee->lock, flags);
2304 bcm->ieee->iw_mode = iw_mode;
2305 spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2306 if (iw_mode == IW_MODE_MONITOR)
2307 net_dev->type = ARPHRD_IEEE80211;
2308 else
2309 net_dev->type = ARPHRD_ETHER;
2310
2311 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2312 /* Reset status to infrastructured mode */
2313 status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
2314 status &= ~BCM43xx_SBF_MODE_PROMISC;
2315 status |= BCM43xx_SBF_MODE_NOTADHOC;
2316
2317 /* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
2318 status |= BCM43xx_SBF_MODE_PROMISC;
2319
2320 switch (iw_mode) {
2321 case IW_MODE_MONITOR:
2322 status |= BCM43xx_SBF_MODE_MONITOR;
2323 status |= BCM43xx_SBF_MODE_PROMISC;
2324 break;
2325 case IW_MODE_ADHOC:
2326 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2327 break;
2328 case IW_MODE_MASTER:
2329 status |= BCM43xx_SBF_MODE_AP;
2330 break;
2331 case IW_MODE_SECOND:
2332 case IW_MODE_REPEAT:
2333 TODO(); /* TODO */
2334 break;
2335 case IW_MODE_INFRA:
2336 /* nothing to be done here... */
2337 break;
2338 default:
2339 dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
2340 }
2341 if (net_dev->flags & IFF_PROMISC)
2342 status |= BCM43xx_SBF_MODE_PROMISC;
2343 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
2344
2345 value = 0x0002;
2346 if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2347 if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
2348 value = 0x0064;
2349 else
2350 value = 0x0032;
2351 }
2352 bcm43xx_write16(bcm, 0x0612, value);
2353 }
2354
2355 /* This is the opposite of bcm43xx_chip_init() */
2356 static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2357 {
2358 bcm43xx_radio_turn_off(bcm);
2359 if (!modparam_noleds)
2360 bcm43xx_leds_exit(bcm);
2361 bcm43xx_gpio_cleanup(bcm);
2362 free_irq(bcm->irq, bcm);
2363 bcm43xx_release_firmware(bcm, 0);
2364 }
2365
2366 /* Initialize the chip
2367 * http://bcm-specs.sipsolutions.net/ChipInit
2368 */
2369 static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2370 {
2371 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2372 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2373 int err;
2374 int tmp;
2375 u32 value32;
2376 u16 value16;
2377
2378 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2379 BCM43xx_SBF_CORE_READY
2380 | BCM43xx_SBF_400);
2381
2382 err = bcm43xx_request_firmware(bcm);
2383 if (err)
2384 goto out;
2385 bcm43xx_upload_microcode(bcm);
2386
2387 err = bcm43xx_initialize_irq(bcm);
2388 if (err)
2389 goto err_release_fw;
2390
2391 err = bcm43xx_gpio_init(bcm);
2392 if (err)
2393 goto err_free_irq;
2394
2395 err = bcm43xx_upload_initvals(bcm);
2396 if (err)
2397 goto err_gpio_cleanup;
2398 bcm43xx_radio_turn_on(bcm);
2399
2400 bcm43xx_write16(bcm, 0x03E6, 0x0000);
2401 err = bcm43xx_phy_init(bcm);
2402 if (err)
2403 goto err_radio_off;
2404
2405 /* Select initial Interference Mitigation. */
2406 tmp = radio->interfmode;
2407 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2408 bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2409
2410 bcm43xx_phy_set_antenna_diversity(bcm);
2411 bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
2412 if (phy->type == BCM43xx_PHYTYPE_B) {
2413 value16 = bcm43xx_read16(bcm, 0x005E);
2414 value16 |= 0x0004;
2415 bcm43xx_write16(bcm, 0x005E, value16);
2416 }
2417 bcm43xx_write32(bcm, 0x0100, 0x01000000);
2418 if (bcm->current_core->rev < 5)
2419 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2420
2421 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2422 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2423 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2424 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2425 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2426 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2427
2428 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2429 value32 |= 0x100000;
2430 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2431
2432 if (bcm43xx_using_pio(bcm)) {
2433 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2434 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2435 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2436 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2437 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2438 }
2439
2440 /* Probe Response Timeout value */
2441 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2442 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2443
2444 /* Initially set the wireless operation mode. */
2445 bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
2446
2447 if (bcm->current_core->rev < 3) {
2448 bcm43xx_write16(bcm, 0x060E, 0x0000);
2449 bcm43xx_write16(bcm, 0x0610, 0x8000);
2450 bcm43xx_write16(bcm, 0x0604, 0x0000);
2451 bcm43xx_write16(bcm, 0x0606, 0x0200);
2452 } else {
2453 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2454 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2455 }
2456 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2457 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0001DC00);
2458 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2459 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0000DC00);
2460 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0001DC00);
2461
2462 value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2463 value32 |= 0x00100000;
2464 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2465
2466 bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2467
2468 assert(err == 0);
2469 dprintk(KERN_INFO PFX "Chip initialized\n");
2470 out:
2471 return err;
2472
2473 err_radio_off:
2474 bcm43xx_radio_turn_off(bcm);
2475 err_gpio_cleanup:
2476 bcm43xx_gpio_cleanup(bcm);
2477 err_free_irq:
2478 free_irq(bcm->irq, bcm);
2479 err_release_fw:
2480 bcm43xx_release_firmware(bcm, 1);
2481 goto out;
2482 }
2483
2484 /* Validate chip access
2485 * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2486 static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2487 {
2488 u32 value;
2489 u32 shm_backup;
2490
2491 shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2492 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
2493 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2494 goto error;
2495 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
2496 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2497 goto error;
2498 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2499
2500 value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2501 if ((value | 0x80000000) != 0x80000400)
2502 goto error;
2503
2504 value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2505 if (value != 0x00000000)
2506 goto error;
2507
2508 return 0;
2509 error:
2510 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2511 return -ENODEV;
2512 }
2513
2514 static void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
2515 {
2516 /* Initialize a "phyinfo" structure. The structure is already
2517 * zeroed out.
2518 */
2519 phy->antenna_diversity = 0xFFFF;
2520 phy->savedpctlreg = 0xFFFF;
2521 phy->minlowsig[0] = 0xFFFF;
2522 phy->minlowsig[1] = 0xFFFF;
2523 spin_lock_init(&phy->lock);
2524 }
2525
2526 static void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
2527 {
2528 /* Initialize a "radioinfo" structure. The structure is already
2529 * zeroed out.
2530 */
2531 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2532 radio->channel = 0xFF;
2533 radio->initial_channel = 0xFF;
2534 radio->lofcal = 0xFFFF;
2535 radio->initval = 0xFFFF;
2536 radio->nrssi[0] = -1000;
2537 radio->nrssi[1] = -1000;
2538 }
2539
2540 static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2541 {
2542 int err, i;
2543 int current_core;
2544 u32 core_vendor, core_id, core_rev;
2545 u32 sb_id_hi, chip_id_32 = 0;
2546 u16 pci_device, chip_id_16;
2547 u8 core_count;
2548
2549 memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2550 memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
2551 memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2552 * BCM43xx_MAX_80211_CORES);
2553 memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2554 * BCM43xx_MAX_80211_CORES);
2555 bcm->current_80211_core_idx = -1;
2556 bcm->nr_80211_available = 0;
2557 bcm->current_core = NULL;
2558 bcm->active_80211_core = NULL;
2559
2560 /* map core 0 */
2561 err = _switch_core(bcm, 0);
2562 if (err)
2563 goto out;
2564
2565 /* fetch sb_id_hi from core information registers */
2566 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2567
2568 core_id = (sb_id_hi & 0xFFF0) >> 4;
2569 core_rev = (sb_id_hi & 0xF);
2570 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2571
2572 /* if present, chipcommon is always core 0; read the chipid from it */
2573 if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2574 chip_id_32 = bcm43xx_read32(bcm, 0);
2575 chip_id_16 = chip_id_32 & 0xFFFF;
2576 bcm->core_chipcommon.available = 1;
2577 bcm->core_chipcommon.id = core_id;
2578 bcm->core_chipcommon.rev = core_rev;
2579 bcm->core_chipcommon.index = 0;
2580 /* While we are at it, also read the capabilities. */
2581 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2582 } else {
2583 /* without a chipCommon, use a hard coded table. */
2584 pci_device = bcm->pci_dev->device;
2585 if (pci_device == 0x4301)
2586 chip_id_16 = 0x4301;
2587 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2588 chip_id_16 = 0x4307;
2589 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2590 chip_id_16 = 0x4402;
2591 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2592 chip_id_16 = 0x4610;
2593 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2594 chip_id_16 = 0x4710;
2595 #ifdef CONFIG_BCM947XX
2596 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2597 chip_id_16 = 0x4309;
2598 #endif
2599 else {
2600 printk(KERN_ERR PFX "Could not determine Chip ID\n");
2601 return -ENODEV;
2602 }
2603 }
2604
2605 /* ChipCommon with Core Rev >=4 encodes number of cores,
2606 * otherwise consult hardcoded table */
2607 if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2608 core_count = (chip_id_32 & 0x0F000000) >> 24;
2609 } else {
2610 switch (chip_id_16) {
2611 case 0x4610:
2612 case 0x4704:
2613 case 0x4710:
2614 core_count = 9;
2615 break;
2616 case 0x4310:
2617 core_count = 8;
2618 break;
2619 case 0x5365:
2620 core_count = 7;
2621 break;
2622 case 0x4306:
2623 core_count = 6;
2624 break;
2625 case 0x4301:
2626 case 0x4307:
2627 core_count = 5;
2628 break;
2629 case 0x4402:
2630 core_count = 3;
2631 break;
2632 default:
2633 /* SOL if we get here */
2634 assert(0);
2635 core_count = 1;
2636 }
2637 }
2638
2639 bcm->chip_id = chip_id_16;
2640 bcm->chip_rev = (chip_id_32 & 0x000F0000) >> 16;
2641 bcm->chip_package = (chip_id_32 & 0x00F00000) >> 20;
2642
2643 dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2644 bcm->chip_id, bcm->chip_rev);
2645 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2646 if (bcm->core_chipcommon.available) {
2647 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2648 core_id, core_rev, core_vendor,
2649 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
2650 }
2651
2652 if (bcm->core_chipcommon.available)
2653 current_core = 1;
2654 else
2655 current_core = 0;
2656 for ( ; current_core < core_count; current_core++) {
2657 struct bcm43xx_coreinfo *core;
2658 struct bcm43xx_coreinfo_80211 *ext_80211;
2659
2660 err = _switch_core(bcm, current_core);
2661 if (err)
2662 goto out;
2663 /* Gather information */
2664 /* fetch sb_id_hi from core information registers */
2665 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2666
2667 /* extract core_id, core_rev, core_vendor */
2668 core_id = (sb_id_hi & 0xFFF0) >> 4;
2669 core_rev = (sb_id_hi & 0xF);
2670 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2671
2672 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2673 current_core, core_id, core_rev, core_vendor,
2674 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
2675
2676 core = NULL;
2677 switch (core_id) {
2678 case BCM43xx_COREID_PCI:
2679 core = &bcm->core_pci;
2680 if (core->available) {
2681 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2682 continue;
2683 }
2684 break;
2685 case BCM43xx_COREID_80211:
2686 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2687 core = &(bcm->core_80211[i]);
2688 ext_80211 = &(bcm->core_80211_ext[i]);
2689 if (!core->available)
2690 break;
2691 core = NULL;
2692 }
2693 if (!core) {
2694 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2695 BCM43xx_MAX_80211_CORES);
2696 continue;
2697 }
2698 if (i != 0) {
2699 /* More than one 80211 core is only supported
2700 * by special chips.
2701 * There are chips with two 80211 cores, but with
2702 * dangling pins on the second core. Be careful
2703 * and ignore these cores here.
2704 */
2705 if (bcm->pci_dev->device != 0x4324) {
2706 dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
2707 continue;
2708 }
2709 }
2710 switch (core_rev) {
2711 case 2:
2712 case 4:
2713 case 5:
2714 case 6:
2715 case 7:
2716 case 9:
2717 break;
2718 default:
2719 printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
2720 core_rev);
2721 err = -ENODEV;
2722 goto out;
2723 }
2724 bcm->nr_80211_available++;
2725 bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2726 bcm43xx_init_struct_radioinfo(&ext_80211->radio);
2727 break;
2728 case BCM43xx_COREID_CHIPCOMMON:
2729 printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2730 break;
2731 }
2732 if (core) {
2733 core->available = 1;
2734 core->id = core_id;
2735 core->rev = core_rev;
2736 core->index = current_core;
2737 }
2738 }
2739
2740 if (!bcm->core_80211[0].available) {
2741 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2742 err = -ENODEV;
2743 goto out;
2744 }
2745
2746 err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2747
2748 assert(err == 0);
2749 out:
2750 return err;
2751 }
2752
2753 static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2754 {
2755 const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2756 u8 *bssid = bcm->ieee->bssid;
2757
2758 switch (bcm->ieee->iw_mode) {
2759 case IW_MODE_ADHOC:
2760 random_ether_addr(bssid);
2761 break;
2762 case IW_MODE_MASTER:
2763 case IW_MODE_INFRA:
2764 case IW_MODE_REPEAT:
2765 case IW_MODE_SECOND:
2766 case IW_MODE_MONITOR:
2767 memcpy(bssid, mac, ETH_ALEN);
2768 break;
2769 default:
2770 assert(0);
2771 }
2772 }
2773
2774 static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2775 u16 rate,
2776 int is_ofdm)
2777 {
2778 u16 offset;
2779
2780 if (is_ofdm) {
2781 offset = 0x480;
2782 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2783 }
2784 else {
2785 offset = 0x4C0;
2786 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2787 }
2788 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2789 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2790 }
2791
2792 static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2793 {
2794 switch (bcm43xx_current_phy(bcm)->type) {
2795 case BCM43xx_PHYTYPE_A:
2796 case BCM43xx_PHYTYPE_G:
2797 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2798 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2799 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2800 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2801 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2802 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2803 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2804 case BCM43xx_PHYTYPE_B:
2805 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2806 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2807 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2808 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2809 break;
2810 default:
2811 assert(0);
2812 }
2813 }
2814
2815 static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2816 {
2817 bcm43xx_chip_cleanup(bcm);
2818 bcm43xx_pio_free(bcm);
2819 bcm43xx_dma_free(bcm);
2820
2821 bcm->current_core->initialized = 0;
2822 }
2823
2824 /* http://bcm-specs.sipsolutions.net/80211Init */
2825 static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm)
2826 {
2827 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2828 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2829 u32 ucodeflags;
2830 int err;
2831 u32 sbimconfiglow;
2832 u8 limit;
2833
2834 if (bcm->chip_rev < 5) {
2835 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2836 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2837 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2838 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2839 sbimconfiglow |= 0x32;
2840 else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
2841 sbimconfiglow |= 0x53;
2842 else
2843 assert(0);
2844 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2845 }
2846
2847 bcm43xx_phy_calibrate(bcm);
2848 err = bcm43xx_chip_init(bcm);
2849 if (err)
2850 goto out;
2851
2852 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2853 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2854
2855 if (0 /*FIXME: which condition has to be used here? */)
2856 ucodeflags |= 0x00000010;
2857
2858 /* HW decryption needs to be set now */
2859 ucodeflags |= 0x40000000;
2860
2861 if (phy->type == BCM43xx_PHYTYPE_G) {
2862 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2863 if (phy->rev == 1)
2864 ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2865 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2866 ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
2867 } else if (phy->type == BCM43xx_PHYTYPE_B) {
2868 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2869 if (phy->rev >= 2 && radio->version == 0x2050)
2870 ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2871 }
2872
2873 if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2874 BCM43xx_UCODEFLAGS_OFFSET)) {
2875 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2876 BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2877 }
2878
2879 /* Short/Long Retry Limit.
2880 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2881 * the chip-internal counter.
2882 */
2883 limit = limit_value(modparam_short_retry, 0, 0xF);
2884 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2885 limit = limit_value(modparam_long_retry, 0, 0xF);
2886 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2887
2888 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2889 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2890
2891 bcm43xx_rate_memory_init(bcm);
2892
2893 /* Minimum Contention Window */
2894 if (phy->type == BCM43xx_PHYTYPE_B)
2895 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2896 else
2897 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2898 /* Maximum Contention Window */
2899 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2900
2901 bcm43xx_gen_bssid(bcm);
2902 bcm43xx_write_mac_bssid_templates(bcm);
2903
2904 if (bcm->current_core->rev >= 5)
2905 bcm43xx_write16(bcm, 0x043C, 0x000C);
2906
2907 if (bcm43xx_using_pio(bcm))
2908 err = bcm43xx_pio_init(bcm);
2909 else
2910 err = bcm43xx_dma_init(bcm);
2911 if (err)
2912 goto err_chip_cleanup;
2913 bcm43xx_write16(bcm, 0x0612, 0x0050);
2914 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2915 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2916
2917 bcm43xx_mac_enable(bcm);
2918 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
2919
2920 bcm->current_core->initialized = 1;
2921 out:
2922 return err;
2923
2924 err_chip_cleanup:
2925 bcm43xx_chip_cleanup(bcm);
2926 goto out;
2927 }
2928
2929 static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2930 {
2931 int err;
2932 u16 pci_status;
2933
2934 err = bcm43xx_pctl_set_crystal(bcm, 1);
2935 if (err)
2936 goto out;
2937 bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2938 bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
2939
2940 out:
2941 return err;
2942 }
2943
2944 static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
2945 {
2946 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
2947 bcm43xx_pctl_set_crystal(bcm, 0);
2948 }
2949
2950 static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
2951 u32 address,
2952 u32 data)
2953 {
2954 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
2955 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
2956 }
2957
2958 static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
2959 {
2960 int err;
2961 struct bcm43xx_coreinfo *old_core;
2962
2963 old_core = bcm->current_core;
2964 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2965 if (err)
2966 goto out;
2967
2968 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
2969
2970 bcm43xx_switch_core(bcm, old_core);
2971 assert(err == 0);
2972 out:
2973 return err;
2974 }
2975
2976 /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
2977 * To enable core 0, pass a core_mask of 1<<0
2978 */
2979 static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
2980 u32 core_mask)
2981 {
2982 u32 backplane_flag_nr;
2983 u32 value;
2984 struct bcm43xx_coreinfo *old_core;
2985 int err = 0;
2986
2987 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
2988 backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
2989
2990 old_core = bcm->current_core;
2991 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2992 if (err)
2993 goto out;
2994
2995 if (bcm->core_pci.rev < 6) {
2996 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
2997 value |= (1 << backplane_flag_nr);
2998 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
2999 } else {
3000 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
3001 if (err) {
3002 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3003 goto out_switch_back;
3004 }
3005 value |= core_mask << 8;
3006 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
3007 if (err) {
3008 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3009 goto out_switch_back;
3010 }
3011 }
3012
3013 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3014 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3015 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3016
3017 if (bcm->core_pci.rev < 5) {
3018 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3019 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3020 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3021 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3022 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3023 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3024 err = bcm43xx_pcicore_commit_settings(bcm);
3025 assert(err == 0);
3026 }
3027
3028 out_switch_back:
3029 err = bcm43xx_switch_core(bcm, old_core);
3030 out:
3031 return err;
3032 }
3033
3034 static void bcm43xx_softmac_init(struct bcm43xx_private *bcm)
3035 {
3036 ieee80211softmac_start(bcm->net_dev);
3037 }
3038
3039 static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
3040 {
3041 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3042
3043 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3044 return;
3045
3046 bcm43xx_mac_suspend(bcm);
3047 bcm43xx_phy_lo_g_measure(bcm);
3048 bcm43xx_mac_enable(bcm);
3049 }
3050
3051 static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
3052 {
3053 bcm43xx_phy_lo_mark_all_unused(bcm);
3054 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3055 bcm43xx_mac_suspend(bcm);
3056 bcm43xx_calc_nrssi_slope(bcm);
3057 bcm43xx_mac_enable(bcm);
3058 }
3059 }
3060
3061 static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
3062 {
3063 /* Update device statistics. */
3064 bcm43xx_calculate_link_quality(bcm);
3065 }
3066
3067 static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3068 {
3069 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3070 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
3071
3072 if (phy->type == BCM43xx_PHYTYPE_G) {
3073 //TODO: update_aci_moving_average
3074 if (radio->aci_enable && radio->aci_wlan_automatic) {
3075 bcm43xx_mac_suspend(bcm);
3076 if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3077 if (0 /*TODO: bunch of conditions*/) {
3078 bcm43xx_radio_set_interference_mitigation(bcm,
3079 BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3080 }
3081 } else if (1/*TODO*/) {
3082 /*
3083 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3084 bcm43xx_radio_set_interference_mitigation(bcm,
3085 BCM43xx_RADIO_INTERFMODE_NONE);
3086 }
3087 */
3088 }
3089 bcm43xx_mac_enable(bcm);
3090 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3091 phy->rev == 1) {
3092 //TODO: implement rev1 workaround
3093 }
3094 }
3095 bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3096 //TODO for APHY (temperature?)
3097 }
3098
3099 static void bcm43xx_periodic_task_handler(unsigned long d)
3100 {
3101 struct bcm43xx_private *bcm = (struct bcm43xx_private *)d;
3102 unsigned long flags;
3103 unsigned int state;
3104
3105 bcm43xx_lock_mmio(bcm, flags);
3106
3107 assert(bcm->initialized);
3108 state = bcm->periodic_state;
3109 if (state % 8 == 0)
3110 bcm43xx_periodic_every120sec(bcm);
3111 if (state % 4 == 0)
3112 bcm43xx_periodic_every60sec(bcm);
3113 if (state % 2 == 0)
3114 bcm43xx_periodic_every30sec(bcm);
3115 bcm43xx_periodic_every15sec(bcm);
3116 bcm->periodic_state = state + 1;
3117
3118 mod_timer(&bcm->periodic_tasks, jiffies + (HZ * 15));
3119
3120 bcm43xx_unlock_mmio(bcm, flags);
3121 }
3122
3123 static void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
3124 {
3125 del_timer_sync(&bcm->periodic_tasks);
3126 }
3127
3128 static void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
3129 {
3130 struct timer_list *timer = &(bcm->periodic_tasks);
3131
3132 assert(bcm->initialized);
3133 setup_timer(timer,
3134 bcm43xx_periodic_task_handler,
3135 (unsigned long)bcm);
3136 timer->expires = jiffies;
3137 add_timer(timer);
3138 }
3139
3140 static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3141 {
3142 bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3143 0x0056) * 2;
3144 bcm43xx_clear_keys(bcm);
3145 }
3146
3147 /* This is the opposite of bcm43xx_init_board() */
3148 static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3149 {
3150 int i, err;
3151 unsigned long flags;
3152
3153 bcm43xx_sysfs_unregister(bcm);
3154
3155 bcm43xx_periodic_tasks_delete(bcm);
3156
3157 bcm43xx_lock(bcm, flags);
3158 bcm->initialized = 0;
3159 bcm->shutting_down = 1;
3160 bcm43xx_unlock(bcm, flags);
3161
3162 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3163 if (!bcm->core_80211[i].available)
3164 continue;
3165 if (!bcm->core_80211[i].initialized)
3166 continue;
3167
3168 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3169 assert(err == 0);
3170 bcm43xx_wireless_core_cleanup(bcm);
3171 }
3172
3173 bcm43xx_pctl_set_crystal(bcm, 0);
3174
3175 bcm43xx_lock(bcm, flags);
3176 bcm->shutting_down = 0;
3177 bcm43xx_unlock(bcm, flags);
3178 }
3179
3180 static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3181 {
3182 int i, err;
3183 int connect_phy;
3184 unsigned long flags;
3185
3186 might_sleep();
3187
3188 bcm43xx_lock(bcm, flags);
3189 bcm->initialized = 0;
3190 bcm->shutting_down = 0;
3191 bcm43xx_unlock(bcm, flags);
3192
3193 err = bcm43xx_pctl_set_crystal(bcm, 1);
3194 if (err)
3195 goto out;
3196 err = bcm43xx_pctl_init(bcm);
3197 if (err)
3198 goto err_crystal_off;
3199 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3200 if (err)
3201 goto err_crystal_off;
3202
3203 tasklet_enable(&bcm->isr_tasklet);
3204 for (i = 0; i < bcm->nr_80211_available; i++) {
3205 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3206 assert(err != -ENODEV);
3207 if (err)
3208 goto err_80211_unwind;
3209
3210 /* Enable the selected wireless core.
3211 * Connect PHY only on the first core.
3212 */
3213 if (!bcm43xx_core_enabled(bcm)) {
3214 if (bcm->nr_80211_available == 1) {
3215 connect_phy = bcm43xx_current_phy(bcm)->connected;
3216 } else {
3217 if (i == 0)
3218 connect_phy = 1;
3219 else
3220 connect_phy = 0;
3221 }
3222 bcm43xx_wireless_core_reset(bcm, connect_phy);
3223 }
3224
3225 if (i != 0)
3226 bcm43xx_wireless_core_mark_inactive(bcm, &bcm->core_80211[0]);
3227
3228 err = bcm43xx_wireless_core_init(bcm);
3229 if (err)
3230 goto err_80211_unwind;
3231
3232 if (i != 0) {
3233 bcm43xx_mac_suspend(bcm);
3234 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3235 bcm43xx_radio_turn_off(bcm);
3236 }
3237 }
3238 bcm->active_80211_core = &bcm->core_80211[0];
3239 if (bcm->nr_80211_available >= 2) {
3240 bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
3241 bcm43xx_mac_enable(bcm);
3242 }
3243 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3244 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
3245 dprintk(KERN_INFO PFX "80211 cores initialized\n");
3246 bcm43xx_security_init(bcm);
3247 bcm43xx_softmac_init(bcm);
3248
3249 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
3250
3251 if (bcm43xx_current_radio(bcm)->initial_channel != 0xFF) {
3252 bcm43xx_mac_suspend(bcm);
3253 bcm43xx_radio_selectchannel(bcm, bcm43xx_current_radio(bcm)->initial_channel, 0);
3254 bcm43xx_mac_enable(bcm);
3255 }
3256
3257 /* Initialization of the board is done. Flag it as such. */
3258 bcm43xx_lock(bcm, flags);
3259 bcm->initialized = 1;
3260 bcm43xx_unlock(bcm, flags);
3261
3262 bcm43xx_periodic_tasks_setup(bcm);
3263 bcm43xx_sysfs_register(bcm);
3264 //FIXME: check for bcm43xx_sysfs_register failure. This function is a bit messy regarding unwinding, though...
3265
3266 assert(err == 0);
3267 out:
3268 return err;
3269
3270 err_80211_unwind:
3271 tasklet_disable(&bcm->isr_tasklet);
3272 /* unwind all 80211 initialization */
3273 for (i = 0; i < bcm->nr_80211_available; i++) {
3274 if (!bcm->core_80211[i].initialized)
3275 continue;
3276 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3277 bcm43xx_wireless_core_cleanup(bcm);
3278 }
3279 err_crystal_off:
3280 bcm43xx_pctl_set_crystal(bcm, 0);
3281 goto out;
3282 }
3283
3284 static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3285 {
3286 struct pci_dev *pci_dev = bcm->pci_dev;
3287 int i;
3288
3289 bcm43xx_chipset_detach(bcm);
3290 /* Do _not_ access the chip, after it is detached. */
3291 iounmap(bcm->mmio_addr);
3292
3293 pci_release_regions(pci_dev);
3294 pci_disable_device(pci_dev);
3295
3296 /* Free allocated structures/fields */
3297 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3298 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3299 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3300 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3301 }
3302 }
3303
3304 static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3305 {
3306 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3307 u16 value;
3308 u8 phy_version;
3309 u8 phy_type;
3310 u8 phy_rev;
3311 int phy_rev_ok = 1;
3312 void *p;
3313
3314 value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3315
3316 phy_version = (value & 0xF000) >> 12;
3317 phy_type = (value & 0x0F00) >> 8;
3318 phy_rev = (value & 0x000F);
3319
3320 dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
3321 phy_version, phy_type, phy_rev);
3322
3323 switch (phy_type) {
3324 case BCM43xx_PHYTYPE_A:
3325 if (phy_rev >= 4)
3326 phy_rev_ok = 0;
3327 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3328 * if we switch 80211 cores after init is done.
3329 * As we do not implement on the fly switching between
3330 * wireless cores, I will leave this as a future task.
3331 */
3332 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3333 bcm->ieee->mode = IEEE_A;
3334 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3335 IEEE80211_24GHZ_BAND;
3336 break;
3337 case BCM43xx_PHYTYPE_B:
3338 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3339 phy_rev_ok = 0;
3340 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3341 bcm->ieee->mode = IEEE_B;
3342 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3343 break;
3344 case BCM43xx_PHYTYPE_G:
3345 if (phy_rev > 7)
3346 phy_rev_ok = 0;
3347 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3348 IEEE80211_CCK_MODULATION;
3349 bcm->ieee->mode = IEEE_G;
3350 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3351 break;
3352 default:
3353 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3354 phy_type);
3355 return -ENODEV;
3356 };
3357 if (!phy_rev_ok) {
3358 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3359 phy_rev);
3360 }
3361
3362 phy->version = phy_version;
3363 phy->type = phy_type;
3364 phy->rev = phy_rev;
3365 if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3366 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3367 GFP_KERNEL);
3368 if (!p)
3369 return -ENOMEM;
3370 phy->_lo_pairs = p;
3371 }
3372
3373 return 0;
3374 }
3375
3376 static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3377 {
3378 struct pci_dev *pci_dev = bcm->pci_dev;
3379 struct net_device *net_dev = bcm->net_dev;
3380 int err;
3381 int i;
3382 unsigned long mmio_start, mmio_flags, mmio_len;
3383 u32 coremask;
3384
3385 err = pci_enable_device(pci_dev);
3386 if (err) {
3387 printk(KERN_ERR PFX "unable to wake up pci device (%i)\n", err);
3388 goto out;
3389 }
3390 mmio_start = pci_resource_start(pci_dev, 0);
3391 mmio_flags = pci_resource_flags(pci_dev, 0);
3392 mmio_len = pci_resource_len(pci_dev, 0);
3393 if (!(mmio_flags & IORESOURCE_MEM)) {
3394 printk(KERN_ERR PFX
3395 "%s, region #0 not an MMIO resource, aborting\n",
3396 pci_name(pci_dev));
3397 err = -ENODEV;
3398 goto err_pci_disable;
3399 }
3400 err = pci_request_regions(pci_dev, KBUILD_MODNAME);
3401 if (err) {
3402 printk(KERN_ERR PFX
3403 "could not access PCI resources (%i)\n", err);
3404 goto err_pci_disable;
3405 }
3406 /* enable PCI bus-mastering */
3407 pci_set_master(pci_dev);
3408 bcm->mmio_addr = ioremap(mmio_start, mmio_len);
3409 if (!bcm->mmio_addr) {
3410 printk(KERN_ERR PFX "%s: cannot remap MMIO, aborting\n",
3411 pci_name(pci_dev));
3412 err = -EIO;
3413 goto err_pci_release;
3414 }
3415 bcm->mmio_len = mmio_len;
3416 net_dev->base_addr = (unsigned long)bcm->mmio_addr;
3417
3418 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3419 &bcm->board_vendor);
3420 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3421 &bcm->board_type);
3422 bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3423 &bcm->board_revision);
3424
3425 err = bcm43xx_chipset_attach(bcm);
3426 if (err)
3427 goto err_iounmap;
3428 err = bcm43xx_pctl_init(bcm);
3429 if (err)
3430 goto err_chipset_detach;
3431 err = bcm43xx_probe_cores(bcm);
3432 if (err)
3433 goto err_chipset_detach;
3434
3435 /* Attach all IO cores to the backplane. */
3436 coremask = 0;
3437 for (i = 0; i < bcm->nr_80211_available; i++)
3438 coremask |= (1 << bcm->core_80211[i].index);
3439 //FIXME: Also attach some non80211 cores?
3440 err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3441 if (err) {
3442 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3443 goto err_chipset_detach;
3444 }
3445
3446 err = bcm43xx_sprom_extract(bcm);
3447 if (err)
3448 goto err_chipset_detach;
3449 err = bcm43xx_leds_init(bcm);
3450 if (err)
3451 goto err_chipset_detach;
3452
3453 for (i = 0; i < bcm->nr_80211_available; i++) {
3454 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3455 assert(err != -ENODEV);
3456 if (err)
3457 goto err_80211_unwind;
3458
3459 /* Enable the selected wireless core.
3460 * Connect PHY only on the first core.
3461 */
3462 bcm43xx_wireless_core_reset(bcm, (i == 0));
3463
3464 err = bcm43xx_read_phyinfo(bcm);
3465 if (err && (i == 0))
3466 goto err_80211_unwind;
3467
3468 err = bcm43xx_read_radioinfo(bcm);
3469 if (err && (i == 0))
3470 goto err_80211_unwind;
3471
3472 err = bcm43xx_validate_chip(bcm);
3473 if (err && (i == 0))
3474 goto err_80211_unwind;
3475
3476 bcm43xx_radio_turn_off(bcm);
3477 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3478 if (err)
3479 goto err_80211_unwind;
3480 bcm43xx_wireless_core_disable(bcm);
3481 }
3482 bcm43xx_pctl_set_crystal(bcm, 0);
3483
3484 /* Set the MAC address in the networking subsystem */
3485 if (is_valid_ether_addr(bcm->sprom.et1macaddr))
3486 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3487 else
3488 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3489
3490 bcm43xx_geo_init(bcm);
3491
3492 snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3493 "Broadcom %04X", bcm->chip_id);
3494
3495 assert(err == 0);
3496 out:
3497 return err;
3498
3499 err_80211_unwind:
3500 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3501 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3502 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3503 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3504 }
3505 err_chipset_detach:
3506 bcm43xx_chipset_detach(bcm);
3507 err_iounmap:
3508 iounmap(bcm->mmio_addr);
3509 err_pci_release:
3510 pci_release_regions(pci_dev);
3511 err_pci_disable:
3512 pci_disable_device(pci_dev);
3513 goto out;
3514 }
3515
3516 /* Do the Hardware IO operations to send the txb */
3517 static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3518 struct ieee80211_txb *txb)
3519 {
3520 int err = -ENODEV;
3521
3522 if (bcm43xx_using_pio(bcm))
3523 err = bcm43xx_pio_tx(bcm, txb);
3524 else
3525 err = bcm43xx_dma_tx(bcm, txb);
3526 bcm->net_dev->trans_start = jiffies;
3527
3528 return err;
3529 }
3530
3531 static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3532 u8 channel)
3533 {
3534 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3535 struct bcm43xx_radioinfo *radio;
3536 unsigned long flags;
3537
3538 bcm43xx_lock_mmio(bcm, flags);
3539 if (bcm->initialized) {
3540 bcm43xx_mac_suspend(bcm);
3541 bcm43xx_radio_selectchannel(bcm, channel, 0);
3542 bcm43xx_mac_enable(bcm);
3543 } else {
3544 radio = bcm43xx_current_radio(bcm);
3545 radio->initial_channel = channel;
3546 }
3547 bcm43xx_unlock_mmio(bcm, flags);
3548 }
3549
3550 /* set_security() callback in struct ieee80211_device */
3551 static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3552 struct ieee80211_security *sec)
3553 {
3554 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3555 struct ieee80211_security *secinfo = &bcm->ieee->sec;
3556 unsigned long flags;
3557 int keyidx;
3558
3559 dprintk(KERN_INFO PFX "set security called\n");
3560
3561 bcm43xx_lock_mmio(bcm, flags);
3562
3563 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3564 if (sec->flags & (1<<keyidx)) {
3565 secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3566 secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3567 memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3568 }
3569
3570 if (sec->flags & SEC_ACTIVE_KEY) {
3571 secinfo->active_key = sec->active_key;
3572 dprintk(KERN_INFO PFX " .active_key = %d\n", sec->active_key);
3573 }
3574 if (sec->flags & SEC_UNICAST_GROUP) {
3575 secinfo->unicast_uses_group = sec->unicast_uses_group;
3576 dprintk(KERN_INFO PFX " .unicast_uses_group = %d\n", sec->unicast_uses_group);
3577 }
3578 if (sec->flags & SEC_LEVEL) {
3579 secinfo->level = sec->level;
3580 dprintk(KERN_INFO PFX " .level = %d\n", sec->level);
3581 }
3582 if (sec->flags & SEC_ENABLED) {
3583 secinfo->enabled = sec->enabled;
3584 dprintk(KERN_INFO PFX " .enabled = %d\n", sec->enabled);
3585 }
3586 if (sec->flags & SEC_ENCRYPT) {
3587 secinfo->encrypt = sec->encrypt;
3588 dprintk(KERN_INFO PFX " .encrypt = %d\n", sec->encrypt);
3589 }
3590 if (bcm->initialized && !bcm->ieee->host_encrypt) {
3591 if (secinfo->enabled) {
3592 /* upload WEP keys to hardware */
3593 char null_address[6] = { 0 };
3594 u8 algorithm = 0;
3595 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
3596 if (!(sec->flags & (1<<keyidx)))
3597 continue;
3598 switch (sec->encode_alg[keyidx]) {
3599 case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
3600 case SEC_ALG_WEP:
3601 algorithm = BCM43xx_SEC_ALGO_WEP;
3602 if (secinfo->key_sizes[keyidx] == 13)
3603 algorithm = BCM43xx_SEC_ALGO_WEP104;
3604 break;
3605 case SEC_ALG_TKIP:
3606 FIXME();
3607 algorithm = BCM43xx_SEC_ALGO_TKIP;
3608 break;
3609 case SEC_ALG_CCMP:
3610 FIXME();
3611 algorithm = BCM43xx_SEC_ALGO_AES;
3612 break;
3613 default:
3614 assert(0);
3615 break;
3616 }
3617 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
3618 bcm->key[keyidx].enabled = 1;
3619 bcm->key[keyidx].algorithm = algorithm;
3620 }
3621 } else
3622 bcm43xx_clear_keys(bcm);
3623 }
3624 bcm43xx_unlock_mmio(bcm, flags);
3625 }
3626
3627 /* hard_start_xmit() callback in struct ieee80211_device */
3628 static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
3629 struct net_device *net_dev,
3630 int pri)
3631 {
3632 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3633 int err = -ENODEV;
3634 unsigned long flags;
3635
3636 bcm43xx_lock_mmio(bcm, flags);
3637 if (likely(bcm->initialized))
3638 err = bcm43xx_tx(bcm, txb);
3639 bcm43xx_unlock_mmio(bcm, flags);
3640
3641 return err;
3642 }
3643
3644 static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
3645 {
3646 return &(bcm43xx_priv(net_dev)->ieee->stats);
3647 }
3648
3649 static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
3650 {
3651 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3652 unsigned long flags;
3653
3654 bcm43xx_lock_mmio(bcm, flags);
3655 bcm43xx_controller_restart(bcm, "TX timeout");
3656 bcm43xx_unlock_mmio(bcm, flags);
3657 }
3658
3659 #ifdef CONFIG_NET_POLL_CONTROLLER
3660 static void bcm43xx_net_poll_controller(struct net_device *net_dev)
3661 {
3662 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3663 unsigned long flags;
3664
3665 local_irq_save(flags);
3666 bcm43xx_interrupt_handler(bcm->irq, bcm, NULL);
3667 local_irq_restore(flags);
3668 }
3669 #endif /* CONFIG_NET_POLL_CONTROLLER */
3670
3671 static int bcm43xx_net_open(struct net_device *net_dev)
3672 {
3673 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3674
3675 return bcm43xx_init_board(bcm);
3676 }
3677
3678 static int bcm43xx_net_stop(struct net_device *net_dev)
3679 {
3680 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3681
3682 ieee80211softmac_stop(net_dev);
3683 bcm43xx_disable_interrupts_sync(bcm, NULL);
3684 bcm43xx_free_board(bcm);
3685
3686 return 0;
3687 }
3688
3689 static int bcm43xx_init_private(struct bcm43xx_private *bcm,
3690 struct net_device *net_dev,
3691 struct pci_dev *pci_dev)
3692 {
3693 int err;
3694
3695 bcm->ieee = netdev_priv(net_dev);
3696 bcm->softmac = ieee80211_priv(net_dev);
3697 bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
3698
3699 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3700 bcm->pci_dev = pci_dev;
3701 bcm->net_dev = net_dev;
3702 bcm->bad_frames_preempt = modparam_bad_frames_preempt;
3703 spin_lock_init(&bcm->_lock);
3704 tasklet_init(&bcm->isr_tasklet,
3705 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
3706 (unsigned long)bcm);
3707 tasklet_disable_nosync(&bcm->isr_tasklet);
3708 if (modparam_pio) {
3709 bcm->__using_pio = 1;
3710 } else {
3711 err = pci_set_dma_mask(pci_dev, DMA_30BIT_MASK);
3712 err |= pci_set_consistent_dma_mask(pci_dev, DMA_30BIT_MASK);
3713 if (err) {
3714 #ifdef CONFIG_BCM43XX_PIO
3715 printk(KERN_WARNING PFX "DMA not supported. Falling back to PIO.\n");
3716 bcm->__using_pio = 1;
3717 #else
3718 printk(KERN_ERR PFX "FATAL: DMA not supported and PIO not configured. "
3719 "Recompile the driver with PIO support, please.\n");
3720 return -ENODEV;
3721 #endif /* CONFIG_BCM43XX_PIO */
3722 }
3723 }
3724 bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
3725
3726 /* default to sw encryption for now */
3727 bcm->ieee->host_build_iv = 0;
3728 bcm->ieee->host_encrypt = 1;
3729 bcm->ieee->host_decrypt = 1;
3730
3731 bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
3732 bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
3733 bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
3734 bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
3735
3736 return 0;
3737 }
3738
3739 static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
3740 const struct pci_device_id *ent)
3741 {
3742 struct net_device *net_dev;
3743 struct bcm43xx_private *bcm;
3744 int err;
3745
3746 #ifdef CONFIG_BCM947XX
3747 if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
3748 return -ENODEV;
3749 #endif
3750
3751 #ifdef DEBUG_SINGLE_DEVICE_ONLY
3752 if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
3753 return -ENODEV;
3754 #endif
3755
3756 net_dev = alloc_ieee80211softmac(sizeof(*bcm));
3757 if (!net_dev) {
3758 printk(KERN_ERR PFX
3759 "could not allocate ieee80211 device %s\n",
3760 pci_name(pdev));
3761 err = -ENOMEM;
3762 goto out;
3763 }
3764 /* initialize the net_device struct */
3765 SET_MODULE_OWNER(net_dev);
3766 SET_NETDEV_DEV(net_dev, &pdev->dev);
3767
3768 net_dev->open = bcm43xx_net_open;
3769 net_dev->stop = bcm43xx_net_stop;
3770 net_dev->get_stats = bcm43xx_net_get_stats;
3771 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
3772 #ifdef CONFIG_NET_POLL_CONTROLLER
3773 net_dev->poll_controller = bcm43xx_net_poll_controller;
3774 #endif
3775 net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
3776 net_dev->irq = pdev->irq;
3777 SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
3778
3779 /* initialize the bcm43xx_private struct */
3780 bcm = bcm43xx_priv(net_dev);
3781 memset(bcm, 0, sizeof(*bcm));
3782 err = bcm43xx_init_private(bcm, net_dev, pdev);
3783 if (err)
3784 goto err_free_netdev;
3785
3786 pci_set_drvdata(pdev, net_dev);
3787
3788 err = bcm43xx_attach_board(bcm);
3789 if (err)
3790 goto err_free_netdev;
3791
3792 err = register_netdev(net_dev);
3793 if (err) {
3794 printk(KERN_ERR PFX "Cannot register net device, "
3795 "aborting.\n");
3796 err = -ENOMEM;
3797 goto err_detach_board;
3798 }
3799
3800 bcm43xx_debugfs_add_device(bcm);
3801
3802 assert(err == 0);
3803 out:
3804 return err;
3805
3806 err_detach_board:
3807 bcm43xx_detach_board(bcm);
3808 err_free_netdev:
3809 free_ieee80211softmac(net_dev);
3810 goto out;
3811 }
3812
3813 static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
3814 {
3815 struct net_device *net_dev = pci_get_drvdata(pdev);
3816 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3817
3818 bcm43xx_debugfs_remove_device(bcm);
3819 unregister_netdev(net_dev);
3820 bcm43xx_detach_board(bcm);
3821 assert(bcm->ucode == NULL);
3822 free_ieee80211softmac(net_dev);
3823 }
3824
3825 /* Hard-reset the chip. Do not call this directly.
3826 * Use bcm43xx_controller_restart()
3827 */
3828 static void bcm43xx_chip_reset(void *_bcm)
3829 {
3830 struct bcm43xx_private *bcm = _bcm;
3831 struct net_device *net_dev = bcm->net_dev;
3832 struct pci_dev *pci_dev = bcm->pci_dev;
3833 int err;
3834 int was_initialized = bcm->initialized;
3835
3836 netif_stop_queue(bcm->net_dev);
3837 tasklet_disable(&bcm->isr_tasklet);
3838
3839 bcm->firmware_norelease = 1;
3840 if (was_initialized)
3841 bcm43xx_free_board(bcm);
3842 bcm->firmware_norelease = 0;
3843 bcm43xx_detach_board(bcm);
3844 err = bcm43xx_init_private(bcm, net_dev, pci_dev);
3845 if (err)
3846 goto failure;
3847 err = bcm43xx_attach_board(bcm);
3848 if (err)
3849 goto failure;
3850 if (was_initialized) {
3851 err = bcm43xx_init_board(bcm);
3852 if (err)
3853 goto failure;
3854 }
3855 netif_wake_queue(bcm->net_dev);
3856 printk(KERN_INFO PFX "Controller restarted\n");
3857
3858 return;
3859 failure:
3860 printk(KERN_ERR PFX "Controller restart failed\n");
3861 }
3862
3863 /* Hard-reset the chip.
3864 * This can be called from interrupt or process context.
3865 * Make sure to _not_ re-enable device interrupts after this has been called.
3866 */
3867 void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
3868 {
3869 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3870 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
3871 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
3872 INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
3873 schedule_work(&bcm->restart_work);
3874 }
3875
3876 #ifdef CONFIG_PM
3877
3878 static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
3879 {
3880 struct net_device *net_dev = pci_get_drvdata(pdev);
3881 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3882 unsigned long flags;
3883 int try_to_shutdown = 0, err;
3884
3885 dprintk(KERN_INFO PFX "Suspending...\n");
3886
3887 bcm43xx_lock(bcm, flags);
3888 bcm->was_initialized = bcm->initialized;
3889 if (bcm->initialized)
3890 try_to_shutdown = 1;
3891 bcm43xx_unlock(bcm, flags);
3892
3893 netif_device_detach(net_dev);
3894 if (try_to_shutdown) {
3895 ieee80211softmac_stop(net_dev);
3896 err = bcm43xx_disable_interrupts_sync(bcm, &bcm->irq_savedstate);
3897 if (unlikely(err)) {
3898 dprintk(KERN_ERR PFX "Suspend failed.\n");
3899 return -EAGAIN;
3900 }
3901 bcm->firmware_norelease = 1;
3902 bcm43xx_free_board(bcm);
3903 bcm->firmware_norelease = 0;
3904 }
3905 bcm43xx_chipset_detach(bcm);
3906
3907 pci_save_state(pdev);
3908 pci_disable_device(pdev);
3909 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3910
3911 dprintk(KERN_INFO PFX "Device suspended.\n");
3912
3913 return 0;
3914 }
3915
3916 static int bcm43xx_resume(struct pci_dev *pdev)
3917 {
3918 struct net_device *net_dev = pci_get_drvdata(pdev);
3919 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3920 int err = 0;
3921
3922 dprintk(KERN_INFO PFX "Resuming...\n");
3923
3924 pci_set_power_state(pdev, 0);
3925 pci_enable_device(pdev);
3926 pci_restore_state(pdev);
3927
3928 bcm43xx_chipset_attach(bcm);
3929 if (bcm->was_initialized) {
3930 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3931 err = bcm43xx_init_board(bcm);
3932 }
3933 if (err) {
3934 printk(KERN_ERR PFX "Resume failed!\n");
3935 return err;
3936 }
3937
3938 netif_device_attach(net_dev);
3939
3940 /*FIXME: This should be handled by softmac instead. */
3941 schedule_work(&bcm->softmac->associnfo.work);
3942
3943 dprintk(KERN_INFO PFX "Device resumed.\n");
3944
3945 return 0;
3946 }
3947
3948 #endif /* CONFIG_PM */
3949
3950 static struct pci_driver bcm43xx_pci_driver = {
3951 .name = KBUILD_MODNAME,
3952 .id_table = bcm43xx_pci_tbl,
3953 .probe = bcm43xx_init_one,
3954 .remove = __devexit_p(bcm43xx_remove_one),
3955 #ifdef CONFIG_PM
3956 .suspend = bcm43xx_suspend,
3957 .resume = bcm43xx_resume,
3958 #endif /* CONFIG_PM */
3959 };
3960
3961 static int __init bcm43xx_init(void)
3962 {
3963 printk(KERN_INFO KBUILD_MODNAME " driver\n");
3964 bcm43xx_debugfs_init();
3965 return pci_register_driver(&bcm43xx_pci_driver);
3966 }
3967
3968 static void __exit bcm43xx_exit(void)
3969 {
3970 pci_unregister_driver(&bcm43xx_pci_driver);
3971 bcm43xx_debugfs_exit();
3972 }
3973
3974 module_init(bcm43xx_init)
3975 module_exit(bcm43xx_exit)
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