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Merge ../linux-2.6/
[linux-2.6/kmemtrace.git] / drivers / video / neofb.c
blob2f156b724d1ccf00901de1f6f1eac2c8e0c08100
1 /*
2 * linux/drivers/video/neofb.c -- NeoMagic Framebuffer Driver
3 *
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
5 *
6 *
7 * Card specific code is based on XFree86's neomagic driver.
8 * Framebuffer framework code is based on code of cyber2000fb.
9 *
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file COPYING in the main directory of this
12 * archive for more details.
13 *
14 *
15 * 0.4.1
16 * - Cosmetic changes (dok)
17 *
18 * 0.4
19 * - Toshiba Libretto support, allow modes larger than LCD size if
20 * LCD is disabled, keep BIOS settings if internal/external display
21 * haven't been enabled explicitly
22 * (Thomas J. Moore <dark@mama.indstate.edu>)
23 *
24 * 0.3.3
25 * - Porting over to new fbdev api. (jsimmons)
26 *
27 * 0.3.2
28 * - got rid of all floating point (dok)
29 *
30 * 0.3.1
31 * - added module license (dok)
32 *
33 * 0.3
34 * - hardware accelerated clear and move for 2200 and above (dok)
35 * - maximum allowed dotclock is handled now (dok)
36 *
37 * 0.2.1
38 * - correct panning after X usage (dok)
39 * - added module and kernel parameters (dok)
40 * - no stretching if external display is enabled (dok)
41 *
42 * 0.2
43 * - initial version (dok)
44 *
45 *
46 * TODO
47 * - ioctl for internal/external switching
48 * - blanking
49 * - 32bit depth support, maybe impossible
50 * - disable pan-on-sync, need specs
51 *
52 * BUGS
53 * - white margin on bootup like with tdfxfb (colormap problem?)
54 *
55 */
56
57 #include <linux/config.h>
58 #include <linux/module.h>
59 #include <linux/kernel.h>
60 #include <linux/errno.h>
61 #include <linux/string.h>
62 #include <linux/mm.h>
63 #include <linux/tty.h>
64 #include <linux/slab.h>
65 #include <linux/delay.h>
66 #include <linux/fb.h>
67 #include <linux/pci.h>
68 #include <linux/init.h>
69 #ifdef CONFIG_TOSHIBA
70 #include <linux/toshiba.h>
71 extern int tosh_smm(SMMRegisters *regs);
72 #endif
73
74 #include <asm/io.h>
75 #include <asm/irq.h>
76 #include <asm/pgtable.h>
77 #include <asm/system.h>
78 #include <asm/uaccess.h>
79
80 #ifdef CONFIG_MTRR
81 #include <asm/mtrr.h>
82 #endif
83
84 #include <video/vga.h>
85 #include <video/neomagic.h>
86
87 #define NEOFB_VERSION "0.4.2"
88
89 /* --------------------------------------------------------------------- */
90
91 static int internal;
92 static int external;
93 static int libretto;
94 static int nostretch;
95 static int nopciburst;
96 static char *mode_option __devinitdata = NULL;
97
98 #ifdef MODULE
99
100 MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@convergence.de>");
101 MODULE_LICENSE("GPL");
102 MODULE_DESCRIPTION("FBDev driver for NeoMagic PCI Chips");
103 module_param(internal, bool, 0);
104 MODULE_PARM_DESC(internal, "Enable output on internal LCD Display.");
105 module_param(external, bool, 0);
106 MODULE_PARM_DESC(external, "Enable output on external CRT.");
107 module_param(libretto, bool, 0);
108 MODULE_PARM_DESC(libretto, "Force Libretto 100/110 800x480 LCD.");
109 module_param(nostretch, bool, 0);
110 MODULE_PARM_DESC(nostretch,
111 "Disable stretching of modes smaller than LCD.");
112 module_param(nopciburst, bool, 0);
113 MODULE_PARM_DESC(nopciburst, "Disable PCI burst mode.");
114 module_param(mode_option, charp, 0);
115 MODULE_PARM_DESC(mode_option, "Preferred video mode ('640x480-8@60', etc)");
116
117 #endif
118
119
120 /* --------------------------------------------------------------------- */
121
122 static biosMode bios8[] = {
123 {320, 240, 0x40},
124 {300, 400, 0x42},
125 {640, 400, 0x20},
126 {640, 480, 0x21},
127 {800, 600, 0x23},
128 {1024, 768, 0x25},
129 };
130
131 static biosMode bios16[] = {
132 {320, 200, 0x2e},
133 {320, 240, 0x41},
134 {300, 400, 0x43},
135 {640, 480, 0x31},
136 {800, 600, 0x34},
137 {1024, 768, 0x37},
138 };
139
140 static biosMode bios24[] = {
141 {640, 480, 0x32},
142 {800, 600, 0x35},
143 {1024, 768, 0x38}
144 };
145
146 #ifdef NO_32BIT_SUPPORT_YET
147 /* FIXME: guessed values, wrong */
148 static biosMode bios32[] = {
149 {640, 480, 0x33},
150 {800, 600, 0x36},
151 {1024, 768, 0x39}
152 };
153 #endif
154
155 static inline void write_le32(int regindex, u32 val, const struct neofb_par *par)
156 {
157 writel(val, par->neo2200 + par->cursorOff + regindex);
158 }
159
160 static int neoFindMode(int xres, int yres, int depth)
161 {
162 int xres_s;
163 int i, size;
164 biosMode *mode;
165
166 switch (depth) {
167 case 8:
168 size = ARRAY_SIZE(bios8);
169 mode = bios8;
170 break;
171 case 16:
172 size = ARRAY_SIZE(bios16);
173 mode = bios16;
174 break;
175 case 24:
176 size = ARRAY_SIZE(bios24);
177 mode = bios24;
178 break;
179 #ifdef NO_32BIT_SUPPORT_YET
180 case 32:
181 size = ARRAY_SIZE(bios32);
182 mode = bios32;
183 break;
184 #endif
185 default:
186 return 0;
187 }
188
189 for (i = 0; i < size; i++) {
190 if (xres <= mode[i].x_res) {
191 xres_s = mode[i].x_res;
192 for (; i < size; i++) {
193 if (mode[i].x_res != xres_s)
194 return mode[i - 1].mode;
195 if (yres <= mode[i].y_res)
196 return mode[i].mode;
197 }
198 }
199 }
200 return mode[size - 1].mode;
201 }
202
203 /*
204 * neoCalcVCLK --
205 *
206 * Determine the closest clock frequency to the one requested.
207 */
208 #define REF_FREQ 0xe517 /* 14.31818 in 20.12 fixed point */
209 #define MAX_N 127
210 #define MAX_D 31
211 #define MAX_F 1
212
213 static void neoCalcVCLK(const struct fb_info *info,
214 struct neofb_par *par, long freq)
215 {
216 int n, d, f;
217 int n_best = 0, d_best = 0, f_best = 0;
218 long f_best_diff = (0x7ffff << 12); /* 20.12 */
219 long f_target = (freq << 12) / 1000; /* 20.12 */
220
221 for (f = 0; f <= MAX_F; f++)
222 for (n = 0; n <= MAX_N; n++)
223 for (d = 0; d <= MAX_D; d++) {
224 long f_out; /* 20.12 */
225 long f_diff; /* 20.12 */
226
227 f_out =
228 ((((n + 1) << 12) / ((d +
229 1) *
230 (1 << f))) >> 12)
231 * REF_FREQ;
232 f_diff = abs(f_out - f_target);
233 if (f_diff < f_best_diff) {
234 f_best_diff = f_diff;
235 n_best = n;
236 d_best = d;
237 f_best = f;
238 }
239 }
240
241 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
242 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
243 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
244 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
245 /* NOT_DONE: We are trying the full range of the 2200 clock.
246 We should be able to try n up to 2047 */
247 par->VCLK3NumeratorLow = n_best;
248 par->VCLK3NumeratorHigh = (f_best << 7);
249 } else
250 par->VCLK3NumeratorLow = n_best | (f_best << 7);
251
252 par->VCLK3Denominator = d_best;
253
254 #ifdef NEOFB_DEBUG
255 printk("neoVCLK: f:%d NumLow=%d NumHi=%d Den=%d Df=%d\n",
256 f_target >> 12,
257 par->VCLK3NumeratorLow,
258 par->VCLK3NumeratorHigh,
259 par->VCLK3Denominator, f_best_diff >> 12);
260 #endif
261 }
262
263 /*
264 * vgaHWInit --
265 * Handle the initialization, etc. of a screen.
266 * Return FALSE on failure.
267 */
268
269 static int vgaHWInit(const struct fb_var_screeninfo *var,
270 const struct fb_info *info,
271 struct neofb_par *par, struct xtimings *timings)
272 {
273 par->MiscOutReg = 0x23;
274
275 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
276 par->MiscOutReg |= 0x40;
277
278 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
279 par->MiscOutReg |= 0x80;
280
281 /*
282 * Time Sequencer
283 */
284 par->Sequencer[0] = 0x00;
285 par->Sequencer[1] = 0x01;
286 par->Sequencer[2] = 0x0F;
287 par->Sequencer[3] = 0x00; /* Font select */
288 par->Sequencer[4] = 0x0E; /* Misc */
289
290 /*
291 * CRTC Controller
292 */
293 par->CRTC[0] = (timings->HTotal >> 3) - 5;
294 par->CRTC[1] = (timings->HDisplay >> 3) - 1;
295 par->CRTC[2] = (timings->HDisplay >> 3) - 1;
296 par->CRTC[3] = (((timings->HTotal >> 3) - 1) & 0x1F) | 0x80;
297 par->CRTC[4] = (timings->HSyncStart >> 3);
298 par->CRTC[5] = ((((timings->HTotal >> 3) - 1) & 0x20) << 2)
299 | (((timings->HSyncEnd >> 3)) & 0x1F);
300 par->CRTC[6] = (timings->VTotal - 2) & 0xFF;
301 par->CRTC[7] = (((timings->VTotal - 2) & 0x100) >> 8)
302 | (((timings->VDisplay - 1) & 0x100) >> 7)
303 | ((timings->VSyncStart & 0x100) >> 6)
304 | (((timings->VDisplay - 1) & 0x100) >> 5)
305 | 0x10 | (((timings->VTotal - 2) & 0x200) >> 4)
306 | (((timings->VDisplay - 1) & 0x200) >> 3)
307 | ((timings->VSyncStart & 0x200) >> 2);
308 par->CRTC[8] = 0x00;
309 par->CRTC[9] = (((timings->VDisplay - 1) & 0x200) >> 4) | 0x40;
310
311 if (timings->dblscan)
312 par->CRTC[9] |= 0x80;
313
314 par->CRTC[10] = 0x00;
315 par->CRTC[11] = 0x00;
316 par->CRTC[12] = 0x00;
317 par->CRTC[13] = 0x00;
318 par->CRTC[14] = 0x00;
319 par->CRTC[15] = 0x00;
320 par->CRTC[16] = timings->VSyncStart & 0xFF;
321 par->CRTC[17] = (timings->VSyncEnd & 0x0F) | 0x20;
322 par->CRTC[18] = (timings->VDisplay - 1) & 0xFF;
323 par->CRTC[19] = var->xres_virtual >> 4;
324 par->CRTC[20] = 0x00;
325 par->CRTC[21] = (timings->VDisplay - 1) & 0xFF;
326 par->CRTC[22] = (timings->VTotal - 1) & 0xFF;
327 par->CRTC[23] = 0xC3;
328 par->CRTC[24] = 0xFF;
329
330 /*
331 * are these unnecessary?
332 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
333 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
334 */
335
336 /*
337 * Graphics Display Controller
338 */
339 par->Graphics[0] = 0x00;
340 par->Graphics[1] = 0x00;
341 par->Graphics[2] = 0x00;
342 par->Graphics[3] = 0x00;
343 par->Graphics[4] = 0x00;
344 par->Graphics[5] = 0x40;
345 par->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
346 par->Graphics[7] = 0x0F;
347 par->Graphics[8] = 0xFF;
348
349
350 par->Attribute[0] = 0x00; /* standard colormap translation */
351 par->Attribute[1] = 0x01;
352 par->Attribute[2] = 0x02;
353 par->Attribute[3] = 0x03;
354 par->Attribute[4] = 0x04;
355 par->Attribute[5] = 0x05;
356 par->Attribute[6] = 0x06;
357 par->Attribute[7] = 0x07;
358 par->Attribute[8] = 0x08;
359 par->Attribute[9] = 0x09;
360 par->Attribute[10] = 0x0A;
361 par->Attribute[11] = 0x0B;
362 par->Attribute[12] = 0x0C;
363 par->Attribute[13] = 0x0D;
364 par->Attribute[14] = 0x0E;
365 par->Attribute[15] = 0x0F;
366 par->Attribute[16] = 0x41;
367 par->Attribute[17] = 0xFF;
368 par->Attribute[18] = 0x0F;
369 par->Attribute[19] = 0x00;
370 par->Attribute[20] = 0x00;
371 return 0;
372 }
373
374 static void vgaHWLock(struct vgastate *state)
375 {
376 /* Protect CRTC[0-7] */
377 vga_wcrt(state->vgabase, 0x11, vga_rcrt(state->vgabase, 0x11) | 0x80);
378 }
379
380 static void vgaHWUnlock(void)
381 {
382 /* Unprotect CRTC[0-7] */
383 vga_wcrt(NULL, 0x11, vga_rcrt(NULL, 0x11) & ~0x80);
384 }
385
386 static void neoLock(struct vgastate *state)
387 {
388 vga_wgfx(state->vgabase, 0x09, 0x00);
389 vgaHWLock(state);
390 }
391
392 static void neoUnlock(void)
393 {
394 vgaHWUnlock();
395 vga_wgfx(NULL, 0x09, 0x26);
396 }
397
398 /*
399 * VGA Palette management
400 */
401 static int paletteEnabled = 0;
402
403 static inline void VGAenablePalette(void)
404 {
405 vga_r(NULL, VGA_IS1_RC);
406 vga_w(NULL, VGA_ATT_W, 0x00);
407 paletteEnabled = 1;
408 }
409
410 static inline void VGAdisablePalette(void)
411 {
412 vga_r(NULL, VGA_IS1_RC);
413 vga_w(NULL, VGA_ATT_W, 0x20);
414 paletteEnabled = 0;
415 }
416
417 static inline void VGAwATTR(u8 index, u8 value)
418 {
419 if (paletteEnabled)
420 index &= ~0x20;
421 else
422 index |= 0x20;
423
424 vga_r(NULL, VGA_IS1_RC);
425 vga_wattr(NULL, index, value);
426 }
427
428 static void vgaHWProtect(int on)
429 {
430 unsigned char tmp;
431
432 if (on) {
433 /*
434 * Turn off screen and disable sequencer.
435 */
436 tmp = vga_rseq(NULL, 0x01);
437 vga_wseq(NULL, 0x00, 0x01); /* Synchronous Reset */
438 vga_wseq(NULL, 0x01, tmp | 0x20); /* disable the display */
439
440 VGAenablePalette();
441 } else {
442 /*
443 * Reenable sequencer, then turn on screen.
444 */
445 tmp = vga_rseq(NULL, 0x01);
446 vga_wseq(NULL, 0x01, tmp & ~0x20); /* reenable display */
447 vga_wseq(NULL, 0x00, 0x03); /* clear synchronousreset */
448
449 VGAdisablePalette();
450 }
451 }
452
453 static void vgaHWRestore(const struct fb_info *info,
454 const struct neofb_par *par)
455 {
456 int i;
457
458 vga_w(NULL, VGA_MIS_W, par->MiscOutReg);
459
460 for (i = 1; i < 5; i++)
461 vga_wseq(NULL, i, par->Sequencer[i]);
462
463 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or CRTC[17] */
464 vga_wcrt(NULL, 17, par->CRTC[17] & ~0x80);
465
466 for (i = 0; i < 25; i++)
467 vga_wcrt(NULL, i, par->CRTC[i]);
468
469 for (i = 0; i < 9; i++)
470 vga_wgfx(NULL, i, par->Graphics[i]);
471
472 VGAenablePalette();
473
474 for (i = 0; i < 21; i++)
475 VGAwATTR(i, par->Attribute[i]);
476
477 VGAdisablePalette();
478 }
479
480
481 /* -------------------- Hardware specific routines ------------------------- */
482
483 /*
484 * Hardware Acceleration for Neo2200+
485 */
486 static inline int neo2200_sync(struct fb_info *info)
487 {
488 struct neofb_par *par = info->par;
489
490 while (readl(&par->neo2200->bltStat) & 1);
491 return 0;
492 }
493
494 static inline void neo2200_wait_fifo(struct fb_info *info,
495 int requested_fifo_space)
496 {
497 // ndev->neo.waitfifo_calls++;
498 // ndev->neo.waitfifo_sum += requested_fifo_space;
499
500 /* FIXME: does not work
501 if (neo_fifo_space < requested_fifo_space)
502 {
503 neo_fifo_waitcycles++;
504
505 while (1)
506 {
507 neo_fifo_space = (neo2200->bltStat >> 8);
508 if (neo_fifo_space >= requested_fifo_space)
509 break;
510 }
511 }
512 else
513 {
514 neo_fifo_cache_hits++;
515 }
516
517 neo_fifo_space -= requested_fifo_space;
518 */
519
520 neo2200_sync(info);
521 }
522
523 static inline void neo2200_accel_init(struct fb_info *info,
524 struct fb_var_screeninfo *var)
525 {
526 struct neofb_par *par = info->par;
527 Neo2200 __iomem *neo2200 = par->neo2200;
528 u32 bltMod, pitch;
529
530 neo2200_sync(info);
531
532 switch (var->bits_per_pixel) {
533 case 8:
534 bltMod = NEO_MODE1_DEPTH8;
535 pitch = var->xres_virtual;
536 break;
537 case 15:
538 case 16:
539 bltMod = NEO_MODE1_DEPTH16;
540 pitch = var->xres_virtual * 2;
541 break;
542 case 24:
543 bltMod = NEO_MODE1_DEPTH24;
544 pitch = var->xres_virtual * 3;
545 break;
546 default:
547 printk(KERN_ERR
548 "neofb: neo2200_accel_init: unexpected bits per pixel!\n");
549 return;
550 }
551
552 writel(bltMod << 16, &neo2200->bltStat);
553 writel((pitch << 16) | pitch, &neo2200->pitch);
554 }
555
556 /* --------------------------------------------------------------------- */
557
558 static int
559 neofb_open(struct fb_info *info, int user)
560 {
561 struct neofb_par *par = info->par;
562 int cnt = atomic_read(&par->ref_count);
563
564 if (!cnt) {
565 memset(&par->state, 0, sizeof(struct vgastate));
566 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
567 save_vga(&par->state);
568 }
569 atomic_inc(&par->ref_count);
570 return 0;
571 }
572
573 static int
574 neofb_release(struct fb_info *info, int user)
575 {
576 struct neofb_par *par = info->par;
577 int cnt = atomic_read(&par->ref_count);
578
579 if (!cnt)
580 return -EINVAL;
581 if (cnt == 1) {
582 restore_vga(&par->state);
583 }
584 atomic_dec(&par->ref_count);
585 return 0;
586 }
587
588 static int
589 neofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
590 {
591 struct neofb_par *par = info->par;
592 unsigned int pixclock = var->pixclock;
593 struct xtimings timings;
594 int memlen, vramlen;
595 int mode_ok = 0;
596
597 DBG("neofb_check_var");
598
599 if (!pixclock)
600 pixclock = 10000; /* 10ns = 100MHz */
601 timings.pixclock = 1000000000 / pixclock;
602 if (timings.pixclock < 1)
603 timings.pixclock = 1;
604
605 if (timings.pixclock > par->maxClock)
606 return -EINVAL;
607
608 timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
609 timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
610 timings.HDisplay = var->xres;
611 timings.HSyncStart = timings.HDisplay + var->right_margin;
612 timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
613 timings.HTotal = timings.HSyncEnd + var->left_margin;
614 timings.VDisplay = var->yres;
615 timings.VSyncStart = timings.VDisplay + var->lower_margin;
616 timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
617 timings.VTotal = timings.VSyncEnd + var->upper_margin;
618 timings.sync = var->sync;
619
620 /* Is the mode larger than the LCD panel? */
621 if (par->internal_display &&
622 ((var->xres > par->NeoPanelWidth) ||
623 (var->yres > par->NeoPanelHeight))) {
624 printk(KERN_INFO
625 "Mode (%dx%d) larger than the LCD panel (%dx%d)\n",
626 var->xres, var->yres, par->NeoPanelWidth,
627 par->NeoPanelHeight);
628 return -EINVAL;
629 }
630
631 /* Is the mode one of the acceptable sizes? */
632 if (!par->internal_display)
633 mode_ok = 1;
634 else {
635 switch (var->xres) {
636 case 1280:
637 if (var->yres == 1024)
638 mode_ok = 1;
639 break;
640 case 1024:
641 if (var->yres == 768)
642 mode_ok = 1;
643 break;
644 case 800:
645 if (var->yres == (par->libretto ? 480 : 600))
646 mode_ok = 1;
647 break;
648 case 640:
649 if (var->yres == 480)
650 mode_ok = 1;
651 break;
652 }
653 }
654
655 if (!mode_ok) {
656 printk(KERN_INFO
657 "Mode (%dx%d) won't display properly on LCD\n",
658 var->xres, var->yres);
659 return -EINVAL;
660 }
661
662 var->red.msb_right = 0;
663 var->green.msb_right = 0;
664 var->blue.msb_right = 0;
665
666 switch (var->bits_per_pixel) {
667 case 8: /* PSEUDOCOLOUR, 256 */
668 var->transp.offset = 0;
669 var->transp.length = 0;
670 var->red.offset = 0;
671 var->red.length = 8;
672 var->green.offset = 0;
673 var->green.length = 8;
674 var->blue.offset = 0;
675 var->blue.length = 8;
676 break;
677
678 case 16: /* DIRECTCOLOUR, 64k */
679 var->transp.offset = 0;
680 var->transp.length = 0;
681 var->red.offset = 11;
682 var->red.length = 5;
683 var->green.offset = 5;
684 var->green.length = 6;
685 var->blue.offset = 0;
686 var->blue.length = 5;
687 break;
688
689 case 24: /* TRUECOLOUR, 16m */
690 var->transp.offset = 0;
691 var->transp.length = 0;
692 var->red.offset = 16;
693 var->red.length = 8;
694 var->green.offset = 8;
695 var->green.length = 8;
696 var->blue.offset = 0;
697 var->blue.length = 8;
698 break;
699
700 #ifdef NO_32BIT_SUPPORT_YET
701 case 32: /* TRUECOLOUR, 16m */
702 var->transp.offset = 24;
703 var->transp.length = 8;
704 var->red.offset = 16;
705 var->red.length = 8;
706 var->green.offset = 8;
707 var->green.length = 8;
708 var->blue.offset = 0;
709 var->blue.length = 8;
710 break;
711 #endif
712 default:
713 printk(KERN_WARNING "neofb: no support for %dbpp\n",
714 var->bits_per_pixel);
715 return -EINVAL;
716 }
717
718 vramlen = info->fix.smem_len;
719 if (vramlen > 4 * 1024 * 1024)
720 vramlen = 4 * 1024 * 1024;
721
722 if (var->yres_virtual < var->yres)
723 var->yres_virtual = var->yres;
724 if (var->xres_virtual < var->xres)
725 var->xres_virtual = var->xres;
726
727 memlen = var->xres_virtual * var->bits_per_pixel * var->yres_virtual >> 3;
728
729 if (memlen > vramlen) {
730 var->yres_virtual = vramlen * 8 / (var->xres_virtual *
731 var->bits_per_pixel);
732 memlen = var->xres_virtual * var->bits_per_pixel *
733 var->yres_virtual / 8;
734 }
735
736 /* we must round yres/xres down, we already rounded y/xres_virtual up
737 if it was possible. We should return -EINVAL, but I disagree */
738 if (var->yres_virtual < var->yres)
739 var->yres = var->yres_virtual;
740 if (var->xres_virtual < var->xres)
741 var->xres = var->xres_virtual;
742 if (var->xoffset + var->xres > var->xres_virtual)
743 var->xoffset = var->xres_virtual - var->xres;
744 if (var->yoffset + var->yres > var->yres_virtual)
745 var->yoffset = var->yres_virtual - var->yres;
746
747 var->nonstd = 0;
748 var->height = -1;
749 var->width = -1;
750
751 if (var->bits_per_pixel >= 24 || !par->neo2200)
752 var->accel_flags &= ~FB_ACCELF_TEXT;
753 return 0;
754 }
755
756 static int neofb_set_par(struct fb_info *info)
757 {
758 struct neofb_par *par = info->par;
759 struct xtimings timings;
760 unsigned char temp;
761 int i, clock_hi = 0;
762 int lcd_stretch;
763 int hoffset, voffset;
764
765 DBG("neofb_set_par");
766
767 neoUnlock();
768
769 vgaHWProtect(1); /* Blank the screen */
770
771 timings.dblscan = info->var.vmode & FB_VMODE_DOUBLE;
772 timings.interlaced = info->var.vmode & FB_VMODE_INTERLACED;
773 timings.HDisplay = info->var.xres;
774 timings.HSyncStart = timings.HDisplay + info->var.right_margin;
775 timings.HSyncEnd = timings.HSyncStart + info->var.hsync_len;
776 timings.HTotal = timings.HSyncEnd + info->var.left_margin;
777 timings.VDisplay = info->var.yres;
778 timings.VSyncStart = timings.VDisplay + info->var.lower_margin;
779 timings.VSyncEnd = timings.VSyncStart + info->var.vsync_len;
780 timings.VTotal = timings.VSyncEnd + info->var.upper_margin;
781 timings.sync = info->var.sync;
782 timings.pixclock = PICOS2KHZ(info->var.pixclock);
783
784 if (timings.pixclock < 1)
785 timings.pixclock = 1;
786
787 /*
788 * This will allocate the datastructure and initialize all of the
789 * generic VGA registers.
790 */
791
792 if (vgaHWInit(&info->var, info, par, &timings))
793 return -EINVAL;
794
795 /*
796 * The default value assigned by vgaHW.c is 0x41, but this does
797 * not work for NeoMagic.
798 */
799 par->Attribute[16] = 0x01;
800
801 switch (info->var.bits_per_pixel) {
802 case 8:
803 par->CRTC[0x13] = info->var.xres_virtual >> 3;
804 par->ExtCRTOffset = info->var.xres_virtual >> 11;
805 par->ExtColorModeSelect = 0x11;
806 break;
807 case 16:
808 par->CRTC[0x13] = info->var.xres_virtual >> 2;
809 par->ExtCRTOffset = info->var.xres_virtual >> 10;
810 par->ExtColorModeSelect = 0x13;
811 break;
812 case 24:
813 par->CRTC[0x13] = (info->var.xres_virtual * 3) >> 3;
814 par->ExtCRTOffset = (info->var.xres_virtual * 3) >> 11;
815 par->ExtColorModeSelect = 0x14;
816 break;
817 #ifdef NO_32BIT_SUPPORT_YET
818 case 32: /* FIXME: guessed values */
819 par->CRTC[0x13] = info->var.xres_virtual >> 1;
820 par->ExtCRTOffset = info->var.xres_virtual >> 9;
821 par->ExtColorModeSelect = 0x15;
822 break;
823 #endif
824 default:
825 break;
826 }
827
828 par->ExtCRTDispAddr = 0x10;
829
830 /* Vertical Extension */
831 par->VerticalExt = (((timings.VTotal - 2) & 0x400) >> 10)
832 | (((timings.VDisplay - 1) & 0x400) >> 9)
833 | (((timings.VSyncStart) & 0x400) >> 8)
834 | (((timings.VSyncStart) & 0x400) >> 7);
835
836 /* Fast write bursts on unless disabled. */
837 if (par->pci_burst)
838 par->SysIfaceCntl1 = 0x30;
839 else
840 par->SysIfaceCntl1 = 0x00;
841
842 par->SysIfaceCntl2 = 0xc0; /* VESA Bios sets this to 0x80! */
843
844 /* Initialize: by default, we want display config register to be read */
845 par->PanelDispCntlRegRead = 1;
846
847 /* Enable any user specified display devices. */
848 par->PanelDispCntlReg1 = 0x00;
849 if (par->internal_display)
850 par->PanelDispCntlReg1 |= 0x02;
851 if (par->external_display)
852 par->PanelDispCntlReg1 |= 0x01;
853
854 /* If the user did not specify any display devices, then... */
855 if (par->PanelDispCntlReg1 == 0x00) {
856 /* Default to internal (i.e., LCD) only. */
857 par->PanelDispCntlReg1 = vga_rgfx(NULL, 0x20) & 0x03;
858 }
859
860 /* If we are using a fixed mode, then tell the chip we are. */
861 switch (info->var.xres) {
862 case 1280:
863 par->PanelDispCntlReg1 |= 0x60;
864 break;
865 case 1024:
866 par->PanelDispCntlReg1 |= 0x40;
867 break;
868 case 800:
869 par->PanelDispCntlReg1 |= 0x20;
870 break;
871 case 640:
872 default:
873 break;
874 }
875
876 /* Setup shadow register locking. */
877 switch (par->PanelDispCntlReg1 & 0x03) {
878 case 0x01: /* External CRT only mode: */
879 par->GeneralLockReg = 0x00;
880 /* We need to program the VCLK for external display only mode. */
881 par->ProgramVCLK = 1;
882 break;
883 case 0x02: /* Internal LCD only mode: */
884 case 0x03: /* Simultaneous internal/external (LCD/CRT) mode: */
885 par->GeneralLockReg = 0x01;
886 /* Don't program the VCLK when using the LCD. */
887 par->ProgramVCLK = 0;
888 break;
889 }
890
891 /*
892 * If the screen is to be stretched, turn on stretching for the
893 * various modes.
894 *
895 * OPTION_LCD_STRETCH means stretching should be turned off!
896 */
897 par->PanelDispCntlReg2 = 0x00;
898 par->PanelDispCntlReg3 = 0x00;
899
900 if (par->lcd_stretch && (par->PanelDispCntlReg1 == 0x02) && /* LCD only */
901 (info->var.xres != par->NeoPanelWidth)) {
902 switch (info->var.xres) {
903 case 320: /* Needs testing. KEM -- 24 May 98 */
904 case 400: /* Needs testing. KEM -- 24 May 98 */
905 case 640:
906 case 800:
907 case 1024:
908 lcd_stretch = 1;
909 par->PanelDispCntlReg2 |= 0xC6;
910 break;
911 default:
912 lcd_stretch = 0;
913 /* No stretching in these modes. */
914 }
915 } else
916 lcd_stretch = 0;
917
918 /*
919 * If the screen is to be centerd, turn on the centering for the
920 * various modes.
921 */
922 par->PanelVertCenterReg1 = 0x00;
923 par->PanelVertCenterReg2 = 0x00;
924 par->PanelVertCenterReg3 = 0x00;
925 par->PanelVertCenterReg4 = 0x00;
926 par->PanelVertCenterReg5 = 0x00;
927 par->PanelHorizCenterReg1 = 0x00;
928 par->PanelHorizCenterReg2 = 0x00;
929 par->PanelHorizCenterReg3 = 0x00;
930 par->PanelHorizCenterReg4 = 0x00;
931 par->PanelHorizCenterReg5 = 0x00;
932
933
934 if (par->PanelDispCntlReg1 & 0x02) {
935 if (info->var.xres == par->NeoPanelWidth) {
936 /*
937 * No centering required when the requested display width
938 * equals the panel width.
939 */
940 } else {
941 par->PanelDispCntlReg2 |= 0x01;
942 par->PanelDispCntlReg3 |= 0x10;
943
944 /* Calculate the horizontal and vertical offsets. */
945 if (!lcd_stretch) {
946 hoffset =
947 ((par->NeoPanelWidth -
948 info->var.xres) >> 4) - 1;
949 voffset =
950 ((par->NeoPanelHeight -
951 info->var.yres) >> 1) - 2;
952 } else {
953 /* Stretched modes cannot be centered. */
954 hoffset = 0;
955 voffset = 0;
956 }
957
958 switch (info->var.xres) {
959 case 320: /* Needs testing. KEM -- 24 May 98 */
960 par->PanelHorizCenterReg3 = hoffset;
961 par->PanelVertCenterReg2 = voffset;
962 break;
963 case 400: /* Needs testing. KEM -- 24 May 98 */
964 par->PanelHorizCenterReg4 = hoffset;
965 par->PanelVertCenterReg1 = voffset;
966 break;
967 case 640:
968 par->PanelHorizCenterReg1 = hoffset;
969 par->PanelVertCenterReg3 = voffset;
970 break;
971 case 800:
972 par->PanelHorizCenterReg2 = hoffset;
973 par->PanelVertCenterReg4 = voffset;
974 break;
975 case 1024:
976 par->PanelHorizCenterReg5 = hoffset;
977 par->PanelVertCenterReg5 = voffset;
978 break;
979 case 1280:
980 default:
981 /* No centering in these modes. */
982 break;
983 }
984 }
985 }
986
987 par->biosMode =
988 neoFindMode(info->var.xres, info->var.yres,
989 info->var.bits_per_pixel);
990
991 /*
992 * Calculate the VCLK that most closely matches the requested dot
993 * clock.
994 */
995 neoCalcVCLK(info, par, timings.pixclock);
996
997 /* Since we program the clocks ourselves, always use VCLK3. */
998 par->MiscOutReg |= 0x0C;
999
1000 /* alread unlocked above */
1001 /* BOGUS vga_wgfx(NULL, 0x09, 0x26); */
1002
1003 /* don't know what this is, but it's 0 from bootup anyway */
1004 vga_wgfx(NULL, 0x15, 0x00);
1005
1006 /* was set to 0x01 by my bios in text and vesa modes */
1007 vga_wgfx(NULL, 0x0A, par->GeneralLockReg);
1008
1009 /*
1010 * The color mode needs to be set before calling vgaHWRestore
1011 * to ensure the DAC is initialized properly.
1012 *
1013 * NOTE: Make sure we don't change bits make sure we don't change
1014 * any reserved bits.
1015 */
1016 temp = vga_rgfx(NULL, 0x90);
1017 switch (info->fix.accel) {
1018 case FB_ACCEL_NEOMAGIC_NM2070:
1019 temp &= 0xF0; /* Save bits 7:4 */
1020 temp |= (par->ExtColorModeSelect & ~0xF0);
1021 break;
1022 case FB_ACCEL_NEOMAGIC_NM2090:
1023 case FB_ACCEL_NEOMAGIC_NM2093:
1024 case FB_ACCEL_NEOMAGIC_NM2097:
1025 case FB_ACCEL_NEOMAGIC_NM2160:
1026 case FB_ACCEL_NEOMAGIC_NM2200:
1027 case FB_ACCEL_NEOMAGIC_NM2230:
1028 case FB_ACCEL_NEOMAGIC_NM2360:
1029 case FB_ACCEL_NEOMAGIC_NM2380:
1030 temp &= 0x70; /* Save bits 6:4 */
1031 temp |= (par->ExtColorModeSelect & ~0x70);
1032 break;
1033 }
1034
1035 vga_wgfx(NULL, 0x90, temp);
1036
1037 /*
1038 * In some rare cases a lockup might occur if we don't delay
1039 * here. (Reported by Miles Lane)
1040 */
1041 //mdelay(200);
1042
1043 /*
1044 * Disable horizontal and vertical graphics and text expansions so
1045 * that vgaHWRestore works properly.
1046 */
1047 temp = vga_rgfx(NULL, 0x25);
1048 temp &= 0x39;
1049 vga_wgfx(NULL, 0x25, temp);
1050
1051 /*
1052 * Sleep for 200ms to make sure that the two operations above have
1053 * had time to take effect.
1054 */
1055 mdelay(200);
1056
1057 /*
1058 * This function handles restoring the generic VGA registers. */
1059 vgaHWRestore(info, par);
1060
1061 /* linear colormap for non palettized modes */
1062 switch (info->var.bits_per_pixel) {
1063 case 8:
1064 /* PseudoColor, 256 */
1065 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1066 break;
1067 case 16:
1068 /* TrueColor, 64k */
1069 info->fix.visual = FB_VISUAL_TRUECOLOR;
1070
1071 for (i = 0; i < 64; i++) {
1072 outb(i, 0x3c8);
1073
1074 outb(i << 1, 0x3c9);
1075 outb(i, 0x3c9);
1076 outb(i << 1, 0x3c9);
1077 }
1078 break;
1079 case 24:
1080 #ifdef NO_32BIT_SUPPORT_YET
1081 case 32:
1082 #endif
1083 /* TrueColor, 16m */
1084 info->fix.visual = FB_VISUAL_TRUECOLOR;
1085
1086 for (i = 0; i < 256; i++) {
1087 outb(i, 0x3c8);
1088
1089 outb(i, 0x3c9);
1090 outb(i, 0x3c9);
1091 outb(i, 0x3c9);
1092 }
1093 break;
1094 }
1095
1096 vga_wgfx(NULL, 0x0E, par->ExtCRTDispAddr);
1097 vga_wgfx(NULL, 0x0F, par->ExtCRTOffset);
1098 temp = vga_rgfx(NULL, 0x10);
1099 temp &= 0x0F; /* Save bits 3:0 */
1100 temp |= (par->SysIfaceCntl1 & ~0x0F); /* VESA Bios sets bit 1! */
1101 vga_wgfx(NULL, 0x10, temp);
1102
1103 vga_wgfx(NULL, 0x11, par->SysIfaceCntl2);
1104 vga_wgfx(NULL, 0x15, 0 /*par->SingleAddrPage */ );
1105 vga_wgfx(NULL, 0x16, 0 /*par->DualAddrPage */ );
1106
1107 temp = vga_rgfx(NULL, 0x20);
1108 switch (info->fix.accel) {
1109 case FB_ACCEL_NEOMAGIC_NM2070:
1110 temp &= 0xFC; /* Save bits 7:2 */
1111 temp |= (par->PanelDispCntlReg1 & ~0xFC);
1112 break;
1113 case FB_ACCEL_NEOMAGIC_NM2090:
1114 case FB_ACCEL_NEOMAGIC_NM2093:
1115 case FB_ACCEL_NEOMAGIC_NM2097:
1116 case FB_ACCEL_NEOMAGIC_NM2160:
1117 temp &= 0xDC; /* Save bits 7:6,4:2 */
1118 temp |= (par->PanelDispCntlReg1 & ~0xDC);
1119 break;
1120 case FB_ACCEL_NEOMAGIC_NM2200:
1121 case FB_ACCEL_NEOMAGIC_NM2230:
1122 case FB_ACCEL_NEOMAGIC_NM2360:
1123 case FB_ACCEL_NEOMAGIC_NM2380:
1124 temp &= 0x98; /* Save bits 7,4:3 */
1125 temp |= (par->PanelDispCntlReg1 & ~0x98);
1126 break;
1127 }
1128 vga_wgfx(NULL, 0x20, temp);
1129
1130 temp = vga_rgfx(NULL, 0x25);
1131 temp &= 0x38; /* Save bits 5:3 */
1132 temp |= (par->PanelDispCntlReg2 & ~0x38);
1133 vga_wgfx(NULL, 0x25, temp);
1134
1135 if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
1136 temp = vga_rgfx(NULL, 0x30);
1137 temp &= 0xEF; /* Save bits 7:5 and bits 3:0 */
1138 temp |= (par->PanelDispCntlReg3 & ~0xEF);
1139 vga_wgfx(NULL, 0x30, temp);
1140 }
1141
1142 vga_wgfx(NULL, 0x28, par->PanelVertCenterReg1);
1143 vga_wgfx(NULL, 0x29, par->PanelVertCenterReg2);
1144 vga_wgfx(NULL, 0x2a, par->PanelVertCenterReg3);
1145
1146 if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
1147 vga_wgfx(NULL, 0x32, par->PanelVertCenterReg4);
1148 vga_wgfx(NULL, 0x33, par->PanelHorizCenterReg1);
1149 vga_wgfx(NULL, 0x34, par->PanelHorizCenterReg2);
1150 vga_wgfx(NULL, 0x35, par->PanelHorizCenterReg3);
1151 }
1152
1153 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2160)
1154 vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
1155
1156 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
1157 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
1158 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
1159 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
1160 vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
1161 vga_wgfx(NULL, 0x37, par->PanelVertCenterReg5);
1162 vga_wgfx(NULL, 0x38, par->PanelHorizCenterReg5);
1163
1164 clock_hi = 1;
1165 }
1166
1167 /* Program VCLK3 if needed. */
1168 if (par->ProgramVCLK && ((vga_rgfx(NULL, 0x9B) != par->VCLK3NumeratorLow)
1169 || (vga_rgfx(NULL, 0x9F) != par->VCLK3Denominator)
1170 || (clock_hi && ((vga_rgfx(NULL, 0x8F) & ~0x0f)
1171 != (par->VCLK3NumeratorHigh &
1172 ~0x0F))))) {
1173 vga_wgfx(NULL, 0x9B, par->VCLK3NumeratorLow);
1174 if (clock_hi) {
1175 temp = vga_rgfx(NULL, 0x8F);
1176 temp &= 0x0F; /* Save bits 3:0 */
1177 temp |= (par->VCLK3NumeratorHigh & ~0x0F);
1178 vga_wgfx(NULL, 0x8F, temp);
1179 }
1180 vga_wgfx(NULL, 0x9F, par->VCLK3Denominator);
1181 }
1182
1183 if (par->biosMode)
1184 vga_wcrt(NULL, 0x23, par->biosMode);
1185
1186 vga_wgfx(NULL, 0x93, 0xc0); /* Gives 5x faster framebuffer writes !!! */
1187
1188 /* Program vertical extension register */
1189 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
1190 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
1191 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
1192 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
1193 vga_wcrt(NULL, 0x70, par->VerticalExt);
1194 }
1195
1196 vgaHWProtect(0); /* Turn on screen */
1197
1198 /* Calling this also locks offset registers required in update_start */
1199 neoLock(&par->state);
1200
1201 info->fix.line_length =
1202 info->var.xres_virtual * (info->var.bits_per_pixel >> 3);
1203
1204 switch (info->fix.accel) {
1205 case FB_ACCEL_NEOMAGIC_NM2200:
1206 case FB_ACCEL_NEOMAGIC_NM2230:
1207 case FB_ACCEL_NEOMAGIC_NM2360:
1208 case FB_ACCEL_NEOMAGIC_NM2380:
1209 neo2200_accel_init(info, &info->var);
1210 break;
1211 default:
1212 break;
1213 }
1214 return 0;
1215 }
1216
1217 static void neofb_update_start(struct fb_info *info,
1218 struct fb_var_screeninfo *var)
1219 {
1220 struct neofb_par *par = info->par;
1221 struct vgastate *state = &par->state;
1222 int oldExtCRTDispAddr;
1223 int Base;
1224
1225 DBG("neofb_update_start");
1226
1227 Base = (var->yoffset * var->xres_virtual + var->xoffset) >> 2;
1228 Base *= (var->bits_per_pixel + 7) / 8;
1229
1230 neoUnlock();
1231
1232 /*
1233 * These are the generic starting address registers.
1234 */
1235 vga_wcrt(state->vgabase, 0x0C, (Base & 0x00FF00) >> 8);
1236 vga_wcrt(state->vgabase, 0x0D, (Base & 0x00FF));
1237
1238 /*
1239 * Make sure we don't clobber some other bits that might already
1240 * have been set. NOTE: NM2200 has a writable bit 3, but it shouldn't
1241 * be needed.
1242 */
1243 oldExtCRTDispAddr = vga_rgfx(NULL, 0x0E);
1244 vga_wgfx(state->vgabase, 0x0E, (((Base >> 16) & 0x0f) | (oldExtCRTDispAddr & 0xf0)));
1245
1246 neoLock(state);
1247 }
1248
1249 /*
1250 * Pan or Wrap the Display
1251 */
1252 static int neofb_pan_display(struct fb_var_screeninfo *var,
1253 struct fb_info *info)
1254 {
1255 u_int y_bottom;
1256
1257 y_bottom = var->yoffset;
1258
1259 if (!(var->vmode & FB_VMODE_YWRAP))
1260 y_bottom += var->yres;
1261
1262 if (var->xoffset > (var->xres_virtual - var->xres))
1263 return -EINVAL;
1264 if (y_bottom > info->var.yres_virtual)
1265 return -EINVAL;
1266
1267 neofb_update_start(info, var);
1268
1269 info->var.xoffset = var->xoffset;
1270 info->var.yoffset = var->yoffset;
1271
1272 if (var->vmode & FB_VMODE_YWRAP)
1273 info->var.vmode |= FB_VMODE_YWRAP;
1274 else
1275 info->var.vmode &= ~FB_VMODE_YWRAP;
1276 return 0;
1277 }
1278
1279 static int neofb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1280 u_int transp, struct fb_info *fb)
1281 {
1282 if (regno >= fb->cmap.len || regno > 255)
1283 return -EINVAL;
1284
1285 switch (fb->var.bits_per_pixel) {
1286 case 8:
1287 outb(regno, 0x3c8);
1288
1289 outb(red >> 10, 0x3c9);
1290 outb(green >> 10, 0x3c9);
1291 outb(blue >> 10, 0x3c9);
1292 break;
1293 case 16:
1294 ((u32 *) fb->pseudo_palette)[regno] =
1295 ((red & 0xf800)) | ((green & 0xfc00) >> 5) |
1296 ((blue & 0xf800) >> 11);
1297 break;
1298 case 24:
1299 ((u32 *) fb->pseudo_palette)[regno] =
1300 ((red & 0xff00) << 8) | ((green & 0xff00)) |
1301 ((blue & 0xff00) >> 8);
1302 break;
1303 #ifdef NO_32BIT_SUPPORT_YET
1304 case 32:
1305 ((u32 *) fb->pseudo_palette)[regno] =
1306 ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) |
1307 ((green & 0xff00)) | ((blue & 0xff00) >> 8);
1308 break;
1309 #endif
1310 default:
1311 return 1;
1312 }
1313 return 0;
1314 }
1315
1316 /*
1317 * (Un)Blank the display.
1318 */
1319 static int neofb_blank(int blank_mode, struct fb_info *info)
1320 {
1321 /*
1322 * Blank the screen if blank_mode != 0, else unblank.
1323 * Return 0 if blanking succeeded, != 0 if un-/blanking failed due to
1324 * e.g. a video mode which doesn't support it. Implements VESA suspend
1325 * and powerdown modes for monitors, and backlight control on LCDs.
1326 * blank_mode == 0: unblanked (backlight on)
1327 * blank_mode == 1: blank (backlight on)
1328 * blank_mode == 2: suspend vsync (backlight off)
1329 * blank_mode == 3: suspend hsync (backlight off)
1330 * blank_mode == 4: powerdown (backlight off)
1331 *
1332 * wms...Enable VESA DPMS compatible powerdown mode
1333 * run "setterm -powersave powerdown" to take advantage
1334 */
1335 struct neofb_par *par = info->par;
1336 int seqflags, lcdflags, dpmsflags, reg, tmpdisp;
1337
1338 /*
1339 * Read back the register bits related to display configuration. They might
1340 * have been changed underneath the driver via Fn key stroke.
1341 */
1342 neoUnlock();
1343 tmpdisp = vga_rgfx(NULL, 0x20) & 0x03;
1344 neoLock(&par->state);
1345
1346 /* In case we blank the screen, we want to store the possibly new
1347 * configuration in the driver. During un-blank, we re-apply this setting,
1348 * since the LCD bit will be cleared in order to switch off the backlight.
1349 */
1350 if (par->PanelDispCntlRegRead) {
1351 par->PanelDispCntlReg1 = tmpdisp;
1352 }
1353 par->PanelDispCntlRegRead = !blank_mode;
1354
1355 switch (blank_mode) {
1356 case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */
1357 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1358 lcdflags = 0; /* LCD off */
1359 dpmsflags = NEO_GR01_SUPPRESS_HSYNC |
1360 NEO_GR01_SUPPRESS_VSYNC;
1361 #ifdef CONFIG_TOSHIBA
1362 /* Do we still need this ? */
1363 /* attempt to turn off backlight on toshiba; also turns off external */
1364 {
1365 SMMRegisters regs;
1366
1367 regs.eax = 0xff00; /* HCI_SET */
1368 regs.ebx = 0x0002; /* HCI_BACKLIGHT */
1369 regs.ecx = 0x0000; /* HCI_DISABLE */
1370 tosh_smm(&regs);
1371 }
1372 #endif
1373 break;
1374 case FB_BLANK_HSYNC_SUSPEND: /* hsync off */
1375 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1376 lcdflags = 0; /* LCD off */
1377 dpmsflags = NEO_GR01_SUPPRESS_HSYNC;
1378 break;
1379 case FB_BLANK_VSYNC_SUSPEND: /* vsync off */
1380 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1381 lcdflags = 0; /* LCD off */
1382 dpmsflags = NEO_GR01_SUPPRESS_VSYNC;
1383 break;
1384 case FB_BLANK_NORMAL: /* just blank screen (backlight stays on) */
1385 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1386 /*
1387 * During a blank operation with the LID shut, we might store "LCD off"
1388 * by mistake. Due to timing issues, the BIOS may switch the lights
1389 * back on, and we turn it back off once we "unblank".
1390 *
1391 * So here is an attempt to implement ">=" - if we are in the process
1392 * of unblanking, and the LCD bit is unset in the driver but set in the
1393 * register, we must keep it.
1394 */
1395 lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
1396 dpmsflags = 0x00; /* no hsync/vsync suppression */
1397 break;
1398 case FB_BLANK_UNBLANK: /* unblank */
1399 seqflags = 0; /* Enable sequencer */
1400 lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
1401 dpmsflags = 0x00; /* no hsync/vsync suppression */
1402 #ifdef CONFIG_TOSHIBA
1403 /* Do we still need this ? */
1404 /* attempt to re-enable backlight/external on toshiba */
1405 {
1406 SMMRegisters regs;
1407
1408 regs.eax = 0xff00; /* HCI_SET */
1409 regs.ebx = 0x0002; /* HCI_BACKLIGHT */
1410 regs.ecx = 0x0001; /* HCI_ENABLE */
1411 tosh_smm(&regs);
1412 }
1413 #endif
1414 break;
1415 default: /* Anything else we don't understand; return 1 to tell
1416 * fb_blank we didn't aactually do anything */
1417 return 1;
1418 }
1419
1420 neoUnlock();
1421 reg = (vga_rseq(NULL, 0x01) & ~0x20) | seqflags;
1422 vga_wseq(NULL, 0x01, reg);
1423 reg = (vga_rgfx(NULL, 0x20) & ~0x02) | lcdflags;
1424 vga_wgfx(NULL, 0x20, reg);
1425 reg = (vga_rgfx(NULL, 0x01) & ~0xF0) | 0x80 | dpmsflags;
1426 vga_wgfx(NULL, 0x01, reg);
1427 neoLock(&par->state);
1428 return 0;
1429 }
1430
1431 static void
1432 neo2200_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1433 {
1434 struct neofb_par *par = info->par;
1435 u_long dst, rop;
1436
1437 dst = rect->dx + rect->dy * info->var.xres_virtual;
1438 rop = rect->rop ? 0x060000 : 0x0c0000;
1439
1440 neo2200_wait_fifo(info, 4);
1441
1442 /* set blt control */
1443 writel(NEO_BC3_FIFO_EN |
1444 NEO_BC0_SRC_IS_FG | NEO_BC3_SKIP_MAPPING |
1445 // NEO_BC3_DST_XY_ADDR |
1446 // NEO_BC3_SRC_XY_ADDR |
1447 rop, &par->neo2200->bltCntl);
1448
1449 switch (info->var.bits_per_pixel) {
1450 case 8:
1451 writel(rect->color, &par->neo2200->fgColor);
1452 break;
1453 case 16:
1454 case 24:
1455 writel(((u32 *) (info->pseudo_palette))[rect->color],
1456 &par->neo2200->fgColor);
1457 break;
1458 }
1459
1460 writel(dst * ((info->var.bits_per_pixel + 7) >> 3),
1461 &par->neo2200->dstStart);
1462 writel((rect->height << 16) | (rect->width & 0xffff),
1463 &par->neo2200->xyExt);
1464 }
1465
1466 static void
1467 neo2200_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1468 {
1469 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
1470 struct neofb_par *par = info->par;
1471 u_long src, dst, bltCntl;
1472
1473 bltCntl = NEO_BC3_FIFO_EN | NEO_BC3_SKIP_MAPPING | 0x0C0000;
1474
1475 if ((dy > sy) || ((dy == sy) && (dx > sx))) {
1476 /* Start with the lower right corner */
1477 sy += (area->height - 1);
1478 dy += (area->height - 1);
1479 sx += (area->width - 1);
1480 dx += (area->width - 1);
1481
1482 bltCntl |= NEO_BC0_X_DEC | NEO_BC0_DST_Y_DEC | NEO_BC0_SRC_Y_DEC;
1483 }
1484
1485 src = sx * (info->var.bits_per_pixel >> 3) + sy*info->fix.line_length;
1486 dst = dx * (info->var.bits_per_pixel >> 3) + dy*info->fix.line_length;
1487
1488 neo2200_wait_fifo(info, 4);
1489
1490 /* set blt control */
1491 writel(bltCntl, &par->neo2200->bltCntl);
1492
1493 writel(src, &par->neo2200->srcStart);
1494 writel(dst, &par->neo2200->dstStart);
1495 writel((area->height << 16) | (area->width & 0xffff),
1496 &par->neo2200->xyExt);
1497 }
1498
1499 static void
1500 neo2200_imageblit(struct fb_info *info, const struct fb_image *image)
1501 {
1502 struct neofb_par *par = info->par;
1503 int s_pitch = (image->width * image->depth + 7) >> 3;
1504 int scan_align = info->pixmap.scan_align - 1;
1505 int buf_align = info->pixmap.buf_align - 1;
1506 int bltCntl_flags, d_pitch, data_len;
1507
1508 // The data is padded for the hardware
1509 d_pitch = (s_pitch + scan_align) & ~scan_align;
1510 data_len = ((d_pitch * image->height) + buf_align) & ~buf_align;
1511
1512 neo2200_sync(info);
1513
1514 if (image->depth == 1) {
1515 if (info->var.bits_per_pixel == 24 && image->width < 16) {
1516 /* FIXME. There is a bug with accelerated color-expanded
1517 * transfers in 24 bit mode if the image being transferred
1518 * is less than 16 bits wide. This is due to insufficient
1519 * padding when writing the image. We need to adjust
1520 * struct fb_pixmap. Not yet done. */
1521 return cfb_imageblit(info, image);
1522 }
1523 bltCntl_flags = NEO_BC0_SRC_MONO;
1524 } else if (image->depth == info->var.bits_per_pixel) {
1525 bltCntl_flags = 0;
1526 } else {
1527 /* We don't currently support hardware acceleration if image
1528 * depth is different from display */
1529 return cfb_imageblit(info, image);
1530 }
1531
1532 switch (info->var.bits_per_pixel) {
1533 case 8:
1534 writel(image->fg_color, &par->neo2200->fgColor);
1535 writel(image->bg_color, &par->neo2200->bgColor);
1536 break;
1537 case 16:
1538 case 24:
1539 writel(((u32 *) (info->pseudo_palette))[image->fg_color],
1540 &par->neo2200->fgColor);
1541 writel(((u32 *) (info->pseudo_palette))[image->bg_color],
1542 &par->neo2200->bgColor);
1543 break;
1544 }
1545
1546 writel(NEO_BC0_SYS_TO_VID |
1547 NEO_BC3_SKIP_MAPPING | bltCntl_flags |
1548 // NEO_BC3_DST_XY_ADDR |
1549 0x0c0000, &par->neo2200->bltCntl);
1550
1551 writel(0, &par->neo2200->srcStart);
1552 // par->neo2200->dstStart = (image->dy << 16) | (image->dx & 0xffff);
1553 writel(((image->dx & 0xffff) * (info->var.bits_per_pixel >> 3) +
1554 image->dy * info->fix.line_length), &par->neo2200->dstStart);
1555 writel((image->height << 16) | (image->width & 0xffff),
1556 &par->neo2200->xyExt);
1557
1558 memcpy_toio(par->mmio_vbase + 0x100000, image->data, data_len);
1559 }
1560
1561 static void
1562 neofb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1563 {
1564 switch (info->fix.accel) {
1565 case FB_ACCEL_NEOMAGIC_NM2200:
1566 case FB_ACCEL_NEOMAGIC_NM2230:
1567 case FB_ACCEL_NEOMAGIC_NM2360:
1568 case FB_ACCEL_NEOMAGIC_NM2380:
1569 neo2200_fillrect(info, rect);
1570 break;
1571 default:
1572 cfb_fillrect(info, rect);
1573 break;
1574 }
1575 }
1576
1577 static void
1578 neofb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1579 {
1580 switch (info->fix.accel) {
1581 case FB_ACCEL_NEOMAGIC_NM2200:
1582 case FB_ACCEL_NEOMAGIC_NM2230:
1583 case FB_ACCEL_NEOMAGIC_NM2360:
1584 case FB_ACCEL_NEOMAGIC_NM2380:
1585 neo2200_copyarea(info, area);
1586 break;
1587 default:
1588 cfb_copyarea(info, area);
1589 break;
1590 }
1591 }
1592
1593 static void
1594 neofb_imageblit(struct fb_info *info, const struct fb_image *image)
1595 {
1596 switch (info->fix.accel) {
1597 case FB_ACCEL_NEOMAGIC_NM2200:
1598 case FB_ACCEL_NEOMAGIC_NM2230:
1599 case FB_ACCEL_NEOMAGIC_NM2360:
1600 case FB_ACCEL_NEOMAGIC_NM2380:
1601 neo2200_imageblit(info, image);
1602 break;
1603 default:
1604 cfb_imageblit(info, image);
1605 break;
1606 }
1607 }
1608
1609 static int
1610 neofb_sync(struct fb_info *info)
1611 {
1612 switch (info->fix.accel) {
1613 case FB_ACCEL_NEOMAGIC_NM2200:
1614 case FB_ACCEL_NEOMAGIC_NM2230:
1615 case FB_ACCEL_NEOMAGIC_NM2360:
1616 case FB_ACCEL_NEOMAGIC_NM2380:
1617 neo2200_sync(info);
1618 break;
1619 default:
1620 break;
1621 }
1622 return 0;
1623 }
1624
1625 /*
1626 static void
1627 neofb_draw_cursor(struct fb_info *info, u8 *dst, u8 *src, unsigned int width)
1628 {
1629 //memset_io(info->sprite.addr, 0xff, 1);
1630 }
1631
1632 static int
1633 neofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1634 {
1635 struct neofb_par *par = (struct neofb_par *) info->par;
1636
1637 * Disable cursor *
1638 write_le32(NEOREG_CURSCNTL, ~NEO_CURS_ENABLE, par);
1639
1640 if (cursor->set & FB_CUR_SETPOS) {
1641 u32 x = cursor->image.dx;
1642 u32 y = cursor->image.dy;
1643
1644 info->cursor.image.dx = x;
1645 info->cursor.image.dy = y;
1646 write_le32(NEOREG_CURSX, x, par);
1647 write_le32(NEOREG_CURSY, y, par);
1648 }
1649
1650 if (cursor->set & FB_CUR_SETSIZE) {
1651 info->cursor.image.height = cursor->image.height;
1652 info->cursor.image.width = cursor->image.width;
1653 }
1654
1655 if (cursor->set & FB_CUR_SETHOT)
1656 info->cursor.hot = cursor->hot;
1657
1658 if (cursor->set & FB_CUR_SETCMAP) {
1659 if (cursor->image.depth == 1) {
1660 u32 fg = cursor->image.fg_color;
1661 u32 bg = cursor->image.bg_color;
1662
1663 info->cursor.image.fg_color = fg;
1664 info->cursor.image.bg_color = bg;
1665
1666 fg = ((fg & 0xff0000) >> 16) | ((fg & 0xff) << 16) | (fg & 0xff00);
1667 bg = ((bg & 0xff0000) >> 16) | ((bg & 0xff) << 16) | (bg & 0xff00);
1668 write_le32(NEOREG_CURSFGCOLOR, fg, par);
1669 write_le32(NEOREG_CURSBGCOLOR, bg, par);
1670 }
1671 }
1672
1673 if (cursor->set & FB_CUR_SETSHAPE)
1674 fb_load_cursor_image(info);
1675
1676 if (info->cursor.enable)
1677 write_le32(NEOREG_CURSCNTL, NEO_CURS_ENABLE, par);
1678 return 0;
1679 }
1680 */
1681
1682 static struct fb_ops neofb_ops = {
1683 .owner = THIS_MODULE,
1684 .fb_open = neofb_open,
1685 .fb_release = neofb_release,
1686 .fb_check_var = neofb_check_var,
1687 .fb_set_par = neofb_set_par,
1688 .fb_setcolreg = neofb_setcolreg,
1689 .fb_pan_display = neofb_pan_display,
1690 .fb_blank = neofb_blank,
1691 .fb_sync = neofb_sync,
1692 .fb_fillrect = neofb_fillrect,
1693 .fb_copyarea = neofb_copyarea,
1694 .fb_imageblit = neofb_imageblit,
1695 };
1696
1697 /* --------------------------------------------------------------------- */
1698
1699 static struct fb_videomode __devinitdata mode800x480 = {
1700 .xres = 800,
1701 .yres = 480,
1702 .pixclock = 25000,
1703 .left_margin = 88,
1704 .right_margin = 40,
1705 .upper_margin = 23,
1706 .lower_margin = 1,
1707 .hsync_len = 128,
1708 .vsync_len = 4,
1709 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1710 .vmode = FB_VMODE_NONINTERLACED
1711 };
1712
1713 static int __devinit neo_map_mmio(struct fb_info *info,
1714 struct pci_dev *dev)
1715 {
1716 struct neofb_par *par = info->par;
1717
1718 DBG("neo_map_mmio");
1719
1720 switch (info->fix.accel) {
1721 case FB_ACCEL_NEOMAGIC_NM2070:
1722 info->fix.mmio_start = pci_resource_start(dev, 0)+
1723 0x100000;
1724 break;
1725 case FB_ACCEL_NEOMAGIC_NM2090:
1726 case FB_ACCEL_NEOMAGIC_NM2093:
1727 info->fix.mmio_start = pci_resource_start(dev, 0)+
1728 0x200000;
1729 break;
1730 case FB_ACCEL_NEOMAGIC_NM2160:
1731 case FB_ACCEL_NEOMAGIC_NM2097:
1732 case FB_ACCEL_NEOMAGIC_NM2200:
1733 case FB_ACCEL_NEOMAGIC_NM2230:
1734 case FB_ACCEL_NEOMAGIC_NM2360:
1735 case FB_ACCEL_NEOMAGIC_NM2380:
1736 info->fix.mmio_start = pci_resource_start(dev, 1);
1737 break;
1738 default:
1739 info->fix.mmio_start = pci_resource_start(dev, 0);
1740 }
1741 info->fix.mmio_len = MMIO_SIZE;
1742
1743 if (!request_mem_region
1744 (info->fix.mmio_start, MMIO_SIZE, "memory mapped I/O")) {
1745 printk("neofb: memory mapped IO in use\n");
1746 return -EBUSY;
1747 }
1748
1749 par->mmio_vbase = ioremap(info->fix.mmio_start, MMIO_SIZE);
1750 if (!par->mmio_vbase) {
1751 printk("neofb: unable to map memory mapped IO\n");
1752 release_mem_region(info->fix.mmio_start,
1753 info->fix.mmio_len);
1754 return -ENOMEM;
1755 } else
1756 printk(KERN_INFO "neofb: mapped io at %p\n",
1757 par->mmio_vbase);
1758 return 0;
1759 }
1760
1761 static void neo_unmap_mmio(struct fb_info *info)
1762 {
1763 struct neofb_par *par = info->par;
1764
1765 DBG("neo_unmap_mmio");
1766
1767 iounmap(par->mmio_vbase);
1768 par->mmio_vbase = NULL;
1769
1770 release_mem_region(info->fix.mmio_start,
1771 info->fix.mmio_len);
1772 }
1773
1774 static int __devinit neo_map_video(struct fb_info *info,
1775 struct pci_dev *dev, int video_len)
1776 {
1777 //unsigned long addr;
1778
1779 DBG("neo_map_video");
1780
1781 info->fix.smem_start = pci_resource_start(dev, 0);
1782 info->fix.smem_len = video_len;
1783
1784 if (!request_mem_region(info->fix.smem_start, info->fix.smem_len,
1785 "frame buffer")) {
1786 printk("neofb: frame buffer in use\n");
1787 return -EBUSY;
1788 }
1789
1790 info->screen_base =
1791 ioremap(info->fix.smem_start, info->fix.smem_len);
1792 if (!info->screen_base) {
1793 printk("neofb: unable to map screen memory\n");
1794 release_mem_region(info->fix.smem_start,
1795 info->fix.smem_len);
1796 return -ENOMEM;
1797 } else
1798 printk(KERN_INFO "neofb: mapped framebuffer at %p\n",
1799 info->screen_base);
1800
1801 #ifdef CONFIG_MTRR
1802 ((struct neofb_par *)(info->par))->mtrr =
1803 mtrr_add(info->fix.smem_start, pci_resource_len(dev, 0),
1804 MTRR_TYPE_WRCOMB, 1);
1805 #endif
1806
1807 /* Clear framebuffer, it's all white in memory after boot */
1808 memset_io(info->screen_base, 0, info->fix.smem_len);
1809
1810 /* Allocate Cursor drawing pad.
1811 info->fix.smem_len -= PAGE_SIZE;
1812 addr = info->fix.smem_start + info->fix.smem_len;
1813 write_le32(NEOREG_CURSMEMPOS, ((0x000f & (addr >> 10)) << 8) |
1814 ((0x0ff0 & (addr >> 10)) >> 4), par);
1815 addr = (unsigned long) info->screen_base + info->fix.smem_len;
1816 info->sprite.addr = (u8 *) addr; */
1817 return 0;
1818 }
1819
1820 static void neo_unmap_video(struct fb_info *info)
1821 {
1822 DBG("neo_unmap_video");
1823
1824 #ifdef CONFIG_MTRR
1825 {
1826 struct neofb_par *par = info->par;
1827
1828 mtrr_del(par->mtrr, info->fix.smem_start,
1829 info->fix.smem_len);
1830 }
1831 #endif
1832 iounmap(info->screen_base);
1833 info->screen_base = NULL;
1834
1835 release_mem_region(info->fix.smem_start,
1836 info->fix.smem_len);
1837 }
1838
1839 static int __devinit neo_scan_monitor(struct fb_info *info)
1840 {
1841 struct neofb_par *par = info->par;
1842 unsigned char type, display;
1843 int w;
1844
1845 // Eventually we will have i2c support.
1846 info->monspecs.modedb = kmalloc(sizeof(struct fb_videomode), GFP_KERNEL);
1847 if (!info->monspecs.modedb)
1848 return -ENOMEM;
1849 info->monspecs.modedb_len = 1;
1850
1851 /* Determine the panel type */
1852 vga_wgfx(NULL, 0x09, 0x26);
1853 type = vga_rgfx(NULL, 0x21);
1854 display = vga_rgfx(NULL, 0x20);
1855 if (!par->internal_display && !par->external_display) {
1856 par->internal_display = display & 2 || !(display & 3) ? 1 : 0;
1857 par->external_display = display & 1;
1858 printk (KERN_INFO "Autodetected %s display\n",
1859 par->internal_display && par->external_display ? "simultaneous" :
1860 par->internal_display ? "internal" : "external");
1861 }
1862
1863 /* Determine panel width -- used in NeoValidMode. */
1864 w = vga_rgfx(NULL, 0x20);
1865 vga_wgfx(NULL, 0x09, 0x00);
1866 switch ((w & 0x18) >> 3) {
1867 case 0x00:
1868 // 640x480@60
1869 par->NeoPanelWidth = 640;
1870 par->NeoPanelHeight = 480;
1871 memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
1872 break;
1873 case 0x01:
1874 par->NeoPanelWidth = 800;
1875 if (par->libretto) {
1876 par->NeoPanelHeight = 480;
1877 memcpy(info->monspecs.modedb, &mode800x480, sizeof(struct fb_videomode));
1878 } else {
1879 // 800x600@60
1880 par->NeoPanelHeight = 600;
1881 memcpy(info->monspecs.modedb, &vesa_modes[8], sizeof(struct fb_videomode));
1882 }
1883 break;
1884 case 0x02:
1885 // 1024x768@60
1886 par->NeoPanelWidth = 1024;
1887 par->NeoPanelHeight = 768;
1888 memcpy(info->monspecs.modedb, &vesa_modes[13], sizeof(struct fb_videomode));
1889 break;
1890 case 0x03:
1891 /* 1280x1024@60 panel support needs to be added */
1892 #ifdef NOT_DONE
1893 par->NeoPanelWidth = 1280;
1894 par->NeoPanelHeight = 1024;
1895 memcpy(info->monspecs.modedb, &vesa_modes[20], sizeof(struct fb_videomode));
1896 break;
1897 #else
1898 printk(KERN_ERR
1899 "neofb: Only 640x480, 800x600/480 and 1024x768 panels are currently supported\n");
1900 return -1;
1901 #endif
1902 default:
1903 // 640x480@60
1904 par->NeoPanelWidth = 640;
1905 par->NeoPanelHeight = 480;
1906 memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
1907 break;
1908 }
1909
1910 printk(KERN_INFO "Panel is a %dx%d %s %s display\n",
1911 par->NeoPanelWidth,
1912 par->NeoPanelHeight,
1913 (type & 0x02) ? "color" : "monochrome",
1914 (type & 0x10) ? "TFT" : "dual scan");
1915 return 0;
1916 }
1917
1918 static int __devinit neo_init_hw(struct fb_info *info)
1919 {
1920 struct neofb_par *par = info->par;
1921 int videoRam = 896;
1922 int maxClock = 65000;
1923 int CursorMem = 1024;
1924 int CursorOff = 0x100;
1925 int linearSize = 1024;
1926 int maxWidth = 1024;
1927 int maxHeight = 1024;
1928
1929 DBG("neo_init_hw");
1930
1931 neoUnlock();
1932
1933 #if 0
1934 printk(KERN_DEBUG "--- Neo extended register dump ---\n");
1935 for (int w = 0; w < 0x85; w++)
1936 printk(KERN_DEBUG "CR %p: %p\n", (void *) w,
1937 (void *) vga_rcrt(NULL, w);
1938 for (int w = 0; w < 0xC7; w++)
1939 printk(KERN_DEBUG "GR %p: %p\n", (void *) w,
1940 (void *) vga_rgfx(NULL, w));
1941 #endif
1942 switch (info->fix.accel) {
1943 case FB_ACCEL_NEOMAGIC_NM2070:
1944 videoRam = 896;
1945 maxClock = 65000;
1946 CursorMem = 2048;
1947 CursorOff = 0x100;
1948 linearSize = 1024;
1949 maxWidth = 1024;
1950 maxHeight = 1024;
1951 break;
1952 case FB_ACCEL_NEOMAGIC_NM2090:
1953 case FB_ACCEL_NEOMAGIC_NM2093:
1954 videoRam = 1152;
1955 maxClock = 80000;
1956 CursorMem = 2048;
1957 CursorOff = 0x100;
1958 linearSize = 2048;
1959 maxWidth = 1024;
1960 maxHeight = 1024;
1961 break;
1962 case FB_ACCEL_NEOMAGIC_NM2097:
1963 videoRam = 1152;
1964 maxClock = 80000;
1965 CursorMem = 1024;
1966 CursorOff = 0x100;
1967 linearSize = 2048;
1968 maxWidth = 1024;
1969 maxHeight = 1024;
1970 break;
1971 case FB_ACCEL_NEOMAGIC_NM2160:
1972 videoRam = 2048;
1973 maxClock = 90000;
1974 CursorMem = 1024;
1975 CursorOff = 0x100;
1976 linearSize = 2048;
1977 maxWidth = 1024;
1978 maxHeight = 1024;
1979 break;
1980 case FB_ACCEL_NEOMAGIC_NM2200:
1981 videoRam = 2560;
1982 maxClock = 110000;
1983 CursorMem = 1024;
1984 CursorOff = 0x1000;
1985 linearSize = 4096;
1986 maxWidth = 1280;
1987 maxHeight = 1024; /* ???? */
1988
1989 par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
1990 break;
1991 case FB_ACCEL_NEOMAGIC_NM2230:
1992 videoRam = 3008;
1993 maxClock = 110000;
1994 CursorMem = 1024;
1995 CursorOff = 0x1000;
1996 linearSize = 4096;
1997 maxWidth = 1280;
1998 maxHeight = 1024; /* ???? */
1999
2000 par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
2001 break;
2002 case FB_ACCEL_NEOMAGIC_NM2360:
2003 videoRam = 4096;
2004 maxClock = 110000;
2005 CursorMem = 1024;
2006 CursorOff = 0x1000;
2007 linearSize = 4096;
2008 maxWidth = 1280;
2009 maxHeight = 1024; /* ???? */
2010
2011 par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
2012 break;
2013 case FB_ACCEL_NEOMAGIC_NM2380:
2014 videoRam = 6144;
2015 maxClock = 110000;
2016 CursorMem = 1024;
2017 CursorOff = 0x1000;
2018 linearSize = 8192;
2019 maxWidth = 1280;
2020 maxHeight = 1024; /* ???? */
2021
2022 par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
2023 break;
2024 }
2025 /*
2026 info->sprite.size = CursorMem;
2027 info->sprite.scan_align = 1;
2028 info->sprite.buf_align = 1;
2029 info->sprite.flags = FB_PIXMAP_IO;
2030 info->sprite.outbuf = neofb_draw_cursor;
2031 */
2032 par->maxClock = maxClock;
2033 par->cursorOff = CursorOff;
2034 return ((videoRam * 1024));
2035 }
2036
2037
2038 static struct fb_info *__devinit neo_alloc_fb_info(struct pci_dev *dev, const struct
2039 pci_device_id *id)
2040 {
2041 struct fb_info *info;
2042 struct neofb_par *par;
2043
2044 info = framebuffer_alloc(sizeof(struct neofb_par), &dev->dev);
2045
2046 if (!info)
2047 return NULL;
2048
2049 par = info->par;
2050
2051 info->fix.accel = id->driver_data;
2052
2053 par->pci_burst = !nopciburst;
2054 par->lcd_stretch = !nostretch;
2055 par->libretto = libretto;
2056
2057 par->internal_display = internal;
2058 par->external_display = external;
2059 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
2060
2061 switch (info->fix.accel) {
2062 case FB_ACCEL_NEOMAGIC_NM2070:
2063 sprintf(info->fix.id, "MagicGraph 128");
2064 break;
2065 case FB_ACCEL_NEOMAGIC_NM2090:
2066 sprintf(info->fix.id, "MagicGraph 128V");
2067 break;
2068 case FB_ACCEL_NEOMAGIC_NM2093:
2069 sprintf(info->fix.id, "MagicGraph 128ZV");
2070 break;
2071 case FB_ACCEL_NEOMAGIC_NM2097:
2072 sprintf(info->fix.id, "MagicGraph 128ZV+");
2073 break;
2074 case FB_ACCEL_NEOMAGIC_NM2160:
2075 sprintf(info->fix.id, "MagicGraph 128XD");
2076 break;
2077 case FB_ACCEL_NEOMAGIC_NM2200:
2078 sprintf(info->fix.id, "MagicGraph 256AV");
2079 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2080 FBINFO_HWACCEL_COPYAREA |
2081 FBINFO_HWACCEL_FILLRECT;
2082 break;
2083 case FB_ACCEL_NEOMAGIC_NM2230:
2084 sprintf(info->fix.id, "MagicGraph 256AV+");
2085 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2086 FBINFO_HWACCEL_COPYAREA |
2087 FBINFO_HWACCEL_FILLRECT;
2088 break;
2089 case FB_ACCEL_NEOMAGIC_NM2360:
2090 sprintf(info->fix.id, "MagicGraph 256ZX");
2091 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2092 FBINFO_HWACCEL_COPYAREA |
2093 FBINFO_HWACCEL_FILLRECT;
2094 break;
2095 case FB_ACCEL_NEOMAGIC_NM2380:
2096 sprintf(info->fix.id, "MagicGraph 256XL+");
2097 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2098 FBINFO_HWACCEL_COPYAREA |
2099 FBINFO_HWACCEL_FILLRECT;
2100 break;
2101 }
2102
2103 info->fix.type = FB_TYPE_PACKED_PIXELS;
2104 info->fix.type_aux = 0;
2105 info->fix.xpanstep = 0;
2106 info->fix.ypanstep = 4;
2107 info->fix.ywrapstep = 0;
2108 info->fix.accel = id->driver_data;
2109
2110 info->fbops = &neofb_ops;
2111 info->pseudo_palette = par->palette;
2112 return info;
2113 }
2114
2115 static void neo_free_fb_info(struct fb_info *info)
2116 {
2117 if (info) {
2118 /*
2119 * Free the colourmap
2120 */
2121 fb_dealloc_cmap(&info->cmap);
2122 framebuffer_release(info);
2123 }
2124 }
2125
2126 /* --------------------------------------------------------------------- */
2127
2128 static int __devinit neofb_probe(struct pci_dev *dev,
2129 const struct pci_device_id *id)
2130 {
2131 struct fb_info *info;
2132 u_int h_sync, v_sync;
2133 int video_len, err;
2134
2135 DBG("neofb_probe");
2136
2137 err = pci_enable_device(dev);
2138 if (err)
2139 return err;
2140
2141 err = -ENOMEM;
2142 info = neo_alloc_fb_info(dev, id);
2143 if (!info)
2144 return err;
2145
2146 err = neo_map_mmio(info, dev);
2147 if (err)
2148 goto err_map_mmio;
2149
2150 err = neo_scan_monitor(info);
2151 if (err)
2152 goto err_scan_monitor;
2153
2154 video_len = neo_init_hw(info);
2155 if (video_len < 0) {
2156 err = video_len;
2157 goto err_init_hw;
2158 }
2159
2160 err = neo_map_video(info, dev, video_len);
2161 if (err)
2162 goto err_init_hw;
2163
2164 if (!fb_find_mode(&info->var, info, mode_option, NULL, 0,
2165 info->monspecs.modedb, 16)) {
2166 printk(KERN_ERR "neofb: Unable to find usable video mode.\n");
2167 goto err_map_video;
2168 }
2169
2170 /*
2171 * Calculate the hsync and vsync frequencies. Note that
2172 * we split the 1e12 constant up so that we can preserve
2173 * the precision and fit the results into 32-bit registers.
2174 * (1953125000 * 512 = 1e12)
2175 */
2176 h_sync = 1953125000 / info->var.pixclock;
2177 h_sync =
2178 h_sync * 512 / (info->var.xres + info->var.left_margin +
2179 info->var.right_margin + info->var.hsync_len);
2180 v_sync =
2181 h_sync / (info->var.yres + info->var.upper_margin +
2182 info->var.lower_margin + info->var.vsync_len);
2183
2184 printk(KERN_INFO "neofb v" NEOFB_VERSION
2185 ": %dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2186 info->fix.smem_len >> 10, info->var.xres,
2187 info->var.yres, h_sync / 1000, h_sync % 1000, v_sync);
2188
2189 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
2190 goto err_map_video;
2191
2192 err = register_framebuffer(info);
2193 if (err < 0)
2194 goto err_reg_fb;
2195
2196 printk(KERN_INFO "fb%d: %s frame buffer device\n",
2197 info->node, info->fix.id);
2198
2199 /*
2200 * Our driver data
2201 */
2202 pci_set_drvdata(dev, info);
2203 return 0;
2204
2205 err_reg_fb:
2206 fb_dealloc_cmap(&info->cmap);
2207 err_map_video:
2208 neo_unmap_video(info);
2209 err_init_hw:
2210 fb_destroy_modedb(info->monspecs.modedb);
2211 err_scan_monitor:
2212 neo_unmap_mmio(info);
2213 err_map_mmio:
2214 neo_free_fb_info(info);
2215 return err;
2216 }
2217
2218 static void __devexit neofb_remove(struct pci_dev *dev)
2219 {
2220 struct fb_info *info = pci_get_drvdata(dev);
2221
2222 DBG("neofb_remove");
2223
2224 if (info) {
2225 /*
2226 * If unregister_framebuffer fails, then
2227 * we will be leaving hooks that could cause
2228 * oopsen laying around.
2229 */
2230 if (unregister_framebuffer(info))
2231 printk(KERN_WARNING
2232 "neofb: danger danger! Oopsen imminent!\n");
2233
2234 neo_unmap_video(info);
2235 fb_destroy_modedb(info->monspecs.modedb);
2236 neo_unmap_mmio(info);
2237 neo_free_fb_info(info);
2238
2239 /*
2240 * Ensure that the driver data is no longer
2241 * valid.
2242 */
2243 pci_set_drvdata(dev, NULL);
2244 }
2245 }
2246
2247 static struct pci_device_id neofb_devices[] = {
2248 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2070,
2249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2070},
2250
2251 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2090,
2252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2090},
2253
2254 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2093,
2255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2093},
2256
2257 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2097,
2258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2097},
2259
2260 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2160,
2261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2160},
2262
2263 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2200,
2264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2200},
2265
2266 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2230,
2267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2230},
2268
2269 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2360,
2270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2360},
2271
2272 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2380,
2273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2380},
2274
2275 {0, 0, 0, 0, 0, 0, 0}
2276 };
2277
2278 MODULE_DEVICE_TABLE(pci, neofb_devices);
2279
2280 static struct pci_driver neofb_driver = {
2281 .name = "neofb",
2282 .id_table = neofb_devices,
2283 .probe = neofb_probe,
2284 .remove = __devexit_p(neofb_remove)
2285 };
2286
2287 /* ************************* init in-kernel code ************************** */
2288
2289 #ifndef MODULE
2290 static int __init neofb_setup(char *options)
2291 {
2292 char *this_opt;
2293
2294 DBG("neofb_setup");
2295
2296 if (!options || !*options)
2297 return 0;
2298
2299 while ((this_opt = strsep(&options, ",")) != NULL) {
2300 if (!*this_opt)
2301 continue;
2302
2303 if (!strncmp(this_opt, "internal", 8))
2304 internal = 1;
2305 else if (!strncmp(this_opt, "external", 8))
2306 external = 1;
2307 else if (!strncmp(this_opt, "nostretch", 9))
2308 nostretch = 1;
2309 else if (!strncmp(this_opt, "nopciburst", 10))
2310 nopciburst = 1;
2311 else if (!strncmp(this_opt, "libretto", 8))
2312 libretto = 1;
2313 else
2314 mode_option = this_opt;
2315 }
2316 return 0;
2317 }
2318 #endif /* MODULE */
2319
2320 static int __init neofb_init(void)
2321 {
2322 #ifndef MODULE
2323 char *option = NULL;
2324
2325 if (fb_get_options("neofb", &option))
2326 return -ENODEV;
2327 neofb_setup(option);
2328 #endif
2329 return pci_register_driver(&neofb_driver);
2330 }
2331
2332 module_init(neofb_init);
2333
2334 #ifdef MODULE
2335 static void __exit neofb_exit(void)
2336 {
2337 pci_unregister_driver(&neofb_driver);
2338 }
2339
2340 module_exit(neofb_exit);
2341 #endif /* MODULE */
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