2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
42 #define FORCEDETH_VERSION "0.61"
43 #define DRV_NAME "forcedeth"
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
68 #define dprintk printk
70 #define dprintk(x...) do { } while (0)
73 #define TX_WORK_PER_LOOP 64
74 #define RX_WORK_PER_LOOP 64
80 #define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI 0x00040 /* device supports MSI */
87 #define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */
91 #define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */
92 #define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */
93 #define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */
94 #define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */
95 #define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */
96 #define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
97 #define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
98 #define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */
99 #define DEV_HAS_GEAR_MODE 0x80000 /* device supports gear mode */
102 NvRegIrqStatus
= 0x000,
103 #define NVREG_IRQSTAT_MIIEVENT 0x040
104 #define NVREG_IRQSTAT_MASK 0x81ff
105 NvRegIrqMask
= 0x004,
106 #define NVREG_IRQ_RX_ERROR 0x0001
107 #define NVREG_IRQ_RX 0x0002
108 #define NVREG_IRQ_RX_NOBUF 0x0004
109 #define NVREG_IRQ_TX_ERR 0x0008
110 #define NVREG_IRQ_TX_OK 0x0010
111 #define NVREG_IRQ_TIMER 0x0020
112 #define NVREG_IRQ_LINK 0x0040
113 #define NVREG_IRQ_RX_FORCED 0x0080
114 #define NVREG_IRQ_TX_FORCED 0x0100
115 #define NVREG_IRQ_RECOVER_ERROR 0x8000
116 #define NVREG_IRQMASK_THROUGHPUT 0x00df
117 #define NVREG_IRQMASK_CPU 0x0060
118 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
119 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
120 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
122 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
123 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
124 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
126 NvRegUnknownSetupReg6
= 0x008,
127 #define NVREG_UNKSETUP6_VAL 3
130 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
131 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
133 NvRegPollingInterval
= 0x00c,
134 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
135 #define NVREG_POLL_DEFAULT_CPU 13
136 NvRegMSIMap0
= 0x020,
137 NvRegMSIMap1
= 0x024,
138 NvRegMSIIrqMask
= 0x030,
139 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
141 #define NVREG_MISC1_PAUSE_TX 0x01
142 #define NVREG_MISC1_HD 0x02
143 #define NVREG_MISC1_FORCE 0x3b0f3c
145 NvRegMacReset
= 0x34,
146 #define NVREG_MAC_RESET_ASSERT 0x0F3
147 NvRegTransmitterControl
= 0x084,
148 #define NVREG_XMITCTL_START 0x01
149 #define NVREG_XMITCTL_MGMT_ST 0x40000000
150 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
151 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
152 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
153 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
154 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
155 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
156 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
157 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
158 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
159 NvRegTransmitterStatus
= 0x088,
160 #define NVREG_XMITSTAT_BUSY 0x01
162 NvRegPacketFilterFlags
= 0x8c,
163 #define NVREG_PFF_PAUSE_RX 0x08
164 #define NVREG_PFF_ALWAYS 0x7F0000
165 #define NVREG_PFF_PROMISC 0x80
166 #define NVREG_PFF_MYADDR 0x20
167 #define NVREG_PFF_LOOPBACK 0x10
169 NvRegOffloadConfig
= 0x90,
170 #define NVREG_OFFLOAD_HOMEPHY 0x601
171 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
172 NvRegReceiverControl
= 0x094,
173 #define NVREG_RCVCTL_START 0x01
174 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
175 NvRegReceiverStatus
= 0x98,
176 #define NVREG_RCVSTAT_BUSY 0x01
178 NvRegSlotTime
= 0x9c,
179 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
180 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
181 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
182 #define NVREG_SLOTTIME_HALF 0x0000ff00
183 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
184 #define NVREG_SLOTTIME_MASK 0x000000ff
186 NvRegTxDeferral
= 0xA0,
187 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
188 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
189 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
190 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
192 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
193 NvRegRxDeferral
= 0xA4,
194 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
195 NvRegMacAddrA
= 0xA8,
196 NvRegMacAddrB
= 0xAC,
197 NvRegMulticastAddrA
= 0xB0,
198 #define NVREG_MCASTADDRA_FORCE 0x01
199 NvRegMulticastAddrB
= 0xB4,
200 NvRegMulticastMaskA
= 0xB8,
201 #define NVREG_MCASTMASKA_NONE 0xffffffff
202 NvRegMulticastMaskB
= 0xBC,
203 #define NVREG_MCASTMASKB_NONE 0xffff
205 NvRegPhyInterface
= 0xC0,
206 #define PHY_RGMII 0x10000000
207 NvRegBackOffControl
= 0xC4,
208 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
209 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
210 #define NVREG_BKOFFCTRL_SELECT 24
211 #define NVREG_BKOFFCTRL_GEAR 12
213 NvRegTxRingPhysAddr
= 0x100,
214 NvRegRxRingPhysAddr
= 0x104,
215 NvRegRingSizes
= 0x108,
216 #define NVREG_RINGSZ_TXSHIFT 0
217 #define NVREG_RINGSZ_RXSHIFT 16
218 NvRegTransmitPoll
= 0x10c,
219 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
220 NvRegLinkSpeed
= 0x110,
221 #define NVREG_LINKSPEED_FORCE 0x10000
222 #define NVREG_LINKSPEED_10 1000
223 #define NVREG_LINKSPEED_100 100
224 #define NVREG_LINKSPEED_1000 50
225 #define NVREG_LINKSPEED_MASK (0xFFF)
226 NvRegUnknownSetupReg5
= 0x130,
227 #define NVREG_UNKSETUP5_BIT31 (1<<31)
228 NvRegTxWatermark
= 0x13c,
229 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
230 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
231 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
232 NvRegTxRxControl
= 0x144,
233 #define NVREG_TXRXCTL_KICK 0x0001
234 #define NVREG_TXRXCTL_BIT1 0x0002
235 #define NVREG_TXRXCTL_BIT2 0x0004
236 #define NVREG_TXRXCTL_IDLE 0x0008
237 #define NVREG_TXRXCTL_RESET 0x0010
238 #define NVREG_TXRXCTL_RXCHECK 0x0400
239 #define NVREG_TXRXCTL_DESC_1 0
240 #define NVREG_TXRXCTL_DESC_2 0x002100
241 #define NVREG_TXRXCTL_DESC_3 0xc02200
242 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
243 #define NVREG_TXRXCTL_VLANINS 0x00080
244 NvRegTxRingPhysAddrHigh
= 0x148,
245 NvRegRxRingPhysAddrHigh
= 0x14C,
246 NvRegTxPauseFrame
= 0x170,
247 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
248 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
249 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
250 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
251 NvRegMIIStatus
= 0x180,
252 #define NVREG_MIISTAT_ERROR 0x0001
253 #define NVREG_MIISTAT_LINKCHANGE 0x0008
254 #define NVREG_MIISTAT_MASK_RW 0x0007
255 #define NVREG_MIISTAT_MASK_ALL 0x000f
256 NvRegMIIMask
= 0x184,
257 #define NVREG_MII_LINKCHANGE 0x0008
259 NvRegAdapterControl
= 0x188,
260 #define NVREG_ADAPTCTL_START 0x02
261 #define NVREG_ADAPTCTL_LINKUP 0x04
262 #define NVREG_ADAPTCTL_PHYVALID 0x40000
263 #define NVREG_ADAPTCTL_RUNNING 0x100000
264 #define NVREG_ADAPTCTL_PHYSHIFT 24
265 NvRegMIISpeed
= 0x18c,
266 #define NVREG_MIISPEED_BIT8 (1<<8)
267 #define NVREG_MIIDELAY 5
268 NvRegMIIControl
= 0x190,
269 #define NVREG_MIICTL_INUSE 0x08000
270 #define NVREG_MIICTL_WRITE 0x00400
271 #define NVREG_MIICTL_ADDRSHIFT 5
272 NvRegMIIData
= 0x194,
273 NvRegWakeUpFlags
= 0x200,
274 #define NVREG_WAKEUPFLAGS_VAL 0x7770
275 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
276 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
277 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
278 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
279 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
280 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
281 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
282 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
283 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
284 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
286 NvRegPatternCRC
= 0x204,
287 NvRegPatternMask
= 0x208,
288 NvRegPowerCap
= 0x268,
289 #define NVREG_POWERCAP_D3SUPP (1<<30)
290 #define NVREG_POWERCAP_D2SUPP (1<<26)
291 #define NVREG_POWERCAP_D1SUPP (1<<25)
292 NvRegPowerState
= 0x26c,
293 #define NVREG_POWERSTATE_POWEREDUP 0x8000
294 #define NVREG_POWERSTATE_VALID 0x0100
295 #define NVREG_POWERSTATE_MASK 0x0003
296 #define NVREG_POWERSTATE_D0 0x0000
297 #define NVREG_POWERSTATE_D1 0x0001
298 #define NVREG_POWERSTATE_D2 0x0002
299 #define NVREG_POWERSTATE_D3 0x0003
301 NvRegTxZeroReXmt
= 0x284,
302 NvRegTxOneReXmt
= 0x288,
303 NvRegTxManyReXmt
= 0x28c,
304 NvRegTxLateCol
= 0x290,
305 NvRegTxUnderflow
= 0x294,
306 NvRegTxLossCarrier
= 0x298,
307 NvRegTxExcessDef
= 0x29c,
308 NvRegTxRetryErr
= 0x2a0,
309 NvRegRxFrameErr
= 0x2a4,
310 NvRegRxExtraByte
= 0x2a8,
311 NvRegRxLateCol
= 0x2ac,
313 NvRegRxFrameTooLong
= 0x2b4,
314 NvRegRxOverflow
= 0x2b8,
315 NvRegRxFCSErr
= 0x2bc,
316 NvRegRxFrameAlignErr
= 0x2c0,
317 NvRegRxLenErr
= 0x2c4,
318 NvRegRxUnicast
= 0x2c8,
319 NvRegRxMulticast
= 0x2cc,
320 NvRegRxBroadcast
= 0x2d0,
322 NvRegTxFrame
= 0x2d8,
324 NvRegTxPause
= 0x2e0,
325 NvRegRxPause
= 0x2e4,
326 NvRegRxDropFrame
= 0x2e8,
327 NvRegVlanControl
= 0x300,
328 #define NVREG_VLANCONTROL_ENABLE 0x2000
329 NvRegMSIXMap0
= 0x3e0,
330 NvRegMSIXMap1
= 0x3e4,
331 NvRegMSIXIrqStatus
= 0x3f0,
333 NvRegPowerState2
= 0x600,
334 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
335 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
338 /* Big endian: should work, but is untested */
344 struct ring_desc_ex
{
352 struct ring_desc
* orig
;
353 struct ring_desc_ex
* ex
;
356 #define FLAG_MASK_V1 0xffff0000
357 #define FLAG_MASK_V2 0xffffc000
358 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
359 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
361 #define NV_TX_LASTPACKET (1<<16)
362 #define NV_TX_RETRYERROR (1<<19)
363 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
364 #define NV_TX_FORCED_INTERRUPT (1<<24)
365 #define NV_TX_DEFERRED (1<<26)
366 #define NV_TX_CARRIERLOST (1<<27)
367 #define NV_TX_LATECOLLISION (1<<28)
368 #define NV_TX_UNDERFLOW (1<<29)
369 #define NV_TX_ERROR (1<<30)
370 #define NV_TX_VALID (1<<31)
372 #define NV_TX2_LASTPACKET (1<<29)
373 #define NV_TX2_RETRYERROR (1<<18)
374 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
375 #define NV_TX2_FORCED_INTERRUPT (1<<30)
376 #define NV_TX2_DEFERRED (1<<25)
377 #define NV_TX2_CARRIERLOST (1<<26)
378 #define NV_TX2_LATECOLLISION (1<<27)
379 #define NV_TX2_UNDERFLOW (1<<28)
380 /* error and valid are the same for both */
381 #define NV_TX2_ERROR (1<<30)
382 #define NV_TX2_VALID (1<<31)
383 #define NV_TX2_TSO (1<<28)
384 #define NV_TX2_TSO_SHIFT 14
385 #define NV_TX2_TSO_MAX_SHIFT 14
386 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
387 #define NV_TX2_CHECKSUM_L3 (1<<27)
388 #define NV_TX2_CHECKSUM_L4 (1<<26)
390 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
392 #define NV_RX_DESCRIPTORVALID (1<<16)
393 #define NV_RX_MISSEDFRAME (1<<17)
394 #define NV_RX_SUBSTRACT1 (1<<18)
395 #define NV_RX_ERROR1 (1<<23)
396 #define NV_RX_ERROR2 (1<<24)
397 #define NV_RX_ERROR3 (1<<25)
398 #define NV_RX_ERROR4 (1<<26)
399 #define NV_RX_CRCERR (1<<27)
400 #define NV_RX_OVERFLOW (1<<28)
401 #define NV_RX_FRAMINGERR (1<<29)
402 #define NV_RX_ERROR (1<<30)
403 #define NV_RX_AVAIL (1<<31)
405 #define NV_RX2_CHECKSUMMASK (0x1C000000)
406 #define NV_RX2_CHECKSUM_IP (0x10000000)
407 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
408 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
409 #define NV_RX2_DESCRIPTORVALID (1<<29)
410 #define NV_RX2_SUBSTRACT1 (1<<25)
411 #define NV_RX2_ERROR1 (1<<18)
412 #define NV_RX2_ERROR2 (1<<19)
413 #define NV_RX2_ERROR3 (1<<20)
414 #define NV_RX2_ERROR4 (1<<21)
415 #define NV_RX2_CRCERR (1<<22)
416 #define NV_RX2_OVERFLOW (1<<23)
417 #define NV_RX2_FRAMINGERR (1<<24)
418 /* error and avail are the same for both */
419 #define NV_RX2_ERROR (1<<30)
420 #define NV_RX2_AVAIL (1<<31)
422 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
423 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
425 /* Miscelaneous hardware related defines: */
426 #define NV_PCI_REGSZ_VER1 0x270
427 #define NV_PCI_REGSZ_VER2 0x2d4
428 #define NV_PCI_REGSZ_VER3 0x604
430 /* various timeout delays: all in usec */
431 #define NV_TXRX_RESET_DELAY 4
432 #define NV_TXSTOP_DELAY1 10
433 #define NV_TXSTOP_DELAY1MAX 500000
434 #define NV_TXSTOP_DELAY2 100
435 #define NV_RXSTOP_DELAY1 10
436 #define NV_RXSTOP_DELAY1MAX 500000
437 #define NV_RXSTOP_DELAY2 100
438 #define NV_SETUP5_DELAY 5
439 #define NV_SETUP5_DELAYMAX 50000
440 #define NV_POWERUP_DELAY 5
441 #define NV_POWERUP_DELAYMAX 5000
442 #define NV_MIIBUSY_DELAY 50
443 #define NV_MIIPHY_DELAY 10
444 #define NV_MIIPHY_DELAYMAX 10000
445 #define NV_MAC_RESET_DELAY 64
447 #define NV_WAKEUPPATTERNS 5
448 #define NV_WAKEUPMASKENTRIES 4
450 /* General driver defaults */
451 #define NV_WATCHDOG_TIMEO (5*HZ)
453 #define RX_RING_DEFAULT 128
454 #define TX_RING_DEFAULT 256
455 #define RX_RING_MIN 128
456 #define TX_RING_MIN 64
457 #define RING_MAX_DESC_VER_1 1024
458 #define RING_MAX_DESC_VER_2_3 16384
460 /* rx/tx mac addr + type + vlan + align + slack*/
461 #define NV_RX_HEADERS (64)
462 /* even more slack. */
463 #define NV_RX_ALLOC_PAD (64)
465 /* maximum mtu size */
466 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
467 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
469 #define OOM_REFILL (1+HZ/20)
470 #define POLL_WAIT (1+HZ/100)
471 #define LINK_TIMEOUT (3*HZ)
472 #define STATS_INTERVAL (10*HZ)
476 * The nic supports three different descriptor types:
477 * - DESC_VER_1: Original
478 * - DESC_VER_2: support for jumbo frames.
479 * - DESC_VER_3: 64-bit format.
486 #define PHY_OUI_MARVELL 0x5043
487 #define PHY_OUI_CICADA 0x03f1
488 #define PHY_OUI_VITESSE 0x01c1
489 #define PHY_OUI_REALTEK 0x0732
490 #define PHY_OUI_REALTEK2 0x0020
491 #define PHYID1_OUI_MASK 0x03ff
492 #define PHYID1_OUI_SHFT 6
493 #define PHYID2_OUI_MASK 0xfc00
494 #define PHYID2_OUI_SHFT 10
495 #define PHYID2_MODEL_MASK 0x03f0
496 #define PHY_MODEL_REALTEK_8211 0x0110
497 #define PHY_REV_MASK 0x0001
498 #define PHY_REV_REALTEK_8211B 0x0000
499 #define PHY_REV_REALTEK_8211C 0x0001
500 #define PHY_MODEL_REALTEK_8201 0x0200
501 #define PHY_MODEL_MARVELL_E3016 0x0220
502 #define PHY_MARVELL_E3016_INITMASK 0x0300
503 #define PHY_CICADA_INIT1 0x0f000
504 #define PHY_CICADA_INIT2 0x0e00
505 #define PHY_CICADA_INIT3 0x01000
506 #define PHY_CICADA_INIT4 0x0200
507 #define PHY_CICADA_INIT5 0x0004
508 #define PHY_CICADA_INIT6 0x02000
509 #define PHY_VITESSE_INIT_REG1 0x1f
510 #define PHY_VITESSE_INIT_REG2 0x10
511 #define PHY_VITESSE_INIT_REG3 0x11
512 #define PHY_VITESSE_INIT_REG4 0x12
513 #define PHY_VITESSE_INIT_MSK1 0xc
514 #define PHY_VITESSE_INIT_MSK2 0x0180
515 #define PHY_VITESSE_INIT1 0x52b5
516 #define PHY_VITESSE_INIT2 0xaf8a
517 #define PHY_VITESSE_INIT3 0x8
518 #define PHY_VITESSE_INIT4 0x8f8a
519 #define PHY_VITESSE_INIT5 0xaf86
520 #define PHY_VITESSE_INIT6 0x8f86
521 #define PHY_VITESSE_INIT7 0xaf82
522 #define PHY_VITESSE_INIT8 0x0100
523 #define PHY_VITESSE_INIT9 0x8f82
524 #define PHY_VITESSE_INIT10 0x0
525 #define PHY_REALTEK_INIT_REG1 0x1f
526 #define PHY_REALTEK_INIT_REG2 0x19
527 #define PHY_REALTEK_INIT_REG3 0x13
528 #define PHY_REALTEK_INIT_REG4 0x14
529 #define PHY_REALTEK_INIT_REG5 0x18
530 #define PHY_REALTEK_INIT_REG6 0x11
531 #define PHY_REALTEK_INIT1 0x0000
532 #define PHY_REALTEK_INIT2 0x8e00
533 #define PHY_REALTEK_INIT3 0x0001
534 #define PHY_REALTEK_INIT4 0xad17
535 #define PHY_REALTEK_INIT5 0xfb54
536 #define PHY_REALTEK_INIT6 0xf5c7
537 #define PHY_REALTEK_INIT7 0x1000
538 #define PHY_REALTEK_INIT8 0x0003
539 #define PHY_REALTEK_INIT_MSK1 0x0003
541 #define PHY_GIGABIT 0x0100
543 #define PHY_TIMEOUT 0x1
544 #define PHY_ERROR 0x2
548 #define PHY_HALF 0x100
550 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
551 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
552 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
553 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
554 #define NV_PAUSEFRAME_RX_REQ 0x0010
555 #define NV_PAUSEFRAME_TX_REQ 0x0020
556 #define NV_PAUSEFRAME_AUTONEG 0x0040
558 /* MSI/MSI-X defines */
559 #define NV_MSI_X_MAX_VECTORS 8
560 #define NV_MSI_X_VECTORS_MASK 0x000f
561 #define NV_MSI_CAPABLE 0x0010
562 #define NV_MSI_X_CAPABLE 0x0020
563 #define NV_MSI_ENABLED 0x0040
564 #define NV_MSI_X_ENABLED 0x0080
566 #define NV_MSI_X_VECTOR_ALL 0x0
567 #define NV_MSI_X_VECTOR_RX 0x0
568 #define NV_MSI_X_VECTOR_TX 0x1
569 #define NV_MSI_X_VECTOR_OTHER 0x2
571 #define NV_RESTART_TX 0x1
572 #define NV_RESTART_RX 0x2
574 #define NV_TX_LIMIT_COUNT 16
577 struct nv_ethtool_str
{
578 char name
[ETH_GSTRING_LEN
];
581 static const struct nv_ethtool_str nv_estats_str
[] = {
586 { "tx_late_collision" },
587 { "tx_fifo_errors" },
588 { "tx_carrier_errors" },
589 { "tx_excess_deferral" },
590 { "tx_retry_error" },
591 { "rx_frame_error" },
593 { "rx_late_collision" },
595 { "rx_frame_too_long" },
596 { "rx_over_errors" },
598 { "rx_frame_align_error" },
599 { "rx_length_error" },
604 { "rx_errors_total" },
605 { "tx_errors_total" },
607 /* version 2 stats */
616 struct nv_ethtool_stats
{
621 u64 tx_late_collision
;
623 u64 tx_carrier_errors
;
624 u64 tx_excess_deferral
;
628 u64 rx_late_collision
;
630 u64 rx_frame_too_long
;
633 u64 rx_frame_align_error
;
642 /* version 2 stats */
651 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
652 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
655 #define NV_TEST_COUNT_BASE 3
656 #define NV_TEST_COUNT_EXTENDED 4
658 static const struct nv_ethtool_str nv_etests_str
[] = {
659 { "link (online/offline)" },
660 { "register (offline) " },
661 { "interrupt (offline) " },
662 { "loopback (offline) " }
665 struct register_test
{
670 static const struct register_test nv_registers_test
[] = {
671 { NvRegUnknownSetupReg6
, 0x01 },
672 { NvRegMisc1
, 0x03c },
673 { NvRegOffloadConfig
, 0x03ff },
674 { NvRegMulticastAddrA
, 0xffffffff },
675 { NvRegTxWatermark
, 0x0ff },
676 { NvRegWakeUpFlags
, 0x07777 },
683 unsigned int dma_len
;
684 struct ring_desc_ex
*first_tx_desc
;
685 struct nv_skb_map
*next_tx_ctx
;
690 * All hardware access under dev->priv->lock, except the performance
692 * - rx is (pseudo-) lockless: it relies on the single-threading provided
693 * by the arch code for interrupts.
694 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
695 * needs dev->priv->lock :-(
696 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
699 /* in dev: base, irq */
703 struct net_device
*dev
;
704 struct napi_struct napi
;
707 * Locking: spin_lock(&np->lock); */
708 struct nv_ethtool_stats estats
;
716 unsigned int phy_oui
;
717 unsigned int phy_model
;
718 unsigned int phy_rev
;
723 /* General data: RO fields */
724 dma_addr_t ring_addr
;
725 struct pci_dev
*pci_dev
;
739 /* rx specific fields.
740 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
742 union ring_type get_rx
, put_rx
, first_rx
, last_rx
;
743 struct nv_skb_map
*get_rx_ctx
, *put_rx_ctx
;
744 struct nv_skb_map
*first_rx_ctx
, *last_rx_ctx
;
745 struct nv_skb_map
*rx_skb
;
747 union ring_type rx_ring
;
748 unsigned int rx_buf_sz
;
749 unsigned int pkt_limit
;
750 struct timer_list oom_kick
;
751 struct timer_list nic_poll
;
752 struct timer_list stats_poll
;
756 /* media detection workaround.
757 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
760 unsigned long link_timeout
;
762 * tx specific fields.
764 union ring_type get_tx
, put_tx
, first_tx
, last_tx
;
765 struct nv_skb_map
*get_tx_ctx
, *put_tx_ctx
;
766 struct nv_skb_map
*first_tx_ctx
, *last_tx_ctx
;
767 struct nv_skb_map
*tx_skb
;
769 union ring_type tx_ring
;
773 u32 tx_pkts_in_progress
;
774 struct nv_skb_map
*tx_change_owner
;
775 struct nv_skb_map
*tx_end_flip
;
779 struct vlan_group
*vlangrp
;
781 /* msi/msi-x fields */
783 struct msix_entry msi_x_entry
[NV_MSI_X_MAX_VECTORS
];
790 * Maximum number of loops until we assume that a bit in the irq mask
791 * is stuck. Overridable with module param.
793 static int max_interrupt_work
= 5;
796 * Optimization can be either throuput mode or cpu mode
798 * Throughput Mode: Every tx and rx packet will generate an interrupt.
799 * CPU Mode: Interrupts are controlled by a timer.
802 NV_OPTIMIZATION_MODE_THROUGHPUT
,
803 NV_OPTIMIZATION_MODE_CPU
805 static int optimization_mode
= NV_OPTIMIZATION_MODE_THROUGHPUT
;
808 * Poll interval for timer irq
810 * This interval determines how frequent an interrupt is generated.
811 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
812 * Min = 0, and Max = 65535
814 static int poll_interval
= -1;
823 static int msi
= NV_MSI_INT_ENABLED
;
829 NV_MSIX_INT_DISABLED
,
832 static int msix
= NV_MSIX_INT_DISABLED
;
838 NV_DMA_64BIT_DISABLED
,
841 static int dma_64bit
= NV_DMA_64BIT_ENABLED
;
844 * Crossover Detection
845 * Realtek 8201 phy + some OEM boards do not work properly.
848 NV_CROSSOVER_DETECTION_DISABLED
,
849 NV_CROSSOVER_DETECTION_ENABLED
851 static int phy_cross
= NV_CROSSOVER_DETECTION_DISABLED
;
853 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
855 return netdev_priv(dev
);
858 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
860 return ((struct fe_priv
*)netdev_priv(dev
))->base
;
863 static inline void pci_push(u8 __iomem
*base
)
865 /* force out pending posted writes */
869 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
871 return le32_to_cpu(prd
->flaglen
)
872 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
875 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
877 return le32_to_cpu(prd
->flaglen
) & LEN_MASK_V2
;
880 static bool nv_optimized(struct fe_priv
*np
)
882 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
887 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
888 int delay
, int delaymax
, const char *msg
)
890 u8 __iomem
*base
= get_hwbase(dev
);
901 } while ((readl(base
+ offset
) & mask
) != target
);
905 #define NV_SETUP_RX_RING 0x01
906 #define NV_SETUP_TX_RING 0x02
908 static inline u32
dma_low(dma_addr_t addr
)
913 static inline u32
dma_high(dma_addr_t addr
)
915 return addr
>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
918 static void setup_hw_rings(struct net_device
*dev
, int rxtx_flags
)
920 struct fe_priv
*np
= get_nvpriv(dev
);
921 u8 __iomem
*base
= get_hwbase(dev
);
923 if (!nv_optimized(np
)) {
924 if (rxtx_flags
& NV_SETUP_RX_RING
) {
925 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
927 if (rxtx_flags
& NV_SETUP_TX_RING
) {
928 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
931 if (rxtx_flags
& NV_SETUP_RX_RING
) {
932 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
933 writel(dma_high(np
->ring_addr
), base
+ NvRegRxRingPhysAddrHigh
);
935 if (rxtx_flags
& NV_SETUP_TX_RING
) {
936 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
937 writel(dma_high(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddrHigh
);
942 static void free_rings(struct net_device
*dev
)
944 struct fe_priv
*np
= get_nvpriv(dev
);
946 if (!nv_optimized(np
)) {
947 if (np
->rx_ring
.orig
)
948 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
949 np
->rx_ring
.orig
, np
->ring_addr
);
952 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
953 np
->rx_ring
.ex
, np
->ring_addr
);
961 static int using_multi_irqs(struct net_device
*dev
)
963 struct fe_priv
*np
= get_nvpriv(dev
);
965 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
966 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
967 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1)))
973 static void nv_enable_irq(struct net_device
*dev
)
975 struct fe_priv
*np
= get_nvpriv(dev
);
977 if (!using_multi_irqs(dev
)) {
978 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
979 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
981 enable_irq(np
->pci_dev
->irq
);
983 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
984 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
985 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
989 static void nv_disable_irq(struct net_device
*dev
)
991 struct fe_priv
*np
= get_nvpriv(dev
);
993 if (!using_multi_irqs(dev
)) {
994 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
995 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
997 disable_irq(np
->pci_dev
->irq
);
999 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1000 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1001 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1005 /* In MSIX mode, a write to irqmask behaves as XOR */
1006 static void nv_enable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1008 u8 __iomem
*base
= get_hwbase(dev
);
1010 writel(mask
, base
+ NvRegIrqMask
);
1013 static void nv_disable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1015 struct fe_priv
*np
= get_nvpriv(dev
);
1016 u8 __iomem
*base
= get_hwbase(dev
);
1018 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
1019 writel(mask
, base
+ NvRegIrqMask
);
1021 if (np
->msi_flags
& NV_MSI_ENABLED
)
1022 writel(0, base
+ NvRegMSIIrqMask
);
1023 writel(0, base
+ NvRegIrqMask
);
1027 #define MII_READ (-1)
1028 /* mii_rw: read/write a register on the PHY.
1030 * Caller must guarantee serialization
1032 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
1034 u8 __iomem
*base
= get_hwbase(dev
);
1038 writel(NVREG_MIISTAT_MASK_RW
, base
+ NvRegMIIStatus
);
1040 reg
= readl(base
+ NvRegMIIControl
);
1041 if (reg
& NVREG_MIICTL_INUSE
) {
1042 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
1043 udelay(NV_MIIBUSY_DELAY
);
1046 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
1047 if (value
!= MII_READ
) {
1048 writel(value
, base
+ NvRegMIIData
);
1049 reg
|= NVREG_MIICTL_WRITE
;
1051 writel(reg
, base
+ NvRegMIIControl
);
1053 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
1054 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
1055 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
1056 dev
->name
, miireg
, addr
);
1058 } else if (value
!= MII_READ
) {
1059 /* it was a write operation - fewer failures are detectable */
1060 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1061 dev
->name
, value
, miireg
, addr
);
1063 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
1064 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
1065 dev
->name
, miireg
, addr
);
1068 retval
= readl(base
+ NvRegMIIData
);
1069 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1070 dev
->name
, miireg
, addr
, retval
);
1076 static int phy_reset(struct net_device
*dev
, u32 bmcr_setup
)
1078 struct fe_priv
*np
= netdev_priv(dev
);
1080 unsigned int tries
= 0;
1082 miicontrol
= BMCR_RESET
| bmcr_setup
;
1083 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
1087 /* wait for 500ms */
1090 /* must wait till reset is deasserted */
1091 while (miicontrol
& BMCR_RESET
) {
1093 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1094 /* FIXME: 100 tries seem excessive */
1101 static int phy_init(struct net_device
*dev
)
1103 struct fe_priv
*np
= get_nvpriv(dev
);
1104 u8 __iomem
*base
= get_hwbase(dev
);
1105 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
1107 /* phy errata for E3016 phy */
1108 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
1109 reg
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1110 reg
&= ~PHY_MARVELL_E3016_INITMASK
;
1111 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, reg
)) {
1112 printk(KERN_INFO
"%s: phy write to errata reg failed.\n", pci_name(np
->pci_dev
));
1116 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1117 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1118 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1119 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1120 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1123 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
)) {
1124 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1127 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1128 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1131 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
)) {
1132 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1135 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
)) {
1136 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1139 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
)) {
1140 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1143 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1144 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1148 if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1149 if (np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
1150 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
1151 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
1152 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
1153 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
1154 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
1155 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
1156 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) {
1157 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1158 phy_reserved
|= PHY_REALTEK_INIT7
;
1159 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, phy_reserved
)) {
1160 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1167 /* set advertise register */
1168 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1169 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|ADVERTISE_PAUSE_ASYM
|ADVERTISE_PAUSE_CAP
);
1170 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
1171 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
1175 /* get phy interface type */
1176 phyinterface
= readl(base
+ NvRegPhyInterface
);
1178 /* see if gigabit phy */
1179 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1180 if (mii_status
& PHY_GIGABIT
) {
1181 np
->gigabit
= PHY_GIGABIT
;
1182 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
1183 mii_control_1000
&= ~ADVERTISE_1000HALF
;
1184 if (phyinterface
& PHY_RGMII
)
1185 mii_control_1000
|= ADVERTISE_1000FULL
;
1187 mii_control_1000
&= ~ADVERTISE_1000FULL
;
1189 if (mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, mii_control_1000
)) {
1190 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1197 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1198 mii_control
|= BMCR_ANENABLE
;
1201 * (certain phys need bmcr to be setup with reset)
1203 if (phy_reset(dev
, mii_control
)) {
1204 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
1208 /* phy vendor specific configuration */
1209 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
1210 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
1211 phy_reserved
&= ~(PHY_CICADA_INIT1
| PHY_CICADA_INIT2
);
1212 phy_reserved
|= (PHY_CICADA_INIT3
| PHY_CICADA_INIT4
);
1213 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
1214 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1217 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1218 phy_reserved
|= PHY_CICADA_INIT5
;
1219 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
1220 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1224 if (np
->phy_oui
== PHY_OUI_CICADA
) {
1225 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
1226 phy_reserved
|= PHY_CICADA_INIT6
;
1227 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
1228 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1232 if (np
->phy_oui
== PHY_OUI_VITESSE
) {
1233 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT1
)) {
1234 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1237 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT2
)) {
1238 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1241 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1242 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1243 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1246 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1247 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1248 phy_reserved
|= PHY_VITESSE_INIT3
;
1249 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1250 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1253 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT4
)) {
1254 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1257 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT5
)) {
1258 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1261 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1262 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1263 phy_reserved
|= PHY_VITESSE_INIT3
;
1264 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1265 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1268 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1269 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1270 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1273 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT6
)) {
1274 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1277 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT7
)) {
1278 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1281 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1282 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1283 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1286 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1287 phy_reserved
&= ~PHY_VITESSE_INIT_MSK2
;
1288 phy_reserved
|= PHY_VITESSE_INIT8
;
1289 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1290 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1293 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT9
)) {
1294 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1297 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT10
)) {
1298 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1302 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1303 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1304 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1305 /* reset could have cleared these out, set them back */
1306 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1307 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1310 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
)) {
1311 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1314 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1315 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1318 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
)) {
1319 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1322 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
)) {
1323 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1326 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
)) {
1327 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1330 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1331 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1335 if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1336 if (np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
1337 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
1338 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
1339 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
1340 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
1341 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
1342 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
1343 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) {
1344 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1345 phy_reserved
|= PHY_REALTEK_INIT7
;
1346 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, phy_reserved
)) {
1347 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1351 if (phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
1352 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1353 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1356 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
1357 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
1358 phy_reserved
|= PHY_REALTEK_INIT3
;
1359 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
)) {
1360 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1363 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1364 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1371 /* some phys clear out pause advertisment on reset, set it back */
1372 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
);
1374 /* restart auto negotiation */
1375 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1376 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
1377 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1384 static void nv_start_rx(struct net_device
*dev
)
1386 struct fe_priv
*np
= netdev_priv(dev
);
1387 u8 __iomem
*base
= get_hwbase(dev
);
1388 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1390 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
1391 /* Already running? Stop it. */
1392 if ((readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) && !np
->mac_in_use
) {
1393 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1394 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1397 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1399 rx_ctrl
|= NVREG_RCVCTL_START
;
1401 rx_ctrl
&= ~NVREG_RCVCTL_RX_PATH_EN
;
1402 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1403 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1404 dev
->name
, np
->duplex
, np
->linkspeed
);
1408 static void nv_stop_rx(struct net_device
*dev
)
1410 struct fe_priv
*np
= netdev_priv(dev
);
1411 u8 __iomem
*base
= get_hwbase(dev
);
1412 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1414 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
1415 if (!np
->mac_in_use
)
1416 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1418 rx_ctrl
|= NVREG_RCVCTL_RX_PATH_EN
;
1419 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1420 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
1421 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
1422 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
1424 udelay(NV_RXSTOP_DELAY2
);
1425 if (!np
->mac_in_use
)
1426 writel(0, base
+ NvRegLinkSpeed
);
1429 static void nv_start_tx(struct net_device
*dev
)
1431 struct fe_priv
*np
= netdev_priv(dev
);
1432 u8 __iomem
*base
= get_hwbase(dev
);
1433 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1435 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
1436 tx_ctrl
|= NVREG_XMITCTL_START
;
1438 tx_ctrl
&= ~NVREG_XMITCTL_TX_PATH_EN
;
1439 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1443 static void nv_stop_tx(struct net_device
*dev
)
1445 struct fe_priv
*np
= netdev_priv(dev
);
1446 u8 __iomem
*base
= get_hwbase(dev
);
1447 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1449 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
1450 if (!np
->mac_in_use
)
1451 tx_ctrl
&= ~NVREG_XMITCTL_START
;
1453 tx_ctrl
|= NVREG_XMITCTL_TX_PATH_EN
;
1454 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1455 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
1456 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
1457 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
1459 udelay(NV_TXSTOP_DELAY2
);
1460 if (!np
->mac_in_use
)
1461 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
1462 base
+ NvRegTransmitPoll
);
1465 static void nv_start_rxtx(struct net_device
*dev
)
1471 static void nv_stop_rxtx(struct net_device
*dev
)
1477 static void nv_txrx_reset(struct net_device
*dev
)
1479 struct fe_priv
*np
= netdev_priv(dev
);
1480 u8 __iomem
*base
= get_hwbase(dev
);
1482 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
1483 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1485 udelay(NV_TXRX_RESET_DELAY
);
1486 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1490 static void nv_mac_reset(struct net_device
*dev
)
1492 struct fe_priv
*np
= netdev_priv(dev
);
1493 u8 __iomem
*base
= get_hwbase(dev
);
1494 u32 temp1
, temp2
, temp3
;
1496 dprintk(KERN_DEBUG
"%s: nv_mac_reset\n", dev
->name
);
1498 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1501 /* save registers since they will be cleared on reset */
1502 temp1
= readl(base
+ NvRegMacAddrA
);
1503 temp2
= readl(base
+ NvRegMacAddrB
);
1504 temp3
= readl(base
+ NvRegTransmitPoll
);
1506 writel(NVREG_MAC_RESET_ASSERT
, base
+ NvRegMacReset
);
1508 udelay(NV_MAC_RESET_DELAY
);
1509 writel(0, base
+ NvRegMacReset
);
1511 udelay(NV_MAC_RESET_DELAY
);
1513 /* restore saved registers */
1514 writel(temp1
, base
+ NvRegMacAddrA
);
1515 writel(temp2
, base
+ NvRegMacAddrB
);
1516 writel(temp3
, base
+ NvRegTransmitPoll
);
1518 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1522 static void nv_get_hw_stats(struct net_device
*dev
)
1524 struct fe_priv
*np
= netdev_priv(dev
);
1525 u8 __iomem
*base
= get_hwbase(dev
);
1527 np
->estats
.tx_bytes
+= readl(base
+ NvRegTxCnt
);
1528 np
->estats
.tx_zero_rexmt
+= readl(base
+ NvRegTxZeroReXmt
);
1529 np
->estats
.tx_one_rexmt
+= readl(base
+ NvRegTxOneReXmt
);
1530 np
->estats
.tx_many_rexmt
+= readl(base
+ NvRegTxManyReXmt
);
1531 np
->estats
.tx_late_collision
+= readl(base
+ NvRegTxLateCol
);
1532 np
->estats
.tx_fifo_errors
+= readl(base
+ NvRegTxUnderflow
);
1533 np
->estats
.tx_carrier_errors
+= readl(base
+ NvRegTxLossCarrier
);
1534 np
->estats
.tx_excess_deferral
+= readl(base
+ NvRegTxExcessDef
);
1535 np
->estats
.tx_retry_error
+= readl(base
+ NvRegTxRetryErr
);
1536 np
->estats
.rx_frame_error
+= readl(base
+ NvRegRxFrameErr
);
1537 np
->estats
.rx_extra_byte
+= readl(base
+ NvRegRxExtraByte
);
1538 np
->estats
.rx_late_collision
+= readl(base
+ NvRegRxLateCol
);
1539 np
->estats
.rx_runt
+= readl(base
+ NvRegRxRunt
);
1540 np
->estats
.rx_frame_too_long
+= readl(base
+ NvRegRxFrameTooLong
);
1541 np
->estats
.rx_over_errors
+= readl(base
+ NvRegRxOverflow
);
1542 np
->estats
.rx_crc_errors
+= readl(base
+ NvRegRxFCSErr
);
1543 np
->estats
.rx_frame_align_error
+= readl(base
+ NvRegRxFrameAlignErr
);
1544 np
->estats
.rx_length_error
+= readl(base
+ NvRegRxLenErr
);
1545 np
->estats
.rx_unicast
+= readl(base
+ NvRegRxUnicast
);
1546 np
->estats
.rx_multicast
+= readl(base
+ NvRegRxMulticast
);
1547 np
->estats
.rx_broadcast
+= readl(base
+ NvRegRxBroadcast
);
1548 np
->estats
.rx_packets
=
1549 np
->estats
.rx_unicast
+
1550 np
->estats
.rx_multicast
+
1551 np
->estats
.rx_broadcast
;
1552 np
->estats
.rx_errors_total
=
1553 np
->estats
.rx_crc_errors
+
1554 np
->estats
.rx_over_errors
+
1555 np
->estats
.rx_frame_error
+
1556 (np
->estats
.rx_frame_align_error
- np
->estats
.rx_extra_byte
) +
1557 np
->estats
.rx_late_collision
+
1558 np
->estats
.rx_runt
+
1559 np
->estats
.rx_frame_too_long
;
1560 np
->estats
.tx_errors_total
=
1561 np
->estats
.tx_late_collision
+
1562 np
->estats
.tx_fifo_errors
+
1563 np
->estats
.tx_carrier_errors
+
1564 np
->estats
.tx_excess_deferral
+
1565 np
->estats
.tx_retry_error
;
1567 if (np
->driver_data
& DEV_HAS_STATISTICS_V2
) {
1568 np
->estats
.tx_deferral
+= readl(base
+ NvRegTxDef
);
1569 np
->estats
.tx_packets
+= readl(base
+ NvRegTxFrame
);
1570 np
->estats
.rx_bytes
+= readl(base
+ NvRegRxCnt
);
1571 np
->estats
.tx_pause
+= readl(base
+ NvRegTxPause
);
1572 np
->estats
.rx_pause
+= readl(base
+ NvRegRxPause
);
1573 np
->estats
.rx_drop_frame
+= readl(base
+ NvRegRxDropFrame
);
1578 * nv_get_stats: dev->get_stats function
1579 * Get latest stats value from the nic.
1580 * Called with read_lock(&dev_base_lock) held for read -
1581 * only synchronized against unregister_netdevice.
1583 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
1585 struct fe_priv
*np
= netdev_priv(dev
);
1587 /* If the nic supports hw counters then retrieve latest values */
1588 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
)) {
1589 nv_get_hw_stats(dev
);
1591 /* copy to net_device stats */
1592 dev
->stats
.tx_bytes
= np
->estats
.tx_bytes
;
1593 dev
->stats
.tx_fifo_errors
= np
->estats
.tx_fifo_errors
;
1594 dev
->stats
.tx_carrier_errors
= np
->estats
.tx_carrier_errors
;
1595 dev
->stats
.rx_crc_errors
= np
->estats
.rx_crc_errors
;
1596 dev
->stats
.rx_over_errors
= np
->estats
.rx_over_errors
;
1597 dev
->stats
.rx_errors
= np
->estats
.rx_errors_total
;
1598 dev
->stats
.tx_errors
= np
->estats
.tx_errors_total
;
1605 * nv_alloc_rx: fill rx ring entries.
1606 * Return 1 if the allocations for the skbs failed and the
1607 * rx engine is without Available descriptors
1609 static int nv_alloc_rx(struct net_device
*dev
)
1611 struct fe_priv
*np
= netdev_priv(dev
);
1612 struct ring_desc
* less_rx
;
1614 less_rx
= np
->get_rx
.orig
;
1615 if (less_rx
-- == np
->first_rx
.orig
)
1616 less_rx
= np
->last_rx
.orig
;
1618 while (np
->put_rx
.orig
!= less_rx
) {
1619 struct sk_buff
*skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1621 np
->put_rx_ctx
->skb
= skb
;
1622 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1625 PCI_DMA_FROMDEVICE
);
1626 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1627 np
->put_rx
.orig
->buf
= cpu_to_le32(np
->put_rx_ctx
->dma
);
1629 np
->put_rx
.orig
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
1630 if (unlikely(np
->put_rx
.orig
++ == np
->last_rx
.orig
))
1631 np
->put_rx
.orig
= np
->first_rx
.orig
;
1632 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1633 np
->put_rx_ctx
= np
->first_rx_ctx
;
1641 static int nv_alloc_rx_optimized(struct net_device
*dev
)
1643 struct fe_priv
*np
= netdev_priv(dev
);
1644 struct ring_desc_ex
* less_rx
;
1646 less_rx
= np
->get_rx
.ex
;
1647 if (less_rx
-- == np
->first_rx
.ex
)
1648 less_rx
= np
->last_rx
.ex
;
1650 while (np
->put_rx
.ex
!= less_rx
) {
1651 struct sk_buff
*skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1653 np
->put_rx_ctx
->skb
= skb
;
1654 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1657 PCI_DMA_FROMDEVICE
);
1658 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1659 np
->put_rx
.ex
->bufhigh
= cpu_to_le32(dma_high(np
->put_rx_ctx
->dma
));
1660 np
->put_rx
.ex
->buflow
= cpu_to_le32(dma_low(np
->put_rx_ctx
->dma
));
1662 np
->put_rx
.ex
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
1663 if (unlikely(np
->put_rx
.ex
++ == np
->last_rx
.ex
))
1664 np
->put_rx
.ex
= np
->first_rx
.ex
;
1665 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1666 np
->put_rx_ctx
= np
->first_rx_ctx
;
1674 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1675 #ifdef CONFIG_FORCEDETH_NAPI
1676 static void nv_do_rx_refill(unsigned long data
)
1678 struct net_device
*dev
= (struct net_device
*) data
;
1679 struct fe_priv
*np
= netdev_priv(dev
);
1681 /* Just reschedule NAPI rx processing */
1682 netif_rx_schedule(dev
, &np
->napi
);
1685 static void nv_do_rx_refill(unsigned long data
)
1687 struct net_device
*dev
= (struct net_device
*) data
;
1688 struct fe_priv
*np
= netdev_priv(dev
);
1691 if (!using_multi_irqs(dev
)) {
1692 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1693 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1695 disable_irq(np
->pci_dev
->irq
);
1697 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1699 if (!nv_optimized(np
))
1700 retcode
= nv_alloc_rx(dev
);
1702 retcode
= nv_alloc_rx_optimized(dev
);
1704 spin_lock_irq(&np
->lock
);
1705 if (!np
->in_shutdown
)
1706 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1707 spin_unlock_irq(&np
->lock
);
1709 if (!using_multi_irqs(dev
)) {
1710 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1711 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1713 enable_irq(np
->pci_dev
->irq
);
1715 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1720 static void nv_init_rx(struct net_device
*dev
)
1722 struct fe_priv
*np
= netdev_priv(dev
);
1725 np
->get_rx
= np
->put_rx
= np
->first_rx
= np
->rx_ring
;
1727 if (!nv_optimized(np
))
1728 np
->last_rx
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
-1];
1730 np
->last_rx
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
-1];
1731 np
->get_rx_ctx
= np
->put_rx_ctx
= np
->first_rx_ctx
= np
->rx_skb
;
1732 np
->last_rx_ctx
= &np
->rx_skb
[np
->rx_ring_size
-1];
1734 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1735 if (!nv_optimized(np
)) {
1736 np
->rx_ring
.orig
[i
].flaglen
= 0;
1737 np
->rx_ring
.orig
[i
].buf
= 0;
1739 np
->rx_ring
.ex
[i
].flaglen
= 0;
1740 np
->rx_ring
.ex
[i
].txvlan
= 0;
1741 np
->rx_ring
.ex
[i
].bufhigh
= 0;
1742 np
->rx_ring
.ex
[i
].buflow
= 0;
1744 np
->rx_skb
[i
].skb
= NULL
;
1745 np
->rx_skb
[i
].dma
= 0;
1749 static void nv_init_tx(struct net_device
*dev
)
1751 struct fe_priv
*np
= netdev_priv(dev
);
1754 np
->get_tx
= np
->put_tx
= np
->first_tx
= np
->tx_ring
;
1756 if (!nv_optimized(np
))
1757 np
->last_tx
.orig
= &np
->tx_ring
.orig
[np
->tx_ring_size
-1];
1759 np
->last_tx
.ex
= &np
->tx_ring
.ex
[np
->tx_ring_size
-1];
1760 np
->get_tx_ctx
= np
->put_tx_ctx
= np
->first_tx_ctx
= np
->tx_skb
;
1761 np
->last_tx_ctx
= &np
->tx_skb
[np
->tx_ring_size
-1];
1762 np
->tx_pkts_in_progress
= 0;
1763 np
->tx_change_owner
= NULL
;
1764 np
->tx_end_flip
= NULL
;
1766 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1767 if (!nv_optimized(np
)) {
1768 np
->tx_ring
.orig
[i
].flaglen
= 0;
1769 np
->tx_ring
.orig
[i
].buf
= 0;
1771 np
->tx_ring
.ex
[i
].flaglen
= 0;
1772 np
->tx_ring
.ex
[i
].txvlan
= 0;
1773 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1774 np
->tx_ring
.ex
[i
].buflow
= 0;
1776 np
->tx_skb
[i
].skb
= NULL
;
1777 np
->tx_skb
[i
].dma
= 0;
1778 np
->tx_skb
[i
].dma_len
= 0;
1779 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1780 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1784 static int nv_init_ring(struct net_device
*dev
)
1786 struct fe_priv
*np
= netdev_priv(dev
);
1791 if (!nv_optimized(np
))
1792 return nv_alloc_rx(dev
);
1794 return nv_alloc_rx_optimized(dev
);
1797 static int nv_release_txskb(struct net_device
*dev
, struct nv_skb_map
* tx_skb
)
1799 struct fe_priv
*np
= netdev_priv(dev
);
1802 pci_unmap_page(np
->pci_dev
, tx_skb
->dma
,
1808 dev_kfree_skb_any(tx_skb
->skb
);
1816 static void nv_drain_tx(struct net_device
*dev
)
1818 struct fe_priv
*np
= netdev_priv(dev
);
1821 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1822 if (!nv_optimized(np
)) {
1823 np
->tx_ring
.orig
[i
].flaglen
= 0;
1824 np
->tx_ring
.orig
[i
].buf
= 0;
1826 np
->tx_ring
.ex
[i
].flaglen
= 0;
1827 np
->tx_ring
.ex
[i
].txvlan
= 0;
1828 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1829 np
->tx_ring
.ex
[i
].buflow
= 0;
1831 if (nv_release_txskb(dev
, &np
->tx_skb
[i
]))
1832 dev
->stats
.tx_dropped
++;
1833 np
->tx_skb
[i
].dma
= 0;
1834 np
->tx_skb
[i
].dma_len
= 0;
1835 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1836 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1838 np
->tx_pkts_in_progress
= 0;
1839 np
->tx_change_owner
= NULL
;
1840 np
->tx_end_flip
= NULL
;
1843 static void nv_drain_rx(struct net_device
*dev
)
1845 struct fe_priv
*np
= netdev_priv(dev
);
1848 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1849 if (!nv_optimized(np
)) {
1850 np
->rx_ring
.orig
[i
].flaglen
= 0;
1851 np
->rx_ring
.orig
[i
].buf
= 0;
1853 np
->rx_ring
.ex
[i
].flaglen
= 0;
1854 np
->rx_ring
.ex
[i
].txvlan
= 0;
1855 np
->rx_ring
.ex
[i
].bufhigh
= 0;
1856 np
->rx_ring
.ex
[i
].buflow
= 0;
1859 if (np
->rx_skb
[i
].skb
) {
1860 pci_unmap_single(np
->pci_dev
, np
->rx_skb
[i
].dma
,
1861 (skb_end_pointer(np
->rx_skb
[i
].skb
) -
1862 np
->rx_skb
[i
].skb
->data
),
1863 PCI_DMA_FROMDEVICE
);
1864 dev_kfree_skb(np
->rx_skb
[i
].skb
);
1865 np
->rx_skb
[i
].skb
= NULL
;
1870 static void nv_drain_rxtx(struct net_device
*dev
)
1876 static inline u32
nv_get_empty_tx_slots(struct fe_priv
*np
)
1878 return (u32
)(np
->tx_ring_size
- ((np
->tx_ring_size
+ (np
->put_tx_ctx
- np
->get_tx_ctx
)) % np
->tx_ring_size
));
1881 static void nv_legacybackoff_reseed(struct net_device
*dev
)
1883 u8 __iomem
*base
= get_hwbase(dev
);
1888 reg
= readl(base
+ NvRegSlotTime
) & ~NVREG_SLOTTIME_MASK
;
1889 get_random_bytes(&low
, sizeof(low
));
1890 reg
|= low
& NVREG_SLOTTIME_MASK
;
1892 /* Need to stop tx before change takes effect.
1893 * Caller has already gained np->lock.
1895 tx_status
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
;
1899 writel(reg
, base
+ NvRegSlotTime
);
1905 /* Gear Backoff Seeds */
1906 #define BACKOFF_SEEDSET_ROWS 8
1907 #define BACKOFF_SEEDSET_LFSRS 15
1909 /* Known Good seed sets */
1910 static const u32 main_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
1911 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1912 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1913 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1914 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
1915 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
1916 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
1917 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
1918 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
1920 static const u32 gear_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
1921 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1922 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1923 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
1924 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1925 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1926 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1927 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1928 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
1930 static void nv_gear_backoff_reseed(struct net_device
*dev
)
1932 u8 __iomem
*base
= get_hwbase(dev
);
1933 u32 miniseed1
, miniseed2
, miniseed2_reversed
, miniseed3
, miniseed3_reversed
;
1934 u32 temp
, seedset
, combinedSeed
;
1937 /* Setup seed for free running LFSR */
1938 /* We are going to read the time stamp counter 3 times
1939 and swizzle bits around to increase randomness */
1940 get_random_bytes(&miniseed1
, sizeof(miniseed1
));
1941 miniseed1
&= 0x0fff;
1945 get_random_bytes(&miniseed2
, sizeof(miniseed2
));
1946 miniseed2
&= 0x0fff;
1949 miniseed2_reversed
=
1950 ((miniseed2
& 0xF00) >> 8) |
1951 (miniseed2
& 0x0F0) |
1952 ((miniseed2
& 0x00F) << 8);
1954 get_random_bytes(&miniseed3
, sizeof(miniseed3
));
1955 miniseed3
&= 0x0fff;
1958 miniseed3_reversed
=
1959 ((miniseed3
& 0xF00) >> 8) |
1960 (miniseed3
& 0x0F0) |
1961 ((miniseed3
& 0x00F) << 8);
1963 combinedSeed
= ((miniseed1
^ miniseed2_reversed
) << 12) |
1964 (miniseed2
^ miniseed3_reversed
);
1966 /* Seeds can not be zero */
1967 if ((combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
) == 0)
1968 combinedSeed
|= 0x08;
1969 if ((combinedSeed
& (NVREG_BKOFFCTRL_SEED_MASK
<< NVREG_BKOFFCTRL_GEAR
)) == 0)
1970 combinedSeed
|= 0x8000;
1972 /* No need to disable tx here */
1973 temp
= NVREG_BKOFFCTRL_DEFAULT
| (0 << NVREG_BKOFFCTRL_SELECT
);
1974 temp
|= combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
;
1975 temp
|= combinedSeed
>> NVREG_BKOFFCTRL_GEAR
;
1976 writel(temp
,base
+ NvRegBackOffControl
);
1978 /* Setup seeds for all gear LFSRs. */
1979 get_random_bytes(&seedset
, sizeof(seedset
));
1980 seedset
= seedset
% BACKOFF_SEEDSET_ROWS
;
1981 for (i
= 1; i
<= BACKOFF_SEEDSET_LFSRS
; i
++)
1983 temp
= NVREG_BKOFFCTRL_DEFAULT
| (i
<< NVREG_BKOFFCTRL_SELECT
);
1984 temp
|= main_seedset
[seedset
][i
-1] & 0x3ff;
1985 temp
|= ((gear_seedset
[seedset
][i
-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR
);
1986 writel(temp
, base
+ NvRegBackOffControl
);
1991 * nv_start_xmit: dev->hard_start_xmit function
1992 * Called with netif_tx_lock held.
1994 static int nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1996 struct fe_priv
*np
= netdev_priv(dev
);
1998 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
1999 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2003 u32 size
= skb
->len
-skb
->data_len
;
2004 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2006 struct ring_desc
* put_tx
;
2007 struct ring_desc
* start_tx
;
2008 struct ring_desc
* prev_tx
;
2009 struct nv_skb_map
* prev_tx_ctx
;
2010 unsigned long flags
;
2012 /* add fragments to entries count */
2013 for (i
= 0; i
< fragments
; i
++) {
2014 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
2015 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2018 empty_slots
= nv_get_empty_tx_slots(np
);
2019 if (unlikely(empty_slots
<= entries
)) {
2020 spin_lock_irqsave(&np
->lock
, flags
);
2021 netif_stop_queue(dev
);
2023 spin_unlock_irqrestore(&np
->lock
, flags
);
2024 return NETDEV_TX_BUSY
;
2027 start_tx
= put_tx
= np
->put_tx
.orig
;
2029 /* setup the header buffer */
2032 prev_tx_ctx
= np
->put_tx_ctx
;
2033 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2034 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2036 np
->put_tx_ctx
->dma_len
= bcnt
;
2037 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2038 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2040 tx_flags
= np
->tx_flags
;
2043 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2044 put_tx
= np
->first_tx
.orig
;
2045 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2046 np
->put_tx_ctx
= np
->first_tx_ctx
;
2049 /* setup the fragments */
2050 for (i
= 0; i
< fragments
; i
++) {
2051 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2052 u32 size
= frag
->size
;
2057 prev_tx_ctx
= np
->put_tx_ctx
;
2058 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2059 np
->put_tx_ctx
->dma
= pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
2061 np
->put_tx_ctx
->dma_len
= bcnt
;
2062 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2063 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2067 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2068 put_tx
= np
->first_tx
.orig
;
2069 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2070 np
->put_tx_ctx
= np
->first_tx_ctx
;
2074 /* set last fragment flag */
2075 prev_tx
->flaglen
|= cpu_to_le32(tx_flags_extra
);
2077 /* save skb in this slot's context area */
2078 prev_tx_ctx
->skb
= skb
;
2080 if (skb_is_gso(skb
))
2081 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2083 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2084 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2086 spin_lock_irqsave(&np
->lock
, flags
);
2089 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2090 np
->put_tx
.orig
= put_tx
;
2092 spin_unlock_irqrestore(&np
->lock
, flags
);
2094 dprintk(KERN_DEBUG
"%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2095 dev
->name
, entries
, tx_flags_extra
);
2098 for (j
=0; j
<64; j
++) {
2100 dprintk("\n%03x:", j
);
2101 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2106 dev
->trans_start
= jiffies
;
2107 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2108 return NETDEV_TX_OK
;
2111 static int nv_start_xmit_optimized(struct sk_buff
*skb
, struct net_device
*dev
)
2113 struct fe_priv
*np
= netdev_priv(dev
);
2116 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2120 u32 size
= skb
->len
-skb
->data_len
;
2121 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2123 struct ring_desc_ex
* put_tx
;
2124 struct ring_desc_ex
* start_tx
;
2125 struct ring_desc_ex
* prev_tx
;
2126 struct nv_skb_map
* prev_tx_ctx
;
2127 struct nv_skb_map
* start_tx_ctx
;
2128 unsigned long flags
;
2130 /* add fragments to entries count */
2131 for (i
= 0; i
< fragments
; i
++) {
2132 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
2133 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2136 empty_slots
= nv_get_empty_tx_slots(np
);
2137 if (unlikely(empty_slots
<= entries
)) {
2138 spin_lock_irqsave(&np
->lock
, flags
);
2139 netif_stop_queue(dev
);
2141 spin_unlock_irqrestore(&np
->lock
, flags
);
2142 return NETDEV_TX_BUSY
;
2145 start_tx
= put_tx
= np
->put_tx
.ex
;
2146 start_tx_ctx
= np
->put_tx_ctx
;
2148 /* setup the header buffer */
2151 prev_tx_ctx
= np
->put_tx_ctx
;
2152 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2153 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2155 np
->put_tx_ctx
->dma_len
= bcnt
;
2156 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2157 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2158 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2160 tx_flags
= NV_TX2_VALID
;
2163 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2164 put_tx
= np
->first_tx
.ex
;
2165 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2166 np
->put_tx_ctx
= np
->first_tx_ctx
;
2169 /* setup the fragments */
2170 for (i
= 0; i
< fragments
; i
++) {
2171 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2172 u32 size
= frag
->size
;
2177 prev_tx_ctx
= np
->put_tx_ctx
;
2178 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2179 np
->put_tx_ctx
->dma
= pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
2181 np
->put_tx_ctx
->dma_len
= bcnt
;
2182 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2183 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2184 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2188 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2189 put_tx
= np
->first_tx
.ex
;
2190 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2191 np
->put_tx_ctx
= np
->first_tx_ctx
;
2195 /* set last fragment flag */
2196 prev_tx
->flaglen
|= cpu_to_le32(NV_TX2_LASTPACKET
);
2198 /* save skb in this slot's context area */
2199 prev_tx_ctx
->skb
= skb
;
2201 if (skb_is_gso(skb
))
2202 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2204 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2205 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2208 if (likely(!np
->vlangrp
)) {
2209 start_tx
->txvlan
= 0;
2211 if (vlan_tx_tag_present(skb
))
2212 start_tx
->txvlan
= cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT
| vlan_tx_tag_get(skb
));
2214 start_tx
->txvlan
= 0;
2217 spin_lock_irqsave(&np
->lock
, flags
);
2220 /* Limit the number of outstanding tx. Setup all fragments, but
2221 * do not set the VALID bit on the first descriptor. Save a pointer
2222 * to that descriptor and also for next skb_map element.
2225 if (np
->tx_pkts_in_progress
== NV_TX_LIMIT_COUNT
) {
2226 if (!np
->tx_change_owner
)
2227 np
->tx_change_owner
= start_tx_ctx
;
2229 /* remove VALID bit */
2230 tx_flags
&= ~NV_TX2_VALID
;
2231 start_tx_ctx
->first_tx_desc
= start_tx
;
2232 start_tx_ctx
->next_tx_ctx
= np
->put_tx_ctx
;
2233 np
->tx_end_flip
= np
->put_tx_ctx
;
2235 np
->tx_pkts_in_progress
++;
2240 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2241 np
->put_tx
.ex
= put_tx
;
2243 spin_unlock_irqrestore(&np
->lock
, flags
);
2245 dprintk(KERN_DEBUG
"%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2246 dev
->name
, entries
, tx_flags_extra
);
2249 for (j
=0; j
<64; j
++) {
2251 dprintk("\n%03x:", j
);
2252 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2257 dev
->trans_start
= jiffies
;
2258 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2259 return NETDEV_TX_OK
;
2262 static inline void nv_tx_flip_ownership(struct net_device
*dev
)
2264 struct fe_priv
*np
= netdev_priv(dev
);
2266 np
->tx_pkts_in_progress
--;
2267 if (np
->tx_change_owner
) {
2268 np
->tx_change_owner
->first_tx_desc
->flaglen
|=
2269 cpu_to_le32(NV_TX2_VALID
);
2270 np
->tx_pkts_in_progress
++;
2272 np
->tx_change_owner
= np
->tx_change_owner
->next_tx_ctx
;
2273 if (np
->tx_change_owner
== np
->tx_end_flip
)
2274 np
->tx_change_owner
= NULL
;
2276 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2281 * nv_tx_done: check for completed packets, release the skbs.
2283 * Caller must own np->lock.
2285 static void nv_tx_done(struct net_device
*dev
)
2287 struct fe_priv
*np
= netdev_priv(dev
);
2289 struct ring_desc
* orig_get_tx
= np
->get_tx
.orig
;
2291 while ((np
->get_tx
.orig
!= np
->put_tx
.orig
) &&
2292 !((flags
= le32_to_cpu(np
->get_tx
.orig
->flaglen
)) & NV_TX_VALID
)) {
2294 dprintk(KERN_DEBUG
"%s: nv_tx_done: flags 0x%x.\n",
2297 pci_unmap_page(np
->pci_dev
, np
->get_tx_ctx
->dma
,
2298 np
->get_tx_ctx
->dma_len
,
2300 np
->get_tx_ctx
->dma
= 0;
2302 if (np
->desc_ver
== DESC_VER_1
) {
2303 if (flags
& NV_TX_LASTPACKET
) {
2304 if (flags
& NV_TX_ERROR
) {
2305 if (flags
& NV_TX_UNDERFLOW
)
2306 dev
->stats
.tx_fifo_errors
++;
2307 if (flags
& NV_TX_CARRIERLOST
)
2308 dev
->stats
.tx_carrier_errors
++;
2309 if ((flags
& NV_TX_RETRYERROR
) && !(flags
& NV_TX_RETRYCOUNT_MASK
))
2310 nv_legacybackoff_reseed(dev
);
2311 dev
->stats
.tx_errors
++;
2313 dev
->stats
.tx_packets
++;
2314 dev
->stats
.tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2316 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2317 np
->get_tx_ctx
->skb
= NULL
;
2320 if (flags
& NV_TX2_LASTPACKET
) {
2321 if (flags
& NV_TX2_ERROR
) {
2322 if (flags
& NV_TX2_UNDERFLOW
)
2323 dev
->stats
.tx_fifo_errors
++;
2324 if (flags
& NV_TX2_CARRIERLOST
)
2325 dev
->stats
.tx_carrier_errors
++;
2326 if ((flags
& NV_TX2_RETRYERROR
) && !(flags
& NV_TX2_RETRYCOUNT_MASK
))
2327 nv_legacybackoff_reseed(dev
);
2328 dev
->stats
.tx_errors
++;
2330 dev
->stats
.tx_packets
++;
2331 dev
->stats
.tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2333 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2334 np
->get_tx_ctx
->skb
= NULL
;
2337 if (unlikely(np
->get_tx
.orig
++ == np
->last_tx
.orig
))
2338 np
->get_tx
.orig
= np
->first_tx
.orig
;
2339 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2340 np
->get_tx_ctx
= np
->first_tx_ctx
;
2342 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.orig
!= orig_get_tx
))) {
2344 netif_wake_queue(dev
);
2348 static void nv_tx_done_optimized(struct net_device
*dev
, int limit
)
2350 struct fe_priv
*np
= netdev_priv(dev
);
2352 struct ring_desc_ex
* orig_get_tx
= np
->get_tx
.ex
;
2354 while ((np
->get_tx
.ex
!= np
->put_tx
.ex
) &&
2355 !((flags
= le32_to_cpu(np
->get_tx
.ex
->flaglen
)) & NV_TX_VALID
) &&
2358 dprintk(KERN_DEBUG
"%s: nv_tx_done_optimized: flags 0x%x.\n",
2361 pci_unmap_page(np
->pci_dev
, np
->get_tx_ctx
->dma
,
2362 np
->get_tx_ctx
->dma_len
,
2364 np
->get_tx_ctx
->dma
= 0;
2366 if (flags
& NV_TX2_LASTPACKET
) {
2367 if (!(flags
& NV_TX2_ERROR
))
2368 dev
->stats
.tx_packets
++;
2370 if ((flags
& NV_TX2_RETRYERROR
) && !(flags
& NV_TX2_RETRYCOUNT_MASK
)) {
2371 if (np
->driver_data
& DEV_HAS_GEAR_MODE
)
2372 nv_gear_backoff_reseed(dev
);
2374 nv_legacybackoff_reseed(dev
);
2378 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2379 np
->get_tx_ctx
->skb
= NULL
;
2382 nv_tx_flip_ownership(dev
);
2385 if (unlikely(np
->get_tx
.ex
++ == np
->last_tx
.ex
))
2386 np
->get_tx
.ex
= np
->first_tx
.ex
;
2387 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2388 np
->get_tx_ctx
= np
->first_tx_ctx
;
2390 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.ex
!= orig_get_tx
))) {
2392 netif_wake_queue(dev
);
2397 * nv_tx_timeout: dev->tx_timeout function
2398 * Called with netif_tx_lock held.
2400 static void nv_tx_timeout(struct net_device
*dev
)
2402 struct fe_priv
*np
= netdev_priv(dev
);
2403 u8 __iomem
*base
= get_hwbase(dev
);
2406 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2407 status
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2409 status
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2411 printk(KERN_INFO
"%s: Got tx_timeout. irq: %08x\n", dev
->name
, status
);
2416 printk(KERN_INFO
"%s: Ring at %lx\n",
2417 dev
->name
, (unsigned long)np
->ring_addr
);
2418 printk(KERN_INFO
"%s: Dumping tx registers\n", dev
->name
);
2419 for (i
=0;i
<=np
->register_size
;i
+= 32) {
2420 printk(KERN_INFO
"%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2422 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
2423 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
2424 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
2425 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
2427 printk(KERN_INFO
"%s: Dumping tx ring\n", dev
->name
);
2428 for (i
=0;i
<np
->tx_ring_size
;i
+= 4) {
2429 if (!nv_optimized(np
)) {
2430 printk(KERN_INFO
"%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2432 le32_to_cpu(np
->tx_ring
.orig
[i
].buf
),
2433 le32_to_cpu(np
->tx_ring
.orig
[i
].flaglen
),
2434 le32_to_cpu(np
->tx_ring
.orig
[i
+1].buf
),
2435 le32_to_cpu(np
->tx_ring
.orig
[i
+1].flaglen
),
2436 le32_to_cpu(np
->tx_ring
.orig
[i
+2].buf
),
2437 le32_to_cpu(np
->tx_ring
.orig
[i
+2].flaglen
),
2438 le32_to_cpu(np
->tx_ring
.orig
[i
+3].buf
),
2439 le32_to_cpu(np
->tx_ring
.orig
[i
+3].flaglen
));
2441 printk(KERN_INFO
"%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2443 le32_to_cpu(np
->tx_ring
.ex
[i
].bufhigh
),
2444 le32_to_cpu(np
->tx_ring
.ex
[i
].buflow
),
2445 le32_to_cpu(np
->tx_ring
.ex
[i
].flaglen
),
2446 le32_to_cpu(np
->tx_ring
.ex
[i
+1].bufhigh
),
2447 le32_to_cpu(np
->tx_ring
.ex
[i
+1].buflow
),
2448 le32_to_cpu(np
->tx_ring
.ex
[i
+1].flaglen
),
2449 le32_to_cpu(np
->tx_ring
.ex
[i
+2].bufhigh
),
2450 le32_to_cpu(np
->tx_ring
.ex
[i
+2].buflow
),
2451 le32_to_cpu(np
->tx_ring
.ex
[i
+2].flaglen
),
2452 le32_to_cpu(np
->tx_ring
.ex
[i
+3].bufhigh
),
2453 le32_to_cpu(np
->tx_ring
.ex
[i
+3].buflow
),
2454 le32_to_cpu(np
->tx_ring
.ex
[i
+3].flaglen
));
2459 spin_lock_irq(&np
->lock
);
2461 /* 1) stop tx engine */
2464 /* 2) check that the packets were not sent already: */
2465 if (!nv_optimized(np
))
2468 nv_tx_done_optimized(dev
, np
->tx_ring_size
);
2470 /* 3) if there are dead entries: clear everything */
2471 if (np
->get_tx_ctx
!= np
->put_tx_ctx
) {
2472 printk(KERN_DEBUG
"%s: tx_timeout: dead entries!\n", dev
->name
);
2475 setup_hw_rings(dev
, NV_SETUP_TX_RING
);
2478 netif_wake_queue(dev
);
2480 /* 4) restart tx engine */
2482 spin_unlock_irq(&np
->lock
);
2486 * Called when the nic notices a mismatch between the actual data len on the
2487 * wire and the len indicated in the 802 header
2489 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
2491 int hdrlen
; /* length of the 802 header */
2492 int protolen
; /* length as stored in the proto field */
2494 /* 1) calculate len according to header */
2495 if ( ((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== htons(ETH_P_8021Q
)) {
2496 protolen
= ntohs( ((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
2499 protolen
= ntohs( ((struct ethhdr
*)packet
)->h_proto
);
2502 dprintk(KERN_DEBUG
"%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2503 dev
->name
, datalen
, protolen
, hdrlen
);
2504 if (protolen
> ETH_DATA_LEN
)
2505 return datalen
; /* Value in proto field not a len, no checks possible */
2508 /* consistency checks: */
2509 if (datalen
> ETH_ZLEN
) {
2510 if (datalen
>= protolen
) {
2511 /* more data on wire than in 802 header, trim of
2514 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
2515 dev
->name
, protolen
);
2518 /* less data on wire than mentioned in header.
2519 * Discard the packet.
2521 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding long packet.\n",
2526 /* short packet. Accept only if 802 values are also short */
2527 if (protolen
> ETH_ZLEN
) {
2528 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding short packet.\n",
2532 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
2533 dev
->name
, datalen
);
2538 static int nv_rx_process(struct net_device
*dev
, int limit
)
2540 struct fe_priv
*np
= netdev_priv(dev
);
2543 struct sk_buff
*skb
;
2546 while((np
->get_rx
.orig
!= np
->put_rx
.orig
) &&
2547 !((flags
= le32_to_cpu(np
->get_rx
.orig
->flaglen
)) & NV_RX_AVAIL
) &&
2548 (rx_work
< limit
)) {
2550 dprintk(KERN_DEBUG
"%s: nv_rx_process: flags 0x%x.\n",
2554 * the packet is for us - immediately tear down the pci mapping.
2555 * TODO: check if a prefetch of the first cacheline improves
2558 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2559 np
->get_rx_ctx
->dma_len
,
2560 PCI_DMA_FROMDEVICE
);
2561 skb
= np
->get_rx_ctx
->skb
;
2562 np
->get_rx_ctx
->skb
= NULL
;
2566 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
2567 for (j
=0; j
<64; j
++) {
2569 dprintk("\n%03x:", j
);
2570 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2574 /* look at what we actually got: */
2575 if (np
->desc_ver
== DESC_VER_1
) {
2576 if (likely(flags
& NV_RX_DESCRIPTORVALID
)) {
2577 len
= flags
& LEN_MASK_V1
;
2578 if (unlikely(flags
& NV_RX_ERROR
)) {
2579 if (flags
& NV_RX_ERROR4
) {
2580 len
= nv_getlen(dev
, skb
->data
, len
);
2582 dev
->stats
.rx_errors
++;
2587 /* framing errors are soft errors */
2588 else if (flags
& NV_RX_FRAMINGERR
) {
2589 if (flags
& NV_RX_SUBSTRACT1
) {
2593 /* the rest are hard errors */
2595 if (flags
& NV_RX_MISSEDFRAME
)
2596 dev
->stats
.rx_missed_errors
++;
2597 if (flags
& NV_RX_CRCERR
)
2598 dev
->stats
.rx_crc_errors
++;
2599 if (flags
& NV_RX_OVERFLOW
)
2600 dev
->stats
.rx_over_errors
++;
2601 dev
->stats
.rx_errors
++;
2611 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2612 len
= flags
& LEN_MASK_V2
;
2613 if (unlikely(flags
& NV_RX2_ERROR
)) {
2614 if (flags
& NV_RX2_ERROR4
) {
2615 len
= nv_getlen(dev
, skb
->data
, len
);
2617 dev
->stats
.rx_errors
++;
2622 /* framing errors are soft errors */
2623 else if (flags
& NV_RX2_FRAMINGERR
) {
2624 if (flags
& NV_RX2_SUBSTRACT1
) {
2628 /* the rest are hard errors */
2630 if (flags
& NV_RX2_CRCERR
)
2631 dev
->stats
.rx_crc_errors
++;
2632 if (flags
& NV_RX2_OVERFLOW
)
2633 dev
->stats
.rx_over_errors
++;
2634 dev
->stats
.rx_errors
++;
2639 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2640 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2641 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2647 /* got a valid packet - forward it to the network core */
2649 skb
->protocol
= eth_type_trans(skb
, dev
);
2650 dprintk(KERN_DEBUG
"%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2651 dev
->name
, len
, skb
->protocol
);
2652 #ifdef CONFIG_FORCEDETH_NAPI
2653 netif_receive_skb(skb
);
2657 dev
->last_rx
= jiffies
;
2658 dev
->stats
.rx_packets
++;
2659 dev
->stats
.rx_bytes
+= len
;
2661 if (unlikely(np
->get_rx
.orig
++ == np
->last_rx
.orig
))
2662 np
->get_rx
.orig
= np
->first_rx
.orig
;
2663 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2664 np
->get_rx_ctx
= np
->first_rx_ctx
;
2672 static int nv_rx_process_optimized(struct net_device
*dev
, int limit
)
2674 struct fe_priv
*np
= netdev_priv(dev
);
2678 struct sk_buff
*skb
;
2681 while((np
->get_rx
.ex
!= np
->put_rx
.ex
) &&
2682 !((flags
= le32_to_cpu(np
->get_rx
.ex
->flaglen
)) & NV_RX2_AVAIL
) &&
2683 (rx_work
< limit
)) {
2685 dprintk(KERN_DEBUG
"%s: nv_rx_process_optimized: flags 0x%x.\n",
2689 * the packet is for us - immediately tear down the pci mapping.
2690 * TODO: check if a prefetch of the first cacheline improves
2693 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2694 np
->get_rx_ctx
->dma_len
,
2695 PCI_DMA_FROMDEVICE
);
2696 skb
= np
->get_rx_ctx
->skb
;
2697 np
->get_rx_ctx
->skb
= NULL
;
2701 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
2702 for (j
=0; j
<64; j
++) {
2704 dprintk("\n%03x:", j
);
2705 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2709 /* look at what we actually got: */
2710 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2711 len
= flags
& LEN_MASK_V2
;
2712 if (unlikely(flags
& NV_RX2_ERROR
)) {
2713 if (flags
& NV_RX2_ERROR4
) {
2714 len
= nv_getlen(dev
, skb
->data
, len
);
2720 /* framing errors are soft errors */
2721 else if (flags
& NV_RX2_FRAMINGERR
) {
2722 if (flags
& NV_RX2_SUBSTRACT1
) {
2726 /* the rest are hard errors */
2733 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2734 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2735 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2737 /* got a valid packet - forward it to the network core */
2739 skb
->protocol
= eth_type_trans(skb
, dev
);
2740 prefetch(skb
->data
);
2742 dprintk(KERN_DEBUG
"%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2743 dev
->name
, len
, skb
->protocol
);
2745 if (likely(!np
->vlangrp
)) {
2746 #ifdef CONFIG_FORCEDETH_NAPI
2747 netif_receive_skb(skb
);
2752 vlanflags
= le32_to_cpu(np
->get_rx
.ex
->buflow
);
2753 if (vlanflags
& NV_RX3_VLAN_TAG_PRESENT
) {
2754 #ifdef CONFIG_FORCEDETH_NAPI
2755 vlan_hwaccel_receive_skb(skb
, np
->vlangrp
,
2756 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
2758 vlan_hwaccel_rx(skb
, np
->vlangrp
,
2759 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
2762 #ifdef CONFIG_FORCEDETH_NAPI
2763 netif_receive_skb(skb
);
2770 dev
->last_rx
= jiffies
;
2771 dev
->stats
.rx_packets
++;
2772 dev
->stats
.rx_bytes
+= len
;
2777 if (unlikely(np
->get_rx
.ex
++ == np
->last_rx
.ex
))
2778 np
->get_rx
.ex
= np
->first_rx
.ex
;
2779 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2780 np
->get_rx_ctx
= np
->first_rx_ctx
;
2788 static void set_bufsize(struct net_device
*dev
)
2790 struct fe_priv
*np
= netdev_priv(dev
);
2792 if (dev
->mtu
<= ETH_DATA_LEN
)
2793 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
2795 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
2799 * nv_change_mtu: dev->change_mtu function
2800 * Called with dev_base_lock held for read.
2802 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
2804 struct fe_priv
*np
= netdev_priv(dev
);
2807 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
2813 /* return early if the buffer sizes will not change */
2814 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
2816 if (old_mtu
== new_mtu
)
2819 /* synchronized against open : rtnl_lock() held by caller */
2820 if (netif_running(dev
)) {
2821 u8 __iomem
*base
= get_hwbase(dev
);
2823 * It seems that the nic preloads valid ring entries into an
2824 * internal buffer. The procedure for flushing everything is
2825 * guessed, there is probably a simpler approach.
2826 * Changing the MTU is a rare event, it shouldn't matter.
2828 nv_disable_irq(dev
);
2829 netif_tx_lock_bh(dev
);
2830 spin_lock(&np
->lock
);
2834 /* drain rx queue */
2836 /* reinit driver view of the rx queue */
2838 if (nv_init_ring(dev
)) {
2839 if (!np
->in_shutdown
)
2840 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2842 /* reinit nic view of the rx queue */
2843 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
2844 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
2845 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
2846 base
+ NvRegRingSizes
);
2848 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2851 /* restart rx engine */
2853 spin_unlock(&np
->lock
);
2854 netif_tx_unlock_bh(dev
);
2860 static void nv_copy_mac_to_hw(struct net_device
*dev
)
2862 u8 __iomem
*base
= get_hwbase(dev
);
2865 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
2866 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
2867 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
2869 writel(mac
[0], base
+ NvRegMacAddrA
);
2870 writel(mac
[1], base
+ NvRegMacAddrB
);
2874 * nv_set_mac_address: dev->set_mac_address function
2875 * Called with rtnl_lock() held.
2877 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
2879 struct fe_priv
*np
= netdev_priv(dev
);
2880 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
2882 if (!is_valid_ether_addr(macaddr
->sa_data
))
2883 return -EADDRNOTAVAIL
;
2885 /* synchronized against open : rtnl_lock() held by caller */
2886 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
2888 if (netif_running(dev
)) {
2889 netif_tx_lock_bh(dev
);
2890 spin_lock_irq(&np
->lock
);
2892 /* stop rx engine */
2895 /* set mac address */
2896 nv_copy_mac_to_hw(dev
);
2898 /* restart rx engine */
2900 spin_unlock_irq(&np
->lock
);
2901 netif_tx_unlock_bh(dev
);
2903 nv_copy_mac_to_hw(dev
);
2909 * nv_set_multicast: dev->set_multicast function
2910 * Called with netif_tx_lock held.
2912 static void nv_set_multicast(struct net_device
*dev
)
2914 struct fe_priv
*np
= netdev_priv(dev
);
2915 u8 __iomem
*base
= get_hwbase(dev
);
2918 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & NVREG_PFF_PAUSE_RX
;
2920 memset(addr
, 0, sizeof(addr
));
2921 memset(mask
, 0, sizeof(mask
));
2923 if (dev
->flags
& IFF_PROMISC
) {
2924 pff
|= NVREG_PFF_PROMISC
;
2926 pff
|= NVREG_PFF_MYADDR
;
2928 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_list
) {
2932 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
2933 if (dev
->flags
& IFF_ALLMULTI
) {
2934 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
2936 struct dev_mc_list
*walk
;
2938 walk
= dev
->mc_list
;
2939 while (walk
!= NULL
) {
2941 a
= le32_to_cpu(*(__le32
*) walk
->dmi_addr
);
2942 b
= le16_to_cpu(*(__le16
*) (&walk
->dmi_addr
[4]));
2950 addr
[0] = alwaysOn
[0];
2951 addr
[1] = alwaysOn
[1];
2952 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
2953 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
2955 mask
[0] = NVREG_MCASTMASKA_NONE
;
2956 mask
[1] = NVREG_MCASTMASKB_NONE
;
2959 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
2960 pff
|= NVREG_PFF_ALWAYS
;
2961 spin_lock_irq(&np
->lock
);
2963 writel(addr
[0], base
+ NvRegMulticastAddrA
);
2964 writel(addr
[1], base
+ NvRegMulticastAddrB
);
2965 writel(mask
[0], base
+ NvRegMulticastMaskA
);
2966 writel(mask
[1], base
+ NvRegMulticastMaskB
);
2967 writel(pff
, base
+ NvRegPacketFilterFlags
);
2968 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
2971 spin_unlock_irq(&np
->lock
);
2974 static void nv_update_pause(struct net_device
*dev
, u32 pause_flags
)
2976 struct fe_priv
*np
= netdev_priv(dev
);
2977 u8 __iomem
*base
= get_hwbase(dev
);
2979 np
->pause_flags
&= ~(NV_PAUSEFRAME_TX_ENABLE
| NV_PAUSEFRAME_RX_ENABLE
);
2981 if (np
->pause_flags
& NV_PAUSEFRAME_RX_CAPABLE
) {
2982 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & ~NVREG_PFF_PAUSE_RX
;
2983 if (pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) {
2984 writel(pff
|NVREG_PFF_PAUSE_RX
, base
+ NvRegPacketFilterFlags
);
2985 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
2987 writel(pff
, base
+ NvRegPacketFilterFlags
);
2990 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
) {
2991 u32 regmisc
= readl(base
+ NvRegMisc1
) & ~NVREG_MISC1_PAUSE_TX
;
2992 if (pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) {
2993 u32 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V1
;
2994 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
)
2995 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V2
;
2996 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
)
2997 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V3
;
2998 writel(pause_enable
, base
+ NvRegTxPauseFrame
);
2999 writel(regmisc
|NVREG_MISC1_PAUSE_TX
, base
+ NvRegMisc1
);
3000 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3002 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
3003 writel(regmisc
, base
+ NvRegMisc1
);
3009 * nv_update_linkspeed: Setup the MAC according to the link partner
3010 * @dev: Network device to be configured
3012 * The function queries the PHY and checks if there is a link partner.
3013 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3014 * set to 10 MBit HD.
3016 * The function returns 0 if there is no link partner and 1 if there is
3017 * a good link partner.
3019 static int nv_update_linkspeed(struct net_device
*dev
)
3021 struct fe_priv
*np
= netdev_priv(dev
);
3022 u8 __iomem
*base
= get_hwbase(dev
);
3025 int adv_lpa
, adv_pause
, lpa_pause
;
3026 int newls
= np
->linkspeed
;
3027 int newdup
= np
->duplex
;
3030 u32 control_1000
, status_1000
, phyreg
, pause_flags
, txreg
;
3034 /* BMSR_LSTATUS is latched, read it twice:
3035 * we want the current value.
3037 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3038 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3040 if (!(mii_status
& BMSR_LSTATUS
)) {
3041 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
3043 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3049 if (np
->autoneg
== 0) {
3050 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3051 dev
->name
, np
->fixed_mode
);
3052 if (np
->fixed_mode
& LPA_100FULL
) {
3053 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3055 } else if (np
->fixed_mode
& LPA_100HALF
) {
3056 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3058 } else if (np
->fixed_mode
& LPA_10FULL
) {
3059 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3062 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3068 /* check auto negotiation is complete */
3069 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
3070 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3071 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3074 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
3078 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3079 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
3080 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3081 dev
->name
, adv
, lpa
);
3084 if (np
->gigabit
== PHY_GIGABIT
) {
3085 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3086 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_STAT1000
, MII_READ
);
3088 if ((control_1000
& ADVERTISE_1000FULL
) &&
3089 (status_1000
& LPA_1000FULL
)) {
3090 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
3092 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
3098 /* FIXME: handle parallel detection properly */
3099 adv_lpa
= lpa
& adv
;
3100 if (adv_lpa
& LPA_100FULL
) {
3101 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3103 } else if (adv_lpa
& LPA_100HALF
) {
3104 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3106 } else if (adv_lpa
& LPA_10FULL
) {
3107 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3109 } else if (adv_lpa
& LPA_10HALF
) {
3110 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3113 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, adv_lpa
);
3114 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3119 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
3122 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
3123 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
3125 np
->duplex
= newdup
;
3126 np
->linkspeed
= newls
;
3128 /* The transmitter and receiver must be restarted for safe update */
3129 if (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
) {
3130 txrxFlags
|= NV_RESTART_TX
;
3133 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
3134 txrxFlags
|= NV_RESTART_RX
;
3138 if (np
->gigabit
== PHY_GIGABIT
) {
3139 phyreg
= readl(base
+ NvRegSlotTime
);
3140 phyreg
&= ~(0x3FF00);
3141 if (((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
) ||
3142 ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
))
3143 phyreg
|= NVREG_SLOTTIME_10_100_FULL
;
3144 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
3145 phyreg
|= NVREG_SLOTTIME_1000_FULL
;
3146 writel(phyreg
, base
+ NvRegSlotTime
);
3149 phyreg
= readl(base
+ NvRegPhyInterface
);
3150 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
3151 if (np
->duplex
== 0)
3153 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
3155 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3157 writel(phyreg
, base
+ NvRegPhyInterface
);
3159 phy_exp
= mii_rw(dev
, np
->phyaddr
, MII_EXPANSION
, MII_READ
) & EXPANSION_NWAY
; /* autoneg capable */
3160 if (phyreg
& PHY_RGMII
) {
3161 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
) {
3162 txreg
= NVREG_TX_DEFERRAL_RGMII_1000
;
3164 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
)) {
3165 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_10
)
3166 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_10
;
3168 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_100
;
3170 txreg
= NVREG_TX_DEFERRAL_RGMII_10_100
;
3174 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
))
3175 txreg
= NVREG_TX_DEFERRAL_MII_STRETCH
;
3177 txreg
= NVREG_TX_DEFERRAL_DEFAULT
;
3179 writel(txreg
, base
+ NvRegTxDeferral
);
3181 if (np
->desc_ver
== DESC_VER_1
) {
3182 txreg
= NVREG_TX_WM_DESC1_DEFAULT
;
3184 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3185 txreg
= NVREG_TX_WM_DESC2_3_1000
;
3187 txreg
= NVREG_TX_WM_DESC2_3_DEFAULT
;
3189 writel(txreg
, base
+ NvRegTxWatermark
);
3191 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
3194 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
3198 /* setup pause frame */
3199 if (np
->duplex
!= 0) {
3200 if (np
->autoneg
&& np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) {
3201 adv_pause
= adv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3202 lpa_pause
= lpa
& (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
);
3204 switch (adv_pause
) {
3205 case ADVERTISE_PAUSE_CAP
:
3206 if (lpa_pause
& LPA_PAUSE_CAP
) {
3207 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3208 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3209 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3212 case ADVERTISE_PAUSE_ASYM
:
3213 if (lpa_pause
== (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
))
3215 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3218 case ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
:
3219 if (lpa_pause
& LPA_PAUSE_CAP
)
3221 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3222 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3223 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3225 if (lpa_pause
== LPA_PAUSE_ASYM
)
3227 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3232 pause_flags
= np
->pause_flags
;
3235 nv_update_pause(dev
, pause_flags
);
3237 if (txrxFlags
& NV_RESTART_TX
)
3239 if (txrxFlags
& NV_RESTART_RX
)
3245 static void nv_linkchange(struct net_device
*dev
)
3247 if (nv_update_linkspeed(dev
)) {
3248 if (!netif_carrier_ok(dev
)) {
3249 netif_carrier_on(dev
);
3250 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
3254 if (netif_carrier_ok(dev
)) {
3255 netif_carrier_off(dev
);
3256 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
3262 static void nv_link_irq(struct net_device
*dev
)
3264 u8 __iomem
*base
= get_hwbase(dev
);
3267 miistat
= readl(base
+ NvRegMIIStatus
);
3268 writel(NVREG_MIISTAT_LINKCHANGE
, base
+ NvRegMIIStatus
);
3269 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
3271 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
3273 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
3276 static void nv_msi_workaround(struct fe_priv
*np
)
3279 /* Need to toggle the msi irq mask within the ethernet device,
3280 * otherwise, future interrupts will not be detected.
3282 if (np
->msi_flags
& NV_MSI_ENABLED
) {
3283 u8 __iomem
*base
= np
->base
;
3285 writel(0, base
+ NvRegMSIIrqMask
);
3286 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
3290 static irqreturn_t
nv_nic_irq(int foo
, void *data
)
3292 struct net_device
*dev
= (struct net_device
*) data
;
3293 struct fe_priv
*np
= netdev_priv(dev
);
3294 u8 __iomem
*base
= get_hwbase(dev
);
3298 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
3301 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3302 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3303 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
3305 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3306 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
3308 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3309 if (!(events
& np
->irqmask
))
3312 nv_msi_workaround(np
);
3314 spin_lock(&np
->lock
);
3316 spin_unlock(&np
->lock
);
3318 #ifdef CONFIG_FORCEDETH_NAPI
3319 if (events
& NVREG_IRQ_RX_ALL
) {
3320 netif_rx_schedule(dev
, &np
->napi
);
3322 /* Disable furthur receive irq's */
3323 spin_lock(&np
->lock
);
3324 np
->irqmask
&= ~NVREG_IRQ_RX_ALL
;
3326 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3327 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3329 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3330 spin_unlock(&np
->lock
);
3333 if (nv_rx_process(dev
, RX_WORK_PER_LOOP
)) {
3334 if (unlikely(nv_alloc_rx(dev
))) {
3335 spin_lock(&np
->lock
);
3336 if (!np
->in_shutdown
)
3337 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3338 spin_unlock(&np
->lock
);
3342 if (unlikely(events
& NVREG_IRQ_LINK
)) {
3343 spin_lock(&np
->lock
);
3345 spin_unlock(&np
->lock
);
3347 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3348 spin_lock(&np
->lock
);
3350 spin_unlock(&np
->lock
);
3351 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3353 if (unlikely(events
& (NVREG_IRQ_TX_ERR
))) {
3354 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
3357 if (unlikely(events
& (NVREG_IRQ_UNKNOWN
))) {
3358 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
3361 if (unlikely(events
& NVREG_IRQ_RECOVER_ERROR
)) {
3362 spin_lock(&np
->lock
);
3363 /* disable interrupts on the nic */
3364 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3365 writel(0, base
+ NvRegIrqMask
);
3367 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3370 if (!np
->in_shutdown
) {
3371 np
->nic_poll_irq
= np
->irqmask
;
3372 np
->recover_error
= 1;
3373 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3375 spin_unlock(&np
->lock
);
3378 if (unlikely(i
> max_interrupt_work
)) {
3379 spin_lock(&np
->lock
);
3380 /* disable interrupts on the nic */
3381 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3382 writel(0, base
+ NvRegIrqMask
);
3384 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3387 if (!np
->in_shutdown
) {
3388 np
->nic_poll_irq
= np
->irqmask
;
3389 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3391 spin_unlock(&np
->lock
);
3392 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
3397 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
3399 return IRQ_RETVAL(i
);
3403 * All _optimized functions are used to help increase performance
3404 * (reduce CPU and increase throughput). They use descripter version 3,
3405 * compiler directives, and reduce memory accesses.
3407 static irqreturn_t
nv_nic_irq_optimized(int foo
, void *data
)
3409 struct net_device
*dev
= (struct net_device
*) data
;
3410 struct fe_priv
*np
= netdev_priv(dev
);
3411 u8 __iomem
*base
= get_hwbase(dev
);
3415 dprintk(KERN_DEBUG
"%s: nv_nic_irq_optimized\n", dev
->name
);
3418 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3419 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3420 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
3422 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3423 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
3425 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3426 if (!(events
& np
->irqmask
))
3429 nv_msi_workaround(np
);
3431 spin_lock(&np
->lock
);
3432 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3433 spin_unlock(&np
->lock
);
3435 #ifdef CONFIG_FORCEDETH_NAPI
3436 if (events
& NVREG_IRQ_RX_ALL
) {
3437 netif_rx_schedule(dev
, &np
->napi
);
3439 /* Disable furthur receive irq's */
3440 spin_lock(&np
->lock
);
3441 np
->irqmask
&= ~NVREG_IRQ_RX_ALL
;
3443 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3444 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3446 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3447 spin_unlock(&np
->lock
);
3450 if (nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
)) {
3451 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3452 spin_lock(&np
->lock
);
3453 if (!np
->in_shutdown
)
3454 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3455 spin_unlock(&np
->lock
);
3459 if (unlikely(events
& NVREG_IRQ_LINK
)) {
3460 spin_lock(&np
->lock
);
3462 spin_unlock(&np
->lock
);
3464 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3465 spin_lock(&np
->lock
);
3467 spin_unlock(&np
->lock
);
3468 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3470 if (unlikely(events
& (NVREG_IRQ_TX_ERR
))) {
3471 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
3474 if (unlikely(events
& (NVREG_IRQ_UNKNOWN
))) {
3475 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
3478 if (unlikely(events
& NVREG_IRQ_RECOVER_ERROR
)) {
3479 spin_lock(&np
->lock
);
3480 /* disable interrupts on the nic */
3481 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3482 writel(0, base
+ NvRegIrqMask
);
3484 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3487 if (!np
->in_shutdown
) {
3488 np
->nic_poll_irq
= np
->irqmask
;
3489 np
->recover_error
= 1;
3490 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3492 spin_unlock(&np
->lock
);
3496 if (unlikely(i
> max_interrupt_work
)) {
3497 spin_lock(&np
->lock
);
3498 /* disable interrupts on the nic */
3499 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3500 writel(0, base
+ NvRegIrqMask
);
3502 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3505 if (!np
->in_shutdown
) {
3506 np
->nic_poll_irq
= np
->irqmask
;
3507 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3509 spin_unlock(&np
->lock
);
3510 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
3515 dprintk(KERN_DEBUG
"%s: nv_nic_irq_optimized completed\n", dev
->name
);
3517 return IRQ_RETVAL(i
);
3520 static irqreturn_t
nv_nic_irq_tx(int foo
, void *data
)
3522 struct net_device
*dev
= (struct net_device
*) data
;
3523 struct fe_priv
*np
= netdev_priv(dev
);
3524 u8 __iomem
*base
= get_hwbase(dev
);
3527 unsigned long flags
;
3529 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx\n", dev
->name
);
3532 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_TX_ALL
;
3533 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegMSIXIrqStatus
);
3534 dprintk(KERN_DEBUG
"%s: tx irq: %08x\n", dev
->name
, events
);
3535 if (!(events
& np
->irqmask
))
3538 spin_lock_irqsave(&np
->lock
, flags
);
3539 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3540 spin_unlock_irqrestore(&np
->lock
, flags
);
3542 if (unlikely(events
& (NVREG_IRQ_TX_ERR
))) {
3543 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
3546 if (unlikely(i
> max_interrupt_work
)) {
3547 spin_lock_irqsave(&np
->lock
, flags
);
3548 /* disable interrupts on the nic */
3549 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegIrqMask
);
3552 if (!np
->in_shutdown
) {
3553 np
->nic_poll_irq
|= NVREG_IRQ_TX_ALL
;
3554 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3556 spin_unlock_irqrestore(&np
->lock
, flags
);
3557 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev
->name
, i
);
3562 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx completed\n", dev
->name
);
3564 return IRQ_RETVAL(i
);
3567 #ifdef CONFIG_FORCEDETH_NAPI
3568 static int nv_napi_poll(struct napi_struct
*napi
, int budget
)
3570 struct fe_priv
*np
= container_of(napi
, struct fe_priv
, napi
);
3571 struct net_device
*dev
= np
->dev
;
3572 u8 __iomem
*base
= get_hwbase(dev
);
3573 unsigned long flags
;
3576 if (!nv_optimized(np
)) {
3577 pkts
= nv_rx_process(dev
, budget
);
3578 retcode
= nv_alloc_rx(dev
);
3580 pkts
= nv_rx_process_optimized(dev
, budget
);
3581 retcode
= nv_alloc_rx_optimized(dev
);
3585 spin_lock_irqsave(&np
->lock
, flags
);
3586 if (!np
->in_shutdown
)
3587 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3588 spin_unlock_irqrestore(&np
->lock
, flags
);
3591 if (pkts
< budget
) {
3592 /* re-enable receive interrupts */
3593 spin_lock_irqsave(&np
->lock
, flags
);
3595 __netif_rx_complete(dev
, napi
);
3597 np
->irqmask
|= NVREG_IRQ_RX_ALL
;
3598 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3599 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3601 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3603 spin_unlock_irqrestore(&np
->lock
, flags
);
3609 #ifdef CONFIG_FORCEDETH_NAPI
3610 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
3612 struct net_device
*dev
= (struct net_device
*) data
;
3613 struct fe_priv
*np
= netdev_priv(dev
);
3614 u8 __iomem
*base
= get_hwbase(dev
);
3617 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
3618 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
3621 netif_rx_schedule(dev
, &np
->napi
);
3622 /* disable receive interrupts on the nic */
3623 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3629 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
3631 struct net_device
*dev
= (struct net_device
*) data
;
3632 struct fe_priv
*np
= netdev_priv(dev
);
3633 u8 __iomem
*base
= get_hwbase(dev
);
3636 unsigned long flags
;
3638 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx\n", dev
->name
);
3641 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
3642 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
3643 dprintk(KERN_DEBUG
"%s: rx irq: %08x\n", dev
->name
, events
);
3644 if (!(events
& np
->irqmask
))
3647 if (nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
)) {
3648 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3649 spin_lock_irqsave(&np
->lock
, flags
);
3650 if (!np
->in_shutdown
)
3651 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3652 spin_unlock_irqrestore(&np
->lock
, flags
);
3656 if (unlikely(i
> max_interrupt_work
)) {
3657 spin_lock_irqsave(&np
->lock
, flags
);
3658 /* disable interrupts on the nic */
3659 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3662 if (!np
->in_shutdown
) {
3663 np
->nic_poll_irq
|= NVREG_IRQ_RX_ALL
;
3664 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3666 spin_unlock_irqrestore(&np
->lock
, flags
);
3667 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev
->name
, i
);
3671 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx completed\n", dev
->name
);
3673 return IRQ_RETVAL(i
);
3677 static irqreturn_t
nv_nic_irq_other(int foo
, void *data
)
3679 struct net_device
*dev
= (struct net_device
*) data
;
3680 struct fe_priv
*np
= netdev_priv(dev
);
3681 u8 __iomem
*base
= get_hwbase(dev
);
3684 unsigned long flags
;
3686 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other\n", dev
->name
);
3689 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_OTHER
;
3690 writel(NVREG_IRQ_OTHER
, base
+ NvRegMSIXIrqStatus
);
3691 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3692 if (!(events
& np
->irqmask
))
3695 /* check tx in case we reached max loop limit in tx isr */
3696 spin_lock_irqsave(&np
->lock
, flags
);
3697 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3698 spin_unlock_irqrestore(&np
->lock
, flags
);
3700 if (events
& NVREG_IRQ_LINK
) {
3701 spin_lock_irqsave(&np
->lock
, flags
);
3703 spin_unlock_irqrestore(&np
->lock
, flags
);
3705 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
3706 spin_lock_irqsave(&np
->lock
, flags
);
3708 spin_unlock_irqrestore(&np
->lock
, flags
);
3709 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3711 if (events
& NVREG_IRQ_RECOVER_ERROR
) {
3712 spin_lock_irq(&np
->lock
);
3713 /* disable interrupts on the nic */
3714 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3717 if (!np
->in_shutdown
) {
3718 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3719 np
->recover_error
= 1;
3720 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3722 spin_unlock_irq(&np
->lock
);
3725 if (events
& (NVREG_IRQ_UNKNOWN
)) {
3726 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
3729 if (unlikely(i
> max_interrupt_work
)) {
3730 spin_lock_irqsave(&np
->lock
, flags
);
3731 /* disable interrupts on the nic */
3732 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3735 if (!np
->in_shutdown
) {
3736 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3737 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3739 spin_unlock_irqrestore(&np
->lock
, flags
);
3740 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_other.\n", dev
->name
, i
);
3745 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other completed\n", dev
->name
);
3747 return IRQ_RETVAL(i
);
3750 static irqreturn_t
nv_nic_irq_test(int foo
, void *data
)
3752 struct net_device
*dev
= (struct net_device
*) data
;
3753 struct fe_priv
*np
= netdev_priv(dev
);
3754 u8 __iomem
*base
= get_hwbase(dev
);
3757 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test\n", dev
->name
);
3759 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3760 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3761 writel(NVREG_IRQ_TIMER
, base
+ NvRegIrqStatus
);
3763 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3764 writel(NVREG_IRQ_TIMER
, base
+ NvRegMSIXIrqStatus
);
3767 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3768 if (!(events
& NVREG_IRQ_TIMER
))
3769 return IRQ_RETVAL(0);
3771 nv_msi_workaround(np
);
3773 spin_lock(&np
->lock
);
3775 spin_unlock(&np
->lock
);
3777 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test completed\n", dev
->name
);
3779 return IRQ_RETVAL(1);
3782 static void set_msix_vector_map(struct net_device
*dev
, u32 vector
, u32 irqmask
)
3784 u8 __iomem
*base
= get_hwbase(dev
);
3788 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3789 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3790 * the remaining 8 interrupts.
3792 for (i
= 0; i
< 8; i
++) {
3793 if ((irqmask
>> i
) & 0x1) {
3794 msixmap
|= vector
<< (i
<< 2);
3797 writel(readl(base
+ NvRegMSIXMap0
) | msixmap
, base
+ NvRegMSIXMap0
);
3800 for (i
= 0; i
< 8; i
++) {
3801 if ((irqmask
>> (i
+ 8)) & 0x1) {
3802 msixmap
|= vector
<< (i
<< 2);
3805 writel(readl(base
+ NvRegMSIXMap1
) | msixmap
, base
+ NvRegMSIXMap1
);
3808 static int nv_request_irq(struct net_device
*dev
, int intr_test
)
3810 struct fe_priv
*np
= get_nvpriv(dev
);
3811 u8 __iomem
*base
= get_hwbase(dev
);
3814 irqreturn_t (*handler
)(int foo
, void *data
);
3817 handler
= nv_nic_irq_test
;
3819 if (nv_optimized(np
))
3820 handler
= nv_nic_irq_optimized
;
3822 handler
= nv_nic_irq
;
3825 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) {
3826 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
3827 np
->msi_x_entry
[i
].entry
= i
;
3829 if ((ret
= pci_enable_msix(np
->pci_dev
, np
->msi_x_entry
, (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
))) == 0) {
3830 np
->msi_flags
|= NV_MSI_X_ENABLED
;
3831 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
&& !intr_test
) {
3832 /* Request irq for rx handling */
3833 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, &nv_nic_irq_rx
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3834 printk(KERN_INFO
"forcedeth: request_irq failed for rx %d\n", ret
);
3835 pci_disable_msix(np
->pci_dev
);
3836 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3839 /* Request irq for tx handling */
3840 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, &nv_nic_irq_tx
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3841 printk(KERN_INFO
"forcedeth: request_irq failed for tx %d\n", ret
);
3842 pci_disable_msix(np
->pci_dev
);
3843 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3846 /* Request irq for link and timer handling */
3847 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
, &nv_nic_irq_other
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3848 printk(KERN_INFO
"forcedeth: request_irq failed for link %d\n", ret
);
3849 pci_disable_msix(np
->pci_dev
);
3850 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3853 /* map interrupts to their respective vector */
3854 writel(0, base
+ NvRegMSIXMap0
);
3855 writel(0, base
+ NvRegMSIXMap1
);
3856 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_RX
, NVREG_IRQ_RX_ALL
);
3857 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_TX
, NVREG_IRQ_TX_ALL
);
3858 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_OTHER
, NVREG_IRQ_OTHER
);
3860 /* Request irq for all interrupts */
3861 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3862 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
3863 pci_disable_msix(np
->pci_dev
);
3864 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3868 /* map interrupts to vector 0 */
3869 writel(0, base
+ NvRegMSIXMap0
);
3870 writel(0, base
+ NvRegMSIXMap1
);
3874 if (ret
!= 0 && np
->msi_flags
& NV_MSI_CAPABLE
) {
3875 if ((ret
= pci_enable_msi(np
->pci_dev
)) == 0) {
3876 np
->msi_flags
|= NV_MSI_ENABLED
;
3877 dev
->irq
= np
->pci_dev
->irq
;
3878 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3879 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
3880 pci_disable_msi(np
->pci_dev
);
3881 np
->msi_flags
&= ~NV_MSI_ENABLED
;
3882 dev
->irq
= np
->pci_dev
->irq
;
3886 /* map interrupts to vector 0 */
3887 writel(0, base
+ NvRegMSIMap0
);
3888 writel(0, base
+ NvRegMSIMap1
);
3889 /* enable msi vector 0 */
3890 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
3894 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0)
3901 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, dev
);
3903 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, dev
);
3908 static void nv_free_irq(struct net_device
*dev
)
3910 struct fe_priv
*np
= get_nvpriv(dev
);
3913 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
3914 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
3915 free_irq(np
->msi_x_entry
[i
].vector
, dev
);
3917 pci_disable_msix(np
->pci_dev
);
3918 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3920 free_irq(np
->pci_dev
->irq
, dev
);
3921 if (np
->msi_flags
& NV_MSI_ENABLED
) {
3922 pci_disable_msi(np
->pci_dev
);
3923 np
->msi_flags
&= ~NV_MSI_ENABLED
;
3928 static void nv_do_nic_poll(unsigned long data
)
3930 struct net_device
*dev
= (struct net_device
*) data
;
3931 struct fe_priv
*np
= netdev_priv(dev
);
3932 u8 __iomem
*base
= get_hwbase(dev
);
3936 * First disable irq(s) and then
3937 * reenable interrupts on the nic, we have to do this before calling
3938 * nv_nic_irq because that may decide to do otherwise
3941 if (!using_multi_irqs(dev
)) {
3942 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3943 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
3945 disable_irq_lockdep(np
->pci_dev
->irq
);
3948 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
3949 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
3950 mask
|= NVREG_IRQ_RX_ALL
;
3952 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
3953 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
3954 mask
|= NVREG_IRQ_TX_ALL
;
3956 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
3957 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
3958 mask
|= NVREG_IRQ_OTHER
;
3961 np
->nic_poll_irq
= 0;
3963 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3965 if (np
->recover_error
) {
3966 np
->recover_error
= 0;
3967 printk(KERN_INFO
"forcedeth: MAC in recoverable error state\n");
3968 if (netif_running(dev
)) {
3969 netif_tx_lock_bh(dev
);
3970 spin_lock(&np
->lock
);
3974 /* drain rx queue */
3976 /* reinit driver view of the rx queue */
3978 if (nv_init_ring(dev
)) {
3979 if (!np
->in_shutdown
)
3980 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3982 /* reinit nic view of the rx queue */
3983 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
3984 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3985 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3986 base
+ NvRegRingSizes
);
3988 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3991 /* restart rx engine */
3993 spin_unlock(&np
->lock
);
3994 netif_tx_unlock_bh(dev
);
3999 writel(mask
, base
+ NvRegIrqMask
);
4002 if (!using_multi_irqs(dev
)) {
4003 if (nv_optimized(np
))
4004 nv_nic_irq_optimized(0, dev
);
4007 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
4008 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
4010 enable_irq_lockdep(np
->pci_dev
->irq
);
4012 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4013 nv_nic_irq_rx(0, dev
);
4014 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
4016 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4017 nv_nic_irq_tx(0, dev
);
4018 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
4020 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4021 nv_nic_irq_other(0, dev
);
4022 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
4027 #ifdef CONFIG_NET_POLL_CONTROLLER
4028 static void nv_poll_controller(struct net_device
*dev
)
4030 nv_do_nic_poll((unsigned long) dev
);
4034 static void nv_do_stats_poll(unsigned long data
)
4036 struct net_device
*dev
= (struct net_device
*) data
;
4037 struct fe_priv
*np
= netdev_priv(dev
);
4039 nv_get_hw_stats(dev
);
4041 if (!np
->in_shutdown
)
4042 mod_timer(&np
->stats_poll
,
4043 round_jiffies(jiffies
+ STATS_INTERVAL
));
4046 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
4048 struct fe_priv
*np
= netdev_priv(dev
);
4049 strcpy(info
->driver
, DRV_NAME
);
4050 strcpy(info
->version
, FORCEDETH_VERSION
);
4051 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
4054 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4056 struct fe_priv
*np
= netdev_priv(dev
);
4057 wolinfo
->supported
= WAKE_MAGIC
;
4059 spin_lock_irq(&np
->lock
);
4061 wolinfo
->wolopts
= WAKE_MAGIC
;
4062 spin_unlock_irq(&np
->lock
);
4065 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4067 struct fe_priv
*np
= netdev_priv(dev
);
4068 u8 __iomem
*base
= get_hwbase(dev
);
4071 if (wolinfo
->wolopts
== 0) {
4073 } else if (wolinfo
->wolopts
& WAKE_MAGIC
) {
4075 flags
= NVREG_WAKEUPFLAGS_ENABLE
;
4077 if (netif_running(dev
)) {
4078 spin_lock_irq(&np
->lock
);
4079 writel(flags
, base
+ NvRegWakeUpFlags
);
4080 spin_unlock_irq(&np
->lock
);
4085 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4087 struct fe_priv
*np
= netdev_priv(dev
);
4090 spin_lock_irq(&np
->lock
);
4091 ecmd
->port
= PORT_MII
;
4092 if (!netif_running(dev
)) {
4093 /* We do not track link speed / duplex setting if the
4094 * interface is disabled. Force a link check */
4095 if (nv_update_linkspeed(dev
)) {
4096 if (!netif_carrier_ok(dev
))
4097 netif_carrier_on(dev
);
4099 if (netif_carrier_ok(dev
))
4100 netif_carrier_off(dev
);
4104 if (netif_carrier_ok(dev
)) {
4105 switch(np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
4106 case NVREG_LINKSPEED_10
:
4107 ecmd
->speed
= SPEED_10
;
4109 case NVREG_LINKSPEED_100
:
4110 ecmd
->speed
= SPEED_100
;
4112 case NVREG_LINKSPEED_1000
:
4113 ecmd
->speed
= SPEED_1000
;
4116 ecmd
->duplex
= DUPLEX_HALF
;
4118 ecmd
->duplex
= DUPLEX_FULL
;
4124 ecmd
->autoneg
= np
->autoneg
;
4126 ecmd
->advertising
= ADVERTISED_MII
;
4128 ecmd
->advertising
|= ADVERTISED_Autoneg
;
4129 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4130 if (adv
& ADVERTISE_10HALF
)
4131 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
4132 if (adv
& ADVERTISE_10FULL
)
4133 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
4134 if (adv
& ADVERTISE_100HALF
)
4135 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
4136 if (adv
& ADVERTISE_100FULL
)
4137 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
4138 if (np
->gigabit
== PHY_GIGABIT
) {
4139 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4140 if (adv
& ADVERTISE_1000FULL
)
4141 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
4144 ecmd
->supported
= (SUPPORTED_Autoneg
|
4145 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
4146 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
4148 if (np
->gigabit
== PHY_GIGABIT
)
4149 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
4151 ecmd
->phy_address
= np
->phyaddr
;
4152 ecmd
->transceiver
= XCVR_EXTERNAL
;
4154 /* ignore maxtxpkt, maxrxpkt for now */
4155 spin_unlock_irq(&np
->lock
);
4159 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4161 struct fe_priv
*np
= netdev_priv(dev
);
4163 if (ecmd
->port
!= PORT_MII
)
4165 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
4167 if (ecmd
->phy_address
!= np
->phyaddr
) {
4168 /* TODO: support switching between multiple phys. Should be
4169 * trivial, but not enabled due to lack of test hardware. */
4172 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4175 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4176 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
4177 if (np
->gigabit
== PHY_GIGABIT
)
4178 mask
|= ADVERTISED_1000baseT_Full
;
4180 if ((ecmd
->advertising
& mask
) == 0)
4183 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
4184 /* Note: autonegotiation disable, speed 1000 intentionally
4185 * forbidden - noone should need that. */
4187 if (ecmd
->speed
!= SPEED_10
&& ecmd
->speed
!= SPEED_100
)
4189 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
4195 netif_carrier_off(dev
);
4196 if (netif_running(dev
)) {
4197 unsigned long flags
;
4199 nv_disable_irq(dev
);
4200 netif_tx_lock_bh(dev
);
4201 /* with plain spinlock lockdep complains */
4202 spin_lock_irqsave(&np
->lock
, flags
);
4205 * this can take some time, and interrupts are disabled
4206 * due to spin_lock_irqsave, but let's hope no daemon
4207 * is going to change the settings very often...
4209 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4210 * + some minor delays, which is up to a second approximately
4213 spin_unlock_irqrestore(&np
->lock
, flags
);
4214 netif_tx_unlock_bh(dev
);
4217 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4222 /* advertise only what has been requested */
4223 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4224 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4225 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
4226 adv
|= ADVERTISE_10HALF
;
4227 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
4228 adv
|= ADVERTISE_10FULL
;
4229 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
4230 adv
|= ADVERTISE_100HALF
;
4231 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
4232 adv
|= ADVERTISE_100FULL
;
4233 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
4234 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4235 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4236 adv
|= ADVERTISE_PAUSE_ASYM
;
4237 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4239 if (np
->gigabit
== PHY_GIGABIT
) {
4240 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4241 adv
&= ~ADVERTISE_1000FULL
;
4242 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
4243 adv
|= ADVERTISE_1000FULL
;
4244 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4247 if (netif_running(dev
))
4248 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4249 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4250 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4251 bmcr
|= BMCR_ANENABLE
;
4252 /* reset the phy in order for settings to stick,
4253 * and cause autoneg to start */
4254 if (phy_reset(dev
, bmcr
)) {
4255 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4259 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4260 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4267 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4268 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4269 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
4270 adv
|= ADVERTISE_10HALF
;
4271 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
4272 adv
|= ADVERTISE_10FULL
;
4273 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
4274 adv
|= ADVERTISE_100HALF
;
4275 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
4276 adv
|= ADVERTISE_100FULL
;
4277 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4278 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) {/* for rx we set both advertisments but disable tx pause */
4279 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4280 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4282 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
) {
4283 adv
|= ADVERTISE_PAUSE_ASYM
;
4284 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4286 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4287 np
->fixed_mode
= adv
;
4289 if (np
->gigabit
== PHY_GIGABIT
) {
4290 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4291 adv
&= ~ADVERTISE_1000FULL
;
4292 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4295 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4296 bmcr
&= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_SPEED1000
|BMCR_FULLDPLX
);
4297 if (np
->fixed_mode
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
4298 bmcr
|= BMCR_FULLDPLX
;
4299 if (np
->fixed_mode
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
4300 bmcr
|= BMCR_SPEED100
;
4301 if (np
->phy_oui
== PHY_OUI_MARVELL
) {
4302 /* reset the phy in order for forced mode settings to stick */
4303 if (phy_reset(dev
, bmcr
)) {
4304 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4308 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4309 if (netif_running(dev
)) {
4310 /* Wait a bit and then reconfigure the nic. */
4317 if (netif_running(dev
)) {
4325 #define FORCEDETH_REGS_VER 1
4327 static int nv_get_regs_len(struct net_device
*dev
)
4329 struct fe_priv
*np
= netdev_priv(dev
);
4330 return np
->register_size
;
4333 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
4335 struct fe_priv
*np
= netdev_priv(dev
);
4336 u8 __iomem
*base
= get_hwbase(dev
);
4340 regs
->version
= FORCEDETH_REGS_VER
;
4341 spin_lock_irq(&np
->lock
);
4342 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
4343 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
4344 spin_unlock_irq(&np
->lock
);
4347 static int nv_nway_reset(struct net_device
*dev
)
4349 struct fe_priv
*np
= netdev_priv(dev
);
4355 netif_carrier_off(dev
);
4356 if (netif_running(dev
)) {
4357 nv_disable_irq(dev
);
4358 netif_tx_lock_bh(dev
);
4359 spin_lock(&np
->lock
);
4362 spin_unlock(&np
->lock
);
4363 netif_tx_unlock_bh(dev
);
4364 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4367 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4368 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4369 bmcr
|= BMCR_ANENABLE
;
4370 /* reset the phy in order for settings to stick*/
4371 if (phy_reset(dev
, bmcr
)) {
4372 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4376 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4377 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4380 if (netif_running(dev
)) {
4392 static int nv_set_tso(struct net_device
*dev
, u32 value
)
4394 struct fe_priv
*np
= netdev_priv(dev
);
4396 if ((np
->driver_data
& DEV_HAS_CHECKSUM
))
4397 return ethtool_op_set_tso(dev
, value
);
4402 static void nv_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4404 struct fe_priv
*np
= netdev_priv(dev
);
4406 ring
->rx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4407 ring
->rx_mini_max_pending
= 0;
4408 ring
->rx_jumbo_max_pending
= 0;
4409 ring
->tx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4411 ring
->rx_pending
= np
->rx_ring_size
;
4412 ring
->rx_mini_pending
= 0;
4413 ring
->rx_jumbo_pending
= 0;
4414 ring
->tx_pending
= np
->tx_ring_size
;
4417 static int nv_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4419 struct fe_priv
*np
= netdev_priv(dev
);
4420 u8 __iomem
*base
= get_hwbase(dev
);
4421 u8
*rxtx_ring
, *rx_skbuff
, *tx_skbuff
;
4422 dma_addr_t ring_addr
;
4424 if (ring
->rx_pending
< RX_RING_MIN
||
4425 ring
->tx_pending
< TX_RING_MIN
||
4426 ring
->rx_mini_pending
!= 0 ||
4427 ring
->rx_jumbo_pending
!= 0 ||
4428 (np
->desc_ver
== DESC_VER_1
&&
4429 (ring
->rx_pending
> RING_MAX_DESC_VER_1
||
4430 ring
->tx_pending
> RING_MAX_DESC_VER_1
)) ||
4431 (np
->desc_ver
!= DESC_VER_1
&&
4432 (ring
->rx_pending
> RING_MAX_DESC_VER_2_3
||
4433 ring
->tx_pending
> RING_MAX_DESC_VER_2_3
))) {
4437 /* allocate new rings */
4438 if (!nv_optimized(np
)) {
4439 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4440 sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4443 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4444 sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4447 rx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->rx_pending
, GFP_KERNEL
);
4448 tx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->tx_pending
, GFP_KERNEL
);
4449 if (!rxtx_ring
|| !rx_skbuff
|| !tx_skbuff
) {
4450 /* fall back to old rings */
4451 if (!nv_optimized(np
)) {
4453 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4454 rxtx_ring
, ring_addr
);
4457 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4458 rxtx_ring
, ring_addr
);
4467 if (netif_running(dev
)) {
4468 nv_disable_irq(dev
);
4469 netif_tx_lock_bh(dev
);
4470 spin_lock(&np
->lock
);
4480 /* set new values */
4481 np
->rx_ring_size
= ring
->rx_pending
;
4482 np
->tx_ring_size
= ring
->tx_pending
;
4484 if (!nv_optimized(np
)) {
4485 np
->rx_ring
.orig
= (struct ring_desc
*)rxtx_ring
;
4486 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
4488 np
->rx_ring
.ex
= (struct ring_desc_ex
*)rxtx_ring
;
4489 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
4491 np
->rx_skb
= (struct nv_skb_map
*)rx_skbuff
;
4492 np
->tx_skb
= (struct nv_skb_map
*)tx_skbuff
;
4493 np
->ring_addr
= ring_addr
;
4495 memset(np
->rx_skb
, 0, sizeof(struct nv_skb_map
) * np
->rx_ring_size
);
4496 memset(np
->tx_skb
, 0, sizeof(struct nv_skb_map
) * np
->tx_ring_size
);
4498 if (netif_running(dev
)) {
4499 /* reinit driver view of the queues */
4501 if (nv_init_ring(dev
)) {
4502 if (!np
->in_shutdown
)
4503 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4506 /* reinit nic view of the queues */
4507 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4508 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4509 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4510 base
+ NvRegRingSizes
);
4512 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4515 /* restart engines */
4517 spin_unlock(&np
->lock
);
4518 netif_tx_unlock_bh(dev
);
4526 static void nv_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4528 struct fe_priv
*np
= netdev_priv(dev
);
4530 pause
->autoneg
= (np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) != 0;
4531 pause
->rx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) != 0;
4532 pause
->tx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) != 0;
4535 static int nv_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4537 struct fe_priv
*np
= netdev_priv(dev
);
4540 if ((!np
->autoneg
&& np
->duplex
== 0) ||
4541 (np
->autoneg
&& !pause
->autoneg
&& np
->duplex
== 0)) {
4542 printk(KERN_INFO
"%s: can not set pause settings when forced link is in half duplex.\n",
4546 if (pause
->tx_pause
&& !(np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)) {
4547 printk(KERN_INFO
"%s: hardware does not support tx pause frames.\n", dev
->name
);
4551 netif_carrier_off(dev
);
4552 if (netif_running(dev
)) {
4553 nv_disable_irq(dev
);
4554 netif_tx_lock_bh(dev
);
4555 spin_lock(&np
->lock
);
4558 spin_unlock(&np
->lock
);
4559 netif_tx_unlock_bh(dev
);
4562 np
->pause_flags
&= ~(NV_PAUSEFRAME_RX_REQ
|NV_PAUSEFRAME_TX_REQ
);
4563 if (pause
->rx_pause
)
4564 np
->pause_flags
|= NV_PAUSEFRAME_RX_REQ
;
4565 if (pause
->tx_pause
)
4566 np
->pause_flags
|= NV_PAUSEFRAME_TX_REQ
;
4568 if (np
->autoneg
&& pause
->autoneg
) {
4569 np
->pause_flags
|= NV_PAUSEFRAME_AUTONEG
;
4571 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4572 adv
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4573 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
4574 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4575 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4576 adv
|= ADVERTISE_PAUSE_ASYM
;
4577 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4579 if (netif_running(dev
))
4580 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4581 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4582 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4583 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4585 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4586 if (pause
->rx_pause
)
4587 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4588 if (pause
->tx_pause
)
4589 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4591 if (!netif_running(dev
))
4592 nv_update_linkspeed(dev
);
4594 nv_update_pause(dev
, np
->pause_flags
);
4597 if (netif_running(dev
)) {
4604 static u32
nv_get_rx_csum(struct net_device
*dev
)
4606 struct fe_priv
*np
= netdev_priv(dev
);
4607 return (np
->rx_csum
) != 0;
4610 static int nv_set_rx_csum(struct net_device
*dev
, u32 data
)
4612 struct fe_priv
*np
= netdev_priv(dev
);
4613 u8 __iomem
*base
= get_hwbase(dev
);
4616 if (np
->driver_data
& DEV_HAS_CHECKSUM
) {
4619 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
4622 /* vlan is dependent on rx checksum offload */
4623 if (!(np
->vlanctl_bits
& NVREG_VLANCONTROL_ENABLE
))
4624 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_RXCHECK
;
4626 if (netif_running(dev
)) {
4627 spin_lock_irq(&np
->lock
);
4628 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
4629 spin_unlock_irq(&np
->lock
);
4638 static int nv_set_tx_csum(struct net_device
*dev
, u32 data
)
4640 struct fe_priv
*np
= netdev_priv(dev
);
4642 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
4643 return ethtool_op_set_tx_hw_csum(dev
, data
);
4648 static int nv_set_sg(struct net_device
*dev
, u32 data
)
4650 struct fe_priv
*np
= netdev_priv(dev
);
4652 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
4653 return ethtool_op_set_sg(dev
, data
);
4658 static int nv_get_sset_count(struct net_device
*dev
, int sset
)
4660 struct fe_priv
*np
= netdev_priv(dev
);
4664 if (np
->driver_data
& DEV_HAS_TEST_EXTENDED
)
4665 return NV_TEST_COUNT_EXTENDED
;
4667 return NV_TEST_COUNT_BASE
;
4669 if (np
->driver_data
& DEV_HAS_STATISTICS_V1
)
4670 return NV_DEV_STATISTICS_V1_COUNT
;
4671 else if (np
->driver_data
& DEV_HAS_STATISTICS_V2
)
4672 return NV_DEV_STATISTICS_V2_COUNT
;
4680 static void nv_get_ethtool_stats(struct net_device
*dev
, struct ethtool_stats
*estats
, u64
*buffer
)
4682 struct fe_priv
*np
= netdev_priv(dev
);
4685 nv_do_stats_poll((unsigned long)dev
);
4687 memcpy(buffer
, &np
->estats
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(u64
));
4690 static int nv_link_test(struct net_device
*dev
)
4692 struct fe_priv
*np
= netdev_priv(dev
);
4695 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4696 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4698 /* check phy link status */
4699 if (!(mii_status
& BMSR_LSTATUS
))
4705 static int nv_register_test(struct net_device
*dev
)
4707 u8 __iomem
*base
= get_hwbase(dev
);
4709 u32 orig_read
, new_read
;
4712 orig_read
= readl(base
+ nv_registers_test
[i
].reg
);
4714 /* xor with mask to toggle bits */
4715 orig_read
^= nv_registers_test
[i
].mask
;
4717 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4719 new_read
= readl(base
+ nv_registers_test
[i
].reg
);
4721 if ((new_read
& nv_registers_test
[i
].mask
) != (orig_read
& nv_registers_test
[i
].mask
))
4724 /* restore original value */
4725 orig_read
^= nv_registers_test
[i
].mask
;
4726 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4728 } while (nv_registers_test
[++i
].reg
!= 0);
4733 static int nv_interrupt_test(struct net_device
*dev
)
4735 struct fe_priv
*np
= netdev_priv(dev
);
4736 u8 __iomem
*base
= get_hwbase(dev
);
4739 u32 save_msi_flags
, save_poll_interval
= 0;
4741 if (netif_running(dev
)) {
4742 /* free current irq */
4744 save_poll_interval
= readl(base
+NvRegPollingInterval
);
4747 /* flag to test interrupt handler */
4750 /* setup test irq */
4751 save_msi_flags
= np
->msi_flags
;
4752 np
->msi_flags
&= ~NV_MSI_X_VECTORS_MASK
;
4753 np
->msi_flags
|= 0x001; /* setup 1 vector */
4754 if (nv_request_irq(dev
, 1))
4757 /* setup timer interrupt */
4758 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
4759 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4761 nv_enable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4763 /* wait for at least one interrupt */
4766 spin_lock_irq(&np
->lock
);
4768 /* flag should be set within ISR */
4769 testcnt
= np
->intr_test
;
4773 nv_disable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4774 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
4775 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4777 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4779 spin_unlock_irq(&np
->lock
);
4783 np
->msi_flags
= save_msi_flags
;
4785 if (netif_running(dev
)) {
4786 writel(save_poll_interval
, base
+ NvRegPollingInterval
);
4787 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4788 /* restore original irq */
4789 if (nv_request_irq(dev
, 0))
4796 static int nv_loopback_test(struct net_device
*dev
)
4798 struct fe_priv
*np
= netdev_priv(dev
);
4799 u8 __iomem
*base
= get_hwbase(dev
);
4800 struct sk_buff
*tx_skb
, *rx_skb
;
4801 dma_addr_t test_dma_addr
;
4802 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
4804 int len
, i
, pkt_len
;
4806 u32 filter_flags
= 0;
4807 u32 misc1_flags
= 0;
4810 if (netif_running(dev
)) {
4811 nv_disable_irq(dev
);
4812 filter_flags
= readl(base
+ NvRegPacketFilterFlags
);
4813 misc1_flags
= readl(base
+ NvRegMisc1
);
4818 /* reinit driver view of the rx queue */
4822 /* setup hardware for loopback */
4823 writel(NVREG_MISC1_FORCE
, base
+ NvRegMisc1
);
4824 writel(NVREG_PFF_ALWAYS
| NVREG_PFF_LOOPBACK
, base
+ NvRegPacketFilterFlags
);
4826 /* reinit nic view of the rx queue */
4827 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4828 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4829 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4830 base
+ NvRegRingSizes
);
4833 /* restart rx engine */
4836 /* setup packet for tx */
4837 pkt_len
= ETH_DATA_LEN
;
4838 tx_skb
= dev_alloc_skb(pkt_len
);
4840 printk(KERN_ERR
"dev_alloc_skb() failed during loopback test"
4841 " of %s\n", dev
->name
);
4845 test_dma_addr
= pci_map_single(np
->pci_dev
, tx_skb
->data
,
4846 skb_tailroom(tx_skb
),
4847 PCI_DMA_FROMDEVICE
);
4848 pkt_data
= skb_put(tx_skb
, pkt_len
);
4849 for (i
= 0; i
< pkt_len
; i
++)
4850 pkt_data
[i
] = (u8
)(i
& 0xff);
4852 if (!nv_optimized(np
)) {
4853 np
->tx_ring
.orig
[0].buf
= cpu_to_le32(test_dma_addr
);
4854 np
->tx_ring
.orig
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
4856 np
->tx_ring
.ex
[0].bufhigh
= cpu_to_le32(dma_high(test_dma_addr
));
4857 np
->tx_ring
.ex
[0].buflow
= cpu_to_le32(dma_low(test_dma_addr
));
4858 np
->tx_ring
.ex
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
4860 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4861 pci_push(get_hwbase(dev
));
4865 /* check for rx of the packet */
4866 if (!nv_optimized(np
)) {
4867 flags
= le32_to_cpu(np
->rx_ring
.orig
[0].flaglen
);
4868 len
= nv_descr_getlength(&np
->rx_ring
.orig
[0], np
->desc_ver
);
4871 flags
= le32_to_cpu(np
->rx_ring
.ex
[0].flaglen
);
4872 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[0], np
->desc_ver
);
4875 if (flags
& NV_RX_AVAIL
) {
4877 } else if (np
->desc_ver
== DESC_VER_1
) {
4878 if (flags
& NV_RX_ERROR
)
4881 if (flags
& NV_RX2_ERROR
) {
4887 if (len
!= pkt_len
) {
4889 dprintk(KERN_DEBUG
"%s: loopback len mismatch %d vs %d\n",
4890 dev
->name
, len
, pkt_len
);
4892 rx_skb
= np
->rx_skb
[0].skb
;
4893 for (i
= 0; i
< pkt_len
; i
++) {
4894 if (rx_skb
->data
[i
] != (u8
)(i
& 0xff)) {
4896 dprintk(KERN_DEBUG
"%s: loopback pattern check failed on byte %d\n",
4903 dprintk(KERN_DEBUG
"%s: loopback - did not receive test packet\n", dev
->name
);
4906 pci_unmap_page(np
->pci_dev
, test_dma_addr
,
4907 (skb_end_pointer(tx_skb
) - tx_skb
->data
),
4909 dev_kfree_skb_any(tx_skb
);
4914 /* drain rx queue */
4917 if (netif_running(dev
)) {
4918 writel(misc1_flags
, base
+ NvRegMisc1
);
4919 writel(filter_flags
, base
+ NvRegPacketFilterFlags
);
4926 static void nv_self_test(struct net_device
*dev
, struct ethtool_test
*test
, u64
*buffer
)
4928 struct fe_priv
*np
= netdev_priv(dev
);
4929 u8 __iomem
*base
= get_hwbase(dev
);
4931 memset(buffer
, 0, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(u64
));
4933 if (!nv_link_test(dev
)) {
4934 test
->flags
|= ETH_TEST_FL_FAILED
;
4938 if (test
->flags
& ETH_TEST_FL_OFFLINE
) {
4939 if (netif_running(dev
)) {
4940 netif_stop_queue(dev
);
4941 #ifdef CONFIG_FORCEDETH_NAPI
4942 napi_disable(&np
->napi
);
4944 netif_tx_lock_bh(dev
);
4945 spin_lock_irq(&np
->lock
);
4946 nv_disable_hw_interrupts(dev
, np
->irqmask
);
4947 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
4948 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4950 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4955 /* drain rx queue */
4957 spin_unlock_irq(&np
->lock
);
4958 netif_tx_unlock_bh(dev
);
4961 if (!nv_register_test(dev
)) {
4962 test
->flags
|= ETH_TEST_FL_FAILED
;
4966 result
= nv_interrupt_test(dev
);
4968 test
->flags
|= ETH_TEST_FL_FAILED
;
4976 if (!nv_loopback_test(dev
)) {
4977 test
->flags
|= ETH_TEST_FL_FAILED
;
4981 if (netif_running(dev
)) {
4982 /* reinit driver view of the rx queue */
4984 if (nv_init_ring(dev
)) {
4985 if (!np
->in_shutdown
)
4986 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4988 /* reinit nic view of the rx queue */
4989 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4990 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4991 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4992 base
+ NvRegRingSizes
);
4994 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4996 /* restart rx engine */
4998 netif_start_queue(dev
);
4999 #ifdef CONFIG_FORCEDETH_NAPI
5000 napi_enable(&np
->napi
);
5002 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5007 static void nv_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buffer
)
5009 switch (stringset
) {
5011 memcpy(buffer
, &nv_estats_str
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(struct nv_ethtool_str
));
5014 memcpy(buffer
, &nv_etests_str
, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(struct nv_ethtool_str
));
5019 static const struct ethtool_ops ops
= {
5020 .get_drvinfo
= nv_get_drvinfo
,
5021 .get_link
= ethtool_op_get_link
,
5022 .get_wol
= nv_get_wol
,
5023 .set_wol
= nv_set_wol
,
5024 .get_settings
= nv_get_settings
,
5025 .set_settings
= nv_set_settings
,
5026 .get_regs_len
= nv_get_regs_len
,
5027 .get_regs
= nv_get_regs
,
5028 .nway_reset
= nv_nway_reset
,
5029 .set_tso
= nv_set_tso
,
5030 .get_ringparam
= nv_get_ringparam
,
5031 .set_ringparam
= nv_set_ringparam
,
5032 .get_pauseparam
= nv_get_pauseparam
,
5033 .set_pauseparam
= nv_set_pauseparam
,
5034 .get_rx_csum
= nv_get_rx_csum
,
5035 .set_rx_csum
= nv_set_rx_csum
,
5036 .set_tx_csum
= nv_set_tx_csum
,
5037 .set_sg
= nv_set_sg
,
5038 .get_strings
= nv_get_strings
,
5039 .get_ethtool_stats
= nv_get_ethtool_stats
,
5040 .get_sset_count
= nv_get_sset_count
,
5041 .self_test
= nv_self_test
,
5044 static void nv_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
5046 struct fe_priv
*np
= get_nvpriv(dev
);
5048 spin_lock_irq(&np
->lock
);
5050 /* save vlan group */
5054 /* enable vlan on MAC */
5055 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANSTRIP
| NVREG_TXRXCTL_VLANINS
;
5057 /* disable vlan on MAC */
5058 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANSTRIP
;
5059 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANINS
;
5062 writel(np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5064 spin_unlock_irq(&np
->lock
);
5067 /* The mgmt unit and driver use a semaphore to access the phy during init */
5068 static int nv_mgmt_acquire_sema(struct net_device
*dev
)
5070 u8 __iomem
*base
= get_hwbase(dev
);
5072 u32 tx_ctrl
, mgmt_sema
;
5074 for (i
= 0; i
< 10; i
++) {
5075 mgmt_sema
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_SEMA_MASK
;
5076 if (mgmt_sema
== NVREG_XMITCTL_MGMT_SEMA_FREE
)
5081 if (mgmt_sema
!= NVREG_XMITCTL_MGMT_SEMA_FREE
)
5084 for (i
= 0; i
< 2; i
++) {
5085 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5086 tx_ctrl
|= NVREG_XMITCTL_HOST_SEMA_ACQ
;
5087 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
5089 /* verify that semaphore was acquired */
5090 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5091 if (((tx_ctrl
& NVREG_XMITCTL_HOST_SEMA_MASK
) == NVREG_XMITCTL_HOST_SEMA_ACQ
) &&
5092 ((tx_ctrl
& NVREG_XMITCTL_MGMT_SEMA_MASK
) == NVREG_XMITCTL_MGMT_SEMA_FREE
))
5101 static int nv_open(struct net_device
*dev
)
5103 struct fe_priv
*np
= netdev_priv(dev
);
5104 u8 __iomem
*base
= get_hwbase(dev
);
5109 dprintk(KERN_DEBUG
"nv_open: begin\n");
5111 /* erase previous misconfiguration */
5112 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
5114 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5115 writel(0, base
+ NvRegMulticastAddrB
);
5116 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5117 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5118 writel(0, base
+ NvRegPacketFilterFlags
);
5120 writel(0, base
+ NvRegTransmitterControl
);
5121 writel(0, base
+ NvRegReceiverControl
);
5123 writel(0, base
+ NvRegAdapterControl
);
5125 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)
5126 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
5128 /* initialize descriptor rings */
5130 oom
= nv_init_ring(dev
);
5132 writel(0, base
+ NvRegLinkSpeed
);
5133 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5135 writel(0, base
+ NvRegUnknownSetupReg6
);
5137 np
->in_shutdown
= 0;
5140 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5141 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5142 base
+ NvRegRingSizes
);
5144 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
5145 if (np
->desc_ver
== DESC_VER_1
)
5146 writel(NVREG_TX_WM_DESC1_DEFAULT
, base
+ NvRegTxWatermark
);
5148 writel(NVREG_TX_WM_DESC2_3_DEFAULT
, base
+ NvRegTxWatermark
);
5149 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5150 writel(np
->vlanctl_bits
, base
+ NvRegVlanControl
);
5152 writel(NVREG_TXRXCTL_BIT1
|np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5153 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
5154 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
5155 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
5157 writel(0, base
+ NvRegMIIMask
);
5158 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5159 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5161 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
5162 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
5163 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
5164 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5166 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
5168 get_random_bytes(&low
, sizeof(low
));
5169 low
&= NVREG_SLOTTIME_MASK
;
5170 if (np
->desc_ver
== DESC_VER_1
) {
5171 writel(low
|NVREG_SLOTTIME_DEFAULT
, base
+ NvRegSlotTime
);
5173 if (!(np
->driver_data
& DEV_HAS_GEAR_MODE
)) {
5174 /* setup legacy backoff */
5175 writel(NVREG_SLOTTIME_LEGBF_ENABLED
|NVREG_SLOTTIME_10_100_FULL
|low
, base
+ NvRegSlotTime
);
5177 writel(NVREG_SLOTTIME_10_100_FULL
, base
+ NvRegSlotTime
);
5178 nv_gear_backoff_reseed(dev
);
5181 writel(NVREG_TX_DEFERRAL_DEFAULT
, base
+ NvRegTxDeferral
);
5182 writel(NVREG_RX_DEFERRAL_DEFAULT
, base
+ NvRegRxDeferral
);
5183 if (poll_interval
== -1) {
5184 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
)
5185 writel(NVREG_POLL_DEFAULT_THROUGHPUT
, base
+ NvRegPollingInterval
);
5187 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
5190 writel(poll_interval
& 0xFFFF, base
+ NvRegPollingInterval
);
5191 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
5192 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
5193 base
+ NvRegAdapterControl
);
5194 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
5195 writel(NVREG_MII_LINKCHANGE
, base
+ NvRegMIIMask
);
5197 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
5199 i
= readl(base
+ NvRegPowerState
);
5200 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
5201 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
5205 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
5207 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5209 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5210 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5213 if (nv_request_irq(dev
, 0)) {
5217 /* ask for interrupts */
5218 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5220 spin_lock_irq(&np
->lock
);
5221 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5222 writel(0, base
+ NvRegMulticastAddrB
);
5223 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5224 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5225 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5226 /* One manual link speed update: Interrupts are enabled, future link
5227 * speed changes cause interrupts and are handled by nv_link_irq().
5231 miistat
= readl(base
+ NvRegMIIStatus
);
5232 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5233 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
5235 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5238 ret
= nv_update_linkspeed(dev
);
5240 netif_start_queue(dev
);
5241 #ifdef CONFIG_FORCEDETH_NAPI
5242 napi_enable(&np
->napi
);
5246 netif_carrier_on(dev
);
5248 printk(KERN_INFO
"%s: no link during initialization.\n", dev
->name
);
5249 netif_carrier_off(dev
);
5252 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5254 /* start statistics timer */
5255 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
))
5256 mod_timer(&np
->stats_poll
,
5257 round_jiffies(jiffies
+ STATS_INTERVAL
));
5259 spin_unlock_irq(&np
->lock
);
5267 static int nv_close(struct net_device
*dev
)
5269 struct fe_priv
*np
= netdev_priv(dev
);
5272 spin_lock_irq(&np
->lock
);
5273 np
->in_shutdown
= 1;
5274 spin_unlock_irq(&np
->lock
);
5275 #ifdef CONFIG_FORCEDETH_NAPI
5276 napi_disable(&np
->napi
);
5278 synchronize_irq(np
->pci_dev
->irq
);
5280 del_timer_sync(&np
->oom_kick
);
5281 del_timer_sync(&np
->nic_poll
);
5282 del_timer_sync(&np
->stats_poll
);
5284 netif_stop_queue(dev
);
5285 spin_lock_irq(&np
->lock
);
5289 /* disable interrupts on the nic or we will lock up */
5290 base
= get_hwbase(dev
);
5291 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5293 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
5295 spin_unlock_irq(&np
->lock
);
5301 if (np
->wolenabled
) {
5302 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5306 /* FIXME: power down nic */
5311 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
5313 struct net_device
*dev
;
5318 u32 powerstate
, txreg
;
5319 u32 phystate_orig
= 0, phystate
;
5320 int phyinitialized
= 0;
5321 DECLARE_MAC_BUF(mac
);
5322 static int printed_version
;
5324 if (!printed_version
++)
5325 printk(KERN_INFO
"%s: Reverse Engineered nForce ethernet"
5326 " driver. Version %s.\n", DRV_NAME
, FORCEDETH_VERSION
);
5328 dev
= alloc_etherdev(sizeof(struct fe_priv
));
5333 np
= netdev_priv(dev
);
5335 np
->pci_dev
= pci_dev
;
5336 spin_lock_init(&np
->lock
);
5337 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
5339 init_timer(&np
->oom_kick
);
5340 np
->oom_kick
.data
= (unsigned long) dev
;
5341 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
5342 init_timer(&np
->nic_poll
);
5343 np
->nic_poll
.data
= (unsigned long) dev
;
5344 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
5345 init_timer(&np
->stats_poll
);
5346 np
->stats_poll
.data
= (unsigned long) dev
;
5347 np
->stats_poll
.function
= &nv_do_stats_poll
; /* timer handler */
5349 err
= pci_enable_device(pci_dev
);
5353 pci_set_master(pci_dev
);
5355 err
= pci_request_regions(pci_dev
, DRV_NAME
);
5359 if (id
->driver_data
& (DEV_HAS_VLAN
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V2
))
5360 np
->register_size
= NV_PCI_REGSZ_VER3
;
5361 else if (id
->driver_data
& DEV_HAS_STATISTICS_V1
)
5362 np
->register_size
= NV_PCI_REGSZ_VER2
;
5364 np
->register_size
= NV_PCI_REGSZ_VER1
;
5368 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
5369 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
5370 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
5371 pci_resource_len(pci_dev
, i
),
5372 pci_resource_flags(pci_dev
, i
));
5373 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
5374 pci_resource_len(pci_dev
, i
) >= np
->register_size
) {
5375 addr
= pci_resource_start(pci_dev
, i
);
5379 if (i
== DEVICE_COUNT_RESOURCE
) {
5380 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5381 "Couldn't find register window\n");
5385 /* copy of driver data */
5386 np
->driver_data
= id
->driver_data
;
5387 /* copy of device id */
5388 np
->device_id
= id
->device
;
5390 /* handle different descriptor versions */
5391 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
5392 /* packet format 3: supports 40-bit addressing */
5393 np
->desc_ver
= DESC_VER_3
;
5394 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_3
;
5396 if (pci_set_dma_mask(pci_dev
, DMA_39BIT_MASK
))
5397 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5398 "64-bit DMA failed, using 32-bit addressing\n");
5400 dev
->features
|= NETIF_F_HIGHDMA
;
5401 if (pci_set_consistent_dma_mask(pci_dev
, DMA_39BIT_MASK
)) {
5402 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5403 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5406 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
5407 /* packet format 2: supports jumbo frames */
5408 np
->desc_ver
= DESC_VER_2
;
5409 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_2
;
5411 /* original packet format */
5412 np
->desc_ver
= DESC_VER_1
;
5413 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_1
;
5416 np
->pkt_limit
= NV_PKTLIMIT_1
;
5417 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
5418 np
->pkt_limit
= NV_PKTLIMIT_2
;
5420 if (id
->driver_data
& DEV_HAS_CHECKSUM
) {
5422 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
5423 dev
->features
|= NETIF_F_HW_CSUM
| NETIF_F_SG
;
5424 dev
->features
|= NETIF_F_TSO
;
5427 np
->vlanctl_bits
= 0;
5428 if (id
->driver_data
& DEV_HAS_VLAN
) {
5429 np
->vlanctl_bits
= NVREG_VLANCONTROL_ENABLE
;
5430 dev
->features
|= NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
;
5431 dev
->vlan_rx_register
= nv_vlan_rx_register
;
5435 if ((id
->driver_data
& DEV_HAS_MSI
) && msi
) {
5436 np
->msi_flags
|= NV_MSI_CAPABLE
;
5438 if ((id
->driver_data
& DEV_HAS_MSI_X
) && msix
) {
5439 np
->msi_flags
|= NV_MSI_X_CAPABLE
;
5442 np
->pause_flags
= NV_PAUSEFRAME_RX_CAPABLE
| NV_PAUSEFRAME_RX_REQ
| NV_PAUSEFRAME_AUTONEG
;
5443 if ((id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V1
) ||
5444 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
) ||
5445 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
)) {
5446 np
->pause_flags
|= NV_PAUSEFRAME_TX_CAPABLE
| NV_PAUSEFRAME_TX_REQ
;
5451 np
->base
= ioremap(addr
, np
->register_size
);
5454 dev
->base_addr
= (unsigned long)np
->base
;
5456 dev
->irq
= pci_dev
->irq
;
5458 np
->rx_ring_size
= RX_RING_DEFAULT
;
5459 np
->tx_ring_size
= TX_RING_DEFAULT
;
5461 if (!nv_optimized(np
)) {
5462 np
->rx_ring
.orig
= pci_alloc_consistent(pci_dev
,
5463 sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5465 if (!np
->rx_ring
.orig
)
5467 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
5469 np
->rx_ring
.ex
= pci_alloc_consistent(pci_dev
,
5470 sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5472 if (!np
->rx_ring
.ex
)
5474 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
5476 np
->rx_skb
= kcalloc(np
->rx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5477 np
->tx_skb
= kcalloc(np
->tx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5478 if (!np
->rx_skb
|| !np
->tx_skb
)
5481 dev
->open
= nv_open
;
5482 dev
->stop
= nv_close
;
5484 if (!nv_optimized(np
))
5485 dev
->hard_start_xmit
= nv_start_xmit
;
5487 dev
->hard_start_xmit
= nv_start_xmit_optimized
;
5488 dev
->get_stats
= nv_get_stats
;
5489 dev
->change_mtu
= nv_change_mtu
;
5490 dev
->set_mac_address
= nv_set_mac_address
;
5491 dev
->set_multicast_list
= nv_set_multicast
;
5492 #ifdef CONFIG_NET_POLL_CONTROLLER
5493 dev
->poll_controller
= nv_poll_controller
;
5495 #ifdef CONFIG_FORCEDETH_NAPI
5496 netif_napi_add(dev
, &np
->napi
, nv_napi_poll
, RX_WORK_PER_LOOP
);
5498 SET_ETHTOOL_OPS(dev
, &ops
);
5499 dev
->tx_timeout
= nv_tx_timeout
;
5500 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
5502 pci_set_drvdata(pci_dev
, dev
);
5504 /* read the mac address */
5505 base
= get_hwbase(dev
);
5506 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
5507 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
5509 /* check the workaround bit for correct mac address order */
5510 txreg
= readl(base
+ NvRegTransmitPoll
);
5511 if (id
->driver_data
& DEV_HAS_CORRECT_MACADDR
) {
5512 /* mac address is already in correct order */
5513 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5514 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5515 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5516 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5517 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5518 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5519 } else if (txreg
& NVREG_TRANSMITPOLL_MAC_ADDR_REV
) {
5520 /* mac address is already in correct order */
5521 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5522 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5523 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5524 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5525 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5526 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5528 * Set orig mac address back to the reversed version.
5529 * This flag will be cleared during low power transition.
5530 * Therefore, we should always put back the reversed address.
5532 np
->orig_mac
[0] = (dev
->dev_addr
[5] << 0) + (dev
->dev_addr
[4] << 8) +
5533 (dev
->dev_addr
[3] << 16) + (dev
->dev_addr
[2] << 24);
5534 np
->orig_mac
[1] = (dev
->dev_addr
[1] << 0) + (dev
->dev_addr
[0] << 8);
5536 /* need to reverse mac address to correct order */
5537 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
5538 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
5539 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
5540 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
5541 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
5542 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
5543 writel(txreg
|NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5545 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
5547 if (!is_valid_ether_addr(dev
->perm_addr
)) {
5549 * Bad mac address. At least one bios sets the mac address
5550 * to 01:23:45:67:89:ab
5552 dev_printk(KERN_ERR
, &pci_dev
->dev
,
5553 "Invalid Mac address detected: %s\n",
5554 print_mac(mac
, dev
->dev_addr
));
5555 dev_printk(KERN_ERR
, &pci_dev
->dev
,
5556 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5557 dev
->dev_addr
[0] = 0x00;
5558 dev
->dev_addr
[1] = 0x00;
5559 dev
->dev_addr
[2] = 0x6c;
5560 get_random_bytes(&dev
->dev_addr
[3], 3);
5563 dprintk(KERN_DEBUG
"%s: MAC Address %s\n",
5564 pci_name(pci_dev
), print_mac(mac
, dev
->dev_addr
));
5566 /* set mac address */
5567 nv_copy_mac_to_hw(dev
);
5570 writel(0, base
+ NvRegWakeUpFlags
);
5573 if (id
->driver_data
& DEV_HAS_POWER_CNTRL
) {
5575 /* take phy and nic out of low power mode */
5576 powerstate
= readl(base
+ NvRegPowerState2
);
5577 powerstate
&= ~NVREG_POWERSTATE2_POWERUP_MASK
;
5578 if ((id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_12
||
5579 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_13
) &&
5580 pci_dev
->revision
>= 0xA3)
5581 powerstate
|= NVREG_POWERSTATE2_POWERUP_REV_A3
;
5582 writel(powerstate
, base
+ NvRegPowerState2
);
5585 if (np
->desc_ver
== DESC_VER_1
) {
5586 np
->tx_flags
= NV_TX_VALID
;
5588 np
->tx_flags
= NV_TX2_VALID
;
5590 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
) {
5591 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
5592 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5593 np
->msi_flags
|= 0x0003;
5595 np
->irqmask
= NVREG_IRQMASK_CPU
;
5596 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5597 np
->msi_flags
|= 0x0001;
5600 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
5601 np
->irqmask
|= NVREG_IRQ_TIMER
;
5602 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
5603 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
5604 np
->need_linktimer
= 1;
5605 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
5607 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
5608 np
->need_linktimer
= 0;
5611 /* Limit the number of tx's outstanding for hw bug */
5612 if (id
->driver_data
& DEV_NEED_TX_LIMIT
) {
5614 if ((id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
5615 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
5616 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
5617 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
5618 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
5619 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
5620 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
5621 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) &&
5622 pci_dev
->revision
>= 0xA2)
5626 /* clear phy state and temporarily halt phy interrupts */
5627 writel(0, base
+ NvRegMIIMask
);
5628 phystate
= readl(base
+ NvRegAdapterControl
);
5629 if (phystate
& NVREG_ADAPTCTL_RUNNING
) {
5631 phystate
&= ~NVREG_ADAPTCTL_RUNNING
;
5632 writel(phystate
, base
+ NvRegAdapterControl
);
5634 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5636 if (id
->driver_data
& DEV_HAS_MGMT_UNIT
) {
5637 /* management unit running on the mac? */
5638 if (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_PHY_INIT
) {
5639 np
->mac_in_use
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_ST
;
5640 dprintk(KERN_INFO
"%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev
), np
->mac_in_use
);
5641 if (nv_mgmt_acquire_sema(dev
)) {
5642 /* management unit setup the phy already? */
5643 if ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_MASK
) ==
5644 NVREG_XMITCTL_SYNC_PHY_INIT
) {
5645 /* phy is inited by mgmt unit */
5647 dprintk(KERN_INFO
"%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev
));
5649 /* we need to init the phy */
5655 /* find a suitable phy */
5656 for (i
= 1; i
<= 32; i
++) {
5658 int phyaddr
= i
& 0x1F;
5660 spin_lock_irq(&np
->lock
);
5661 id1
= mii_rw(dev
, phyaddr
, MII_PHYSID1
, MII_READ
);
5662 spin_unlock_irq(&np
->lock
);
5663 if (id1
< 0 || id1
== 0xffff)
5665 spin_lock_irq(&np
->lock
);
5666 id2
= mii_rw(dev
, phyaddr
, MII_PHYSID2
, MII_READ
);
5667 spin_unlock_irq(&np
->lock
);
5668 if (id2
< 0 || id2
== 0xffff)
5671 np
->phy_model
= id2
& PHYID2_MODEL_MASK
;
5672 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
5673 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
5674 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
5675 pci_name(pci_dev
), id1
, id2
, phyaddr
);
5676 np
->phyaddr
= phyaddr
;
5677 np
->phy_oui
= id1
| id2
;
5679 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5680 if (np
->phy_oui
== PHY_OUI_REALTEK2
)
5681 np
->phy_oui
= PHY_OUI_REALTEK
;
5682 /* Setup phy revision for Realtek */
5683 if (np
->phy_oui
== PHY_OUI_REALTEK
&& np
->phy_model
== PHY_MODEL_REALTEK_8211
)
5684 np
->phy_rev
= mii_rw(dev
, phyaddr
, MII_RESV1
, MII_READ
) & PHY_REV_MASK
;
5689 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5690 "open: Could not find a valid PHY.\n");
5694 if (!phyinitialized
) {
5698 /* see if it is a gigabit phy */
5699 u32 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
5700 if (mii_status
& PHY_GIGABIT
) {
5701 np
->gigabit
= PHY_GIGABIT
;
5705 /* set default link speed settings */
5706 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
5710 err
= register_netdev(dev
);
5712 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5713 "unable to register netdev: %d\n", err
);
5717 dev_printk(KERN_INFO
, &pci_dev
->dev
, "ifname %s, PHY OUI 0x%x @ %d, "
5718 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5729 dev_printk(KERN_INFO
, &pci_dev
->dev
, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5730 dev
->features
& NETIF_F_HIGHDMA
? "highdma " : "",
5731 dev
->features
& (NETIF_F_HW_CSUM
| NETIF_F_SG
) ?
5733 dev
->features
& (NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
) ?
5735 id
->driver_data
& DEV_HAS_POWER_CNTRL
? "pwrctl " : "",
5736 id
->driver_data
& DEV_HAS_MGMT_UNIT
? "mgmt " : "",
5737 id
->driver_data
& DEV_NEED_TIMERIRQ
? "timirq " : "",
5738 np
->gigabit
== PHY_GIGABIT
? "gbit " : "",
5739 np
->need_linktimer
? "lnktim " : "",
5740 np
->msi_flags
& NV_MSI_CAPABLE
? "msi " : "",
5741 np
->msi_flags
& NV_MSI_X_CAPABLE
? "msi-x " : "",
5748 writel(phystate
|NVREG_ADAPTCTL_RUNNING
, base
+ NvRegAdapterControl
);
5749 pci_set_drvdata(pci_dev
, NULL
);
5753 iounmap(get_hwbase(dev
));
5755 pci_release_regions(pci_dev
);
5757 pci_disable_device(pci_dev
);
5764 static void nv_restore_phy(struct net_device
*dev
)
5766 struct fe_priv
*np
= netdev_priv(dev
);
5767 u16 phy_reserved
, mii_control
;
5769 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
5770 np
->phy_model
== PHY_MODEL_REALTEK_8201
&&
5771 phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
5772 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
);
5773 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
5774 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
5775 phy_reserved
|= PHY_REALTEK_INIT8
;
5776 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
);
5777 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
);
5779 /* restart auto negotiation */
5780 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
5781 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
5782 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
);
5786 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
5788 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
5789 struct fe_priv
*np
= netdev_priv(dev
);
5790 u8 __iomem
*base
= get_hwbase(dev
);
5792 unregister_netdev(dev
);
5794 /* special op: write back the misordered MAC address - otherwise
5795 * the next nv_probe would see a wrong address.
5797 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
5798 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
5799 writel(readl(base
+ NvRegTransmitPoll
) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
5800 base
+ NvRegTransmitPoll
);
5802 /* restore any phy related changes */
5803 nv_restore_phy(dev
);
5805 /* free all structures */
5807 iounmap(get_hwbase(dev
));
5808 pci_release_regions(pci_dev
);
5809 pci_disable_device(pci_dev
);
5811 pci_set_drvdata(pci_dev
, NULL
);
5815 static int nv_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5817 struct net_device
*dev
= pci_get_drvdata(pdev
);
5818 struct fe_priv
*np
= netdev_priv(dev
);
5820 if (!netif_running(dev
))
5823 netif_device_detach(dev
);
5828 pci_save_state(pdev
);
5829 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), np
->wolenabled
);
5830 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
5835 static int nv_resume(struct pci_dev
*pdev
)
5837 struct net_device
*dev
= pci_get_drvdata(pdev
);
5838 u8 __iomem
*base
= get_hwbase(dev
);
5842 if (!netif_running(dev
))
5845 netif_device_attach(dev
);
5847 pci_set_power_state(pdev
, PCI_D0
);
5848 pci_restore_state(pdev
);
5849 pci_enable_wake(pdev
, PCI_D0
, 0);
5851 /* restore mac address reverse flag */
5852 txreg
= readl(base
+ NvRegTransmitPoll
);
5853 txreg
|= NVREG_TRANSMITPOLL_MAC_ADDR_REV
;
5854 writel(txreg
, base
+ NvRegTransmitPoll
);
5857 nv_set_multicast(dev
);
5862 #define nv_suspend NULL
5863 #define nv_resume NULL
5864 #endif /* CONFIG_PM */
5866 static struct pci_device_id pci_tbl
[] = {
5867 { /* nForce Ethernet Controller */
5868 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_1
),
5869 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
5871 { /* nForce2 Ethernet Controller */
5872 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_2
),
5873 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
5875 { /* nForce3 Ethernet Controller */
5876 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_3
),
5877 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
5879 { /* nForce3 Ethernet Controller */
5880 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_4
),
5881 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5883 { /* nForce3 Ethernet Controller */
5884 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_5
),
5885 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5887 { /* nForce3 Ethernet Controller */
5888 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_6
),
5889 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5891 { /* nForce3 Ethernet Controller */
5892 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_7
),
5893 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5895 { /* CK804 Ethernet Controller */
5896 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_8
),
5897 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
5899 { /* CK804 Ethernet Controller */
5900 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_9
),
5901 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
5903 { /* MCP04 Ethernet Controller */
5904 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_10
),
5905 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
5907 { /* MCP04 Ethernet Controller */
5908 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_11
),
5909 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
5911 { /* MCP51 Ethernet Controller */
5912 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_12
),
5913 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
,
5915 { /* MCP51 Ethernet Controller */
5916 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_13
),
5917 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
,
5919 { /* MCP55 Ethernet Controller */
5920 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_14
),
5921 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
,
5923 { /* MCP55 Ethernet Controller */
5924 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_15
),
5925 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
,
5927 { /* MCP61 Ethernet Controller */
5928 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_16
),
5929 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
5931 { /* MCP61 Ethernet Controller */
5932 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_17
),
5933 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
5935 { /* MCP61 Ethernet Controller */
5936 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_18
),
5937 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
5939 { /* MCP61 Ethernet Controller */
5940 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_19
),
5941 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
5943 { /* MCP65 Ethernet Controller */
5944 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_20
),
5945 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
5947 { /* MCP65 Ethernet Controller */
5948 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_21
),
5949 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
5951 { /* MCP65 Ethernet Controller */
5952 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_22
),
5953 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
5955 { /* MCP65 Ethernet Controller */
5956 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_23
),
5957 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
5959 { /* MCP67 Ethernet Controller */
5960 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_24
),
5961 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
5963 { /* MCP67 Ethernet Controller */
5964 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_25
),
5965 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
5967 { /* MCP67 Ethernet Controller */
5968 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_26
),
5969 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
5971 { /* MCP67 Ethernet Controller */
5972 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_27
),
5973 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
5975 { /* MCP73 Ethernet Controller */
5976 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_28
),
5977 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
5979 { /* MCP73 Ethernet Controller */
5980 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_29
),
5981 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
5983 { /* MCP73 Ethernet Controller */
5984 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_30
),
5985 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
5987 { /* MCP73 Ethernet Controller */
5988 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_31
),
5989 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
5991 { /* MCP77 Ethernet Controller */
5992 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_32
),
5993 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
5995 { /* MCP77 Ethernet Controller */
5996 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_33
),
5997 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
5999 { /* MCP77 Ethernet Controller */
6000 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_34
),
6001 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6003 { /* MCP77 Ethernet Controller */
6004 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_35
),
6005 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6007 { /* MCP79 Ethernet Controller */
6008 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_36
),
6009 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6011 { /* MCP79 Ethernet Controller */
6012 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_37
),
6013 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6015 { /* MCP79 Ethernet Controller */
6016 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_38
),
6017 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6019 { /* MCP79 Ethernet Controller */
6020 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_39
),
6021 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6026 static struct pci_driver driver
= {
6028 .id_table
= pci_tbl
,
6030 .remove
= __devexit_p(nv_remove
),
6031 .suspend
= nv_suspend
,
6032 .resume
= nv_resume
,
6035 static int __init
init_nic(void)
6037 return pci_register_driver(&driver
);
6040 static void __exit
exit_nic(void)
6042 pci_unregister_driver(&driver
);
6045 module_param(max_interrupt_work
, int, 0);
6046 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
6047 module_param(optimization_mode
, int, 0);
6048 MODULE_PARM_DESC(optimization_mode
, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
6049 module_param(poll_interval
, int, 0);
6050 MODULE_PARM_DESC(poll_interval
, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6051 module_param(msi
, int, 0);
6052 MODULE_PARM_DESC(msi
, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6053 module_param(msix
, int, 0);
6054 MODULE_PARM_DESC(msix
, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6055 module_param(dma_64bit
, int, 0);
6056 MODULE_PARM_DESC(dma_64bit
, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6057 module_param(phy_cross
, int, 0);
6058 MODULE_PARM_DESC(phy_cross
, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6060 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6061 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6062 MODULE_LICENSE("GPL");
6064 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
6066 module_init(init_nic
);
6067 module_exit(exit_nic
);