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x86_64: check remote IRR bit before migrating level triggered irq
[linux-2.6/kmemtrace.git] / arch / x86_64 / kernel / io_apic.c
blob050141c0602bbd10d6a429d0016ccd8e6fd3ad83
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #ifdef CONFIG_ACPI
35 #include <acpi/acpi_bus.h>
36 #endif
37
38 #include <asm/idle.h>
39 #include <asm/io.h>
40 #include <asm/smp.h>
41 #include <asm/desc.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
44 #include <asm/acpi.h>
45 #include <asm/dma.h>
46 #include <asm/nmi.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49
50 struct irq_cfg {
51 cpumask_t domain;
52 cpumask_t old_domain;
53 unsigned move_cleanup_count;
54 u8 vector;
55 u8 move_in_progress : 1;
56 };
57
58 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
59 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
60 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
61 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
62 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
63 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
64 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
65 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
66 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
67 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
68 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
69 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
70 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
71 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
72 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
73 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
74 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
75 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
76 };
77
78 static int assign_irq_vector(int irq, cpumask_t mask);
79
80 #define __apicdebuginit __init
81
82 int sis_apic_bug; /* not actually supported, dummy for compile */
83
84 static int no_timer_check;
85
86 static int disable_timer_pin_1 __initdata;
87
88 int timer_over_8254 __initdata = 1;
89
90 /* Where if anywhere is the i8259 connect in external int mode */
91 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
92
93 static DEFINE_SPINLOCK(ioapic_lock);
94 DEFINE_SPINLOCK(vector_lock);
95
96 /*
97 * # of IRQ routing registers
98 */
99 int nr_ioapic_registers[MAX_IO_APICS];
100
101 /*
102 * Rough estimation of how many shared IRQs there are, can
103 * be changed anytime.
104 */
105 #define MAX_PLUS_SHARED_IRQS NR_IRQS
106 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
107
108 /*
109 * This is performance-critical, we want to do it O(1)
110 *
111 * the indexing order of this array favors 1:1 mappings
112 * between pins and IRQs.
113 */
114
115 static struct irq_pin_list {
116 short apic, pin, next;
117 } irq_2_pin[PIN_MAP_SIZE];
118
119 struct io_apic {
120 unsigned int index;
121 unsigned int unused[3];
122 unsigned int data;
123 };
124
125 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
126 {
127 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
128 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
129 }
130
131 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
132 {
133 struct io_apic __iomem *io_apic = io_apic_base(apic);
134 writel(reg, &io_apic->index);
135 return readl(&io_apic->data);
136 }
137
138 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
139 {
140 struct io_apic __iomem *io_apic = io_apic_base(apic);
141 writel(reg, &io_apic->index);
142 writel(value, &io_apic->data);
143 }
144
145 /*
146 * Re-write a value: to be used for read-modify-write
147 * cycles where the read already set up the index register.
148 */
149 static inline void io_apic_modify(unsigned int apic, unsigned int value)
150 {
151 struct io_apic __iomem *io_apic = io_apic_base(apic);
152 writel(value, &io_apic->data);
153 }
154
155 static int io_apic_level_ack_pending(unsigned int irq)
156 {
157 struct irq_pin_list *entry;
158 unsigned long flags;
159 int pending = 0;
160
161 spin_lock_irqsave(&ioapic_lock, flags);
162 entry = irq_2_pin + irq;
163 for (;;) {
164 unsigned int reg;
165 int pin;
166
167 pin = entry->pin;
168 if (pin == -1)
169 break;
170 reg = io_apic_read(entry->apic, 0x10 + pin*2);
171 /* Is the remote IRR bit set? */
172 pending |= (reg >> 14) & 1;
173 if (!entry->next)
174 break;
175 entry = irq_2_pin + entry->next;
176 }
177 spin_unlock_irqrestore(&ioapic_lock, flags);
178 return pending;
179 }
180
181 /*
182 * Synchronize the IO-APIC and the CPU by doing
183 * a dummy read from the IO-APIC
184 */
185 static inline void io_apic_sync(unsigned int apic)
186 {
187 struct io_apic __iomem *io_apic = io_apic_base(apic);
188 readl(&io_apic->data);
189 }
190
191 #define __DO_ACTION(R, ACTION, FINAL) \
192 \
193 { \
194 int pin; \
195 struct irq_pin_list *entry = irq_2_pin + irq; \
196 \
197 BUG_ON(irq >= NR_IRQS); \
198 for (;;) { \
199 unsigned int reg; \
200 pin = entry->pin; \
201 if (pin == -1) \
202 break; \
203 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
204 reg ACTION; \
205 io_apic_modify(entry->apic, reg); \
206 FINAL; \
207 if (!entry->next) \
208 break; \
209 entry = irq_2_pin + entry->next; \
210 } \
211 }
212
213 union entry_union {
214 struct { u32 w1, w2; };
215 struct IO_APIC_route_entry entry;
216 };
217
218 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
219 {
220 union entry_union eu;
221 unsigned long flags;
222 spin_lock_irqsave(&ioapic_lock, flags);
223 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
224 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
225 spin_unlock_irqrestore(&ioapic_lock, flags);
226 return eu.entry;
227 }
228
229 /*
230 * When we write a new IO APIC routing entry, we need to write the high
231 * word first! If the mask bit in the low word is clear, we will enable
232 * the interrupt, and we need to make sure the entry is fully populated
233 * before that happens.
234 */
235 static void
236 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
237 {
238 union entry_union eu;
239 eu.entry = e;
240 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
241 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
242 }
243
244 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
245 {
246 unsigned long flags;
247 spin_lock_irqsave(&ioapic_lock, flags);
248 __ioapic_write_entry(apic, pin, e);
249 spin_unlock_irqrestore(&ioapic_lock, flags);
250 }
251
252 /*
253 * When we mask an IO APIC routing entry, we need to write the low
254 * word first, in order to set the mask bit before we change the
255 * high bits!
256 */
257 static void ioapic_mask_entry(int apic, int pin)
258 {
259 unsigned long flags;
260 union entry_union eu = { .entry.mask = 1 };
261
262 spin_lock_irqsave(&ioapic_lock, flags);
263 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
264 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
265 spin_unlock_irqrestore(&ioapic_lock, flags);
266 }
267
268 #ifdef CONFIG_SMP
269 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
270 {
271 int apic, pin;
272 struct irq_pin_list *entry = irq_2_pin + irq;
273
274 BUG_ON(irq >= NR_IRQS);
275 for (;;) {
276 unsigned int reg;
277 apic = entry->apic;
278 pin = entry->pin;
279 if (pin == -1)
280 break;
281 io_apic_write(apic, 0x11 + pin*2, dest);
282 reg = io_apic_read(apic, 0x10 + pin*2);
283 reg &= ~0x000000ff;
284 reg |= vector;
285 io_apic_modify(apic, reg);
286 if (!entry->next)
287 break;
288 entry = irq_2_pin + entry->next;
289 }
290 }
291
292 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
293 {
294 struct irq_cfg *cfg = irq_cfg + irq;
295 unsigned long flags;
296 unsigned int dest;
297 cpumask_t tmp;
298
299 cpus_and(tmp, mask, cpu_online_map);
300 if (cpus_empty(tmp))
301 return;
302
303 if (assign_irq_vector(irq, mask))
304 return;
305
306 cpus_and(tmp, cfg->domain, mask);
307 dest = cpu_mask_to_apicid(tmp);
308
309 /*
310 * Only the high 8 bits are valid.
311 */
312 dest = SET_APIC_LOGICAL_ID(dest);
313
314 spin_lock_irqsave(&ioapic_lock, flags);
315 __target_IO_APIC_irq(irq, dest, cfg->vector);
316 irq_desc[irq].affinity = mask;
317 spin_unlock_irqrestore(&ioapic_lock, flags);
318 }
319 #endif
320
321 /*
322 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
323 * shared ISA-space IRQs, so we have to support them. We are super
324 * fast in the common case, and fast for shared ISA-space IRQs.
325 */
326 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
327 {
328 static int first_free_entry = NR_IRQS;
329 struct irq_pin_list *entry = irq_2_pin + irq;
330
331 BUG_ON(irq >= NR_IRQS);
332 while (entry->next)
333 entry = irq_2_pin + entry->next;
334
335 if (entry->pin != -1) {
336 entry->next = first_free_entry;
337 entry = irq_2_pin + entry->next;
338 if (++first_free_entry >= PIN_MAP_SIZE)
339 panic("io_apic.c: ran out of irq_2_pin entries!");
340 }
341 entry->apic = apic;
342 entry->pin = pin;
343 }
344
345
346 #define DO_ACTION(name,R,ACTION, FINAL) \
347 \
348 static void name##_IO_APIC_irq (unsigned int irq) \
349 __DO_ACTION(R, ACTION, FINAL)
350
351 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
352 /* mask = 1 */
353 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
354 /* mask = 0 */
355
356 static void mask_IO_APIC_irq (unsigned int irq)
357 {
358 unsigned long flags;
359
360 spin_lock_irqsave(&ioapic_lock, flags);
361 __mask_IO_APIC_irq(irq);
362 spin_unlock_irqrestore(&ioapic_lock, flags);
363 }
364
365 static void unmask_IO_APIC_irq (unsigned int irq)
366 {
367 unsigned long flags;
368
369 spin_lock_irqsave(&ioapic_lock, flags);
370 __unmask_IO_APIC_irq(irq);
371 spin_unlock_irqrestore(&ioapic_lock, flags);
372 }
373
374 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
375 {
376 struct IO_APIC_route_entry entry;
377
378 /* Check delivery_mode to be sure we're not clearing an SMI pin */
379 entry = ioapic_read_entry(apic, pin);
380 if (entry.delivery_mode == dest_SMI)
381 return;
382 /*
383 * Disable it in the IO-APIC irq-routing table:
384 */
385 ioapic_mask_entry(apic, pin);
386 }
387
388 static void clear_IO_APIC (void)
389 {
390 int apic, pin;
391
392 for (apic = 0; apic < nr_ioapics; apic++)
393 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
394 clear_IO_APIC_pin(apic, pin);
395 }
396
397 int skip_ioapic_setup;
398 int ioapic_force;
399
400 /* dummy parsing: see setup.c */
401
402 static int __init disable_ioapic_setup(char *str)
403 {
404 skip_ioapic_setup = 1;
405 return 0;
406 }
407 early_param("noapic", disable_ioapic_setup);
408
409 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
410 static int __init disable_timer_pin_setup(char *arg)
411 {
412 disable_timer_pin_1 = 1;
413 return 1;
414 }
415 __setup("disable_timer_pin_1", disable_timer_pin_setup);
416
417 static int __init setup_disable_8254_timer(char *s)
418 {
419 timer_over_8254 = -1;
420 return 1;
421 }
422 static int __init setup_enable_8254_timer(char *s)
423 {
424 timer_over_8254 = 2;
425 return 1;
426 }
427
428 __setup("disable_8254_timer", setup_disable_8254_timer);
429 __setup("enable_8254_timer", setup_enable_8254_timer);
430
431
432 /*
433 * Find the IRQ entry number of a certain pin.
434 */
435 static int find_irq_entry(int apic, int pin, int type)
436 {
437 int i;
438
439 for (i = 0; i < mp_irq_entries; i++)
440 if (mp_irqs[i].mpc_irqtype == type &&
441 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
442 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
443 mp_irqs[i].mpc_dstirq == pin)
444 return i;
445
446 return -1;
447 }
448
449 /*
450 * Find the pin to which IRQ[irq] (ISA) is connected
451 */
452 static int __init find_isa_irq_pin(int irq, int type)
453 {
454 int i;
455
456 for (i = 0; i < mp_irq_entries; i++) {
457 int lbus = mp_irqs[i].mpc_srcbus;
458
459 if (test_bit(lbus, mp_bus_not_pci) &&
460 (mp_irqs[i].mpc_irqtype == type) &&
461 (mp_irqs[i].mpc_srcbusirq == irq))
462
463 return mp_irqs[i].mpc_dstirq;
464 }
465 return -1;
466 }
467
468 static int __init find_isa_irq_apic(int irq, int type)
469 {
470 int i;
471
472 for (i = 0; i < mp_irq_entries; i++) {
473 int lbus = mp_irqs[i].mpc_srcbus;
474
475 if (test_bit(lbus, mp_bus_not_pci) &&
476 (mp_irqs[i].mpc_irqtype == type) &&
477 (mp_irqs[i].mpc_srcbusirq == irq))
478 break;
479 }
480 if (i < mp_irq_entries) {
481 int apic;
482 for(apic = 0; apic < nr_ioapics; apic++) {
483 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
484 return apic;
485 }
486 }
487
488 return -1;
489 }
490
491 /*
492 * Find a specific PCI IRQ entry.
493 * Not an __init, possibly needed by modules
494 */
495 static int pin_2_irq(int idx, int apic, int pin);
496
497 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
498 {
499 int apic, i, best_guess = -1;
500
501 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
502 bus, slot, pin);
503 if (mp_bus_id_to_pci_bus[bus] == -1) {
504 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
505 return -1;
506 }
507 for (i = 0; i < mp_irq_entries; i++) {
508 int lbus = mp_irqs[i].mpc_srcbus;
509
510 for (apic = 0; apic < nr_ioapics; apic++)
511 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
512 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
513 break;
514
515 if (!test_bit(lbus, mp_bus_not_pci) &&
516 !mp_irqs[i].mpc_irqtype &&
517 (bus == lbus) &&
518 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
519 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
520
521 if (!(apic || IO_APIC_IRQ(irq)))
522 continue;
523
524 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
525 return irq;
526 /*
527 * Use the first all-but-pin matching entry as a
528 * best-guess fuzzy result for broken mptables.
529 */
530 if (best_guess < 0)
531 best_guess = irq;
532 }
533 }
534 BUG_ON(best_guess >= NR_IRQS);
535 return best_guess;
536 }
537
538 /* ISA interrupts are always polarity zero edge triggered,
539 * when listed as conforming in the MP table. */
540
541 #define default_ISA_trigger(idx) (0)
542 #define default_ISA_polarity(idx) (0)
543
544 /* PCI interrupts are always polarity one level triggered,
545 * when listed as conforming in the MP table. */
546
547 #define default_PCI_trigger(idx) (1)
548 #define default_PCI_polarity(idx) (1)
549
550 static int __init MPBIOS_polarity(int idx)
551 {
552 int bus = mp_irqs[idx].mpc_srcbus;
553 int polarity;
554
555 /*
556 * Determine IRQ line polarity (high active or low active):
557 */
558 switch (mp_irqs[idx].mpc_irqflag & 3)
559 {
560 case 0: /* conforms, ie. bus-type dependent polarity */
561 if (test_bit(bus, mp_bus_not_pci))
562 polarity = default_ISA_polarity(idx);
563 else
564 polarity = default_PCI_polarity(idx);
565 break;
566 case 1: /* high active */
567 {
568 polarity = 0;
569 break;
570 }
571 case 2: /* reserved */
572 {
573 printk(KERN_WARNING "broken BIOS!!\n");
574 polarity = 1;
575 break;
576 }
577 case 3: /* low active */
578 {
579 polarity = 1;
580 break;
581 }
582 default: /* invalid */
583 {
584 printk(KERN_WARNING "broken BIOS!!\n");
585 polarity = 1;
586 break;
587 }
588 }
589 return polarity;
590 }
591
592 static int MPBIOS_trigger(int idx)
593 {
594 int bus = mp_irqs[idx].mpc_srcbus;
595 int trigger;
596
597 /*
598 * Determine IRQ trigger mode (edge or level sensitive):
599 */
600 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
601 {
602 case 0: /* conforms, ie. bus-type dependent */
603 if (test_bit(bus, mp_bus_not_pci))
604 trigger = default_ISA_trigger(idx);
605 else
606 trigger = default_PCI_trigger(idx);
607 break;
608 case 1: /* edge */
609 {
610 trigger = 0;
611 break;
612 }
613 case 2: /* reserved */
614 {
615 printk(KERN_WARNING "broken BIOS!!\n");
616 trigger = 1;
617 break;
618 }
619 case 3: /* level */
620 {
621 trigger = 1;
622 break;
623 }
624 default: /* invalid */
625 {
626 printk(KERN_WARNING "broken BIOS!!\n");
627 trigger = 0;
628 break;
629 }
630 }
631 return trigger;
632 }
633
634 static inline int irq_polarity(int idx)
635 {
636 return MPBIOS_polarity(idx);
637 }
638
639 static inline int irq_trigger(int idx)
640 {
641 return MPBIOS_trigger(idx);
642 }
643
644 static int pin_2_irq(int idx, int apic, int pin)
645 {
646 int irq, i;
647 int bus = mp_irqs[idx].mpc_srcbus;
648
649 /*
650 * Debugging check, we are in big trouble if this message pops up!
651 */
652 if (mp_irqs[idx].mpc_dstirq != pin)
653 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
654
655 if (test_bit(bus, mp_bus_not_pci)) {
656 irq = mp_irqs[idx].mpc_srcbusirq;
657 } else {
658 /*
659 * PCI IRQs are mapped in order
660 */
661 i = irq = 0;
662 while (i < apic)
663 irq += nr_ioapic_registers[i++];
664 irq += pin;
665 }
666 BUG_ON(irq >= NR_IRQS);
667 return irq;
668 }
669
670 static int __assign_irq_vector(int irq, cpumask_t mask)
671 {
672 /*
673 * NOTE! The local APIC isn't very good at handling
674 * multiple interrupts at the same interrupt level.
675 * As the interrupt level is determined by taking the
676 * vector number and shifting that right by 4, we
677 * want to spread these out a bit so that they don't
678 * all fall in the same interrupt level.
679 *
680 * Also, we've got to be careful not to trash gate
681 * 0x80, because int 0x80 is hm, kind of importantish. ;)
682 */
683 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
684 unsigned int old_vector;
685 int cpu;
686 struct irq_cfg *cfg;
687
688 BUG_ON((unsigned)irq >= NR_IRQS);
689 cfg = &irq_cfg[irq];
690
691 /* Only try and allocate irqs on cpus that are present */
692 cpus_and(mask, mask, cpu_online_map);
693
694 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
695 return -EBUSY;
696
697 old_vector = cfg->vector;
698 if (old_vector) {
699 cpumask_t tmp;
700 cpus_and(tmp, cfg->domain, mask);
701 if (!cpus_empty(tmp))
702 return 0;
703 }
704
705 for_each_cpu_mask(cpu, mask) {
706 cpumask_t domain, new_mask;
707 int new_cpu;
708 int vector, offset;
709
710 domain = vector_allocation_domain(cpu);
711 cpus_and(new_mask, domain, cpu_online_map);
712
713 vector = current_vector;
714 offset = current_offset;
715 next:
716 vector += 8;
717 if (vector >= FIRST_SYSTEM_VECTOR) {
718 /* If we run out of vectors on large boxen, must share them. */
719 offset = (offset + 1) % 8;
720 vector = FIRST_DEVICE_VECTOR + offset;
721 }
722 if (unlikely(current_vector == vector))
723 continue;
724 if (vector == IA32_SYSCALL_VECTOR)
725 goto next;
726 for_each_cpu_mask(new_cpu, new_mask)
727 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
728 goto next;
729 /* Found one! */
730 current_vector = vector;
731 current_offset = offset;
732 if (old_vector) {
733 cfg->move_in_progress = 1;
734 cfg->old_domain = cfg->domain;
735 }
736 for_each_cpu_mask(new_cpu, new_mask)
737 per_cpu(vector_irq, new_cpu)[vector] = irq;
738 cfg->vector = vector;
739 cfg->domain = domain;
740 return 0;
741 }
742 return -ENOSPC;
743 }
744
745 static int assign_irq_vector(int irq, cpumask_t mask)
746 {
747 int err;
748 unsigned long flags;
749
750 spin_lock_irqsave(&vector_lock, flags);
751 err = __assign_irq_vector(irq, mask);
752 spin_unlock_irqrestore(&vector_lock, flags);
753 return err;
754 }
755
756 static void __clear_irq_vector(int irq)
757 {
758 struct irq_cfg *cfg;
759 cpumask_t mask;
760 int cpu, vector;
761
762 BUG_ON((unsigned)irq >= NR_IRQS);
763 cfg = &irq_cfg[irq];
764 BUG_ON(!cfg->vector);
765
766 vector = cfg->vector;
767 cpus_and(mask, cfg->domain, cpu_online_map);
768 for_each_cpu_mask(cpu, mask)
769 per_cpu(vector_irq, cpu)[vector] = -1;
770
771 cfg->vector = 0;
772 cfg->domain = CPU_MASK_NONE;
773 }
774
775 void __setup_vector_irq(int cpu)
776 {
777 /* Initialize vector_irq on a new cpu */
778 /* This function must be called with vector_lock held */
779 int irq, vector;
780
781 /* Mark the inuse vectors */
782 for (irq = 0; irq < NR_IRQS; ++irq) {
783 if (!cpu_isset(cpu, irq_cfg[irq].domain))
784 continue;
785 vector = irq_cfg[irq].vector;
786 per_cpu(vector_irq, cpu)[vector] = irq;
787 }
788 /* Mark the free vectors */
789 for (vector = 0; vector < NR_VECTORS; ++vector) {
790 irq = per_cpu(vector_irq, cpu)[vector];
791 if (irq < 0)
792 continue;
793 if (!cpu_isset(cpu, irq_cfg[irq].domain))
794 per_cpu(vector_irq, cpu)[vector] = -1;
795 }
796 }
797
798
799 static struct irq_chip ioapic_chip;
800
801 static void ioapic_register_intr(int irq, unsigned long trigger)
802 {
803 if (trigger)
804 set_irq_chip_and_handler_name(irq, &ioapic_chip,
805 handle_fasteoi_irq, "fasteoi");
806 else
807 set_irq_chip_and_handler_name(irq, &ioapic_chip,
808 handle_edge_irq, "edge");
809 }
810
811 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
812 int trigger, int polarity)
813 {
814 struct irq_cfg *cfg = irq_cfg + irq;
815 struct IO_APIC_route_entry entry;
816 cpumask_t mask;
817
818 if (!IO_APIC_IRQ(irq))
819 return;
820
821 mask = TARGET_CPUS;
822 if (assign_irq_vector(irq, mask))
823 return;
824
825 cpus_and(mask, cfg->domain, mask);
826
827 apic_printk(APIC_VERBOSE,KERN_DEBUG
828 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
829 "IRQ %d Mode:%i Active:%i)\n",
830 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
831 irq, trigger, polarity);
832
833 /*
834 * add it to the IO-APIC irq-routing table:
835 */
836 memset(&entry,0,sizeof(entry));
837
838 entry.delivery_mode = INT_DELIVERY_MODE;
839 entry.dest_mode = INT_DEST_MODE;
840 entry.dest = cpu_mask_to_apicid(mask);
841 entry.mask = 0; /* enable IRQ */
842 entry.trigger = trigger;
843 entry.polarity = polarity;
844 entry.vector = cfg->vector;
845
846 /* Mask level triggered irqs.
847 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
848 */
849 if (trigger)
850 entry.mask = 1;
851
852 ioapic_register_intr(irq, trigger);
853 if (irq < 16)
854 disable_8259A_irq(irq);
855
856 ioapic_write_entry(apic, pin, entry);
857 }
858
859 static void __init setup_IO_APIC_irqs(void)
860 {
861 int apic, pin, idx, irq, first_notcon = 1;
862
863 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
864
865 for (apic = 0; apic < nr_ioapics; apic++) {
866 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
867
868 idx = find_irq_entry(apic,pin,mp_INT);
869 if (idx == -1) {
870 if (first_notcon) {
871 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
872 first_notcon = 0;
873 } else
874 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
875 continue;
876 }
877
878 irq = pin_2_irq(idx, apic, pin);
879 add_pin_to_irq(irq, apic, pin);
880
881 setup_IO_APIC_irq(apic, pin, irq,
882 irq_trigger(idx), irq_polarity(idx));
883 }
884 }
885
886 if (!first_notcon)
887 apic_printk(APIC_VERBOSE," not connected.\n");
888 }
889
890 /*
891 * Set up the 8259A-master output pin as broadcast to all
892 * CPUs.
893 */
894 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
895 {
896 struct IO_APIC_route_entry entry;
897 unsigned long flags;
898
899 memset(&entry,0,sizeof(entry));
900
901 disable_8259A_irq(0);
902
903 /* mask LVT0 */
904 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
905
906 /*
907 * We use logical delivery to get the timer IRQ
908 * to the first CPU.
909 */
910 entry.dest_mode = INT_DEST_MODE;
911 entry.mask = 0; /* unmask IRQ now */
912 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
913 entry.delivery_mode = INT_DELIVERY_MODE;
914 entry.polarity = 0;
915 entry.trigger = 0;
916 entry.vector = vector;
917
918 /*
919 * The timer IRQ doesn't have to know that behind the
920 * scene we have a 8259A-master in AEOI mode ...
921 */
922 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
923
924 /*
925 * Add it to the IO-APIC irq-routing table:
926 */
927 spin_lock_irqsave(&ioapic_lock, flags);
928 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
929 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
930 spin_unlock_irqrestore(&ioapic_lock, flags);
931
932 enable_8259A_irq(0);
933 }
934
935 void __apicdebuginit print_IO_APIC(void)
936 {
937 int apic, i;
938 union IO_APIC_reg_00 reg_00;
939 union IO_APIC_reg_01 reg_01;
940 union IO_APIC_reg_02 reg_02;
941 unsigned long flags;
942
943 if (apic_verbosity == APIC_QUIET)
944 return;
945
946 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
947 for (i = 0; i < nr_ioapics; i++)
948 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
949 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
950
951 /*
952 * We are a bit conservative about what we expect. We have to
953 * know about every hardware change ASAP.
954 */
955 printk(KERN_INFO "testing the IO APIC.......................\n");
956
957 for (apic = 0; apic < nr_ioapics; apic++) {
958
959 spin_lock_irqsave(&ioapic_lock, flags);
960 reg_00.raw = io_apic_read(apic, 0);
961 reg_01.raw = io_apic_read(apic, 1);
962 if (reg_01.bits.version >= 0x10)
963 reg_02.raw = io_apic_read(apic, 2);
964 spin_unlock_irqrestore(&ioapic_lock, flags);
965
966 printk("\n");
967 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
968 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
969 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
970
971 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
972 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
973
974 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
975 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
976
977 if (reg_01.bits.version >= 0x10) {
978 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
979 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
980 }
981
982 printk(KERN_DEBUG ".... IRQ redirection table:\n");
983
984 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
985 " Stat Dmod Deli Vect: \n");
986
987 for (i = 0; i <= reg_01.bits.entries; i++) {
988 struct IO_APIC_route_entry entry;
989
990 entry = ioapic_read_entry(apic, i);
991
992 printk(KERN_DEBUG " %02x %03X ",
993 i,
994 entry.dest
995 );
996
997 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
998 entry.mask,
999 entry.trigger,
1000 entry.irr,
1001 entry.polarity,
1002 entry.delivery_status,
1003 entry.dest_mode,
1004 entry.delivery_mode,
1005 entry.vector
1006 );
1007 }
1008 }
1009 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1010 for (i = 0; i < NR_IRQS; i++) {
1011 struct irq_pin_list *entry = irq_2_pin + i;
1012 if (entry->pin < 0)
1013 continue;
1014 printk(KERN_DEBUG "IRQ%d ", i);
1015 for (;;) {
1016 printk("-> %d:%d", entry->apic, entry->pin);
1017 if (!entry->next)
1018 break;
1019 entry = irq_2_pin + entry->next;
1020 }
1021 printk("\n");
1022 }
1023
1024 printk(KERN_INFO ".................................... done.\n");
1025
1026 return;
1027 }
1028
1029 #if 0
1030
1031 static __apicdebuginit void print_APIC_bitfield (int base)
1032 {
1033 unsigned int v;
1034 int i, j;
1035
1036 if (apic_verbosity == APIC_QUIET)
1037 return;
1038
1039 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1040 for (i = 0; i < 8; i++) {
1041 v = apic_read(base + i*0x10);
1042 for (j = 0; j < 32; j++) {
1043 if (v & (1<<j))
1044 printk("1");
1045 else
1046 printk("0");
1047 }
1048 printk("\n");
1049 }
1050 }
1051
1052 void __apicdebuginit print_local_APIC(void * dummy)
1053 {
1054 unsigned int v, ver, maxlvt;
1055
1056 if (apic_verbosity == APIC_QUIET)
1057 return;
1058
1059 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1060 smp_processor_id(), hard_smp_processor_id());
1061 v = apic_read(APIC_ID);
1062 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1063 v = apic_read(APIC_LVR);
1064 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1065 ver = GET_APIC_VERSION(v);
1066 maxlvt = get_maxlvt();
1067
1068 v = apic_read(APIC_TASKPRI);
1069 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1070
1071 v = apic_read(APIC_ARBPRI);
1072 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1073 v & APIC_ARBPRI_MASK);
1074 v = apic_read(APIC_PROCPRI);
1075 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1076
1077 v = apic_read(APIC_EOI);
1078 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1079 v = apic_read(APIC_RRR);
1080 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1081 v = apic_read(APIC_LDR);
1082 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1083 v = apic_read(APIC_DFR);
1084 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1085 v = apic_read(APIC_SPIV);
1086 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1087
1088 printk(KERN_DEBUG "... APIC ISR field:\n");
1089 print_APIC_bitfield(APIC_ISR);
1090 printk(KERN_DEBUG "... APIC TMR field:\n");
1091 print_APIC_bitfield(APIC_TMR);
1092 printk(KERN_DEBUG "... APIC IRR field:\n");
1093 print_APIC_bitfield(APIC_IRR);
1094
1095 v = apic_read(APIC_ESR);
1096 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1097
1098 v = apic_read(APIC_ICR);
1099 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1100 v = apic_read(APIC_ICR2);
1101 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1102
1103 v = apic_read(APIC_LVTT);
1104 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1105
1106 if (maxlvt > 3) { /* PC is LVT#4. */
1107 v = apic_read(APIC_LVTPC);
1108 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1109 }
1110 v = apic_read(APIC_LVT0);
1111 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1112 v = apic_read(APIC_LVT1);
1113 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1114
1115 if (maxlvt > 2) { /* ERR is LVT#3. */
1116 v = apic_read(APIC_LVTERR);
1117 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1118 }
1119
1120 v = apic_read(APIC_TMICT);
1121 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1122 v = apic_read(APIC_TMCCT);
1123 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1124 v = apic_read(APIC_TDCR);
1125 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1126 printk("\n");
1127 }
1128
1129 void print_all_local_APICs (void)
1130 {
1131 on_each_cpu(print_local_APIC, NULL, 1, 1);
1132 }
1133
1134 void __apicdebuginit print_PIC(void)
1135 {
1136 unsigned int v;
1137 unsigned long flags;
1138
1139 if (apic_verbosity == APIC_QUIET)
1140 return;
1141
1142 printk(KERN_DEBUG "\nprinting PIC contents\n");
1143
1144 spin_lock_irqsave(&i8259A_lock, flags);
1145
1146 v = inb(0xa1) << 8 | inb(0x21);
1147 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1148
1149 v = inb(0xa0) << 8 | inb(0x20);
1150 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1151
1152 outb(0x0b,0xa0);
1153 outb(0x0b,0x20);
1154 v = inb(0xa0) << 8 | inb(0x20);
1155 outb(0x0a,0xa0);
1156 outb(0x0a,0x20);
1157
1158 spin_unlock_irqrestore(&i8259A_lock, flags);
1159
1160 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1161
1162 v = inb(0x4d1) << 8 | inb(0x4d0);
1163 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1164 }
1165
1166 #endif /* 0 */
1167
1168 static void __init enable_IO_APIC(void)
1169 {
1170 union IO_APIC_reg_01 reg_01;
1171 int i8259_apic, i8259_pin;
1172 int i, apic;
1173 unsigned long flags;
1174
1175 for (i = 0; i < PIN_MAP_SIZE; i++) {
1176 irq_2_pin[i].pin = -1;
1177 irq_2_pin[i].next = 0;
1178 }
1179
1180 /*
1181 * The number of IO-APIC IRQ registers (== #pins):
1182 */
1183 for (apic = 0; apic < nr_ioapics; apic++) {
1184 spin_lock_irqsave(&ioapic_lock, flags);
1185 reg_01.raw = io_apic_read(apic, 1);
1186 spin_unlock_irqrestore(&ioapic_lock, flags);
1187 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1188 }
1189 for(apic = 0; apic < nr_ioapics; apic++) {
1190 int pin;
1191 /* See if any of the pins is in ExtINT mode */
1192 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1193 struct IO_APIC_route_entry entry;
1194 entry = ioapic_read_entry(apic, pin);
1195
1196 /* If the interrupt line is enabled and in ExtInt mode
1197 * I have found the pin where the i8259 is connected.
1198 */
1199 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1200 ioapic_i8259.apic = apic;
1201 ioapic_i8259.pin = pin;
1202 goto found_i8259;
1203 }
1204 }
1205 }
1206 found_i8259:
1207 /* Look to see what if the MP table has reported the ExtINT */
1208 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1209 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1210 /* Trust the MP table if nothing is setup in the hardware */
1211 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1212 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1213 ioapic_i8259.pin = i8259_pin;
1214 ioapic_i8259.apic = i8259_apic;
1215 }
1216 /* Complain if the MP table and the hardware disagree */
1217 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1218 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1219 {
1220 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1221 }
1222
1223 /*
1224 * Do not trust the IO-APIC being empty at bootup
1225 */
1226 clear_IO_APIC();
1227 }
1228
1229 /*
1230 * Not an __init, needed by the reboot code
1231 */
1232 void disable_IO_APIC(void)
1233 {
1234 /*
1235 * Clear the IO-APIC before rebooting:
1236 */
1237 clear_IO_APIC();
1238
1239 /*
1240 * If the i8259 is routed through an IOAPIC
1241 * Put that IOAPIC in virtual wire mode
1242 * so legacy interrupts can be delivered.
1243 */
1244 if (ioapic_i8259.pin != -1) {
1245 struct IO_APIC_route_entry entry;
1246
1247 memset(&entry, 0, sizeof(entry));
1248 entry.mask = 0; /* Enabled */
1249 entry.trigger = 0; /* Edge */
1250 entry.irr = 0;
1251 entry.polarity = 0; /* High */
1252 entry.delivery_status = 0;
1253 entry.dest_mode = 0; /* Physical */
1254 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1255 entry.vector = 0;
1256 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
1257
1258 /*
1259 * Add it to the IO-APIC irq-routing table:
1260 */
1261 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1262 }
1263
1264 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1265 }
1266
1267 /*
1268 * There is a nasty bug in some older SMP boards, their mptable lies
1269 * about the timer IRQ. We do the following to work around the situation:
1270 *
1271 * - timer IRQ defaults to IO-APIC IRQ
1272 * - if this function detects that timer IRQs are defunct, then we fall
1273 * back to ISA timer IRQs
1274 */
1275 static int __init timer_irq_works(void)
1276 {
1277 unsigned long t1 = jiffies;
1278
1279 local_irq_enable();
1280 /* Let ten ticks pass... */
1281 mdelay((10 * 1000) / HZ);
1282
1283 /*
1284 * Expect a few ticks at least, to be sure some possible
1285 * glue logic does not lock up after one or two first
1286 * ticks in a non-ExtINT mode. Also the local APIC
1287 * might have cached one ExtINT interrupt. Finally, at
1288 * least one tick may be lost due to delays.
1289 */
1290
1291 /* jiffies wrap? */
1292 if (jiffies - t1 > 4)
1293 return 1;
1294 return 0;
1295 }
1296
1297 /*
1298 * In the SMP+IOAPIC case it might happen that there are an unspecified
1299 * number of pending IRQ events unhandled. These cases are very rare,
1300 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1301 * better to do it this way as thus we do not have to be aware of
1302 * 'pending' interrupts in the IRQ path, except at this point.
1303 */
1304 /*
1305 * Edge triggered needs to resend any interrupt
1306 * that was delayed but this is now handled in the device
1307 * independent code.
1308 */
1309
1310 /*
1311 * Starting up a edge-triggered IO-APIC interrupt is
1312 * nasty - we need to make sure that we get the edge.
1313 * If it is already asserted for some reason, we need
1314 * return 1 to indicate that is was pending.
1315 *
1316 * This is not complete - we should be able to fake
1317 * an edge even if it isn't on the 8259A...
1318 */
1319
1320 static unsigned int startup_ioapic_irq(unsigned int irq)
1321 {
1322 int was_pending = 0;
1323 unsigned long flags;
1324
1325 spin_lock_irqsave(&ioapic_lock, flags);
1326 if (irq < 16) {
1327 disable_8259A_irq(irq);
1328 if (i8259A_irq_pending(irq))
1329 was_pending = 1;
1330 }
1331 __unmask_IO_APIC_irq(irq);
1332 spin_unlock_irqrestore(&ioapic_lock, flags);
1333
1334 return was_pending;
1335 }
1336
1337 static int ioapic_retrigger_irq(unsigned int irq)
1338 {
1339 struct irq_cfg *cfg = &irq_cfg[irq];
1340 cpumask_t mask;
1341 unsigned long flags;
1342
1343 spin_lock_irqsave(&vector_lock, flags);
1344 cpus_clear(mask);
1345 cpu_set(first_cpu(cfg->domain), mask);
1346
1347 send_IPI_mask(mask, cfg->vector);
1348 spin_unlock_irqrestore(&vector_lock, flags);
1349
1350 return 1;
1351 }
1352
1353 /*
1354 * Level and edge triggered IO-APIC interrupts need different handling,
1355 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1356 * handled with the level-triggered descriptor, but that one has slightly
1357 * more overhead. Level-triggered interrupts cannot be handled with the
1358 * edge-triggered handler, without risking IRQ storms and other ugly
1359 * races.
1360 */
1361
1362 #ifdef CONFIG_SMP
1363 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1364 {
1365 unsigned vector, me;
1366 ack_APIC_irq();
1367 exit_idle();
1368 irq_enter();
1369
1370 me = smp_processor_id();
1371 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1372 unsigned int irq;
1373 struct irq_desc *desc;
1374 struct irq_cfg *cfg;
1375 irq = __get_cpu_var(vector_irq)[vector];
1376 if (irq >= NR_IRQS)
1377 continue;
1378
1379 desc = irq_desc + irq;
1380 cfg = irq_cfg + irq;
1381 spin_lock(&desc->lock);
1382 if (!cfg->move_cleanup_count)
1383 goto unlock;
1384
1385 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1386 goto unlock;
1387
1388 __get_cpu_var(vector_irq)[vector] = -1;
1389 cfg->move_cleanup_count--;
1390 unlock:
1391 spin_unlock(&desc->lock);
1392 }
1393
1394 irq_exit();
1395 }
1396
1397 static void irq_complete_move(unsigned int irq)
1398 {
1399 struct irq_cfg *cfg = irq_cfg + irq;
1400 unsigned vector, me;
1401
1402 if (likely(!cfg->move_in_progress))
1403 return;
1404
1405 vector = ~get_irq_regs()->orig_rax;
1406 me = smp_processor_id();
1407 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1408 cpumask_t cleanup_mask;
1409
1410 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1411 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1412 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1413 cfg->move_in_progress = 0;
1414 }
1415 }
1416 #else
1417 static inline void irq_complete_move(unsigned int irq) {}
1418 #endif
1419
1420 static void ack_apic_edge(unsigned int irq)
1421 {
1422 irq_complete_move(irq);
1423 move_native_irq(irq);
1424 ack_APIC_irq();
1425 }
1426
1427 static void ack_apic_level(unsigned int irq)
1428 {
1429 int do_unmask_irq = 0;
1430
1431 irq_complete_move(irq);
1432 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1433 /* If we are moving the irq we need to mask it */
1434 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1435 do_unmask_irq = 1;
1436 mask_IO_APIC_irq(irq);
1437 }
1438 #endif
1439
1440 /*
1441 * We must acknowledge the irq before we move it or the acknowledge will
1442 * not propagate properly.
1443 */
1444 ack_APIC_irq();
1445
1446 /* Now we can move and renable the irq */
1447 if (unlikely(do_unmask_irq)) {
1448 /* Only migrate the irq if the ack has been received.
1449 *
1450 * On rare occasions the broadcast level triggered ack gets
1451 * delayed going to ioapics, and if we reprogram the
1452 * vector while Remote IRR is still set the irq will never
1453 * fire again.
1454 *
1455 * To prevent this scenario we read the Remote IRR bit
1456 * of the ioapic. This has two effects.
1457 * - On any sane system the read of the ioapic will
1458 * flush writes (and acks) going to the ioapic from
1459 * this cpu.
1460 * - We get to see if the ACK has actually been delivered.
1461 *
1462 * Based on failed experiments of reprogramming the
1463 * ioapic entry from outside of irq context starting
1464 * with masking the ioapic entry and then polling until
1465 * Remote IRR was clear before reprogramming the
1466 * ioapic I don't trust the Remote IRR bit to be
1467 * completey accurate.
1468 *
1469 * However there appears to be no other way to plug
1470 * this race, so if the Remote IRR bit is not
1471 * accurate and is causing problems then it is a hardware bug
1472 * and you can go talk to the chipset vendor about it.
1473 */
1474 if (!io_apic_level_ack_pending(irq))
1475 move_masked_irq(irq);
1476 unmask_IO_APIC_irq(irq);
1477 }
1478 }
1479
1480 static struct irq_chip ioapic_chip __read_mostly = {
1481 .name = "IO-APIC",
1482 .startup = startup_ioapic_irq,
1483 .mask = mask_IO_APIC_irq,
1484 .unmask = unmask_IO_APIC_irq,
1485 .ack = ack_apic_edge,
1486 .eoi = ack_apic_level,
1487 #ifdef CONFIG_SMP
1488 .set_affinity = set_ioapic_affinity_irq,
1489 #endif
1490 .retrigger = ioapic_retrigger_irq,
1491 };
1492
1493 static inline void init_IO_APIC_traps(void)
1494 {
1495 int irq;
1496
1497 /*
1498 * NOTE! The local APIC isn't very good at handling
1499 * multiple interrupts at the same interrupt level.
1500 * As the interrupt level is determined by taking the
1501 * vector number and shifting that right by 4, we
1502 * want to spread these out a bit so that they don't
1503 * all fall in the same interrupt level.
1504 *
1505 * Also, we've got to be careful not to trash gate
1506 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1507 */
1508 for (irq = 0; irq < NR_IRQS ; irq++) {
1509 int tmp = irq;
1510 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1511 /*
1512 * Hmm.. We don't have an entry for this,
1513 * so default to an old-fashioned 8259
1514 * interrupt if we can..
1515 */
1516 if (irq < 16)
1517 make_8259A_irq(irq);
1518 else
1519 /* Strange. Oh, well.. */
1520 irq_desc[irq].chip = &no_irq_chip;
1521 }
1522 }
1523 }
1524
1525 static void enable_lapic_irq (unsigned int irq)
1526 {
1527 unsigned long v;
1528
1529 v = apic_read(APIC_LVT0);
1530 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1531 }
1532
1533 static void disable_lapic_irq (unsigned int irq)
1534 {
1535 unsigned long v;
1536
1537 v = apic_read(APIC_LVT0);
1538 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1539 }
1540
1541 static void ack_lapic_irq (unsigned int irq)
1542 {
1543 ack_APIC_irq();
1544 }
1545
1546 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1547
1548 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1549 .name = "local-APIC",
1550 .typename = "local-APIC-edge",
1551 .startup = NULL, /* startup_irq() not used for IRQ0 */
1552 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1553 .enable = enable_lapic_irq,
1554 .disable = disable_lapic_irq,
1555 .ack = ack_lapic_irq,
1556 .end = end_lapic_irq,
1557 };
1558
1559 static void setup_nmi (void)
1560 {
1561 /*
1562 * Dirty trick to enable the NMI watchdog ...
1563 * We put the 8259A master into AEOI mode and
1564 * unmask on all local APICs LVT0 as NMI.
1565 *
1566 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1567 * is from Maciej W. Rozycki - so we do not have to EOI from
1568 * the NMI handler or the timer interrupt.
1569 */
1570 printk(KERN_INFO "activating NMI Watchdog ...");
1571
1572 enable_NMI_through_LVT0(NULL);
1573
1574 printk(" done.\n");
1575 }
1576
1577 /*
1578 * This looks a bit hackish but it's about the only one way of sending
1579 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1580 * not support the ExtINT mode, unfortunately. We need to send these
1581 * cycles as some i82489DX-based boards have glue logic that keeps the
1582 * 8259A interrupt line asserted until INTA. --macro
1583 */
1584 static inline void unlock_ExtINT_logic(void)
1585 {
1586 int apic, pin, i;
1587 struct IO_APIC_route_entry entry0, entry1;
1588 unsigned char save_control, save_freq_select;
1589 unsigned long flags;
1590
1591 pin = find_isa_irq_pin(8, mp_INT);
1592 apic = find_isa_irq_apic(8, mp_INT);
1593 if (pin == -1)
1594 return;
1595
1596 spin_lock_irqsave(&ioapic_lock, flags);
1597 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1598 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1599 spin_unlock_irqrestore(&ioapic_lock, flags);
1600 clear_IO_APIC_pin(apic, pin);
1601
1602 memset(&entry1, 0, sizeof(entry1));
1603
1604 entry1.dest_mode = 0; /* physical delivery */
1605 entry1.mask = 0; /* unmask IRQ now */
1606 entry1.dest = hard_smp_processor_id();
1607 entry1.delivery_mode = dest_ExtINT;
1608 entry1.polarity = entry0.polarity;
1609 entry1.trigger = 0;
1610 entry1.vector = 0;
1611
1612 spin_lock_irqsave(&ioapic_lock, flags);
1613 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1614 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1615 spin_unlock_irqrestore(&ioapic_lock, flags);
1616
1617 save_control = CMOS_READ(RTC_CONTROL);
1618 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1619 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1620 RTC_FREQ_SELECT);
1621 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1622
1623 i = 100;
1624 while (i-- > 0) {
1625 mdelay(10);
1626 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1627 i -= 10;
1628 }
1629
1630 CMOS_WRITE(save_control, RTC_CONTROL);
1631 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1632 clear_IO_APIC_pin(apic, pin);
1633
1634 spin_lock_irqsave(&ioapic_lock, flags);
1635 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1636 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1637 spin_unlock_irqrestore(&ioapic_lock, flags);
1638 }
1639
1640 /*
1641 * This code may look a bit paranoid, but it's supposed to cooperate with
1642 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1643 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1644 * fanatically on his truly buggy board.
1645 *
1646 * FIXME: really need to revamp this for modern platforms only.
1647 */
1648 static inline void check_timer(void)
1649 {
1650 struct irq_cfg *cfg = irq_cfg + 0;
1651 int apic1, pin1, apic2, pin2;
1652
1653 /*
1654 * get/set the timer IRQ vector:
1655 */
1656 disable_8259A_irq(0);
1657 assign_irq_vector(0, TARGET_CPUS);
1658
1659 /*
1660 * Subtle, code in do_timer_interrupt() expects an AEOI
1661 * mode for the 8259A whenever interrupts are routed
1662 * through I/O APICs. Also IRQ0 has to be enabled in
1663 * the 8259A which implies the virtual wire has to be
1664 * disabled in the local APIC.
1665 */
1666 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1667 init_8259A(1);
1668 if (timer_over_8254 > 0)
1669 enable_8259A_irq(0);
1670
1671 pin1 = find_isa_irq_pin(0, mp_INT);
1672 apic1 = find_isa_irq_apic(0, mp_INT);
1673 pin2 = ioapic_i8259.pin;
1674 apic2 = ioapic_i8259.apic;
1675
1676 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1677 cfg->vector, apic1, pin1, apic2, pin2);
1678
1679 if (pin1 != -1) {
1680 /*
1681 * Ok, does IRQ0 through the IOAPIC work?
1682 */
1683 unmask_IO_APIC_irq(0);
1684 if (!no_timer_check && timer_irq_works()) {
1685 nmi_watchdog_default();
1686 if (nmi_watchdog == NMI_IO_APIC) {
1687 disable_8259A_irq(0);
1688 setup_nmi();
1689 enable_8259A_irq(0);
1690 }
1691 if (disable_timer_pin_1 > 0)
1692 clear_IO_APIC_pin(0, pin1);
1693 return;
1694 }
1695 clear_IO_APIC_pin(apic1, pin1);
1696 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1697 "connected to IO-APIC\n");
1698 }
1699
1700 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1701 "through the 8259A ... ");
1702 if (pin2 != -1) {
1703 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1704 apic2, pin2);
1705 /*
1706 * legacy devices should be connected to IO APIC #0
1707 */
1708 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1709 if (timer_irq_works()) {
1710 apic_printk(APIC_VERBOSE," works.\n");
1711 nmi_watchdog_default();
1712 if (nmi_watchdog == NMI_IO_APIC) {
1713 setup_nmi();
1714 }
1715 return;
1716 }
1717 /*
1718 * Cleanup, just in case ...
1719 */
1720 clear_IO_APIC_pin(apic2, pin2);
1721 }
1722 apic_printk(APIC_VERBOSE," failed.\n");
1723
1724 if (nmi_watchdog == NMI_IO_APIC) {
1725 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1726 nmi_watchdog = 0;
1727 }
1728
1729 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1730
1731 disable_8259A_irq(0);
1732 irq_desc[0].chip = &lapic_irq_type;
1733 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1734 enable_8259A_irq(0);
1735
1736 if (timer_irq_works()) {
1737 apic_printk(APIC_VERBOSE," works.\n");
1738 return;
1739 }
1740 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1741 apic_printk(APIC_VERBOSE," failed.\n");
1742
1743 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1744
1745 init_8259A(0);
1746 make_8259A_irq(0);
1747 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1748
1749 unlock_ExtINT_logic();
1750
1751 if (timer_irq_works()) {
1752 apic_printk(APIC_VERBOSE," works.\n");
1753 return;
1754 }
1755 apic_printk(APIC_VERBOSE," failed :(.\n");
1756 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1757 }
1758
1759 static int __init notimercheck(char *s)
1760 {
1761 no_timer_check = 1;
1762 return 1;
1763 }
1764 __setup("no_timer_check", notimercheck);
1765
1766 /*
1767 *
1768 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1769 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1770 * Linux doesn't really care, as it's not actually used
1771 * for any interrupt handling anyway.
1772 */
1773 #define PIC_IRQS (1<<2)
1774
1775 void __init setup_IO_APIC(void)
1776 {
1777 enable_IO_APIC();
1778
1779 if (acpi_ioapic)
1780 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1781 else
1782 io_apic_irqs = ~PIC_IRQS;
1783
1784 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1785
1786 sync_Arb_IDs();
1787 setup_IO_APIC_irqs();
1788 init_IO_APIC_traps();
1789 check_timer();
1790 if (!acpi_ioapic)
1791 print_IO_APIC();
1792 }
1793
1794 struct sysfs_ioapic_data {
1795 struct sys_device dev;
1796 struct IO_APIC_route_entry entry[0];
1797 };
1798 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1799
1800 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1801 {
1802 struct IO_APIC_route_entry *entry;
1803 struct sysfs_ioapic_data *data;
1804 int i;
1805
1806 data = container_of(dev, struct sysfs_ioapic_data, dev);
1807 entry = data->entry;
1808 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1809 *entry = ioapic_read_entry(dev->id, i);
1810
1811 return 0;
1812 }
1813
1814 static int ioapic_resume(struct sys_device *dev)
1815 {
1816 struct IO_APIC_route_entry *entry;
1817 struct sysfs_ioapic_data *data;
1818 unsigned long flags;
1819 union IO_APIC_reg_00 reg_00;
1820 int i;
1821
1822 data = container_of(dev, struct sysfs_ioapic_data, dev);
1823 entry = data->entry;
1824
1825 spin_lock_irqsave(&ioapic_lock, flags);
1826 reg_00.raw = io_apic_read(dev->id, 0);
1827 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1828 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1829 io_apic_write(dev->id, 0, reg_00.raw);
1830 }
1831 spin_unlock_irqrestore(&ioapic_lock, flags);
1832 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1833 ioapic_write_entry(dev->id, i, entry[i]);
1834
1835 return 0;
1836 }
1837
1838 static struct sysdev_class ioapic_sysdev_class = {
1839 set_kset_name("ioapic"),
1840 .suspend = ioapic_suspend,
1841 .resume = ioapic_resume,
1842 };
1843
1844 static int __init ioapic_init_sysfs(void)
1845 {
1846 struct sys_device * dev;
1847 int i, size, error = 0;
1848
1849 error = sysdev_class_register(&ioapic_sysdev_class);
1850 if (error)
1851 return error;
1852
1853 for (i = 0; i < nr_ioapics; i++ ) {
1854 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1855 * sizeof(struct IO_APIC_route_entry);
1856 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1857 if (!mp_ioapic_data[i]) {
1858 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1859 continue;
1860 }
1861 memset(mp_ioapic_data[i], 0, size);
1862 dev = &mp_ioapic_data[i]->dev;
1863 dev->id = i;
1864 dev->cls = &ioapic_sysdev_class;
1865 error = sysdev_register(dev);
1866 if (error) {
1867 kfree(mp_ioapic_data[i]);
1868 mp_ioapic_data[i] = NULL;
1869 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1870 continue;
1871 }
1872 }
1873
1874 return 0;
1875 }
1876
1877 device_initcall(ioapic_init_sysfs);
1878
1879 /*
1880 * Dynamic irq allocate and deallocation
1881 */
1882 int create_irq(void)
1883 {
1884 /* Allocate an unused irq */
1885 int irq;
1886 int new;
1887 unsigned long flags;
1888
1889 irq = -ENOSPC;
1890 spin_lock_irqsave(&vector_lock, flags);
1891 for (new = (NR_IRQS - 1); new >= 0; new--) {
1892 if (platform_legacy_irq(new))
1893 continue;
1894 if (irq_cfg[new].vector != 0)
1895 continue;
1896 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1897 irq = new;
1898 break;
1899 }
1900 spin_unlock_irqrestore(&vector_lock, flags);
1901
1902 if (irq >= 0) {
1903 dynamic_irq_init(irq);
1904 }
1905 return irq;
1906 }
1907
1908 void destroy_irq(unsigned int irq)
1909 {
1910 unsigned long flags;
1911
1912 dynamic_irq_cleanup(irq);
1913
1914 spin_lock_irqsave(&vector_lock, flags);
1915 __clear_irq_vector(irq);
1916 spin_unlock_irqrestore(&vector_lock, flags);
1917 }
1918
1919 /*
1920 * MSI mesage composition
1921 */
1922 #ifdef CONFIG_PCI_MSI
1923 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1924 {
1925 struct irq_cfg *cfg = irq_cfg + irq;
1926 int err;
1927 unsigned dest;
1928 cpumask_t tmp;
1929
1930 tmp = TARGET_CPUS;
1931 err = assign_irq_vector(irq, tmp);
1932 if (!err) {
1933 cpus_and(tmp, cfg->domain, tmp);
1934 dest = cpu_mask_to_apicid(tmp);
1935
1936 msg->address_hi = MSI_ADDR_BASE_HI;
1937 msg->address_lo =
1938 MSI_ADDR_BASE_LO |
1939 ((INT_DEST_MODE == 0) ?
1940 MSI_ADDR_DEST_MODE_PHYSICAL:
1941 MSI_ADDR_DEST_MODE_LOGICAL) |
1942 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1943 MSI_ADDR_REDIRECTION_CPU:
1944 MSI_ADDR_REDIRECTION_LOWPRI) |
1945 MSI_ADDR_DEST_ID(dest);
1946
1947 msg->data =
1948 MSI_DATA_TRIGGER_EDGE |
1949 MSI_DATA_LEVEL_ASSERT |
1950 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1951 MSI_DATA_DELIVERY_FIXED:
1952 MSI_DATA_DELIVERY_LOWPRI) |
1953 MSI_DATA_VECTOR(cfg->vector);
1954 }
1955 return err;
1956 }
1957
1958 #ifdef CONFIG_SMP
1959 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1960 {
1961 struct irq_cfg *cfg = irq_cfg + irq;
1962 struct msi_msg msg;
1963 unsigned int dest;
1964 cpumask_t tmp;
1965
1966 cpus_and(tmp, mask, cpu_online_map);
1967 if (cpus_empty(tmp))
1968 return;
1969
1970 if (assign_irq_vector(irq, mask))
1971 return;
1972
1973 cpus_and(tmp, cfg->domain, mask);
1974 dest = cpu_mask_to_apicid(tmp);
1975
1976 read_msi_msg(irq, &msg);
1977
1978 msg.data &= ~MSI_DATA_VECTOR_MASK;
1979 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1980 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1981 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1982
1983 write_msi_msg(irq, &msg);
1984 irq_desc[irq].affinity = mask;
1985 }
1986 #endif /* CONFIG_SMP */
1987
1988 /*
1989 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1990 * which implement the MSI or MSI-X Capability Structure.
1991 */
1992 static struct irq_chip msi_chip = {
1993 .name = "PCI-MSI",
1994 .unmask = unmask_msi_irq,
1995 .mask = mask_msi_irq,
1996 .ack = ack_apic_edge,
1997 #ifdef CONFIG_SMP
1998 .set_affinity = set_msi_irq_affinity,
1999 #endif
2000 .retrigger = ioapic_retrigger_irq,
2001 };
2002
2003 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2004 {
2005 struct msi_msg msg;
2006 int irq, ret;
2007 irq = create_irq();
2008 if (irq < 0)
2009 return irq;
2010
2011 ret = msi_compose_msg(dev, irq, &msg);
2012 if (ret < 0) {
2013 destroy_irq(irq);
2014 return ret;
2015 }
2016
2017 set_irq_msi(irq, desc);
2018 write_msi_msg(irq, &msg);
2019
2020 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2021
2022 return 0;
2023 }
2024
2025 void arch_teardown_msi_irq(unsigned int irq)
2026 {
2027 destroy_irq(irq);
2028 }
2029
2030 #endif /* CONFIG_PCI_MSI */
2031
2032 /*
2033 * Hypertransport interrupt support
2034 */
2035 #ifdef CONFIG_HT_IRQ
2036
2037 #ifdef CONFIG_SMP
2038
2039 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2040 {
2041 struct ht_irq_msg msg;
2042 fetch_ht_irq_msg(irq, &msg);
2043
2044 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2045 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2046
2047 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2048 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2049
2050 write_ht_irq_msg(irq, &msg);
2051 }
2052
2053 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2054 {
2055 struct irq_cfg *cfg = irq_cfg + irq;
2056 unsigned int dest;
2057 cpumask_t tmp;
2058
2059 cpus_and(tmp, mask, cpu_online_map);
2060 if (cpus_empty(tmp))
2061 return;
2062
2063 if (assign_irq_vector(irq, mask))
2064 return;
2065
2066 cpus_and(tmp, cfg->domain, mask);
2067 dest = cpu_mask_to_apicid(tmp);
2068
2069 target_ht_irq(irq, dest, cfg->vector);
2070 irq_desc[irq].affinity = mask;
2071 }
2072 #endif
2073
2074 static struct irq_chip ht_irq_chip = {
2075 .name = "PCI-HT",
2076 .mask = mask_ht_irq,
2077 .unmask = unmask_ht_irq,
2078 .ack = ack_apic_edge,
2079 #ifdef CONFIG_SMP
2080 .set_affinity = set_ht_irq_affinity,
2081 #endif
2082 .retrigger = ioapic_retrigger_irq,
2083 };
2084
2085 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2086 {
2087 struct irq_cfg *cfg = irq_cfg + irq;
2088 int err;
2089 cpumask_t tmp;
2090
2091 tmp = TARGET_CPUS;
2092 err = assign_irq_vector(irq, tmp);
2093 if (!err) {
2094 struct ht_irq_msg msg;
2095 unsigned dest;
2096
2097 cpus_and(tmp, cfg->domain, tmp);
2098 dest = cpu_mask_to_apicid(tmp);
2099
2100 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2101
2102 msg.address_lo =
2103 HT_IRQ_LOW_BASE |
2104 HT_IRQ_LOW_DEST_ID(dest) |
2105 HT_IRQ_LOW_VECTOR(cfg->vector) |
2106 ((INT_DEST_MODE == 0) ?
2107 HT_IRQ_LOW_DM_PHYSICAL :
2108 HT_IRQ_LOW_DM_LOGICAL) |
2109 HT_IRQ_LOW_RQEOI_EDGE |
2110 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2111 HT_IRQ_LOW_MT_FIXED :
2112 HT_IRQ_LOW_MT_ARBITRATED) |
2113 HT_IRQ_LOW_IRQ_MASKED;
2114
2115 write_ht_irq_msg(irq, &msg);
2116
2117 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2118 handle_edge_irq, "edge");
2119 }
2120 return err;
2121 }
2122 #endif /* CONFIG_HT_IRQ */
2123
2124 /* --------------------------------------------------------------------------
2125 ACPI-based IOAPIC Configuration
2126 -------------------------------------------------------------------------- */
2127
2128 #ifdef CONFIG_ACPI
2129
2130 #define IO_APIC_MAX_ID 0xFE
2131
2132 int __init io_apic_get_redir_entries (int ioapic)
2133 {
2134 union IO_APIC_reg_01 reg_01;
2135 unsigned long flags;
2136
2137 spin_lock_irqsave(&ioapic_lock, flags);
2138 reg_01.raw = io_apic_read(ioapic, 1);
2139 spin_unlock_irqrestore(&ioapic_lock, flags);
2140
2141 return reg_01.bits.entries;
2142 }
2143
2144
2145 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2146 {
2147 if (!IO_APIC_IRQ(irq)) {
2148 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2149 ioapic);
2150 return -EINVAL;
2151 }
2152
2153 /*
2154 * IRQs < 16 are already in the irq_2_pin[] map
2155 */
2156 if (irq >= 16)
2157 add_pin_to_irq(irq, ioapic, pin);
2158
2159 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2160
2161 return 0;
2162 }
2163
2164 #endif /* CONFIG_ACPI */
2165
2166
2167 /*
2168 * This function currently is only a helper for the i386 smp boot process where
2169 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2170 * so mask in all cases should simply be TARGET_CPUS
2171 */
2172 #ifdef CONFIG_SMP
2173 void __init setup_ioapic_dest(void)
2174 {
2175 int pin, ioapic, irq, irq_entry;
2176
2177 if (skip_ioapic_setup == 1)
2178 return;
2179
2180 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2181 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2182 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2183 if (irq_entry == -1)
2184 continue;
2185 irq = pin_2_irq(irq_entry, ioapic, pin);
2186
2187 /* setup_IO_APIC_irqs could fail to get vector for some device
2188 * when you have too many devices, because at that time only boot
2189 * cpu is online.
2190 */
2191 if (!irq_cfg[irq].vector)
2192 setup_IO_APIC_irq(ioapic, pin, irq,
2193 irq_trigger(irq_entry),
2194 irq_polarity(irq_entry));
2195 else
2196 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2197 }
2198
2199 }
2200 }
2201 #endif
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