4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O
13 * APIC code. In particular, we now have separate
14 * handlers for edge and level triggered
16 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
17 * allocation PCI to vector mapping, shared PCI
19 * 00/10/27 D. Mosberger Document things a bit more to make them more
20 * understandable. Clean up much of the old
22 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts
23 * and fixes for ACPI S5(SoftOff) support.
24 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
25 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt
26 * vectors in iosapic_set_affinity(),
27 * initializations for /proc/irq/#/smp_affinity
28 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
29 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
30 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to
31 * IOSAPIC mapping error
32 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
33 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system
34 * interrupt, vector, etc.)
35 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's
37 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
38 * Remove iosapic_address & gsi_base from
39 * external interfaces. Rationalize
40 * __init/__devinit attributes.
41 * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
42 * Updated to work with irq migration necessary
46 * Here is what the interrupt logic between a PCI device and the kernel looks
49 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
50 * INTD). The device is uniquely identified by its bus-, and slot-number
51 * (the function number does not matter here because all functions share
52 * the same interrupt lines).
54 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
55 * controller. Multiple interrupt lines may have to share the same
56 * IOSAPIC pin (if they're level triggered and use the same polarity).
57 * Each interrupt line has a unique Global System Interrupt (GSI) number
58 * which can be calculated as the sum of the controller's base GSI number
59 * and the IOSAPIC pin number to which the line connects.
61 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
62 * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then
65 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is
66 * used as architecture-independent interrupt handling mechanism in Linux.
67 * As an IRQ is a number, we have to have
68 * IA-64 interrupt vector number <-> IRQ number mapping. On smaller
69 * systems, we use one-to-one mapping between IA-64 vector and IRQ. A
70 * platform can implement platform_irq_to_vector(irq) and
71 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
72 * Please see also include/asm-ia64/hw_irq.h for those APIs.
74 * To sum up, there are three levels of mappings involved:
76 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
78 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
79 * describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ
80 * (isa_irq) is the only exception in this source code.
83 #include <linux/acpi.h>
84 #include <linux/init.h>
85 #include <linux/irq.h>
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/pci.h>
89 #include <linux/smp.h>
90 #include <linux/string.h>
91 #include <linux/bootmem.h>
93 #include <asm/delay.h>
94 #include <asm/hw_irq.h>
96 #include <asm/iosapic.h>
97 #include <asm/machvec.h>
98 #include <asm/processor.h>
99 #include <asm/ptrace.h>
100 #include <asm/system.h>
102 #undef DEBUG_INTERRUPT_ROUTING
104 #ifdef DEBUG_INTERRUPT_ROUTING
105 #define DBG(fmt...) printk(fmt)
110 #define NR_PREALLOCATE_RTE_ENTRIES \
111 (PAGE_SIZE / sizeof(struct iosapic_rte_info))
112 #define RTE_PREALLOCATED (1)
114 static DEFINE_SPINLOCK(iosapic_lock
);
117 * These tables map IA-64 vectors to the IOSAPIC pin that generates this
123 static struct iosapic
{
124 char __iomem
*addr
; /* base address of IOSAPIC */
125 unsigned int gsi_base
; /* GSI base */
126 unsigned short num_rte
; /* # of RTEs on this IOSAPIC */
127 int rtes_inuse
; /* # of RTEs in use on this IOSAPIC */
129 unsigned short node
; /* numa node association via pxm */
131 spinlock_t lock
; /* lock for indirect reg access */
132 } iosapic_lists
[NR_IOSAPICS
];
134 struct iosapic_rte_info
{
135 struct list_head rte_list
; /* RTEs sharing the same vector */
136 char rte_index
; /* IOSAPIC RTE index */
137 int refcnt
; /* reference counter */
138 unsigned int flags
; /* flags */
139 struct iosapic
*iosapic
;
140 } ____cacheline_aligned
;
142 static struct iosapic_intr_info
{
143 struct list_head rtes
; /* RTEs using this vector (empty =>
144 * not an IOSAPIC interrupt) */
145 int count
; /* # of RTEs that shares this vector */
146 u32 low32
; /* current value of low word of
147 * Redirection table entry */
148 unsigned int dest
; /* destination CPU physical ID */
149 unsigned char dmode
: 3; /* delivery mode (see iosapic.h) */
150 unsigned char polarity
: 1; /* interrupt polarity
152 unsigned char trigger
: 1; /* trigger mode (see iosapic.h) */
153 } iosapic_intr_info
[NR_IRQS
];
155 static unsigned char pcat_compat __devinitdata
; /* 8259 compatibility flag */
157 static int iosapic_kmalloc_ok
;
158 static LIST_HEAD(free_rte_list
);
161 iosapic_write(struct iosapic
*iosapic
, unsigned int reg
, u32 val
)
165 spin_lock_irqsave(&iosapic
->lock
, flags
);
166 __iosapic_write(iosapic
->addr
, reg
, val
);
167 spin_unlock_irqrestore(&iosapic
->lock
, flags
);
171 * Find an IOSAPIC associated with a GSI
174 find_iosapic (unsigned int gsi
)
178 for (i
= 0; i
< NR_IOSAPICS
; i
++) {
179 if ((unsigned) (gsi
- iosapic_lists
[i
].gsi_base
) <
180 iosapic_lists
[i
].num_rte
)
187 static inline int __gsi_to_irq(unsigned int gsi
)
190 struct iosapic_intr_info
*info
;
191 struct iosapic_rte_info
*rte
;
193 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
194 info
= &iosapic_intr_info
[irq
];
195 list_for_each_entry(rte
, &info
->rtes
, rte_list
)
196 if (rte
->iosapic
->gsi_base
+ rte
->rte_index
== gsi
)
203 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
204 * entry exists, return -1.
207 gsi_to_vector (unsigned int gsi
)
209 int irq
= __gsi_to_irq(gsi
);
210 if (check_irq_used(irq
) < 0)
212 return irq_to_vector(irq
);
216 gsi_to_irq (unsigned int gsi
)
221 spin_lock_irqsave(&iosapic_lock
, flags
);
222 irq
= __gsi_to_irq(gsi
);
223 spin_unlock_irqrestore(&iosapic_lock
, flags
);
227 static struct iosapic_rte_info
*find_rte(unsigned int irq
, unsigned int gsi
)
229 struct iosapic_rte_info
*rte
;
231 list_for_each_entry(rte
, &iosapic_intr_info
[irq
].rtes
, rte_list
)
232 if (rte
->iosapic
->gsi_base
+ rte
->rte_index
== gsi
)
238 set_rte (unsigned int gsi
, unsigned int irq
, unsigned int dest
, int mask
)
240 unsigned long pol
, trigger
, dmode
;
244 struct iosapic_rte_info
*rte
;
245 ia64_vector vector
= irq_to_vector(irq
);
247 DBG(KERN_DEBUG
"IOSAPIC: routing vector %d to 0x%x\n", vector
, dest
);
249 rte
= find_rte(irq
, gsi
);
251 return; /* not an IOSAPIC interrupt */
253 rte_index
= rte
->rte_index
;
254 pol
= iosapic_intr_info
[irq
].polarity
;
255 trigger
= iosapic_intr_info
[irq
].trigger
;
256 dmode
= iosapic_intr_info
[irq
].dmode
;
258 redir
= (dmode
== IOSAPIC_LOWEST_PRIORITY
) ? 1 : 0;
261 set_irq_affinity_info(irq
, (int)(dest
& 0xffff), redir
);
264 low32
= ((pol
<< IOSAPIC_POLARITY_SHIFT
) |
265 (trigger
<< IOSAPIC_TRIGGER_SHIFT
) |
266 (dmode
<< IOSAPIC_DELIVERY_SHIFT
) |
267 ((mask
? 1 : 0) << IOSAPIC_MASK_SHIFT
) |
270 /* dest contains both id and eid */
271 high32
= (dest
<< IOSAPIC_DEST_SHIFT
);
273 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_HIGH(rte_index
), high32
);
274 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
275 iosapic_intr_info
[irq
].low32
= low32
;
276 iosapic_intr_info
[irq
].dest
= dest
;
280 nop (unsigned int irq
)
288 kexec_disable_iosapic(void)
290 struct iosapic_intr_info
*info
;
291 struct iosapic_rte_info
*rte
;
295 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
296 info
= &iosapic_intr_info
[irq
];
297 vec
= irq_to_vector(irq
);
298 list_for_each_entry(rte
, &info
->rtes
,
300 iosapic_write(rte
->iosapic
,
301 IOSAPIC_RTE_LOW(rte
->rte_index
),
303 iosapic_eoi(rte
->iosapic
->addr
, vec
);
310 mask_irq (unsigned int irq
)
314 struct iosapic_rte_info
*rte
;
316 if (list_empty(&iosapic_intr_info
[irq
].rtes
))
317 return; /* not an IOSAPIC interrupt! */
319 /* set only the mask bit */
320 low32
= iosapic_intr_info
[irq
].low32
|= IOSAPIC_MASK
;
321 list_for_each_entry(rte
, &iosapic_intr_info
[irq
].rtes
, rte_list
) {
322 rte_index
= rte
->rte_index
;
323 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
328 unmask_irq (unsigned int irq
)
332 struct iosapic_rte_info
*rte
;
334 if (list_empty(&iosapic_intr_info
[irq
].rtes
))
335 return; /* not an IOSAPIC interrupt! */
337 low32
= iosapic_intr_info
[irq
].low32
&= ~IOSAPIC_MASK
;
338 list_for_each_entry(rte
, &iosapic_intr_info
[irq
].rtes
, rte_list
) {
339 rte_index
= rte
->rte_index
;
340 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
346 iosapic_set_affinity (unsigned int irq
, cpumask_t mask
)
351 int redir
= (irq
& IA64_IRQ_REDIRECTED
) ? 1 : 0;
352 struct iosapic_rte_info
*rte
;
353 struct iosapic
*iosapic
;
355 irq
&= (~IA64_IRQ_REDIRECTED
);
357 if (cpus_empty(mask
))
360 dest
= cpu_physical_id(first_cpu(mask
));
362 if (list_empty(&iosapic_intr_info
[irq
].rtes
))
363 return; /* not an IOSAPIC interrupt */
365 set_irq_affinity_info(irq
, dest
, redir
);
367 /* dest contains both id and eid */
368 high32
= dest
<< IOSAPIC_DEST_SHIFT
;
370 low32
= iosapic_intr_info
[irq
].low32
& ~(7 << IOSAPIC_DELIVERY_SHIFT
);
372 /* change delivery mode to lowest priority */
373 low32
|= (IOSAPIC_LOWEST_PRIORITY
<< IOSAPIC_DELIVERY_SHIFT
);
375 /* change delivery mode to fixed */
376 low32
|= (IOSAPIC_FIXED
<< IOSAPIC_DELIVERY_SHIFT
);
378 iosapic_intr_info
[irq
].low32
= low32
;
379 iosapic_intr_info
[irq
].dest
= dest
;
380 list_for_each_entry(rte
, &iosapic_intr_info
[irq
].rtes
, rte_list
) {
381 iosapic
= rte
->iosapic
;
382 rte_index
= rte
->rte_index
;
383 iosapic_write(iosapic
, IOSAPIC_RTE_HIGH(rte_index
), high32
);
384 iosapic_write(iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
390 * Handlers for level-triggered interrupts.
394 iosapic_startup_level_irq (unsigned int irq
)
401 iosapic_end_level_irq (unsigned int irq
)
403 ia64_vector vec
= irq_to_vector(irq
);
404 struct iosapic_rte_info
*rte
;
406 move_native_irq(irq
);
407 list_for_each_entry(rte
, &iosapic_intr_info
[irq
].rtes
, rte_list
)
408 iosapic_eoi(rte
->iosapic
->addr
, vec
);
411 #define iosapic_shutdown_level_irq mask_irq
412 #define iosapic_enable_level_irq unmask_irq
413 #define iosapic_disable_level_irq mask_irq
414 #define iosapic_ack_level_irq nop
416 struct irq_chip irq_type_iosapic_level
= {
417 .name
= "IO-SAPIC-level",
418 .startup
= iosapic_startup_level_irq
,
419 .shutdown
= iosapic_shutdown_level_irq
,
420 .enable
= iosapic_enable_level_irq
,
421 .disable
= iosapic_disable_level_irq
,
422 .ack
= iosapic_ack_level_irq
,
423 .end
= iosapic_end_level_irq
,
425 .unmask
= unmask_irq
,
426 .set_affinity
= iosapic_set_affinity
430 * Handlers for edge-triggered interrupts.
434 iosapic_startup_edge_irq (unsigned int irq
)
438 * IOSAPIC simply drops interrupts pended while the
439 * corresponding pin was masked, so we can't know if an
440 * interrupt is pending already. Let's hope not...
446 iosapic_ack_edge_irq (unsigned int irq
)
448 irq_desc_t
*idesc
= irq_desc
+ irq
;
450 move_native_irq(irq
);
452 * Once we have recorded IRQ_PENDING already, we can mask the
453 * interrupt for real. This prevents IRQ storms from unhandled
456 if ((idesc
->status
& (IRQ_PENDING
|IRQ_DISABLED
)) ==
457 (IRQ_PENDING
|IRQ_DISABLED
))
461 #define iosapic_enable_edge_irq unmask_irq
462 #define iosapic_disable_edge_irq nop
463 #define iosapic_end_edge_irq nop
465 struct irq_chip irq_type_iosapic_edge
= {
466 .name
= "IO-SAPIC-edge",
467 .startup
= iosapic_startup_edge_irq
,
468 .shutdown
= iosapic_disable_edge_irq
,
469 .enable
= iosapic_enable_edge_irq
,
470 .disable
= iosapic_disable_edge_irq
,
471 .ack
= iosapic_ack_edge_irq
,
472 .end
= iosapic_end_edge_irq
,
474 .unmask
= unmask_irq
,
475 .set_affinity
= iosapic_set_affinity
479 iosapic_version (char __iomem
*addr
)
482 * IOSAPIC Version Register return 32 bit structure like:
484 * unsigned int version : 8;
485 * unsigned int reserved1 : 8;
486 * unsigned int max_redir : 8;
487 * unsigned int reserved2 : 8;
490 return __iosapic_read(addr
, IOSAPIC_VERSION
);
493 static int iosapic_find_sharable_irq(unsigned long trigger
, unsigned long pol
)
495 int i
, irq
= -ENOSPC
, min_count
= -1;
496 struct iosapic_intr_info
*info
;
499 * shared vectors for edge-triggered interrupts are not
502 if (trigger
== IOSAPIC_EDGE
)
505 for (i
= 0; i
<= NR_IRQS
; i
++) {
506 info
= &iosapic_intr_info
[i
];
507 if (info
->trigger
== trigger
&& info
->polarity
== pol
&&
508 (info
->dmode
== IOSAPIC_FIXED
||
509 info
->dmode
== IOSAPIC_LOWEST_PRIORITY
) &&
510 can_request_irq(i
, IRQF_SHARED
)) {
511 if (min_count
== -1 || info
->count
< min_count
) {
513 min_count
= info
->count
;
521 * if the given vector is already owned by other,
522 * assign a new vector for the other and make the vector available
525 iosapic_reassign_vector (int irq
)
529 if (!list_empty(&iosapic_intr_info
[irq
].rtes
)) {
530 new_irq
= create_irq();
532 panic("%s: out of interrupt vectors!\n", __FUNCTION__
);
533 printk(KERN_INFO
"Reassigning vector %d to %d\n",
534 irq_to_vector(irq
), irq_to_vector(new_irq
));
535 memcpy(&iosapic_intr_info
[new_irq
], &iosapic_intr_info
[irq
],
536 sizeof(struct iosapic_intr_info
));
537 INIT_LIST_HEAD(&iosapic_intr_info
[new_irq
].rtes
);
538 list_move(iosapic_intr_info
[irq
].rtes
.next
,
539 &iosapic_intr_info
[new_irq
].rtes
);
540 memset(&iosapic_intr_info
[irq
], 0,
541 sizeof(struct iosapic_intr_info
));
542 iosapic_intr_info
[irq
].low32
= IOSAPIC_MASK
;
543 INIT_LIST_HEAD(&iosapic_intr_info
[irq
].rtes
);
547 static struct iosapic_rte_info
*iosapic_alloc_rte (void)
550 struct iosapic_rte_info
*rte
;
551 int preallocated
= 0;
553 if (!iosapic_kmalloc_ok
&& list_empty(&free_rte_list
)) {
554 rte
= alloc_bootmem(sizeof(struct iosapic_rte_info
) *
555 NR_PREALLOCATE_RTE_ENTRIES
);
558 for (i
= 0; i
< NR_PREALLOCATE_RTE_ENTRIES
; i
++, rte
++)
559 list_add(&rte
->rte_list
, &free_rte_list
);
562 if (!list_empty(&free_rte_list
)) {
563 rte
= list_entry(free_rte_list
.next
, struct iosapic_rte_info
,
565 list_del(&rte
->rte_list
);
568 rte
= kmalloc(sizeof(struct iosapic_rte_info
), GFP_ATOMIC
);
573 memset(rte
, 0, sizeof(struct iosapic_rte_info
));
575 rte
->flags
|= RTE_PREALLOCATED
;
580 static void iosapic_free_rte (struct iosapic_rte_info
*rte
)
582 if (rte
->flags
& RTE_PREALLOCATED
)
583 list_add_tail(&rte
->rte_list
, &free_rte_list
);
588 static inline int irq_is_shared (int irq
)
590 return (iosapic_intr_info
[irq
].count
> 1);
594 register_intr (unsigned int gsi
, int irq
, unsigned char delivery
,
595 unsigned long polarity
, unsigned long trigger
)
598 struct hw_interrupt_type
*irq_type
;
600 struct iosapic_rte_info
*rte
;
602 index
= find_iosapic(gsi
);
604 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n",
609 rte
= find_rte(irq
, gsi
);
611 rte
= iosapic_alloc_rte();
613 printk(KERN_WARNING
"%s: cannot allocate memory\n",
618 rte
->iosapic
= &iosapic_lists
[index
];
619 rte
->rte_index
= gsi
- rte
->iosapic
->gsi_base
;
621 list_add_tail(&rte
->rte_list
, &iosapic_intr_info
[irq
].rtes
);
622 iosapic_intr_info
[irq
].count
++;
623 iosapic_lists
[index
].rtes_inuse
++;
625 else if (rte
->refcnt
== NO_REF_RTE
) {
626 struct iosapic_intr_info
*info
= &iosapic_intr_info
[irq
];
627 if (info
->count
> 0 &&
628 (info
->trigger
!= trigger
|| info
->polarity
!= polarity
)){
630 "%s: cannot override the interrupt\n",
635 iosapic_intr_info
[irq
].count
++;
636 iosapic_lists
[index
].rtes_inuse
++;
639 iosapic_intr_info
[irq
].polarity
= polarity
;
640 iosapic_intr_info
[irq
].dmode
= delivery
;
641 iosapic_intr_info
[irq
].trigger
= trigger
;
643 if (trigger
== IOSAPIC_EDGE
)
644 irq_type
= &irq_type_iosapic_edge
;
646 irq_type
= &irq_type_iosapic_level
;
648 idesc
= irq_desc
+ irq
;
649 if (idesc
->chip
!= irq_type
) {
650 if (idesc
->chip
!= &no_irq_type
)
652 "%s: changing vector %d from %s to %s\n",
653 __FUNCTION__
, irq_to_vector(irq
),
654 idesc
->chip
->name
, irq_type
->name
);
655 idesc
->chip
= irq_type
;
661 get_target_cpu (unsigned int gsi
, int irq
)
665 extern int cpe_vector
;
668 * In case of vector shared by multiple RTEs, all RTEs that
669 * share the vector need to use the same destination CPU.
671 if (!list_empty(&iosapic_intr_info
[irq
].rtes
))
672 return iosapic_intr_info
[irq
].dest
;
675 * If the platform supports redirection via XTP, let it
676 * distribute interrupts.
678 if (smp_int_redirect
& SMP_IRQ_REDIRECTION
)
679 return cpu_physical_id(smp_processor_id());
682 * Some interrupts (ACPI SCI, for instance) are registered
683 * before the BSP is marked as online.
685 if (!cpu_online(smp_processor_id()))
686 return cpu_physical_id(smp_processor_id());
689 if (cpe_vector
> 0 && irq_to_vector(irq
) == IA64_CPEP_VECTOR
)
690 return get_cpei_target_cpu();
695 int num_cpus
, cpu_index
, iosapic_index
, numa_cpu
, i
= 0;
698 iosapic_index
= find_iosapic(gsi
);
699 if (iosapic_index
< 0 ||
700 iosapic_lists
[iosapic_index
].node
== MAX_NUMNODES
)
701 goto skip_numa_setup
;
703 cpu_mask
= node_to_cpumask(iosapic_lists
[iosapic_index
].node
);
705 for_each_cpu_mask(numa_cpu
, cpu_mask
) {
706 if (!cpu_online(numa_cpu
))
707 cpu_clear(numa_cpu
, cpu_mask
);
710 num_cpus
= cpus_weight(cpu_mask
);
713 goto skip_numa_setup
;
715 /* Use irq assignment to distribute across cpus in node */
716 cpu_index
= irq
% num_cpus
;
718 for (numa_cpu
= first_cpu(cpu_mask
) ; i
< cpu_index
; i
++)
719 numa_cpu
= next_cpu(numa_cpu
, cpu_mask
);
721 if (numa_cpu
!= NR_CPUS
)
722 return cpu_physical_id(numa_cpu
);
727 * Otherwise, round-robin interrupt vectors across all the
728 * processors. (It'd be nice if we could be smarter in the
732 if (++cpu
>= NR_CPUS
)
734 } while (!cpu_online(cpu
));
736 return cpu_physical_id(cpu
);
737 #else /* CONFIG_SMP */
738 return cpu_physical_id(smp_processor_id());
743 * ACPI can describe IOSAPIC interrupts via static tables and namespace
744 * methods. This provides an interface to register those interrupts and
745 * program the IOSAPIC RTE.
748 iosapic_register_intr (unsigned int gsi
,
749 unsigned long polarity
, unsigned long trigger
)
751 int irq
, mask
= 1, err
;
754 struct iosapic_rte_info
*rte
;
758 * If this GSI has already been registered (i.e., it's a
759 * shared interrupt, or we lost a race to register it),
760 * don't touch the RTE.
762 spin_lock_irqsave(&iosapic_lock
, flags
);
763 irq
= __gsi_to_irq(gsi
);
765 rte
= find_rte(irq
, gsi
);
766 if(iosapic_intr_info
[irq
].count
== 0) {
767 assign_irq_vector(irq
);
768 dynamic_irq_init(irq
);
769 } else if (rte
->refcnt
!= NO_REF_RTE
) {
771 goto unlock_iosapic_lock
;
776 /* If vector is running out, we try to find a sharable vector */
778 irq
= iosapic_find_sharable_irq(trigger
, polarity
);
780 goto unlock_iosapic_lock
;
783 spin_lock(&irq_desc
[irq
].lock
);
784 dest
= get_target_cpu(gsi
, irq
);
785 err
= register_intr(gsi
, irq
, IOSAPIC_LOWEST_PRIORITY
,
793 * If the vector is shared and already unmasked for other
794 * interrupt sources, don't mask it.
796 low32
= iosapic_intr_info
[irq
].low32
;
797 if (irq_is_shared(irq
) && !(low32
& IOSAPIC_MASK
))
799 set_rte(gsi
, irq
, dest
, mask
);
801 printk(KERN_INFO
"GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
802 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
803 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
804 cpu_logical_id(dest
), dest
, irq_to_vector(irq
));
806 spin_unlock(&irq_desc
[irq
].lock
);
808 spin_unlock_irqrestore(&iosapic_lock
, flags
);
813 iosapic_unregister_intr (unsigned int gsi
)
819 unsigned long trigger
, polarity
;
821 struct iosapic_rte_info
*rte
;
824 * If the irq associated with the gsi is not found,
825 * iosapic_unregister_intr() is unbalanced. We need to check
826 * this again after getting locks.
828 irq
= gsi_to_irq(gsi
);
830 printk(KERN_ERR
"iosapic_unregister_intr(%u) unbalanced\n",
836 spin_lock_irqsave(&iosapic_lock
, flags
);
837 if ((rte
= find_rte(irq
, gsi
)) == NULL
) {
838 printk(KERN_ERR
"iosapic_unregister_intr(%u) unbalanced\n",
844 if (--rte
->refcnt
> 0)
847 idesc
= irq_desc
+ irq
;
848 rte
->refcnt
= NO_REF_RTE
;
850 /* Mask the interrupt */
851 low32
= iosapic_intr_info
[irq
].low32
| IOSAPIC_MASK
;
852 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte
->rte_index
), low32
);
854 iosapic_intr_info
[irq
].count
--;
855 index
= find_iosapic(gsi
);
856 iosapic_lists
[index
].rtes_inuse
--;
857 WARN_ON(iosapic_lists
[index
].rtes_inuse
< 0);
859 trigger
= iosapic_intr_info
[irq
].trigger
;
860 polarity
= iosapic_intr_info
[irq
].polarity
;
861 dest
= iosapic_intr_info
[irq
].dest
;
863 "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
864 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
865 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
866 cpu_logical_id(dest
), dest
, irq_to_vector(irq
));
868 if (iosapic_intr_info
[irq
].count
== 0) {
871 cpus_setall(idesc
->affinity
);
873 /* Clear the interrupt information */
874 iosapic_intr_info
[irq
].dest
= 0;
875 iosapic_intr_info
[irq
].dmode
= 0;
876 iosapic_intr_info
[irq
].polarity
= 0;
877 iosapic_intr_info
[irq
].trigger
= 0;
878 iosapic_intr_info
[irq
].low32
|= IOSAPIC_MASK
;
880 /* Destroy and reserve IRQ */
881 destroy_and_reserve_irq(irq
);
884 spin_unlock_irqrestore(&iosapic_lock
, flags
);
888 * ACPI calls this when it finds an entry for a platform interrupt.
891 iosapic_register_platform_intr (u32 int_type
, unsigned int gsi
,
892 int iosapic_vector
, u16 eid
, u16 id
,
893 unsigned long polarity
, unsigned long trigger
)
895 static const char * const name
[] = {"unknown", "PMI", "INIT", "CPEI"};
896 unsigned char delivery
;
897 int irq
, vector
, mask
= 0;
898 unsigned int dest
= ((id
<< 8) | eid
) & 0xffff;
901 case ACPI_INTERRUPT_PMI
:
902 irq
= vector
= iosapic_vector
;
903 bind_irq_vector(irq
, vector
);
905 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
906 * we need to make sure the vector is available
908 iosapic_reassign_vector(irq
);
909 delivery
= IOSAPIC_PMI
;
911 case ACPI_INTERRUPT_INIT
:
914 panic("%s: out of interrupt vectors!\n", __FUNCTION__
);
915 vector
= irq_to_vector(irq
);
916 delivery
= IOSAPIC_INIT
;
918 case ACPI_INTERRUPT_CPEI
:
919 irq
= vector
= IA64_CPE_VECTOR
;
920 BUG_ON(bind_irq_vector(irq
, vector
));
921 delivery
= IOSAPIC_LOWEST_PRIORITY
;
925 printk(KERN_ERR
"%s: invalid int type 0x%x\n", __FUNCTION__
,
930 register_intr(gsi
, irq
, delivery
, polarity
, trigger
);
933 "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
935 int_type
< ARRAY_SIZE(name
) ? name
[int_type
] : "unknown",
936 int_type
, gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
937 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
938 cpu_logical_id(dest
), dest
, vector
);
940 set_rte(gsi
, irq
, dest
, mask
);
945 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
948 iosapic_override_isa_irq (unsigned int isa_irq
, unsigned int gsi
,
949 unsigned long polarity
,
950 unsigned long trigger
)
953 unsigned int dest
= cpu_physical_id(smp_processor_id());
955 irq
= vector
= isa_irq_to_vector(isa_irq
);
956 BUG_ON(bind_irq_vector(irq
, vector
));
957 register_intr(gsi
, irq
, IOSAPIC_LOWEST_PRIORITY
, polarity
, trigger
);
959 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
960 isa_irq
, gsi
, trigger
== IOSAPIC_EDGE
? "edge" : "level",
961 polarity
== IOSAPIC_POL_HIGH
? "high" : "low",
962 cpu_logical_id(dest
), dest
, vector
);
964 set_rte(gsi
, irq
, dest
, 1);
968 iosapic_system_init (int system_pcat_compat
)
972 for (irq
= 0; irq
< NR_IRQS
; ++irq
) {
973 iosapic_intr_info
[irq
].low32
= IOSAPIC_MASK
;
975 INIT_LIST_HEAD(&iosapic_intr_info
[irq
].rtes
);
977 iosapic_intr_info
[irq
].count
= 0;
980 pcat_compat
= system_pcat_compat
;
983 * Disable the compatibility mode interrupts (8259 style),
984 * needs IN/OUT support enabled.
987 "%s: Disabling PC-AT compatible 8259 interrupts\n",
999 for (index
= 0; index
< NR_IOSAPICS
; index
++)
1000 if (!iosapic_lists
[index
].addr
)
1003 printk(KERN_WARNING
"%s: failed to allocate iosapic\n", __FUNCTION__
);
1008 iosapic_free (int index
)
1010 memset(&iosapic_lists
[index
], 0, sizeof(iosapic_lists
[0]));
1014 iosapic_check_gsi_range (unsigned int gsi_base
, unsigned int ver
)
1017 unsigned int gsi_end
, base
, end
;
1019 /* check gsi range */
1020 gsi_end
= gsi_base
+ ((ver
>> 16) & 0xff);
1021 for (index
= 0; index
< NR_IOSAPICS
; index
++) {
1022 if (!iosapic_lists
[index
].addr
)
1025 base
= iosapic_lists
[index
].gsi_base
;
1026 end
= base
+ iosapic_lists
[index
].num_rte
- 1;
1028 if (gsi_end
< base
|| end
< gsi_base
)
1037 iosapic_init (unsigned long phys_addr
, unsigned int gsi_base
)
1039 int num_rte
, err
, index
;
1040 unsigned int isa_irq
, ver
;
1042 unsigned long flags
;
1044 spin_lock_irqsave(&iosapic_lock
, flags
);
1045 index
= find_iosapic(gsi_base
);
1047 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1051 addr
= ioremap(phys_addr
, 0);
1052 ver
= iosapic_version(addr
);
1053 if ((err
= iosapic_check_gsi_range(gsi_base
, ver
))) {
1055 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1060 * The MAX_REDIR register holds the highest input pin number
1061 * (starting from 0). We add 1 so that we can use it for
1062 * number of pins (= RTEs)
1064 num_rte
= ((ver
>> 16) & 0xff) + 1;
1066 index
= iosapic_alloc();
1067 iosapic_lists
[index
].addr
= addr
;
1068 iosapic_lists
[index
].gsi_base
= gsi_base
;
1069 iosapic_lists
[index
].num_rte
= num_rte
;
1071 iosapic_lists
[index
].node
= MAX_NUMNODES
;
1073 spin_lock_init(&iosapic_lists
[index
].lock
);
1074 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1076 if ((gsi_base
== 0) && pcat_compat
) {
1078 * Map the legacy ISA devices into the IOSAPIC data. Some of
1079 * these may get reprogrammed later on with data from the ACPI
1080 * Interrupt Source Override table.
1082 for (isa_irq
= 0; isa_irq
< 16; ++isa_irq
)
1083 iosapic_override_isa_irq(isa_irq
, isa_irq
,
1090 #ifdef CONFIG_HOTPLUG
1092 iosapic_remove (unsigned int gsi_base
)
1095 unsigned long flags
;
1097 spin_lock_irqsave(&iosapic_lock
, flags
);
1098 index
= find_iosapic(gsi_base
);
1100 printk(KERN_WARNING
"%s: No IOSAPIC for GSI base %u\n",
1101 __FUNCTION__
, gsi_base
);
1105 if (iosapic_lists
[index
].rtes_inuse
) {
1107 printk(KERN_WARNING
"%s: IOSAPIC for GSI base %u is busy\n",
1108 __FUNCTION__
, gsi_base
);
1112 iounmap(iosapic_lists
[index
].addr
);
1113 iosapic_free(index
);
1115 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1118 #endif /* CONFIG_HOTPLUG */
1122 map_iosapic_to_node(unsigned int gsi_base
, int node
)
1126 index
= find_iosapic(gsi_base
);
1128 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n",
1129 __FUNCTION__
, gsi_base
);
1132 iosapic_lists
[index
].node
= node
;
1137 static int __init
iosapic_enable_kmalloc (void)
1139 iosapic_kmalloc_ok
= 1;
1142 core_initcall (iosapic_enable_kmalloc
);