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Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/perex/alsa
[linux-2.6/kmemtrace.git] / drivers / ata / ahci.c
blob6f089b899a1a7e9587bbba731f9b9047e7c15eae
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_enable_alpm(struct ata_port *ap,
53 enum link_pm policy);
54 static void ahci_disable_alpm(struct ata_port *ap);
55
56 enum {
57 AHCI_PCI_BAR = 5,
58 AHCI_MAX_PORTS = 32,
59 AHCI_MAX_SG = 168, /* hardware max is 64K */
60 AHCI_DMA_BOUNDARY = 0xffffffff,
61 AHCI_USE_CLUSTERING = 1,
62 AHCI_MAX_CMDS = 32,
63 AHCI_CMD_SZ = 32,
64 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
65 AHCI_RX_FIS_SZ = 256,
66 AHCI_CMD_TBL_CDB = 0x40,
67 AHCI_CMD_TBL_HDR_SZ = 0x80,
68 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
69 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
70 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
71 AHCI_RX_FIS_SZ,
72 AHCI_IRQ_ON_SG = (1 << 31),
73 AHCI_CMD_ATAPI = (1 << 5),
74 AHCI_CMD_WRITE = (1 << 6),
75 AHCI_CMD_PREFETCH = (1 << 7),
76 AHCI_CMD_RESET = (1 << 8),
77 AHCI_CMD_CLR_BUSY = (1 << 10),
78
79 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
80 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
81 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
82
83 board_ahci = 0,
84 board_ahci_vt8251 = 1,
85 board_ahci_ign_iferr = 2,
86 board_ahci_sb600 = 3,
87 board_ahci_mv = 4,
88
89 /* global controller registers */
90 HOST_CAP = 0x00, /* host capabilities */
91 HOST_CTL = 0x04, /* global host control */
92 HOST_IRQ_STAT = 0x08, /* interrupt status */
93 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
94 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
95
96 /* HOST_CTL bits */
97 HOST_RESET = (1 << 0), /* reset controller; self-clear */
98 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
99 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
100
101 /* HOST_CAP bits */
102 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
103 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
104 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
105 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
106 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
107 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
108 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
109 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
110
111 /* registers for each SATA port */
112 PORT_LST_ADDR = 0x00, /* command list DMA addr */
113 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
114 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
115 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
116 PORT_IRQ_STAT = 0x10, /* interrupt status */
117 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
118 PORT_CMD = 0x18, /* port command */
119 PORT_TFDATA = 0x20, /* taskfile data */
120 PORT_SIG = 0x24, /* device TF signature */
121 PORT_CMD_ISSUE = 0x38, /* command issue */
122 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
123 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
124 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
125 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
126 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
127
128 /* PORT_IRQ_{STAT,MASK} bits */
129 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
130 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
131 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
132 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
133 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
134 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
135 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
136 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
137
138 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
139 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
140 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
141 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
142 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
143 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
144 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
145 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
146 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
147
148 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
149 PORT_IRQ_IF_ERR |
150 PORT_IRQ_CONNECT |
151 PORT_IRQ_PHYRDY |
152 PORT_IRQ_UNK_FIS |
153 PORT_IRQ_BAD_PMP,
154 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
155 PORT_IRQ_TF_ERR |
156 PORT_IRQ_HBUS_DATA_ERR,
157 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
158 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
159 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
160
161 /* PORT_CMD bits */
162 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
163 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
164 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
165 PORT_CMD_PMP = (1 << 17), /* PMP attached */
166 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
167 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
168 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
169 PORT_CMD_CLO = (1 << 3), /* Command list override */
170 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
171 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
172 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
173
174 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
175 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
176 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
177 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
178
179 /* hpriv->flags bits */
180 AHCI_HFLAG_NO_NCQ = (1 << 0),
181 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
182 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
183 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
184 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
185 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
186 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
187 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
188
189 /* ap->flags bits */
190
191 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
192 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
193 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
194 ATA_FLAG_IPM,
195 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
196
197 ICH_MAP = 0x90, /* ICH MAP register */
198 };
199
200 struct ahci_cmd_hdr {
201 __le32 opts;
202 __le32 status;
203 __le32 tbl_addr;
204 __le32 tbl_addr_hi;
205 __le32 reserved[4];
206 };
207
208 struct ahci_sg {
209 __le32 addr;
210 __le32 addr_hi;
211 __le32 reserved;
212 __le32 flags_size;
213 };
214
215 struct ahci_host_priv {
216 unsigned int flags; /* AHCI_HFLAG_* */
217 u32 cap; /* cap to use */
218 u32 port_map; /* port map to use */
219 u32 saved_cap; /* saved initial cap */
220 u32 saved_port_map; /* saved initial port_map */
221 };
222
223 struct ahci_port_priv {
224 struct ata_link *active_link;
225 struct ahci_cmd_hdr *cmd_slot;
226 dma_addr_t cmd_slot_dma;
227 void *cmd_tbl;
228 dma_addr_t cmd_tbl_dma;
229 void *rx_fis;
230 dma_addr_t rx_fis_dma;
231 /* for NCQ spurious interrupt analysis */
232 unsigned int ncq_saw_d2h:1;
233 unsigned int ncq_saw_dmas:1;
234 unsigned int ncq_saw_sdb:1;
235 u32 intr_mask; /* interrupts to enable */
236 };
237
238 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
239 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
240 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
241 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
242 static void ahci_irq_clear(struct ata_port *ap);
243 static int ahci_port_start(struct ata_port *ap);
244 static void ahci_port_stop(struct ata_port *ap);
245 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
246 static void ahci_qc_prep(struct ata_queued_cmd *qc);
247 static u8 ahci_check_status(struct ata_port *ap);
248 static void ahci_freeze(struct ata_port *ap);
249 static void ahci_thaw(struct ata_port *ap);
250 static void ahci_pmp_attach(struct ata_port *ap);
251 static void ahci_pmp_detach(struct ata_port *ap);
252 static void ahci_error_handler(struct ata_port *ap);
253 static void ahci_vt8251_error_handler(struct ata_port *ap);
254 static void ahci_p5wdh_error_handler(struct ata_port *ap);
255 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
256 static int ahci_port_resume(struct ata_port *ap);
257 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
258 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
259 u32 opts);
260 #ifdef CONFIG_PM
261 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
262 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
263 static int ahci_pci_device_resume(struct pci_dev *pdev);
264 #endif
265
266 static struct class_device_attribute *ahci_shost_attrs[] = {
267 &class_device_attr_link_power_management_policy,
268 NULL
269 };
270
271 static struct scsi_host_template ahci_sht = {
272 .module = THIS_MODULE,
273 .name = DRV_NAME,
274 .ioctl = ata_scsi_ioctl,
275 .queuecommand = ata_scsi_queuecmd,
276 .change_queue_depth = ata_scsi_change_queue_depth,
277 .can_queue = AHCI_MAX_CMDS - 1,
278 .this_id = ATA_SHT_THIS_ID,
279 .sg_tablesize = AHCI_MAX_SG,
280 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
281 .emulated = ATA_SHT_EMULATED,
282 .use_clustering = AHCI_USE_CLUSTERING,
283 .proc_name = DRV_NAME,
284 .dma_boundary = AHCI_DMA_BOUNDARY,
285 .slave_configure = ata_scsi_slave_config,
286 .slave_destroy = ata_scsi_slave_destroy,
287 .bios_param = ata_std_bios_param,
288 .shost_attrs = ahci_shost_attrs,
289 };
290
291 static const struct ata_port_operations ahci_ops = {
292 .check_status = ahci_check_status,
293 .check_altstatus = ahci_check_status,
294 .dev_select = ata_noop_dev_select,
295
296 .tf_read = ahci_tf_read,
297
298 .qc_defer = sata_pmp_qc_defer_cmd_switch,
299 .qc_prep = ahci_qc_prep,
300 .qc_issue = ahci_qc_issue,
301
302 .irq_clear = ahci_irq_clear,
303
304 .scr_read = ahci_scr_read,
305 .scr_write = ahci_scr_write,
306
307 .freeze = ahci_freeze,
308 .thaw = ahci_thaw,
309
310 .error_handler = ahci_error_handler,
311 .post_internal_cmd = ahci_post_internal_cmd,
312
313 .pmp_attach = ahci_pmp_attach,
314 .pmp_detach = ahci_pmp_detach,
315
316 #ifdef CONFIG_PM
317 .port_suspend = ahci_port_suspend,
318 .port_resume = ahci_port_resume,
319 #endif
320 .enable_pm = ahci_enable_alpm,
321 .disable_pm = ahci_disable_alpm,
322
323 .port_start = ahci_port_start,
324 .port_stop = ahci_port_stop,
325 };
326
327 static const struct ata_port_operations ahci_vt8251_ops = {
328 .check_status = ahci_check_status,
329 .check_altstatus = ahci_check_status,
330 .dev_select = ata_noop_dev_select,
331
332 .tf_read = ahci_tf_read,
333
334 .qc_defer = sata_pmp_qc_defer_cmd_switch,
335 .qc_prep = ahci_qc_prep,
336 .qc_issue = ahci_qc_issue,
337
338 .irq_clear = ahci_irq_clear,
339
340 .scr_read = ahci_scr_read,
341 .scr_write = ahci_scr_write,
342
343 .freeze = ahci_freeze,
344 .thaw = ahci_thaw,
345
346 .error_handler = ahci_vt8251_error_handler,
347 .post_internal_cmd = ahci_post_internal_cmd,
348
349 .pmp_attach = ahci_pmp_attach,
350 .pmp_detach = ahci_pmp_detach,
351
352 #ifdef CONFIG_PM
353 .port_suspend = ahci_port_suspend,
354 .port_resume = ahci_port_resume,
355 #endif
356
357 .port_start = ahci_port_start,
358 .port_stop = ahci_port_stop,
359 };
360
361 static const struct ata_port_operations ahci_p5wdh_ops = {
362 .check_status = ahci_check_status,
363 .check_altstatus = ahci_check_status,
364 .dev_select = ata_noop_dev_select,
365
366 .tf_read = ahci_tf_read,
367
368 .qc_defer = sata_pmp_qc_defer_cmd_switch,
369 .qc_prep = ahci_qc_prep,
370 .qc_issue = ahci_qc_issue,
371
372 .irq_clear = ahci_irq_clear,
373
374 .scr_read = ahci_scr_read,
375 .scr_write = ahci_scr_write,
376
377 .freeze = ahci_freeze,
378 .thaw = ahci_thaw,
379
380 .error_handler = ahci_p5wdh_error_handler,
381 .post_internal_cmd = ahci_post_internal_cmd,
382
383 .pmp_attach = ahci_pmp_attach,
384 .pmp_detach = ahci_pmp_detach,
385
386 #ifdef CONFIG_PM
387 .port_suspend = ahci_port_suspend,
388 .port_resume = ahci_port_resume,
389 #endif
390
391 .port_start = ahci_port_start,
392 .port_stop = ahci_port_stop,
393 };
394
395 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
396
397 static const struct ata_port_info ahci_port_info[] = {
398 /* board_ahci */
399 {
400 .flags = AHCI_FLAG_COMMON,
401 .link_flags = AHCI_LFLAG_COMMON,
402 .pio_mask = 0x1f, /* pio0-4 */
403 .udma_mask = ATA_UDMA6,
404 .port_ops = &ahci_ops,
405 },
406 /* board_ahci_vt8251 */
407 {
408 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
409 .flags = AHCI_FLAG_COMMON,
410 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
411 .pio_mask = 0x1f, /* pio0-4 */
412 .udma_mask = ATA_UDMA6,
413 .port_ops = &ahci_vt8251_ops,
414 },
415 /* board_ahci_ign_iferr */
416 {
417 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
418 .flags = AHCI_FLAG_COMMON,
419 .link_flags = AHCI_LFLAG_COMMON,
420 .pio_mask = 0x1f, /* pio0-4 */
421 .udma_mask = ATA_UDMA6,
422 .port_ops = &ahci_ops,
423 },
424 /* board_ahci_sb600 */
425 {
426 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
427 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
428 .flags = AHCI_FLAG_COMMON,
429 .link_flags = AHCI_LFLAG_COMMON,
430 .pio_mask = 0x1f, /* pio0-4 */
431 .udma_mask = ATA_UDMA6,
432 .port_ops = &ahci_ops,
433 },
434 /* board_ahci_mv */
435 {
436 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
437 AHCI_HFLAG_MV_PATA),
438 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
439 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
440 .link_flags = AHCI_LFLAG_COMMON,
441 .pio_mask = 0x1f, /* pio0-4 */
442 .udma_mask = ATA_UDMA6,
443 .port_ops = &ahci_ops,
444 },
445 };
446
447 static const struct pci_device_id ahci_pci_tbl[] = {
448 /* Intel */
449 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
450 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
451 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
452 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
453 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
454 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
455 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
456 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
457 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
458 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
459 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
460 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
461 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
462 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
463 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
464 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
465 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
466 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
467 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
468 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
469 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
470 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
471 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
472 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
473 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
474 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
476 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
477 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
478
479 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
480 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
481 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
482
483 /* ATI */
484 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
485 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
486 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
487 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
488 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
489 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
490 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
491
492 /* VIA */
493 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
494 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
495
496 /* NVIDIA */
497 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
498 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
499 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
500 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
501 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
502 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
503 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
504 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
505 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
506 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
507 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
508 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
509 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
510 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
511 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
512 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
513 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
514 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
515 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
516 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
517 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
518 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
524 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
525 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
526 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
527 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
528 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
529 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
536 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
537 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
538 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
539 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
540 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
541 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
542 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
548 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
549 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
550 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
551 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
552 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
553
554 /* SiS */
555 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
556 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
557 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
558
559 /* Marvell */
560 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
561
562 /* Generic, PCI class code for AHCI */
563 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
564 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
565
566 { } /* terminate list */
567 };
568
569
570 static struct pci_driver ahci_pci_driver = {
571 .name = DRV_NAME,
572 .id_table = ahci_pci_tbl,
573 .probe = ahci_init_one,
574 .remove = ata_pci_remove_one,
575 #ifdef CONFIG_PM
576 .suspend = ahci_pci_device_suspend,
577 .resume = ahci_pci_device_resume,
578 #endif
579 };
580
581
582 static inline int ahci_nr_ports(u32 cap)
583 {
584 return (cap & 0x1f) + 1;
585 }
586
587 static inline void __iomem *__ahci_port_base(struct ata_host *host,
588 unsigned int port_no)
589 {
590 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
591
592 return mmio + 0x100 + (port_no * 0x80);
593 }
594
595 static inline void __iomem *ahci_port_base(struct ata_port *ap)
596 {
597 return __ahci_port_base(ap->host, ap->port_no);
598 }
599
600 static void ahci_enable_ahci(void __iomem *mmio)
601 {
602 u32 tmp;
603
604 /* turn on AHCI_EN */
605 tmp = readl(mmio + HOST_CTL);
606 if (!(tmp & HOST_AHCI_EN)) {
607 tmp |= HOST_AHCI_EN;
608 writel(tmp, mmio + HOST_CTL);
609 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
610 WARN_ON(!(tmp & HOST_AHCI_EN));
611 }
612 }
613
614 /**
615 * ahci_save_initial_config - Save and fixup initial config values
616 * @pdev: target PCI device
617 * @hpriv: host private area to store config values
618 *
619 * Some registers containing configuration info might be setup by
620 * BIOS and might be cleared on reset. This function saves the
621 * initial values of those registers into @hpriv such that they
622 * can be restored after controller reset.
623 *
624 * If inconsistent, config values are fixed up by this function.
625 *
626 * LOCKING:
627 * None.
628 */
629 static void ahci_save_initial_config(struct pci_dev *pdev,
630 struct ahci_host_priv *hpriv)
631 {
632 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
633 u32 cap, port_map;
634 int i;
635
636 /* make sure AHCI mode is enabled before accessing CAP */
637 ahci_enable_ahci(mmio);
638
639 /* Values prefixed with saved_ are written back to host after
640 * reset. Values without are used for driver operation.
641 */
642 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
643 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
644
645 /* some chips have errata preventing 64bit use */
646 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
647 dev_printk(KERN_INFO, &pdev->dev,
648 "controller can't do 64bit DMA, forcing 32bit\n");
649 cap &= ~HOST_CAP_64;
650 }
651
652 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
653 dev_printk(KERN_INFO, &pdev->dev,
654 "controller can't do NCQ, turning off CAP_NCQ\n");
655 cap &= ~HOST_CAP_NCQ;
656 }
657
658 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
659 dev_printk(KERN_INFO, &pdev->dev,
660 "controller can't do PMP, turning off CAP_PMP\n");
661 cap &= ~HOST_CAP_PMP;
662 }
663
664 /*
665 * Temporary Marvell 6145 hack: PATA port presence
666 * is asserted through the standard AHCI port
667 * presence register, as bit 4 (counting from 0)
668 */
669 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
670 dev_printk(KERN_ERR, &pdev->dev,
671 "MV_AHCI HACK: port_map %x -> %x\n",
672 hpriv->port_map,
673 hpriv->port_map & 0xf);
674
675 port_map &= 0xf;
676 }
677
678 /* cross check port_map and cap.n_ports */
679 if (port_map) {
680 u32 tmp_port_map = port_map;
681 int n_ports = ahci_nr_ports(cap);
682
683 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
684 if (tmp_port_map & (1 << i)) {
685 n_ports--;
686 tmp_port_map &= ~(1 << i);
687 }
688 }
689
690 /* If n_ports and port_map are inconsistent, whine and
691 * clear port_map and let it be generated from n_ports.
692 */
693 if (n_ports || tmp_port_map) {
694 dev_printk(KERN_WARNING, &pdev->dev,
695 "nr_ports (%u) and implemented port map "
696 "(0x%x) don't match, using nr_ports\n",
697 ahci_nr_ports(cap), port_map);
698 port_map = 0;
699 }
700 }
701
702 /* fabricate port_map from cap.nr_ports */
703 if (!port_map) {
704 port_map = (1 << ahci_nr_ports(cap)) - 1;
705 dev_printk(KERN_WARNING, &pdev->dev,
706 "forcing PORTS_IMPL to 0x%x\n", port_map);
707
708 /* write the fixed up value to the PI register */
709 hpriv->saved_port_map = port_map;
710 }
711
712 /* record values to use during operation */
713 hpriv->cap = cap;
714 hpriv->port_map = port_map;
715 }
716
717 /**
718 * ahci_restore_initial_config - Restore initial config
719 * @host: target ATA host
720 *
721 * Restore initial config stored by ahci_save_initial_config().
722 *
723 * LOCKING:
724 * None.
725 */
726 static void ahci_restore_initial_config(struct ata_host *host)
727 {
728 struct ahci_host_priv *hpriv = host->private_data;
729 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
730
731 writel(hpriv->saved_cap, mmio + HOST_CAP);
732 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
733 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
734 }
735
736 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
737 {
738 static const int offset[] = {
739 [SCR_STATUS] = PORT_SCR_STAT,
740 [SCR_CONTROL] = PORT_SCR_CTL,
741 [SCR_ERROR] = PORT_SCR_ERR,
742 [SCR_ACTIVE] = PORT_SCR_ACT,
743 [SCR_NOTIFICATION] = PORT_SCR_NTF,
744 };
745 struct ahci_host_priv *hpriv = ap->host->private_data;
746
747 if (sc_reg < ARRAY_SIZE(offset) &&
748 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
749 return offset[sc_reg];
750 return 0;
751 }
752
753 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
754 {
755 void __iomem *port_mmio = ahci_port_base(ap);
756 int offset = ahci_scr_offset(ap, sc_reg);
757
758 if (offset) {
759 *val = readl(port_mmio + offset);
760 return 0;
761 }
762 return -EINVAL;
763 }
764
765 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
766 {
767 void __iomem *port_mmio = ahci_port_base(ap);
768 int offset = ahci_scr_offset(ap, sc_reg);
769
770 if (offset) {
771 writel(val, port_mmio + offset);
772 return 0;
773 }
774 return -EINVAL;
775 }
776
777 static void ahci_start_engine(struct ata_port *ap)
778 {
779 void __iomem *port_mmio = ahci_port_base(ap);
780 u32 tmp;
781
782 /* start DMA */
783 tmp = readl(port_mmio + PORT_CMD);
784 tmp |= PORT_CMD_START;
785 writel(tmp, port_mmio + PORT_CMD);
786 readl(port_mmio + PORT_CMD); /* flush */
787 }
788
789 static int ahci_stop_engine(struct ata_port *ap)
790 {
791 void __iomem *port_mmio = ahci_port_base(ap);
792 u32 tmp;
793
794 tmp = readl(port_mmio + PORT_CMD);
795
796 /* check if the HBA is idle */
797 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
798 return 0;
799
800 /* setting HBA to idle */
801 tmp &= ~PORT_CMD_START;
802 writel(tmp, port_mmio + PORT_CMD);
803
804 /* wait for engine to stop. This could be as long as 500 msec */
805 tmp = ata_wait_register(port_mmio + PORT_CMD,
806 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
807 if (tmp & PORT_CMD_LIST_ON)
808 return -EIO;
809
810 return 0;
811 }
812
813 static void ahci_start_fis_rx(struct ata_port *ap)
814 {
815 void __iomem *port_mmio = ahci_port_base(ap);
816 struct ahci_host_priv *hpriv = ap->host->private_data;
817 struct ahci_port_priv *pp = ap->private_data;
818 u32 tmp;
819
820 /* set FIS registers */
821 if (hpriv->cap & HOST_CAP_64)
822 writel((pp->cmd_slot_dma >> 16) >> 16,
823 port_mmio + PORT_LST_ADDR_HI);
824 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
825
826 if (hpriv->cap & HOST_CAP_64)
827 writel((pp->rx_fis_dma >> 16) >> 16,
828 port_mmio + PORT_FIS_ADDR_HI);
829 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
830
831 /* enable FIS reception */
832 tmp = readl(port_mmio + PORT_CMD);
833 tmp |= PORT_CMD_FIS_RX;
834 writel(tmp, port_mmio + PORT_CMD);
835
836 /* flush */
837 readl(port_mmio + PORT_CMD);
838 }
839
840 static int ahci_stop_fis_rx(struct ata_port *ap)
841 {
842 void __iomem *port_mmio = ahci_port_base(ap);
843 u32 tmp;
844
845 /* disable FIS reception */
846 tmp = readl(port_mmio + PORT_CMD);
847 tmp &= ~PORT_CMD_FIS_RX;
848 writel(tmp, port_mmio + PORT_CMD);
849
850 /* wait for completion, spec says 500ms, give it 1000 */
851 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
852 PORT_CMD_FIS_ON, 10, 1000);
853 if (tmp & PORT_CMD_FIS_ON)
854 return -EBUSY;
855
856 return 0;
857 }
858
859 static void ahci_power_up(struct ata_port *ap)
860 {
861 struct ahci_host_priv *hpriv = ap->host->private_data;
862 void __iomem *port_mmio = ahci_port_base(ap);
863 u32 cmd;
864
865 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
866
867 /* spin up device */
868 if (hpriv->cap & HOST_CAP_SSS) {
869 cmd |= PORT_CMD_SPIN_UP;
870 writel(cmd, port_mmio + PORT_CMD);
871 }
872
873 /* wake up link */
874 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
875 }
876
877 static void ahci_disable_alpm(struct ata_port *ap)
878 {
879 struct ahci_host_priv *hpriv = ap->host->private_data;
880 void __iomem *port_mmio = ahci_port_base(ap);
881 u32 cmd;
882 struct ahci_port_priv *pp = ap->private_data;
883
884 /* IPM bits should be disabled by libata-core */
885 /* get the existing command bits */
886 cmd = readl(port_mmio + PORT_CMD);
887
888 /* disable ALPM and ASP */
889 cmd &= ~PORT_CMD_ASP;
890 cmd &= ~PORT_CMD_ALPE;
891
892 /* force the interface back to active */
893 cmd |= PORT_CMD_ICC_ACTIVE;
894
895 /* write out new cmd value */
896 writel(cmd, port_mmio + PORT_CMD);
897 cmd = readl(port_mmio + PORT_CMD);
898
899 /* wait 10ms to be sure we've come out of any low power state */
900 msleep(10);
901
902 /* clear out any PhyRdy stuff from interrupt status */
903 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
904
905 /* go ahead and clean out PhyRdy Change from Serror too */
906 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
907
908 /*
909 * Clear flag to indicate that we should ignore all PhyRdy
910 * state changes
911 */
912 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
913
914 /*
915 * Enable interrupts on Phy Ready.
916 */
917 pp->intr_mask |= PORT_IRQ_PHYRDY;
918 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
919
920 /*
921 * don't change the link pm policy - we can be called
922 * just to turn of link pm temporarily
923 */
924 }
925
926 static int ahci_enable_alpm(struct ata_port *ap,
927 enum link_pm policy)
928 {
929 struct ahci_host_priv *hpriv = ap->host->private_data;
930 void __iomem *port_mmio = ahci_port_base(ap);
931 u32 cmd;
932 struct ahci_port_priv *pp = ap->private_data;
933 u32 asp;
934
935 /* Make sure the host is capable of link power management */
936 if (!(hpriv->cap & HOST_CAP_ALPM))
937 return -EINVAL;
938
939 switch (policy) {
940 case MAX_PERFORMANCE:
941 case NOT_AVAILABLE:
942 /*
943 * if we came here with NOT_AVAILABLE,
944 * it just means this is the first time we
945 * have tried to enable - default to max performance,
946 * and let the user go to lower power modes on request.
947 */
948 ahci_disable_alpm(ap);
949 return 0;
950 case MIN_POWER:
951 /* configure HBA to enter SLUMBER */
952 asp = PORT_CMD_ASP;
953 break;
954 case MEDIUM_POWER:
955 /* configure HBA to enter PARTIAL */
956 asp = 0;
957 break;
958 default:
959 return -EINVAL;
960 }
961
962 /*
963 * Disable interrupts on Phy Ready. This keeps us from
964 * getting woken up due to spurious phy ready interrupts
965 * TBD - Hot plug should be done via polling now, is
966 * that even supported?
967 */
968 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
969 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
970
971 /*
972 * Set a flag to indicate that we should ignore all PhyRdy
973 * state changes since these can happen now whenever we
974 * change link state
975 */
976 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
977
978 /* get the existing command bits */
979 cmd = readl(port_mmio + PORT_CMD);
980
981 /*
982 * Set ASP based on Policy
983 */
984 cmd |= asp;
985
986 /*
987 * Setting this bit will instruct the HBA to aggressively
988 * enter a lower power link state when it's appropriate and
989 * based on the value set above for ASP
990 */
991 cmd |= PORT_CMD_ALPE;
992
993 /* write out new cmd value */
994 writel(cmd, port_mmio + PORT_CMD);
995 cmd = readl(port_mmio + PORT_CMD);
996
997 /* IPM bits should be set by libata-core */
998 return 0;
999 }
1000
1001 #ifdef CONFIG_PM
1002 static void ahci_power_down(struct ata_port *ap)
1003 {
1004 struct ahci_host_priv *hpriv = ap->host->private_data;
1005 void __iomem *port_mmio = ahci_port_base(ap);
1006 u32 cmd, scontrol;
1007
1008 if (!(hpriv->cap & HOST_CAP_SSS))
1009 return;
1010
1011 /* put device into listen mode, first set PxSCTL.DET to 0 */
1012 scontrol = readl(port_mmio + PORT_SCR_CTL);
1013 scontrol &= ~0xf;
1014 writel(scontrol, port_mmio + PORT_SCR_CTL);
1015
1016 /* then set PxCMD.SUD to 0 */
1017 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1018 cmd &= ~PORT_CMD_SPIN_UP;
1019 writel(cmd, port_mmio + PORT_CMD);
1020 }
1021 #endif
1022
1023 static void ahci_start_port(struct ata_port *ap)
1024 {
1025 /* enable FIS reception */
1026 ahci_start_fis_rx(ap);
1027
1028 /* enable DMA */
1029 ahci_start_engine(ap);
1030 }
1031
1032 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1033 {
1034 int rc;
1035
1036 /* disable DMA */
1037 rc = ahci_stop_engine(ap);
1038 if (rc) {
1039 *emsg = "failed to stop engine";
1040 return rc;
1041 }
1042
1043 /* disable FIS reception */
1044 rc = ahci_stop_fis_rx(ap);
1045 if (rc) {
1046 *emsg = "failed stop FIS RX";
1047 return rc;
1048 }
1049
1050 return 0;
1051 }
1052
1053 static int ahci_reset_controller(struct ata_host *host)
1054 {
1055 struct pci_dev *pdev = to_pci_dev(host->dev);
1056 struct ahci_host_priv *hpriv = host->private_data;
1057 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1058 u32 tmp;
1059
1060 /* we must be in AHCI mode, before using anything
1061 * AHCI-specific, such as HOST_RESET.
1062 */
1063 ahci_enable_ahci(mmio);
1064
1065 /* global controller reset */
1066 tmp = readl(mmio + HOST_CTL);
1067 if ((tmp & HOST_RESET) == 0) {
1068 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1069 readl(mmio + HOST_CTL); /* flush */
1070 }
1071
1072 /* reset must complete within 1 second, or
1073 * the hardware should be considered fried.
1074 */
1075 ssleep(1);
1076
1077 tmp = readl(mmio + HOST_CTL);
1078 if (tmp & HOST_RESET) {
1079 dev_printk(KERN_ERR, host->dev,
1080 "controller reset failed (0x%x)\n", tmp);
1081 return -EIO;
1082 }
1083
1084 /* turn on AHCI mode */
1085 ahci_enable_ahci(mmio);
1086
1087 /* some registers might be cleared on reset. restore initial values */
1088 ahci_restore_initial_config(host);
1089
1090 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1091 u16 tmp16;
1092
1093 /* configure PCS */
1094 pci_read_config_word(pdev, 0x92, &tmp16);
1095 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1096 tmp16 |= hpriv->port_map;
1097 pci_write_config_word(pdev, 0x92, tmp16);
1098 }
1099 }
1100
1101 return 0;
1102 }
1103
1104 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1105 int port_no, void __iomem *mmio,
1106 void __iomem *port_mmio)
1107 {
1108 const char *emsg = NULL;
1109 int rc;
1110 u32 tmp;
1111
1112 /* make sure port is not active */
1113 rc = ahci_deinit_port(ap, &emsg);
1114 if (rc)
1115 dev_printk(KERN_WARNING, &pdev->dev,
1116 "%s (%d)\n", emsg, rc);
1117
1118 /* clear SError */
1119 tmp = readl(port_mmio + PORT_SCR_ERR);
1120 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1121 writel(tmp, port_mmio + PORT_SCR_ERR);
1122
1123 /* clear port IRQ */
1124 tmp = readl(port_mmio + PORT_IRQ_STAT);
1125 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1126 if (tmp)
1127 writel(tmp, port_mmio + PORT_IRQ_STAT);
1128
1129 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1130 }
1131
1132 static void ahci_init_controller(struct ata_host *host)
1133 {
1134 struct ahci_host_priv *hpriv = host->private_data;
1135 struct pci_dev *pdev = to_pci_dev(host->dev);
1136 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1137 int i;
1138 void __iomem *port_mmio;
1139 u32 tmp;
1140
1141 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1142 port_mmio = __ahci_port_base(host, 4);
1143
1144 writel(0, port_mmio + PORT_IRQ_MASK);
1145
1146 /* clear port IRQ */
1147 tmp = readl(port_mmio + PORT_IRQ_STAT);
1148 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1149 if (tmp)
1150 writel(tmp, port_mmio + PORT_IRQ_STAT);
1151 }
1152
1153 for (i = 0; i < host->n_ports; i++) {
1154 struct ata_port *ap = host->ports[i];
1155
1156 port_mmio = ahci_port_base(ap);
1157 if (ata_port_is_dummy(ap))
1158 continue;
1159
1160 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1161 }
1162
1163 tmp = readl(mmio + HOST_CTL);
1164 VPRINTK("HOST_CTL 0x%x\n", tmp);
1165 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1166 tmp = readl(mmio + HOST_CTL);
1167 VPRINTK("HOST_CTL 0x%x\n", tmp);
1168 }
1169
1170 static unsigned int ahci_dev_classify(struct ata_port *ap)
1171 {
1172 void __iomem *port_mmio = ahci_port_base(ap);
1173 struct ata_taskfile tf;
1174 u32 tmp;
1175
1176 tmp = readl(port_mmio + PORT_SIG);
1177 tf.lbah = (tmp >> 24) & 0xff;
1178 tf.lbam = (tmp >> 16) & 0xff;
1179 tf.lbal = (tmp >> 8) & 0xff;
1180 tf.nsect = (tmp) & 0xff;
1181
1182 return ata_dev_classify(&tf);
1183 }
1184
1185 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1186 u32 opts)
1187 {
1188 dma_addr_t cmd_tbl_dma;
1189
1190 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1191
1192 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1193 pp->cmd_slot[tag].status = 0;
1194 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1195 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1196 }
1197
1198 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1199 {
1200 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1201 struct ahci_host_priv *hpriv = ap->host->private_data;
1202 u32 tmp;
1203 int busy, rc;
1204
1205 /* do we need to kick the port? */
1206 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1207 if (!busy && !force_restart)
1208 return 0;
1209
1210 /* stop engine */
1211 rc = ahci_stop_engine(ap);
1212 if (rc)
1213 goto out_restart;
1214
1215 /* need to do CLO? */
1216 if (!busy) {
1217 rc = 0;
1218 goto out_restart;
1219 }
1220
1221 if (!(hpriv->cap & HOST_CAP_CLO)) {
1222 rc = -EOPNOTSUPP;
1223 goto out_restart;
1224 }
1225
1226 /* perform CLO */
1227 tmp = readl(port_mmio + PORT_CMD);
1228 tmp |= PORT_CMD_CLO;
1229 writel(tmp, port_mmio + PORT_CMD);
1230
1231 rc = 0;
1232 tmp = ata_wait_register(port_mmio + PORT_CMD,
1233 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1234 if (tmp & PORT_CMD_CLO)
1235 rc = -EIO;
1236
1237 /* restart engine */
1238 out_restart:
1239 ahci_start_engine(ap);
1240 return rc;
1241 }
1242
1243 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1244 struct ata_taskfile *tf, int is_cmd, u16 flags,
1245 unsigned long timeout_msec)
1246 {
1247 const u32 cmd_fis_len = 5; /* five dwords */
1248 struct ahci_port_priv *pp = ap->private_data;
1249 void __iomem *port_mmio = ahci_port_base(ap);
1250 u8 *fis = pp->cmd_tbl;
1251 u32 tmp;
1252
1253 /* prep the command */
1254 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1255 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1256
1257 /* issue & wait */
1258 writel(1, port_mmio + PORT_CMD_ISSUE);
1259
1260 if (timeout_msec) {
1261 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1262 1, timeout_msec);
1263 if (tmp & 0x1) {
1264 ahci_kick_engine(ap, 1);
1265 return -EBUSY;
1266 }
1267 } else
1268 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1269
1270 return 0;
1271 }
1272
1273 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1274 int pmp, unsigned long deadline)
1275 {
1276 struct ata_port *ap = link->ap;
1277 const char *reason = NULL;
1278 unsigned long now, msecs;
1279 struct ata_taskfile tf;
1280 int rc;
1281
1282 DPRINTK("ENTER\n");
1283
1284 if (ata_link_offline(link)) {
1285 DPRINTK("PHY reports no device\n");
1286 *class = ATA_DEV_NONE;
1287 return 0;
1288 }
1289
1290 /* prepare for SRST (AHCI-1.1 10.4.1) */
1291 rc = ahci_kick_engine(ap, 1);
1292 if (rc && rc != -EOPNOTSUPP)
1293 ata_link_printk(link, KERN_WARNING,
1294 "failed to reset engine (errno=%d)\n", rc);
1295
1296 ata_tf_init(link->device, &tf);
1297
1298 /* issue the first D2H Register FIS */
1299 msecs = 0;
1300 now = jiffies;
1301 if (time_after(now, deadline))
1302 msecs = jiffies_to_msecs(deadline - now);
1303
1304 tf.ctl |= ATA_SRST;
1305 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1306 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1307 rc = -EIO;
1308 reason = "1st FIS failed";
1309 goto fail;
1310 }
1311
1312 /* spec says at least 5us, but be generous and sleep for 1ms */
1313 msleep(1);
1314
1315 /* issue the second D2H Register FIS */
1316 tf.ctl &= ~ATA_SRST;
1317 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1318
1319 /* wait a while before checking status */
1320 ata_wait_after_reset(ap, deadline);
1321
1322 rc = ata_wait_ready(ap, deadline);
1323 /* link occupied, -ENODEV too is an error */
1324 if (rc) {
1325 reason = "device not ready";
1326 goto fail;
1327 }
1328 *class = ahci_dev_classify(ap);
1329
1330 DPRINTK("EXIT, class=%u\n", *class);
1331 return 0;
1332
1333 fail:
1334 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1335 return rc;
1336 }
1337
1338 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1339 unsigned long deadline)
1340 {
1341 int pmp = 0;
1342
1343 if (link->ap->flags & ATA_FLAG_PMP)
1344 pmp = SATA_PMP_CTRL_PORT;
1345
1346 return ahci_do_softreset(link, class, pmp, deadline);
1347 }
1348
1349 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1350 unsigned long deadline)
1351 {
1352 struct ata_port *ap = link->ap;
1353 struct ahci_port_priv *pp = ap->private_data;
1354 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1355 struct ata_taskfile tf;
1356 int rc;
1357
1358 DPRINTK("ENTER\n");
1359
1360 ahci_stop_engine(ap);
1361
1362 /* clear D2H reception area to properly wait for D2H FIS */
1363 ata_tf_init(link->device, &tf);
1364 tf.command = 0x80;
1365 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1366
1367 rc = sata_std_hardreset(link, class, deadline);
1368
1369 ahci_start_engine(ap);
1370
1371 if (rc == 0 && ata_link_online(link))
1372 *class = ahci_dev_classify(ap);
1373 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1374 *class = ATA_DEV_NONE;
1375
1376 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1377 return rc;
1378 }
1379
1380 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1381 unsigned long deadline)
1382 {
1383 struct ata_port *ap = link->ap;
1384 u32 serror;
1385 int rc;
1386
1387 DPRINTK("ENTER\n");
1388
1389 ahci_stop_engine(ap);
1390
1391 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1392 deadline);
1393
1394 /* vt8251 needs SError cleared for the port to operate */
1395 ahci_scr_read(ap, SCR_ERROR, &serror);
1396 ahci_scr_write(ap, SCR_ERROR, serror);
1397
1398 ahci_start_engine(ap);
1399
1400 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1401
1402 /* vt8251 doesn't clear BSY on signature FIS reception,
1403 * request follow-up softreset.
1404 */
1405 return rc ?: -EAGAIN;
1406 }
1407
1408 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1409 unsigned long deadline)
1410 {
1411 struct ata_port *ap = link->ap;
1412 struct ahci_port_priv *pp = ap->private_data;
1413 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1414 struct ata_taskfile tf;
1415 int rc;
1416
1417 ahci_stop_engine(ap);
1418
1419 /* clear D2H reception area to properly wait for D2H FIS */
1420 ata_tf_init(link->device, &tf);
1421 tf.command = 0x80;
1422 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1423
1424 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1425 deadline);
1426
1427 ahci_start_engine(ap);
1428
1429 if (rc || ata_link_offline(link))
1430 return rc;
1431
1432 /* spec mandates ">= 2ms" before checking status */
1433 msleep(150);
1434
1435 /* The pseudo configuration device on SIMG4726 attached to
1436 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1437 * hardreset if no device is attached to the first downstream
1438 * port && the pseudo device locks up on SRST w/ PMP==0. To
1439 * work around this, wait for !BSY only briefly. If BSY isn't
1440 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1441 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1442 *
1443 * Wait for two seconds. Devices attached to downstream port
1444 * which can't process the following IDENTIFY after this will
1445 * have to be reset again. For most cases, this should
1446 * suffice while making probing snappish enough.
1447 */
1448 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1449 if (rc)
1450 ahci_kick_engine(ap, 0);
1451
1452 return 0;
1453 }
1454
1455 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1456 {
1457 struct ata_port *ap = link->ap;
1458 void __iomem *port_mmio = ahci_port_base(ap);
1459 u32 new_tmp, tmp;
1460
1461 ata_std_postreset(link, class);
1462
1463 /* Make sure port's ATAPI bit is set appropriately */
1464 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1465 if (*class == ATA_DEV_ATAPI)
1466 new_tmp |= PORT_CMD_ATAPI;
1467 else
1468 new_tmp &= ~PORT_CMD_ATAPI;
1469 if (new_tmp != tmp) {
1470 writel(new_tmp, port_mmio + PORT_CMD);
1471 readl(port_mmio + PORT_CMD); /* flush */
1472 }
1473 }
1474
1475 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1476 unsigned long deadline)
1477 {
1478 return ahci_do_softreset(link, class, link->pmp, deadline);
1479 }
1480
1481 static u8 ahci_check_status(struct ata_port *ap)
1482 {
1483 void __iomem *mmio = ap->ioaddr.cmd_addr;
1484
1485 return readl(mmio + PORT_TFDATA) & 0xFF;
1486 }
1487
1488 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1489 {
1490 struct ahci_port_priv *pp = ap->private_data;
1491 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1492
1493 ata_tf_from_fis(d2h_fis, tf);
1494 }
1495
1496 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1497 {
1498 struct scatterlist *sg;
1499 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1500 unsigned int si;
1501
1502 VPRINTK("ENTER\n");
1503
1504 /*
1505 * Next, the S/G list.
1506 */
1507 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1508 dma_addr_t addr = sg_dma_address(sg);
1509 u32 sg_len = sg_dma_len(sg);
1510
1511 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1512 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1513 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1514 }
1515
1516 return si;
1517 }
1518
1519 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1520 {
1521 struct ata_port *ap = qc->ap;
1522 struct ahci_port_priv *pp = ap->private_data;
1523 int is_atapi = ata_is_atapi(qc->tf.protocol);
1524 void *cmd_tbl;
1525 u32 opts;
1526 const u32 cmd_fis_len = 5; /* five dwords */
1527 unsigned int n_elem;
1528
1529 /*
1530 * Fill in command table information. First, the header,
1531 * a SATA Register - Host to Device command FIS.
1532 */
1533 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1534
1535 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1536 if (is_atapi) {
1537 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1538 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1539 }
1540
1541 n_elem = 0;
1542 if (qc->flags & ATA_QCFLAG_DMAMAP)
1543 n_elem = ahci_fill_sg(qc, cmd_tbl);
1544
1545 /*
1546 * Fill in command slot information.
1547 */
1548 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1549 if (qc->tf.flags & ATA_TFLAG_WRITE)
1550 opts |= AHCI_CMD_WRITE;
1551 if (is_atapi)
1552 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1553
1554 ahci_fill_cmd_slot(pp, qc->tag, opts);
1555 }
1556
1557 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1558 {
1559 struct ahci_host_priv *hpriv = ap->host->private_data;
1560 struct ahci_port_priv *pp = ap->private_data;
1561 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1562 struct ata_link *link = NULL;
1563 struct ata_queued_cmd *active_qc;
1564 struct ata_eh_info *active_ehi;
1565 u32 serror;
1566
1567 /* determine active link */
1568 ata_port_for_each_link(link, ap)
1569 if (ata_link_active(link))
1570 break;
1571 if (!link)
1572 link = &ap->link;
1573
1574 active_qc = ata_qc_from_tag(ap, link->active_tag);
1575 active_ehi = &link->eh_info;
1576
1577 /* record irq stat */
1578 ata_ehi_clear_desc(host_ehi);
1579 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1580
1581 /* AHCI needs SError cleared; otherwise, it might lock up */
1582 ahci_scr_read(ap, SCR_ERROR, &serror);
1583 ahci_scr_write(ap, SCR_ERROR, serror);
1584 host_ehi->serror |= serror;
1585
1586 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1587 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1588 irq_stat &= ~PORT_IRQ_IF_ERR;
1589
1590 if (irq_stat & PORT_IRQ_TF_ERR) {
1591 /* If qc is active, charge it; otherwise, the active
1592 * link. There's no active qc on NCQ errors. It will
1593 * be determined by EH by reading log page 10h.
1594 */
1595 if (active_qc)
1596 active_qc->err_mask |= AC_ERR_DEV;
1597 else
1598 active_ehi->err_mask |= AC_ERR_DEV;
1599
1600 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1601 host_ehi->serror &= ~SERR_INTERNAL;
1602 }
1603
1604 if (irq_stat & PORT_IRQ_UNK_FIS) {
1605 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1606
1607 active_ehi->err_mask |= AC_ERR_HSM;
1608 active_ehi->action |= ATA_EH_SOFTRESET;
1609 ata_ehi_push_desc(active_ehi,
1610 "unknown FIS %08x %08x %08x %08x" ,
1611 unk[0], unk[1], unk[2], unk[3]);
1612 }
1613
1614 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1615 active_ehi->err_mask |= AC_ERR_HSM;
1616 active_ehi->action |= ATA_EH_SOFTRESET;
1617 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1618 }
1619
1620 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1621 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1622 host_ehi->action |= ATA_EH_SOFTRESET;
1623 ata_ehi_push_desc(host_ehi, "host bus error");
1624 }
1625
1626 if (irq_stat & PORT_IRQ_IF_ERR) {
1627 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1628 host_ehi->action |= ATA_EH_SOFTRESET;
1629 ata_ehi_push_desc(host_ehi, "interface fatal error");
1630 }
1631
1632 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1633 ata_ehi_hotplugged(host_ehi);
1634 ata_ehi_push_desc(host_ehi, "%s",
1635 irq_stat & PORT_IRQ_CONNECT ?
1636 "connection status changed" : "PHY RDY changed");
1637 }
1638
1639 /* okay, let's hand over to EH */
1640
1641 if (irq_stat & PORT_IRQ_FREEZE)
1642 ata_port_freeze(ap);
1643 else
1644 ata_port_abort(ap);
1645 }
1646
1647 static void ahci_port_intr(struct ata_port *ap)
1648 {
1649 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1650 struct ata_eh_info *ehi = &ap->link.eh_info;
1651 struct ahci_port_priv *pp = ap->private_data;
1652 struct ahci_host_priv *hpriv = ap->host->private_data;
1653 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1654 u32 status, qc_active;
1655 int rc;
1656
1657 status = readl(port_mmio + PORT_IRQ_STAT);
1658 writel(status, port_mmio + PORT_IRQ_STAT);
1659
1660 /* ignore BAD_PMP while resetting */
1661 if (unlikely(resetting))
1662 status &= ~PORT_IRQ_BAD_PMP;
1663
1664 /* If we are getting PhyRdy, this is
1665 * just a power state change, we should
1666 * clear out this, plus the PhyRdy/Comm
1667 * Wake bits from Serror
1668 */
1669 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1670 (status & PORT_IRQ_PHYRDY)) {
1671 status &= ~PORT_IRQ_PHYRDY;
1672 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1673 }
1674
1675 if (unlikely(status & PORT_IRQ_ERROR)) {
1676 ahci_error_intr(ap, status);
1677 return;
1678 }
1679
1680 if (status & PORT_IRQ_SDB_FIS) {
1681 /* If SNotification is available, leave notification
1682 * handling to sata_async_notification(). If not,
1683 * emulate it by snooping SDB FIS RX area.
1684 *
1685 * Snooping FIS RX area is probably cheaper than
1686 * poking SNotification but some constrollers which
1687 * implement SNotification, ICH9 for example, don't
1688 * store AN SDB FIS into receive area.
1689 */
1690 if (hpriv->cap & HOST_CAP_SNTF)
1691 sata_async_notification(ap);
1692 else {
1693 /* If the 'N' bit in word 0 of the FIS is set,
1694 * we just received asynchronous notification.
1695 * Tell libata about it.
1696 */
1697 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1698 u32 f0 = le32_to_cpu(f[0]);
1699
1700 if (f0 & (1 << 15))
1701 sata_async_notification(ap);
1702 }
1703 }
1704
1705 /* pp->active_link is valid iff any command is in flight */
1706 if (ap->qc_active && pp->active_link->sactive)
1707 qc_active = readl(port_mmio + PORT_SCR_ACT);
1708 else
1709 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1710
1711 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1712
1713 /* while resetting, invalid completions are expected */
1714 if (unlikely(rc < 0 && !resetting)) {
1715 ehi->err_mask |= AC_ERR_HSM;
1716 ehi->action |= ATA_EH_SOFTRESET;
1717 ata_port_freeze(ap);
1718 }
1719 }
1720
1721 static void ahci_irq_clear(struct ata_port *ap)
1722 {
1723 /* TODO */
1724 }
1725
1726 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1727 {
1728 struct ata_host *host = dev_instance;
1729 struct ahci_host_priv *hpriv;
1730 unsigned int i, handled = 0;
1731 void __iomem *mmio;
1732 u32 irq_stat, irq_ack = 0;
1733
1734 VPRINTK("ENTER\n");
1735
1736 hpriv = host->private_data;
1737 mmio = host->iomap[AHCI_PCI_BAR];
1738
1739 /* sigh. 0xffffffff is a valid return from h/w */
1740 irq_stat = readl(mmio + HOST_IRQ_STAT);
1741 irq_stat &= hpriv->port_map;
1742 if (!irq_stat)
1743 return IRQ_NONE;
1744
1745 spin_lock(&host->lock);
1746
1747 for (i = 0; i < host->n_ports; i++) {
1748 struct ata_port *ap;
1749
1750 if (!(irq_stat & (1 << i)))
1751 continue;
1752
1753 ap = host->ports[i];
1754 if (ap) {
1755 ahci_port_intr(ap);
1756 VPRINTK("port %u\n", i);
1757 } else {
1758 VPRINTK("port %u (no irq)\n", i);
1759 if (ata_ratelimit())
1760 dev_printk(KERN_WARNING, host->dev,
1761 "interrupt on disabled port %u\n", i);
1762 }
1763
1764 irq_ack |= (1 << i);
1765 }
1766
1767 if (irq_ack) {
1768 writel(irq_ack, mmio + HOST_IRQ_STAT);
1769 handled = 1;
1770 }
1771
1772 spin_unlock(&host->lock);
1773
1774 VPRINTK("EXIT\n");
1775
1776 return IRQ_RETVAL(handled);
1777 }
1778
1779 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1780 {
1781 struct ata_port *ap = qc->ap;
1782 void __iomem *port_mmio = ahci_port_base(ap);
1783 struct ahci_port_priv *pp = ap->private_data;
1784
1785 /* Keep track of the currently active link. It will be used
1786 * in completion path to determine whether NCQ phase is in
1787 * progress.
1788 */
1789 pp->active_link = qc->dev->link;
1790
1791 if (qc->tf.protocol == ATA_PROT_NCQ)
1792 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1793 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1794 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1795
1796 return 0;
1797 }
1798
1799 static void ahci_freeze(struct ata_port *ap)
1800 {
1801 void __iomem *port_mmio = ahci_port_base(ap);
1802
1803 /* turn IRQ off */
1804 writel(0, port_mmio + PORT_IRQ_MASK);
1805 }
1806
1807 static void ahci_thaw(struct ata_port *ap)
1808 {
1809 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1810 void __iomem *port_mmio = ahci_port_base(ap);
1811 u32 tmp;
1812 struct ahci_port_priv *pp = ap->private_data;
1813
1814 /* clear IRQ */
1815 tmp = readl(port_mmio + PORT_IRQ_STAT);
1816 writel(tmp, port_mmio + PORT_IRQ_STAT);
1817 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1818
1819 /* turn IRQ back on */
1820 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1821 }
1822
1823 static void ahci_error_handler(struct ata_port *ap)
1824 {
1825 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1826 /* restart engine */
1827 ahci_stop_engine(ap);
1828 ahci_start_engine(ap);
1829 }
1830
1831 /* perform recovery */
1832 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1833 ahci_hardreset, ahci_postreset,
1834 sata_pmp_std_prereset, ahci_pmp_softreset,
1835 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1836 }
1837
1838 static void ahci_vt8251_error_handler(struct ata_port *ap)
1839 {
1840 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1841 /* restart engine */
1842 ahci_stop_engine(ap);
1843 ahci_start_engine(ap);
1844 }
1845
1846 /* perform recovery */
1847 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1848 ahci_postreset);
1849 }
1850
1851 static void ahci_p5wdh_error_handler(struct ata_port *ap)
1852 {
1853 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1854 /* restart engine */
1855 ahci_stop_engine(ap);
1856 ahci_start_engine(ap);
1857 }
1858
1859 /* perform recovery */
1860 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1861 ahci_postreset);
1862 }
1863
1864 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1865 {
1866 struct ata_port *ap = qc->ap;
1867
1868 /* make DMA engine forget about the failed command */
1869 if (qc->flags & ATA_QCFLAG_FAILED)
1870 ahci_kick_engine(ap, 1);
1871 }
1872
1873 static void ahci_pmp_attach(struct ata_port *ap)
1874 {
1875 void __iomem *port_mmio = ahci_port_base(ap);
1876 struct ahci_port_priv *pp = ap->private_data;
1877 u32 cmd;
1878
1879 cmd = readl(port_mmio + PORT_CMD);
1880 cmd |= PORT_CMD_PMP;
1881 writel(cmd, port_mmio + PORT_CMD);
1882
1883 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1884 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1885 }
1886
1887 static void ahci_pmp_detach(struct ata_port *ap)
1888 {
1889 void __iomem *port_mmio = ahci_port_base(ap);
1890 struct ahci_port_priv *pp = ap->private_data;
1891 u32 cmd;
1892
1893 cmd = readl(port_mmio + PORT_CMD);
1894 cmd &= ~PORT_CMD_PMP;
1895 writel(cmd, port_mmio + PORT_CMD);
1896
1897 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1898 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1899 }
1900
1901 static int ahci_port_resume(struct ata_port *ap)
1902 {
1903 ahci_power_up(ap);
1904 ahci_start_port(ap);
1905
1906 if (ap->nr_pmp_links)
1907 ahci_pmp_attach(ap);
1908 else
1909 ahci_pmp_detach(ap);
1910
1911 return 0;
1912 }
1913
1914 #ifdef CONFIG_PM
1915 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1916 {
1917 const char *emsg = NULL;
1918 int rc;
1919
1920 rc = ahci_deinit_port(ap, &emsg);
1921 if (rc == 0)
1922 ahci_power_down(ap);
1923 else {
1924 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1925 ahci_start_port(ap);
1926 }
1927
1928 return rc;
1929 }
1930
1931 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1932 {
1933 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1934 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1935 u32 ctl;
1936
1937 if (mesg.event == PM_EVENT_SUSPEND) {
1938 /* AHCI spec rev1.1 section 8.3.3:
1939 * Software must disable interrupts prior to requesting a
1940 * transition of the HBA to D3 state.
1941 */
1942 ctl = readl(mmio + HOST_CTL);
1943 ctl &= ~HOST_IRQ_EN;
1944 writel(ctl, mmio + HOST_CTL);
1945 readl(mmio + HOST_CTL); /* flush */
1946 }
1947
1948 return ata_pci_device_suspend(pdev, mesg);
1949 }
1950
1951 static int ahci_pci_device_resume(struct pci_dev *pdev)
1952 {
1953 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1954 int rc;
1955
1956 rc = ata_pci_device_do_resume(pdev);
1957 if (rc)
1958 return rc;
1959
1960 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1961 rc = ahci_reset_controller(host);
1962 if (rc)
1963 return rc;
1964
1965 ahci_init_controller(host);
1966 }
1967
1968 ata_host_resume(host);
1969
1970 return 0;
1971 }
1972 #endif
1973
1974 static int ahci_port_start(struct ata_port *ap)
1975 {
1976 struct device *dev = ap->host->dev;
1977 struct ahci_port_priv *pp;
1978 void *mem;
1979 dma_addr_t mem_dma;
1980 int rc;
1981
1982 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1983 if (!pp)
1984 return -ENOMEM;
1985
1986 rc = ata_pad_alloc(ap, dev);
1987 if (rc)
1988 return rc;
1989
1990 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1991 GFP_KERNEL);
1992 if (!mem)
1993 return -ENOMEM;
1994 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1995
1996 /*
1997 * First item in chunk of DMA memory: 32-slot command table,
1998 * 32 bytes each in size
1999 */
2000 pp->cmd_slot = mem;
2001 pp->cmd_slot_dma = mem_dma;
2002
2003 mem += AHCI_CMD_SLOT_SZ;
2004 mem_dma += AHCI_CMD_SLOT_SZ;
2005
2006 /*
2007 * Second item: Received-FIS area
2008 */
2009 pp->rx_fis = mem;
2010 pp->rx_fis_dma = mem_dma;
2011
2012 mem += AHCI_RX_FIS_SZ;
2013 mem_dma += AHCI_RX_FIS_SZ;
2014
2015 /*
2016 * Third item: data area for storing a single command
2017 * and its scatter-gather table
2018 */
2019 pp->cmd_tbl = mem;
2020 pp->cmd_tbl_dma = mem_dma;
2021
2022 /*
2023 * Save off initial list of interrupts to be enabled.
2024 * This could be changed later
2025 */
2026 pp->intr_mask = DEF_PORT_IRQ;
2027
2028 ap->private_data = pp;
2029
2030 /* engage engines, captain */
2031 return ahci_port_resume(ap);
2032 }
2033
2034 static void ahci_port_stop(struct ata_port *ap)
2035 {
2036 const char *emsg = NULL;
2037 int rc;
2038
2039 /* de-initialize port */
2040 rc = ahci_deinit_port(ap, &emsg);
2041 if (rc)
2042 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2043 }
2044
2045 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2046 {
2047 int rc;
2048
2049 if (using_dac &&
2050 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2051 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2052 if (rc) {
2053 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2054 if (rc) {
2055 dev_printk(KERN_ERR, &pdev->dev,
2056 "64-bit DMA enable failed\n");
2057 return rc;
2058 }
2059 }
2060 } else {
2061 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2062 if (rc) {
2063 dev_printk(KERN_ERR, &pdev->dev,
2064 "32-bit DMA enable failed\n");
2065 return rc;
2066 }
2067 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2068 if (rc) {
2069 dev_printk(KERN_ERR, &pdev->dev,
2070 "32-bit consistent DMA enable failed\n");
2071 return rc;
2072 }
2073 }
2074 return 0;
2075 }
2076
2077 static void ahci_print_info(struct ata_host *host)
2078 {
2079 struct ahci_host_priv *hpriv = host->private_data;
2080 struct pci_dev *pdev = to_pci_dev(host->dev);
2081 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2082 u32 vers, cap, impl, speed;
2083 const char *speed_s;
2084 u16 cc;
2085 const char *scc_s;
2086
2087 vers = readl(mmio + HOST_VERSION);
2088 cap = hpriv->cap;
2089 impl = hpriv->port_map;
2090
2091 speed = (cap >> 20) & 0xf;
2092 if (speed == 1)
2093 speed_s = "1.5";
2094 else if (speed == 2)
2095 speed_s = "3";
2096 else
2097 speed_s = "?";
2098
2099 pci_read_config_word(pdev, 0x0a, &cc);
2100 if (cc == PCI_CLASS_STORAGE_IDE)
2101 scc_s = "IDE";
2102 else if (cc == PCI_CLASS_STORAGE_SATA)
2103 scc_s = "SATA";
2104 else if (cc == PCI_CLASS_STORAGE_RAID)
2105 scc_s = "RAID";
2106 else
2107 scc_s = "unknown";
2108
2109 dev_printk(KERN_INFO, &pdev->dev,
2110 "AHCI %02x%02x.%02x%02x "
2111 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2112 ,
2113
2114 (vers >> 24) & 0xff,
2115 (vers >> 16) & 0xff,
2116 (vers >> 8) & 0xff,
2117 vers & 0xff,
2118
2119 ((cap >> 8) & 0x1f) + 1,
2120 (cap & 0x1f) + 1,
2121 speed_s,
2122 impl,
2123 scc_s);
2124
2125 dev_printk(KERN_INFO, &pdev->dev,
2126 "flags: "
2127 "%s%s%s%s%s%s%s"
2128 "%s%s%s%s%s%s%s\n"
2129 ,
2130
2131 cap & (1 << 31) ? "64bit " : "",
2132 cap & (1 << 30) ? "ncq " : "",
2133 cap & (1 << 29) ? "sntf " : "",
2134 cap & (1 << 28) ? "ilck " : "",
2135 cap & (1 << 27) ? "stag " : "",
2136 cap & (1 << 26) ? "pm " : "",
2137 cap & (1 << 25) ? "led " : "",
2138
2139 cap & (1 << 24) ? "clo " : "",
2140 cap & (1 << 19) ? "nz " : "",
2141 cap & (1 << 18) ? "only " : "",
2142 cap & (1 << 17) ? "pmp " : "",
2143 cap & (1 << 15) ? "pio " : "",
2144 cap & (1 << 14) ? "slum " : "",
2145 cap & (1 << 13) ? "part " : ""
2146 );
2147 }
2148
2149 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2150 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2151 * support PMP and the 4726 either directly exports the device
2152 * attached to the first downstream port or acts as a hardware storage
2153 * controller and emulate a single ATA device (can be RAID 0/1 or some
2154 * other configuration).
2155 *
2156 * When there's no device attached to the first downstream port of the
2157 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2158 * configure the 4726. However, ATA emulation of the device is very
2159 * lame. It doesn't send signature D2H Reg FIS after the initial
2160 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2161 *
2162 * The following function works around the problem by always using
2163 * hardreset on the port and not depending on receiving signature FIS
2164 * afterward. If signature FIS isn't received soon, ATA class is
2165 * assumed without follow-up softreset.
2166 */
2167 static void ahci_p5wdh_workaround(struct ata_host *host)
2168 {
2169 static struct dmi_system_id sysids[] = {
2170 {
2171 .ident = "P5W DH Deluxe",
2172 .matches = {
2173 DMI_MATCH(DMI_SYS_VENDOR,
2174 "ASUSTEK COMPUTER INC"),
2175 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2176 },
2177 },
2178 { }
2179 };
2180 struct pci_dev *pdev = to_pci_dev(host->dev);
2181
2182 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2183 dmi_check_system(sysids)) {
2184 struct ata_port *ap = host->ports[1];
2185
2186 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2187 "Deluxe on-board SIMG4726 workaround\n");
2188
2189 ap->ops = &ahci_p5wdh_ops;
2190 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2191 }
2192 }
2193
2194 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2195 {
2196 static int printed_version;
2197 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2198 const struct ata_port_info *ppi[] = { &pi, NULL };
2199 struct device *dev = &pdev->dev;
2200 struct ahci_host_priv *hpriv;
2201 struct ata_host *host;
2202 int i, rc;
2203
2204 VPRINTK("ENTER\n");
2205
2206 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2207
2208 if (!printed_version++)
2209 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2210
2211 /* acquire resources */
2212 rc = pcim_enable_device(pdev);
2213 if (rc)
2214 return rc;
2215
2216 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2217 if (rc == -EBUSY)
2218 pcim_pin_device(pdev);
2219 if (rc)
2220 return rc;
2221
2222 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2223 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2224 u8 map;
2225
2226 /* ICH6s share the same PCI ID for both piix and ahci
2227 * modes. Enabling ahci mode while MAP indicates
2228 * combined mode is a bad idea. Yield to ata_piix.
2229 */
2230 pci_read_config_byte(pdev, ICH_MAP, &map);
2231 if (map & 0x3) {
2232 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2233 "combined mode, can't enable AHCI mode\n");
2234 return -ENODEV;
2235 }
2236 }
2237
2238 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2239 if (!hpriv)
2240 return -ENOMEM;
2241 hpriv->flags |= (unsigned long)pi.private_data;
2242
2243 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2244 pci_intx(pdev, 1);
2245
2246 /* save initial config */
2247 ahci_save_initial_config(pdev, hpriv);
2248
2249 /* prepare host */
2250 if (hpriv->cap & HOST_CAP_NCQ)
2251 pi.flags |= ATA_FLAG_NCQ;
2252
2253 if (hpriv->cap & HOST_CAP_PMP)
2254 pi.flags |= ATA_FLAG_PMP;
2255
2256 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
2257 if (!host)
2258 return -ENOMEM;
2259 host->iomap = pcim_iomap_table(pdev);
2260 host->private_data = hpriv;
2261
2262 for (i = 0; i < host->n_ports; i++) {
2263 struct ata_port *ap = host->ports[i];
2264 void __iomem *port_mmio = ahci_port_base(ap);
2265
2266 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2267 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2268 0x100 + ap->port_no * 0x80, "port");
2269
2270 /* set initial link pm policy */
2271 ap->pm_policy = NOT_AVAILABLE;
2272
2273 /* standard SATA port setup */
2274 if (hpriv->port_map & (1 << i))
2275 ap->ioaddr.cmd_addr = port_mmio;
2276
2277 /* disabled/not-implemented port */
2278 else
2279 ap->ops = &ata_dummy_port_ops;
2280 }
2281
2282 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2283 ahci_p5wdh_workaround(host);
2284
2285 /* initialize adapter */
2286 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2287 if (rc)
2288 return rc;
2289
2290 rc = ahci_reset_controller(host);
2291 if (rc)
2292 return rc;
2293
2294 ahci_init_controller(host);
2295 ahci_print_info(host);
2296
2297 pci_set_master(pdev);
2298 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2299 &ahci_sht);
2300 }
2301
2302 static int __init ahci_init(void)
2303 {
2304 return pci_register_driver(&ahci_pci_driver);
2305 }
2306
2307 static void __exit ahci_exit(void)
2308 {
2309 pci_unregister_driver(&ahci_pci_driver);
2310 }
2311
2312
2313 MODULE_AUTHOR("Jeff Garzik");
2314 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2315 MODULE_LICENSE("GPL");
2316 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2317 MODULE_VERSION(DRV_VERSION);
2318
2319 module_init(ahci_init);
2320 module_exit(ahci_exit);
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