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atomic.h: add atomic64 cmpxchg, xchg and add_unless to mips
[linux-2.6/kmemtrace.git] / drivers / ata / pata_serverworks.c
blob3956ef26936d3005d601f9ad231effb3be89b83a
1 /*
2 * pata_serverworks.c - Serverworks PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon
7 *
8 * serverworks.c
9 *
10 * Copyright (C) 1998-2000 Michel Aubry
11 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
12 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
13 * Portions copyright (c) 2001 Sun Microsystems
14 *
15 *
16 * RCC/ServerWorks IDE driver for Linux
17 *
18 * OSB4: `Open South Bridge' IDE Interface (fn 1)
19 * supports UDMA mode 2 (33 MB/s)
20 *
21 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
22 * all revisions support UDMA mode 4 (66 MB/s)
23 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
24 *
25 * *** The CSB5 does not provide ANY register ***
26 * *** to detect 80-conductor cable presence. ***
27 *
28 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
29 *
30 * Documentation:
31 * Available under NDA only. Errata info very hard to get.
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <scsi/scsi_host.h>
41 #include <linux/libata.h>
42
43 #define DRV_NAME "pata_serverworks"
44 #define DRV_VERSION "0.4.0"
45
46 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
47 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
48
49 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
50 * can overrun their FIFOs when used with the CSB5 */
51
52 static const char *csb_bad_ata100[] = {
53 "ST320011A",
54 "ST340016A",
55 "ST360021A",
56 "ST380021A",
57 NULL
58 };
59
60 /**
61 * dell_cable - Dell serverworks cable detection
62 * @ap: ATA port to do cable detect
63 *
64 * Dell hide the 40/80 pin select for their interfaces in the top two
65 * bits of the subsystem ID.
66 */
67
68 static int dell_cable(struct ata_port *ap) {
69 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
70
71 if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
72 return ATA_CBL_PATA80;
73 return ATA_CBL_PATA40;
74 }
75
76 /**
77 * sun_cable - Sun Cobalt 'Alpine' cable detection
78 * @ap: ATA port to do cable select
79 *
80 * Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the
81 * subsystem ID the same as dell. We could use one function but we may
82 * need to extend the Dell one in future
83 */
84
85 static int sun_cable(struct ata_port *ap) {
86 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
87
88 if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
89 return ATA_CBL_PATA80;
90 return ATA_CBL_PATA40;
91 }
92
93 /**
94 * osb4_cable - OSB4 cable detect
95 * @ap: ATA port to check
96 *
97 * The OSB4 isn't UDMA66 capable so this is easy
98 */
99
100 static int osb4_cable(struct ata_port *ap) {
101 return ATA_CBL_PATA40;
102 }
103
104 /**
105 * csb4_cable - CSB5/6 cable detect
106 * @ap: ATA port to check
107 *
108 * Serverworks default arrangement is to use the drive side detection
109 * only.
110 */
111
112 static int csb_cable(struct ata_port *ap) {
113 return ATA_CBL_PATA80;
114 }
115
116 struct sv_cable_table {
117 int device;
118 int subvendor;
119 int (*cable_detect)(struct ata_port *ap);
120 };
121
122 /*
123 * Note that we don't copy the old serverworks code because the old
124 * code contains obvious mistakes
125 */
126
127 static struct sv_cable_table cable_detect[] = {
128 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
129 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
130 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable },
131 { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable },
132 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable },
133 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable },
134 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable },
135 { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable },
136 { }
137 };
138
139 /**
140 * serverworks_cable_detect - cable detection
141 * @ap: ATA port
142 *
143 * Perform cable detection according to the device and subvendor
144 * identifications
145 */
146
147 static int serverworks_cable_detect(struct ata_port *ap) {
148 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
149 struct sv_cable_table *cb = cable_detect;
150
151 while(cb->device) {
152 if (cb->device == pdev->device &&
153 (cb->subvendor == pdev->subsystem_vendor ||
154 cb->subvendor == PCI_ANY_ID)) {
155 return cb->cable_detect(ap);
156 }
157 cb++;
158 }
159
160 BUG();
161 return -1; /* kill compiler warning */
162 }
163
164 /**
165 * serverworks_is_csb - Check for CSB or OSB
166 * @pdev: PCI device to check
167 *
168 * Returns true if the device being checked is known to be a CSB
169 * series device.
170 */
171
172 static u8 serverworks_is_csb(struct pci_dev *pdev)
173 {
174 switch (pdev->device) {
175 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
176 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
177 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
178 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
179 return 1;
180 default:
181 break;
182 }
183 return 0;
184 }
185
186 /**
187 * serverworks_osb4_filter - mode selection filter
188 * @adev: ATA device
189 * @mask: Mask of proposed modes
190 *
191 * Filter the offered modes for the device to apply controller
192 * specific rules. OSB4 requires no UDMA for disks due to a FIFO
193 * bug we hit.
194 */
195
196 static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
197 {
198 if (adev->class == ATA_DEV_ATA)
199 mask &= ~ATA_MASK_UDMA;
200 return ata_pci_default_filter(adev, mask);
201 }
202
203
204 /**
205 * serverworks_csb_filter - mode selection filter
206 * @adev: ATA device
207 * @mask: Mask of proposed modes
208 *
209 * Check the blacklist and disable UDMA5 if matched
210 */
211
212 static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
213 {
214 const char *p;
215 char model_num[ATA_ID_PROD_LEN + 1];
216 int i;
217
218 /* Disk, UDMA */
219 if (adev->class != ATA_DEV_ATA)
220 return ata_pci_default_filter(adev, mask);
221
222 /* Actually do need to check */
223 ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
224
225 for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
226 if (!strcmp(p, model_num))
227 mask &= ~(0x1F << ATA_SHIFT_UDMA);
228 }
229 return ata_pci_default_filter(adev, mask);
230 }
231
232
233 /**
234 * serverworks_set_piomode - set initial PIO mode data
235 * @ap: ATA interface
236 * @adev: ATA device
237 *
238 * Program the OSB4/CSB5 timing registers for PIO. The PIO register
239 * load is done as a simple lookup.
240 */
241 static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
242 {
243 static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
244 int offset = 1 + (2 * ap->port_no) - adev->devno;
245 int devbits = (2 * ap->port_no + adev->devno) * 4;
246 u16 csb5_pio;
247 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
248 int pio = adev->pio_mode - XFER_PIO_0;
249
250 pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
251
252 /* The OSB4 just requires the timing but the CSB series want the
253 mode number as well */
254 if (serverworks_is_csb(pdev)) {
255 pci_read_config_word(pdev, 0x4A, &csb5_pio);
256 csb5_pio &= ~(0x0F << devbits);
257 pci_write_config_byte(pdev, 0x4A, csb5_pio | (pio << devbits));
258 }
259 }
260
261 /**
262 * serverworks_set_dmamode - set initial DMA mode data
263 * @ap: ATA interface
264 * @adev: ATA device
265 *
266 * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
267 * chipset. The MWDMA mode values are pulled from a lookup table
268 * while the chipset uses mode number for UDMA.
269 */
270
271 static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
272 {
273 static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
274 int offset = 1 + 2 * ap->port_no - adev->devno;
275 int devbits = (2 * ap->port_no + adev->devno);
276 u8 ultra;
277 u8 ultra_cfg;
278 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
279
280 pci_read_config_byte(pdev, 0x54, &ultra_cfg);
281
282 if (adev->dma_mode >= XFER_UDMA_0) {
283 pci_write_config_byte(pdev, 0x44 + offset, 0x20);
284
285 pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
286 ultra &= ~(0x0F << (ap->port_no * 4));
287 ultra |= (adev->dma_mode - XFER_UDMA_0)
288 << (ap->port_no * 4);
289 pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
290
291 ultra_cfg |= (1 << devbits);
292 } else {
293 pci_write_config_byte(pdev, 0x44 + offset,
294 dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
295 ultra_cfg &= ~(1 << devbits);
296 }
297 pci_write_config_byte(pdev, 0x54, ultra_cfg);
298 }
299
300 static struct scsi_host_template serverworks_sht = {
301 .module = THIS_MODULE,
302 .name = DRV_NAME,
303 .ioctl = ata_scsi_ioctl,
304 .queuecommand = ata_scsi_queuecmd,
305 .can_queue = ATA_DEF_QUEUE,
306 .this_id = ATA_SHT_THIS_ID,
307 .sg_tablesize = LIBATA_MAX_PRD,
308 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
309 .emulated = ATA_SHT_EMULATED,
310 .use_clustering = ATA_SHT_USE_CLUSTERING,
311 .proc_name = DRV_NAME,
312 .dma_boundary = ATA_DMA_BOUNDARY,
313 .slave_configure = ata_scsi_slave_config,
314 .slave_destroy = ata_scsi_slave_destroy,
315 .bios_param = ata_std_bios_param,
316 #ifdef CONFIG_PM
317 .resume = ata_scsi_device_resume,
318 .suspend = ata_scsi_device_suspend,
319 #endif
320 };
321
322 static struct ata_port_operations serverworks_osb4_port_ops = {
323 .port_disable = ata_port_disable,
324 .set_piomode = serverworks_set_piomode,
325 .set_dmamode = serverworks_set_dmamode,
326 .mode_filter = serverworks_osb4_filter,
327
328 .tf_load = ata_tf_load,
329 .tf_read = ata_tf_read,
330 .check_status = ata_check_status,
331 .exec_command = ata_exec_command,
332 .dev_select = ata_std_dev_select,
333
334 .freeze = ata_bmdma_freeze,
335 .thaw = ata_bmdma_thaw,
336 .error_handler = ata_bmdma_error_handler,
337 .post_internal_cmd = ata_bmdma_post_internal_cmd,
338 .cable_detect = serverworks_cable_detect,
339
340 .bmdma_setup = ata_bmdma_setup,
341 .bmdma_start = ata_bmdma_start,
342 .bmdma_stop = ata_bmdma_stop,
343 .bmdma_status = ata_bmdma_status,
344
345 .qc_prep = ata_qc_prep,
346 .qc_issue = ata_qc_issue_prot,
347
348 .data_xfer = ata_data_xfer,
349
350 .irq_handler = ata_interrupt,
351 .irq_clear = ata_bmdma_irq_clear,
352 .irq_on = ata_irq_on,
353 .irq_ack = ata_irq_ack,
354
355 .port_start = ata_port_start,
356 };
357
358 static struct ata_port_operations serverworks_csb_port_ops = {
359 .port_disable = ata_port_disable,
360 .set_piomode = serverworks_set_piomode,
361 .set_dmamode = serverworks_set_dmamode,
362 .mode_filter = serverworks_csb_filter,
363
364 .tf_load = ata_tf_load,
365 .tf_read = ata_tf_read,
366 .check_status = ata_check_status,
367 .exec_command = ata_exec_command,
368 .dev_select = ata_std_dev_select,
369
370 .freeze = ata_bmdma_freeze,
371 .thaw = ata_bmdma_thaw,
372 .error_handler = ata_bmdma_error_handler,
373 .post_internal_cmd = ata_bmdma_post_internal_cmd,
374 .cable_detect = serverworks_cable_detect,
375
376 .bmdma_setup = ata_bmdma_setup,
377 .bmdma_start = ata_bmdma_start,
378 .bmdma_stop = ata_bmdma_stop,
379 .bmdma_status = ata_bmdma_status,
380
381 .qc_prep = ata_qc_prep,
382 .qc_issue = ata_qc_issue_prot,
383
384 .data_xfer = ata_data_xfer,
385
386 .irq_handler = ata_interrupt,
387 .irq_clear = ata_bmdma_irq_clear,
388 .irq_on = ata_irq_on,
389 .irq_ack = ata_irq_ack,
390
391 .port_start = ata_port_start,
392 };
393
394 static int serverworks_fixup_osb4(struct pci_dev *pdev)
395 {
396 u32 reg;
397 struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
398 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
399 if (isa_dev) {
400 pci_read_config_dword(isa_dev, 0x64, &reg);
401 reg &= ~0x00002000; /* disable 600ns interrupt mask */
402 if (!(reg & 0x00004000))
403 printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
404 reg |= 0x00004000; /* enable UDMA/33 support */
405 pci_write_config_dword(isa_dev, 0x64, reg);
406 pci_dev_put(isa_dev);
407 return 0;
408 }
409 printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n");
410 return -ENODEV;
411 }
412
413 static int serverworks_fixup_csb(struct pci_dev *pdev)
414 {
415 u8 rev;
416 u8 btr;
417
418 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
419
420 /* Third Channel Test */
421 if (!(PCI_FUNC(pdev->devfn) & 1)) {
422 struct pci_dev * findev = NULL;
423 u32 reg4c = 0;
424 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
425 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
426 if (findev) {
427 pci_read_config_dword(findev, 0x4C, &reg4c);
428 reg4c &= ~0x000007FF;
429 reg4c |= 0x00000040;
430 reg4c |= 0x00000020;
431 pci_write_config_dword(findev, 0x4C, reg4c);
432 pci_dev_put(findev);
433 }
434 } else {
435 struct pci_dev * findev = NULL;
436 u8 reg41 = 0;
437
438 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
439 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
440 if (findev) {
441 pci_read_config_byte(findev, 0x41, &reg41);
442 reg41 &= ~0x40;
443 pci_write_config_byte(findev, 0x41, reg41);
444 pci_dev_put(findev);
445 }
446 }
447 /* setup the UDMA Control register
448 *
449 * 1. clear bit 6 to enable DMA
450 * 2. enable DMA modes with bits 0-1
451 * 00 : legacy
452 * 01 : udma2
453 * 10 : udma2/udma4
454 * 11 : udma2/udma4/udma5
455 */
456 pci_read_config_byte(pdev, 0x5A, &btr);
457 btr &= ~0x40;
458 if (!(PCI_FUNC(pdev->devfn) & 1))
459 btr |= 0x2;
460 else
461 btr |= (rev >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
462 pci_write_config_byte(pdev, 0x5A, btr);
463
464 return btr;
465 }
466
467 static void serverworks_fixup_ht1000(struct pci_dev *pdev)
468 {
469 u8 btr;
470 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
471 pci_read_config_byte(pdev, 0x5A, &btr);
472 btr &= ~0x40;
473 btr |= 0x3;
474 pci_write_config_byte(pdev, 0x5A, btr);
475 }
476
477
478 static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
479 {
480 int ports = 2;
481 static struct ata_port_info info[4] = {
482 { /* OSB4 */
483 .sht = &serverworks_sht,
484 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
485 .pio_mask = 0x1f,
486 .mwdma_mask = 0x07,
487 .udma_mask = 0x07,
488 .port_ops = &serverworks_osb4_port_ops
489 }, { /* OSB4 no UDMA */
490 .sht = &serverworks_sht,
491 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
492 .pio_mask = 0x1f,
493 .mwdma_mask = 0x07,
494 .udma_mask = 0x00,
495 .port_ops = &serverworks_osb4_port_ops
496 }, { /* CSB5 */
497 .sht = &serverworks_sht,
498 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
499 .pio_mask = 0x1f,
500 .mwdma_mask = 0x07,
501 .udma_mask = 0x1f,
502 .port_ops = &serverworks_csb_port_ops
503 }, { /* CSB5 - later revisions*/
504 .sht = &serverworks_sht,
505 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
506 .pio_mask = 0x1f,
507 .mwdma_mask = 0x07,
508 .udma_mask = 0x3f,
509 .port_ops = &serverworks_csb_port_ops
510 }
511 };
512 static struct ata_port_info *port_info[2];
513 struct ata_port_info *devinfo = &info[id->driver_data];
514
515 /* Force master latency timer to 64 PCI clocks */
516 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
517
518 /* OSB4 : South Bridge and IDE */
519 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
520 /* Select non UDMA capable OSB4 if we can't do fixups */
521 if ( serverworks_fixup_osb4(pdev) < 0)
522 devinfo = &info[1];
523 }
524 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
525 else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
526 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
527 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
528
529 /* If the returned btr is the newer revision then
530 select the right info block */
531 if (serverworks_fixup_csb(pdev) == 3)
532 devinfo = &info[3];
533
534 /* Is this the 3rd channel CSB6 IDE ? */
535 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
536 ports = 1;
537 }
538 /* setup HT1000E */
539 else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
540 serverworks_fixup_ht1000(pdev);
541
542 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
543 ata_pci_clear_simplex(pdev);
544
545 port_info[0] = port_info[1] = devinfo;
546 return ata_pci_init_one(pdev, port_info, ports);
547 }
548
549 #ifdef CONFIG_PM
550 static int serverworks_reinit_one(struct pci_dev *pdev)
551 {
552 /* Force master latency timer to 64 PCI clocks */
553 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
554
555 switch (pdev->device)
556 {
557 case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
558 serverworks_fixup_osb4(pdev);
559 break;
560 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
561 ata_pci_clear_simplex(pdev);
562 /* fall through */
563 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
564 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
565 serverworks_fixup_csb(pdev);
566 break;
567 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
568 serverworks_fixup_ht1000(pdev);
569 break;
570 }
571 return ata_pci_device_resume(pdev);
572 }
573 #endif
574
575 static const struct pci_device_id serverworks[] = {
576 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
577 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
578 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
579 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
580 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
581
582 { },
583 };
584
585 static struct pci_driver serverworks_pci_driver = {
586 .name = DRV_NAME,
587 .id_table = serverworks,
588 .probe = serverworks_init_one,
589 .remove = ata_pci_remove_one,
590 #ifdef CONFIG_PM
591 .suspend = ata_pci_device_suspend,
592 .resume = serverworks_reinit_one,
593 #endif
594 };
595
596 static int __init serverworks_init(void)
597 {
598 return pci_register_driver(&serverworks_pci_driver);
599 }
600
601 static void __exit serverworks_exit(void)
602 {
603 pci_unregister_driver(&serverworks_pci_driver);
604 }
605
606 MODULE_AUTHOR("Alan Cox");
607 MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
608 MODULE_LICENSE("GPL");
609 MODULE_DEVICE_TABLE(pci, serverworks);
610 MODULE_VERSION(DRV_VERSION);
611
612 module_init(serverworks_init);
613 module_exit(serverworks_exit);
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