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[PATCH] clean up computone remaining cli use
[linux-2.6/kmemtrace.git] / drivers / char / drm / radeon_drv.h
blobd92ccee3e54c64b29c9bbc7fcc4b1973386d3644
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 /* General customization:
35 */
36
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20050911"
42
43 /* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading)
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 */
92 #define DRIVER_MAJOR 1
93 #define DRIVER_MINOR 19
94 #define DRIVER_PATCHLEVEL 0
95
96 #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
97 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
98
99 /*
100 * Radeon chip families
101 */
102 enum radeon_family {
103 CHIP_R100,
104 CHIP_RS100,
105 CHIP_RV100,
106 CHIP_R200,
107 CHIP_RV200,
108 CHIP_RS200,
109 CHIP_R250,
110 CHIP_RS250,
111 CHIP_RV250,
112 CHIP_RV280,
113 CHIP_R300,
114 CHIP_RS300,
115 CHIP_R350,
116 CHIP_RV350,
117 CHIP_R420,
118 CHIP_LAST,
119 };
120
121 enum radeon_cp_microcode_version {
122 UCODE_R100,
123 UCODE_R200,
124 UCODE_R300,
125 };
126
127 /*
128 * Chip flags
129 */
130 enum radeon_chip_flags {
131 CHIP_FAMILY_MASK = 0x0000ffffUL,
132 CHIP_FLAGS_MASK = 0xffff0000UL,
133 CHIP_IS_MOBILITY = 0x00010000UL,
134 CHIP_IS_IGP = 0x00020000UL,
135 CHIP_SINGLE_CRTC = 0x00040000UL,
136 CHIP_IS_AGP = 0x00080000UL,
137 CHIP_HAS_HIERZ = 0x00100000UL,
138 CHIP_IS_PCIE = 0x00200000UL,
139 };
140
141 typedef struct drm_radeon_freelist {
142 unsigned int age;
143 drm_buf_t *buf;
144 struct drm_radeon_freelist *next;
145 struct drm_radeon_freelist *prev;
146 } drm_radeon_freelist_t;
147
148 typedef struct drm_radeon_ring_buffer {
149 u32 *start;
150 u32 *end;
151 int size;
152 int size_l2qw;
153
154 u32 tail;
155 u32 tail_mask;
156 int space;
157
158 int high_mark;
159 } drm_radeon_ring_buffer_t;
160
161 typedef struct drm_radeon_depth_clear_t {
162 u32 rb3d_cntl;
163 u32 rb3d_zstencilcntl;
164 u32 se_cntl;
165 } drm_radeon_depth_clear_t;
166
167 struct drm_radeon_driver_file_fields {
168 int64_t radeon_fb_delta;
169 };
170
171 struct mem_block {
172 struct mem_block *next;
173 struct mem_block *prev;
174 int start;
175 int size;
176 DRMFILE filp; /* 0: free, -1: heap, other: real files */
177 };
178
179 struct radeon_surface {
180 int refcount;
181 u32 lower;
182 u32 upper;
183 u32 flags;
184 };
185
186 struct radeon_virt_surface {
187 int surface_index;
188 u32 lower;
189 u32 upper;
190 u32 flags;
191 DRMFILE filp;
192 };
193
194 typedef struct drm_radeon_private {
195 drm_radeon_ring_buffer_t ring;
196 drm_radeon_sarea_t *sarea_priv;
197
198 u32 fb_location;
199
200 int gart_size;
201 u32 gart_vm_start;
202 unsigned long gart_buffers_offset;
203
204 int cp_mode;
205 int cp_running;
206
207 drm_radeon_freelist_t *head;
208 drm_radeon_freelist_t *tail;
209 int last_buf;
210 volatile u32 *scratch;
211 int writeback_works;
212
213 int usec_timeout;
214
215 int microcode_version;
216
217 struct {
218 u32 boxes;
219 int freelist_timeouts;
220 int freelist_loops;
221 int requested_bufs;
222 int last_frame_reads;
223 int last_clear_reads;
224 int clears;
225 int texture_uploads;
226 } stats;
227
228 int do_boxes;
229 int page_flipping;
230 int current_page;
231
232 u32 color_fmt;
233 unsigned int front_offset;
234 unsigned int front_pitch;
235 unsigned int back_offset;
236 unsigned int back_pitch;
237
238 u32 depth_fmt;
239 unsigned int depth_offset;
240 unsigned int depth_pitch;
241
242 u32 front_pitch_offset;
243 u32 back_pitch_offset;
244 u32 depth_pitch_offset;
245
246 drm_radeon_depth_clear_t depth_clear;
247
248 unsigned long fb_offset;
249 unsigned long mmio_offset;
250 unsigned long ring_offset;
251 unsigned long ring_rptr_offset;
252 unsigned long buffers_offset;
253 unsigned long gart_textures_offset;
254
255 drm_local_map_t *sarea;
256 drm_local_map_t *mmio;
257 drm_local_map_t *cp_ring;
258 drm_local_map_t *ring_rptr;
259 drm_local_map_t *gart_textures;
260
261 struct mem_block *gart_heap;
262 struct mem_block *fb_heap;
263
264 /* SW interrupt */
265 wait_queue_head_t swi_queue;
266 atomic_t swi_emitted;
267
268 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
269 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
270
271 unsigned long pcigart_offset;
272 drm_ati_pcigart_info gart_info;
273
274 /* starting from here on, data is preserved accross an open */
275 uint32_t flags; /* see radeon_chip_flags */
276 int is_pci;
277 } drm_radeon_private_t;
278
279 typedef struct drm_radeon_buf_priv {
280 u32 age;
281 } drm_radeon_buf_priv_t;
282
283 typedef struct drm_radeon_kcmd_buffer {
284 int bufsz;
285 char *buf;
286 int nbox;
287 drm_clip_rect_t __user *boxes;
288 } drm_radeon_kcmd_buffer_t;
289
290 extern int radeon_no_wb;
291 extern drm_ioctl_desc_t radeon_ioctls[];
292 extern int radeon_max_ioctl;
293
294 /* radeon_cp.c */
295 extern int radeon_cp_init(DRM_IOCTL_ARGS);
296 extern int radeon_cp_start(DRM_IOCTL_ARGS);
297 extern int radeon_cp_stop(DRM_IOCTL_ARGS);
298 extern int radeon_cp_reset(DRM_IOCTL_ARGS);
299 extern int radeon_cp_idle(DRM_IOCTL_ARGS);
300 extern int radeon_cp_resume(DRM_IOCTL_ARGS);
301 extern int radeon_engine_reset(DRM_IOCTL_ARGS);
302 extern int radeon_fullscreen(DRM_IOCTL_ARGS);
303 extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
304
305 extern void radeon_freelist_reset(drm_device_t * dev);
306 extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
307
308 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
309
310 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
311
312 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
313 extern int radeon_presetup(struct drm_device *dev);
314 extern int radeon_driver_postcleanup(struct drm_device *dev);
315
316 extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
317 extern int radeon_mem_free(DRM_IOCTL_ARGS);
318 extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
319 extern void radeon_mem_takedown(struct mem_block **heap);
320 extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
321
322 /* radeon_irq.c */
323 extern int radeon_irq_emit(DRM_IOCTL_ARGS);
324 extern int radeon_irq_wait(DRM_IOCTL_ARGS);
325
326 extern void radeon_do_release(drm_device_t * dev);
327 extern int radeon_driver_vblank_wait(drm_device_t * dev,
328 unsigned int *sequence);
329 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
330 extern void radeon_driver_irq_preinstall(drm_device_t * dev);
331 extern void radeon_driver_irq_postinstall(drm_device_t * dev);
332 extern void radeon_driver_irq_uninstall(drm_device_t * dev);
333 extern void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp);
334 extern void radeon_driver_pretakedown(drm_device_t * dev);
335 extern int radeon_driver_open_helper(drm_device_t * dev,
336 drm_file_t * filp_priv);
337 extern void radeon_driver_free_filp_priv(drm_device_t * dev,
338 drm_file_t * filp_priv);
339
340 extern int radeon_preinit(struct drm_device *dev, unsigned long flags);
341 extern int radeon_postinit(struct drm_device *dev, unsigned long flags);
342 extern int radeon_postcleanup(struct drm_device *dev);
343
344 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
345 unsigned long arg);
346
347 /* r300_cmdbuf.c */
348 extern void r300_init_reg_flags(void);
349
350 extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
351 drm_file_t * filp_priv,
352 drm_radeon_kcmd_buffer_t * cmdbuf);
353
354 /* Flags for stats.boxes
355 */
356 #define RADEON_BOX_DMA_IDLE 0x1
357 #define RADEON_BOX_RING_FULL 0x2
358 #define RADEON_BOX_FLIP 0x4
359 #define RADEON_BOX_WAIT_IDLE 0x8
360 #define RADEON_BOX_TEXTURE_LOAD 0x10
361
362 /* Register definitions, register access macros and drmAddMap constants
363 * for Radeon kernel driver.
364 */
365
366 #define RADEON_AGP_COMMAND 0x0f60
367 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
368 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
369 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
370 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
371 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
372 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
373 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
374
375 #define RADEON_BUS_CNTL 0x0030
376 # define RADEON_BUS_MASTER_DIS (1 << 6)
377
378 #define RADEON_CLOCK_CNTL_DATA 0x000c
379 # define RADEON_PLL_WR_EN (1 << 7)
380 #define RADEON_CLOCK_CNTL_INDEX 0x0008
381 #define RADEON_CONFIG_APER_SIZE 0x0108
382 #define RADEON_CONFIG_MEMSIZE 0x00f8
383 #define RADEON_CRTC_OFFSET 0x0224
384 #define RADEON_CRTC_OFFSET_CNTL 0x0228
385 # define RADEON_CRTC_TILE_EN (1 << 15)
386 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
387 #define RADEON_CRTC2_OFFSET 0x0324
388 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
389
390 #define RADEON_PCIE_INDEX 0x0030
391 #define RADEON_PCIE_DATA 0x0034
392 #define RADEON_PCIE_TX_GART_CNTL 0x10
393 # define RADEON_PCIE_TX_GART_EN (1 << 0)
394 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
395 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
396 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
397 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
398 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
399 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
400 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
401 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
402 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
403 #define RADEON_PCIE_TX_GART_BASE 0x13
404 #define RADEON_PCIE_TX_GART_START_LO 0x14
405 #define RADEON_PCIE_TX_GART_START_HI 0x15
406 #define RADEON_PCIE_TX_GART_END_LO 0x16
407 #define RADEON_PCIE_TX_GART_END_HI 0x17
408
409 #define RADEON_MPP_TB_CONFIG 0x01c0
410 #define RADEON_MEM_CNTL 0x0140
411 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
412 #define RADEON_AGP_BASE 0x0170
413
414 #define RADEON_RB3D_COLOROFFSET 0x1c40
415 #define RADEON_RB3D_COLORPITCH 0x1c48
416
417 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
418 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
419 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
420 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
421 # define RADEON_GMC_BRUSH_NONE (15 << 4)
422 # define RADEON_GMC_DST_16BPP (4 << 8)
423 # define RADEON_GMC_DST_24BPP (5 << 8)
424 # define RADEON_GMC_DST_32BPP (6 << 8)
425 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
426 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
427 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
428 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
429 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
430 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
431 # define RADEON_ROP3_S 0x00cc0000
432 # define RADEON_ROP3_P 0x00f00000
433 #define RADEON_DP_WRITE_MASK 0x16cc
434 #define RADEON_DST_PITCH_OFFSET 0x142c
435 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
436 # define RADEON_DST_TILE_LINEAR (0 << 30)
437 # define RADEON_DST_TILE_MACRO (1 << 30)
438 # define RADEON_DST_TILE_MICRO (2 << 30)
439 # define RADEON_DST_TILE_BOTH (3 << 30)
440
441 #define RADEON_SCRATCH_REG0 0x15e0
442 #define RADEON_SCRATCH_REG1 0x15e4
443 #define RADEON_SCRATCH_REG2 0x15e8
444 #define RADEON_SCRATCH_REG3 0x15ec
445 #define RADEON_SCRATCH_REG4 0x15f0
446 #define RADEON_SCRATCH_REG5 0x15f4
447 #define RADEON_SCRATCH_UMSK 0x0770
448 #define RADEON_SCRATCH_ADDR 0x0774
449
450 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
451
452 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
453 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
454 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
455
456 #define RADEON_GEN_INT_CNTL 0x0040
457 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
458 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
459 # define RADEON_SW_INT_ENABLE (1 << 25)
460
461 #define RADEON_GEN_INT_STATUS 0x0044
462 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
463 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
464 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
465 # define RADEON_SW_INT_TEST (1 << 25)
466 # define RADEON_SW_INT_TEST_ACK (1 << 25)
467 # define RADEON_SW_INT_FIRE (1 << 26)
468
469 #define RADEON_HOST_PATH_CNTL 0x0130
470 # define RADEON_HDP_SOFT_RESET (1 << 26)
471 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
472 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
473
474 #define RADEON_ISYNC_CNTL 0x1724
475 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
476 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
477 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
478 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
479 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
480 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
481
482 #define RADEON_RBBM_GUICNTL 0x172c
483 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
484 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
485 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
486 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
487
488 #define RADEON_MC_AGP_LOCATION 0x014c
489 #define RADEON_MC_FB_LOCATION 0x0148
490 #define RADEON_MCLK_CNTL 0x0012
491 # define RADEON_FORCEON_MCLKA (1 << 16)
492 # define RADEON_FORCEON_MCLKB (1 << 17)
493 # define RADEON_FORCEON_YCLKA (1 << 18)
494 # define RADEON_FORCEON_YCLKB (1 << 19)
495 # define RADEON_FORCEON_MC (1 << 20)
496 # define RADEON_FORCEON_AIC (1 << 21)
497
498 #define RADEON_PP_BORDER_COLOR_0 0x1d40
499 #define RADEON_PP_BORDER_COLOR_1 0x1d44
500 #define RADEON_PP_BORDER_COLOR_2 0x1d48
501 #define RADEON_PP_CNTL 0x1c38
502 # define RADEON_SCISSOR_ENABLE (1 << 1)
503 #define RADEON_PP_LUM_MATRIX 0x1d00
504 #define RADEON_PP_MISC 0x1c14
505 #define RADEON_PP_ROT_MATRIX_0 0x1d58
506 #define RADEON_PP_TXFILTER_0 0x1c54
507 #define RADEON_PP_TXOFFSET_0 0x1c5c
508 #define RADEON_PP_TXFILTER_1 0x1c6c
509 #define RADEON_PP_TXFILTER_2 0x1c84
510
511 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
512 # define RADEON_RB2D_DC_FLUSH (3 << 0)
513 # define RADEON_RB2D_DC_FREE (3 << 2)
514 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
515 # define RADEON_RB2D_DC_BUSY (1 << 31)
516 #define RADEON_RB3D_CNTL 0x1c3c
517 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
518 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
519 # define RADEON_DITHER_ENABLE (1 << 2)
520 # define RADEON_ROUND_ENABLE (1 << 3)
521 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
522 # define RADEON_DITHER_INIT (1 << 5)
523 # define RADEON_ROP_ENABLE (1 << 6)
524 # define RADEON_STENCIL_ENABLE (1 << 7)
525 # define RADEON_Z_ENABLE (1 << 8)
526 # define RADEON_ZBLOCK16 (1 << 15)
527 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
528 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
529 #define RADEON_RB3D_DEPTHPITCH 0x1c28
530 #define RADEON_RB3D_PLANEMASK 0x1d84
531 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
532 #define RADEON_RB3D_ZCACHE_MODE 0x3250
533 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
534 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
535 # define RADEON_RB3D_ZC_FREE (1 << 2)
536 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
537 # define RADEON_RB3D_ZC_BUSY (1 << 31)
538 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
539 # define RADEON_Z_TEST_MASK (7 << 4)
540 # define RADEON_Z_TEST_ALWAYS (7 << 4)
541 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
542 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
543 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
544 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
545 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
546 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
547 # define RADEON_FORCE_Z_DIRTY (1 << 29)
548 # define RADEON_Z_WRITE_ENABLE (1 << 30)
549 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
550 #define RADEON_RBBM_SOFT_RESET 0x00f0
551 # define RADEON_SOFT_RESET_CP (1 << 0)
552 # define RADEON_SOFT_RESET_HI (1 << 1)
553 # define RADEON_SOFT_RESET_SE (1 << 2)
554 # define RADEON_SOFT_RESET_RE (1 << 3)
555 # define RADEON_SOFT_RESET_PP (1 << 4)
556 # define RADEON_SOFT_RESET_E2 (1 << 5)
557 # define RADEON_SOFT_RESET_RB (1 << 6)
558 # define RADEON_SOFT_RESET_HDP (1 << 7)
559 #define RADEON_RBBM_STATUS 0x0e40
560 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
561 # define RADEON_RBBM_ACTIVE (1 << 31)
562 #define RADEON_RE_LINE_PATTERN 0x1cd0
563 #define RADEON_RE_MISC 0x26c4
564 #define RADEON_RE_TOP_LEFT 0x26c0
565 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
566 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
567 #define RADEON_RE_STIPPLE_DATA 0x1ccc
568
569 #define RADEON_SCISSOR_TL_0 0x1cd8
570 #define RADEON_SCISSOR_BR_0 0x1cdc
571 #define RADEON_SCISSOR_TL_1 0x1ce0
572 #define RADEON_SCISSOR_BR_1 0x1ce4
573 #define RADEON_SCISSOR_TL_2 0x1ce8
574 #define RADEON_SCISSOR_BR_2 0x1cec
575 #define RADEON_SE_COORD_FMT 0x1c50
576 #define RADEON_SE_CNTL 0x1c4c
577 # define RADEON_FFACE_CULL_CW (0 << 0)
578 # define RADEON_BFACE_SOLID (3 << 1)
579 # define RADEON_FFACE_SOLID (3 << 3)
580 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
581 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
582 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
583 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
584 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
585 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
586 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
587 # define RADEON_FOG_SHADE_FLAT (1 << 14)
588 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
589 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
590 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
591 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
592 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
593 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
594 #define RADEON_SE_CNTL_STATUS 0x2140
595 #define RADEON_SE_LINE_WIDTH 0x1db8
596 #define RADEON_SE_VPORT_XSCALE 0x1d98
597 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
598 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
599 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
600 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
601 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
602 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
603 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
604 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
605 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
606 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
607 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
608 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
609 #define RADEON_SURFACE_CNTL 0x0b00
610 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
611 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
612 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
613 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
614 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
615 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
616 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
617 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
618 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
619 #define RADEON_SURFACE0_INFO 0x0b0c
620 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
621 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
622 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
623 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
624 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
625 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
626 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
627 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
628 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
629 #define RADEON_SURFACE1_INFO 0x0b1c
630 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
631 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
632 #define RADEON_SURFACE2_INFO 0x0b2c
633 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
634 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
635 #define RADEON_SURFACE3_INFO 0x0b3c
636 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
637 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
638 #define RADEON_SURFACE4_INFO 0x0b4c
639 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
640 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
641 #define RADEON_SURFACE5_INFO 0x0b5c
642 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
643 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
644 #define RADEON_SURFACE6_INFO 0x0b6c
645 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
646 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
647 #define RADEON_SURFACE7_INFO 0x0b7c
648 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
649 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
650 #define RADEON_SW_SEMAPHORE 0x013c
651
652 #define RADEON_WAIT_UNTIL 0x1720
653 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
654 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
655 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
656 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
657
658 #define RADEON_RB3D_ZMASKOFFSET 0x3234
659 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
660 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
661 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
662
663 /* CP registers */
664 #define RADEON_CP_ME_RAM_ADDR 0x07d4
665 #define RADEON_CP_ME_RAM_RADDR 0x07d8
666 #define RADEON_CP_ME_RAM_DATAH 0x07dc
667 #define RADEON_CP_ME_RAM_DATAL 0x07e0
668
669 #define RADEON_CP_RB_BASE 0x0700
670 #define RADEON_CP_RB_CNTL 0x0704
671 # define RADEON_BUF_SWAP_32BIT (2 << 16)
672 #define RADEON_CP_RB_RPTR_ADDR 0x070c
673 #define RADEON_CP_RB_RPTR 0x0710
674 #define RADEON_CP_RB_WPTR 0x0714
675
676 #define RADEON_CP_RB_WPTR_DELAY 0x0718
677 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
678 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
679
680 #define RADEON_CP_IB_BASE 0x0738
681
682 #define RADEON_CP_CSQ_CNTL 0x0740
683 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
684 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
685 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
686 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
687 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
688 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
689 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
690
691 #define RADEON_AIC_CNTL 0x01d0
692 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
693 #define RADEON_AIC_STAT 0x01d4
694 #define RADEON_AIC_PT_BASE 0x01d8
695 #define RADEON_AIC_LO_ADDR 0x01dc
696 #define RADEON_AIC_HI_ADDR 0x01e0
697 #define RADEON_AIC_TLB_ADDR 0x01e4
698 #define RADEON_AIC_TLB_DATA 0x01e8
699
700 /* CP command packets */
701 #define RADEON_CP_PACKET0 0x00000000
702 # define RADEON_ONE_REG_WR (1 << 15)
703 #define RADEON_CP_PACKET1 0x40000000
704 #define RADEON_CP_PACKET2 0x80000000
705 #define RADEON_CP_PACKET3 0xC0000000
706 # define RADEON_CP_NOP 0x00001000
707 # define RADEON_CP_NEXT_CHAR 0x00001900
708 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
709 # define RADEON_CP_SET_SCISSORS 0x00001E00
710 /* GEN_INDX_PRIM is unsupported starting with R300 */
711 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
712 # define RADEON_WAIT_FOR_IDLE 0x00002600
713 # define RADEON_3D_DRAW_VBUF 0x00002800
714 # define RADEON_3D_DRAW_IMMD 0x00002900
715 # define RADEON_3D_DRAW_INDX 0x00002A00
716 # define RADEON_CP_LOAD_PALETTE 0x00002C00
717 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
718 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
719 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
720 # define RADEON_3D_CLEAR_ZMASK 0x00003200
721 # define RADEON_CP_INDX_BUFFER 0x00003300
722 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
723 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
724 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
725 # define RADEON_3D_CLEAR_HIZ 0x00003700
726 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
727 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
728 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
729 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
730 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
731
732 #define RADEON_CP_PACKET_MASK 0xC0000000
733 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
734 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
735 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
736 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
737
738 #define RADEON_VTX_Z_PRESENT (1 << 31)
739 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
740
741 #define RADEON_PRIM_TYPE_NONE (0 << 0)
742 #define RADEON_PRIM_TYPE_POINT (1 << 0)
743 #define RADEON_PRIM_TYPE_LINE (2 << 0)
744 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
745 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
746 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
747 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
748 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
749 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
750 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
751 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
752 #define RADEON_PRIM_TYPE_MASK 0xf
753 #define RADEON_PRIM_WALK_IND (1 << 4)
754 #define RADEON_PRIM_WALK_LIST (2 << 4)
755 #define RADEON_PRIM_WALK_RING (3 << 4)
756 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
757 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
758 #define RADEON_MAOS_ENABLE (1 << 7)
759 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
760 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
761 #define RADEON_NUM_VERTICES_SHIFT 16
762
763 #define RADEON_COLOR_FORMAT_CI8 2
764 #define RADEON_COLOR_FORMAT_ARGB1555 3
765 #define RADEON_COLOR_FORMAT_RGB565 4
766 #define RADEON_COLOR_FORMAT_ARGB8888 6
767 #define RADEON_COLOR_FORMAT_RGB332 7
768 #define RADEON_COLOR_FORMAT_RGB8 9
769 #define RADEON_COLOR_FORMAT_ARGB4444 15
770
771 #define RADEON_TXFORMAT_I8 0
772 #define RADEON_TXFORMAT_AI88 1
773 #define RADEON_TXFORMAT_RGB332 2
774 #define RADEON_TXFORMAT_ARGB1555 3
775 #define RADEON_TXFORMAT_RGB565 4
776 #define RADEON_TXFORMAT_ARGB4444 5
777 #define RADEON_TXFORMAT_ARGB8888 6
778 #define RADEON_TXFORMAT_RGBA8888 7
779 #define RADEON_TXFORMAT_Y8 8
780 #define RADEON_TXFORMAT_VYUY422 10
781 #define RADEON_TXFORMAT_YVYU422 11
782 #define RADEON_TXFORMAT_DXT1 12
783 #define RADEON_TXFORMAT_DXT23 14
784 #define RADEON_TXFORMAT_DXT45 15
785
786 #define R200_PP_TXCBLEND_0 0x2f00
787 #define R200_PP_TXCBLEND_1 0x2f10
788 #define R200_PP_TXCBLEND_2 0x2f20
789 #define R200_PP_TXCBLEND_3 0x2f30
790 #define R200_PP_TXCBLEND_4 0x2f40
791 #define R200_PP_TXCBLEND_5 0x2f50
792 #define R200_PP_TXCBLEND_6 0x2f60
793 #define R200_PP_TXCBLEND_7 0x2f70
794 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
795 #define R200_PP_TFACTOR_0 0x2ee0
796 #define R200_SE_VTX_FMT_0 0x2088
797 #define R200_SE_VAP_CNTL 0x2080
798 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
799 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
800 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
801 #define R200_PP_TXFILTER_5 0x2ca0
802 #define R200_PP_TXFILTER_4 0x2c80
803 #define R200_PP_TXFILTER_3 0x2c60
804 #define R200_PP_TXFILTER_2 0x2c40
805 #define R200_PP_TXFILTER_1 0x2c20
806 #define R200_PP_TXFILTER_0 0x2c00
807 #define R200_PP_TXOFFSET_5 0x2d78
808 #define R200_PP_TXOFFSET_4 0x2d60
809 #define R200_PP_TXOFFSET_3 0x2d48
810 #define R200_PP_TXOFFSET_2 0x2d30
811 #define R200_PP_TXOFFSET_1 0x2d18
812 #define R200_PP_TXOFFSET_0 0x2d00
813
814 #define R200_PP_CUBIC_FACES_0 0x2c18
815 #define R200_PP_CUBIC_FACES_1 0x2c38
816 #define R200_PP_CUBIC_FACES_2 0x2c58
817 #define R200_PP_CUBIC_FACES_3 0x2c78
818 #define R200_PP_CUBIC_FACES_4 0x2c98
819 #define R200_PP_CUBIC_FACES_5 0x2cb8
820 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
821 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
822 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
823 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
824 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
825 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
826 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
827 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
828 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
829 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
830 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
831 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
832 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
833 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
834 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
835 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
836 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
837 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
838 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
839 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
840 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
841 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
842 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
843 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
844 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
845 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
846 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
847 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
848 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
849 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
850
851 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
852 #define R200_SE_VTE_CNTL 0x20b0
853 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
854 #define R200_PP_TAM_DEBUG3 0x2d9c
855 #define R200_PP_CNTL_X 0x2cc4
856 #define R200_SE_VAP_CNTL_STATUS 0x2140
857 #define R200_RE_SCISSOR_TL_0 0x1cd8
858 #define R200_RE_SCISSOR_TL_1 0x1ce0
859 #define R200_RE_SCISSOR_TL_2 0x1ce8
860 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
861 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
862 #define R200_SE_VTX_STATE_CNTL 0x2180
863 #define R200_RE_POINTSIZE 0x2648
864 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
865
866 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
867 #define RADEON_PP_TEX_SIZE_1 0x1d0c
868 #define RADEON_PP_TEX_SIZE_2 0x1d14
869
870 #define RADEON_PP_CUBIC_FACES_0 0x1d24
871 #define RADEON_PP_CUBIC_FACES_1 0x1d28
872 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
873 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
874 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
875 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
876
877 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
878 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
879 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
880 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
881 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
882 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
883 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
884 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
885 #define R200_3D_DRAW_IMMD_2 0xC0003500
886 #define R200_SE_VTX_FMT_1 0x208c
887 #define R200_RE_CNTL 0x1c50
888
889 #define R200_RB3D_BLENDCOLOR 0x3218
890
891 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
892
893 #define R200_PP_TRI_PERF 0x2cf8
894
895 #define R200_PP_AFS_0 0x2f80
896 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
897
898 /* Constants */
899 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
900
901 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
902 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
903 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
904 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
905 #define RADEON_LAST_DISPATCH 1
906
907 #define RADEON_MAX_VB_AGE 0x7fffffff
908 #define RADEON_MAX_VB_VERTS (0xffff)
909
910 #define RADEON_RING_HIGH_MARK 128
911
912 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
913
914 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
915 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
916 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
917 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
918
919 #define RADEON_WRITE_PLL( addr, val ) \
920 do { \
921 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
922 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
923 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
924 } while (0)
925
926 #define RADEON_WRITE_PCIE( addr, val ) \
927 do { \
928 RADEON_WRITE8( RADEON_PCIE_INDEX, \
929 ((addr) & 0xff)); \
930 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
931 } while (0)
932
933 #define CP_PACKET0( reg, n ) \
934 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
935 #define CP_PACKET0_TABLE( reg, n ) \
936 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
937 #define CP_PACKET1( reg0, reg1 ) \
938 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
939 #define CP_PACKET2() \
940 (RADEON_CP_PACKET2)
941 #define CP_PACKET3( pkt, n ) \
942 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
943
944 /* ================================================================
945 * Engine control helper macros
946 */
947
948 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
949 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
950 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
951 RADEON_WAIT_HOST_IDLECLEAN) ); \
952 } while (0)
953
954 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
955 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
956 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
957 RADEON_WAIT_HOST_IDLECLEAN) ); \
958 } while (0)
959
960 #define RADEON_WAIT_UNTIL_IDLE() do { \
961 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
962 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
963 RADEON_WAIT_3D_IDLECLEAN | \
964 RADEON_WAIT_HOST_IDLECLEAN) ); \
965 } while (0)
966
967 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
968 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
969 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
970 } while (0)
971
972 #define RADEON_FLUSH_CACHE() do { \
973 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
974 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
975 } while (0)
976
977 #define RADEON_PURGE_CACHE() do { \
978 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
979 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
980 } while (0)
981
982 #define RADEON_FLUSH_ZCACHE() do { \
983 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
984 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
985 } while (0)
986
987 #define RADEON_PURGE_ZCACHE() do { \
988 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
989 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
990 } while (0)
991
992 /* ================================================================
993 * Misc helper macros
994 */
995
996 /* Perfbox functionality only.
997 */
998 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
999 do { \
1000 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1001 u32 head = GET_RING_HEAD( dev_priv ); \
1002 if (head == dev_priv->ring.tail) \
1003 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1004 } \
1005 } while (0)
1006
1007 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1008 do { \
1009 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1010 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1011 int __ret = radeon_do_cp_idle( dev_priv ); \
1012 if ( __ret ) return __ret; \
1013 sarea_priv->last_dispatch = 0; \
1014 radeon_freelist_reset( dev ); \
1015 } \
1016 } while (0)
1017
1018 #define RADEON_DISPATCH_AGE( age ) do { \
1019 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1020 OUT_RING( age ); \
1021 } while (0)
1022
1023 #define RADEON_FRAME_AGE( age ) do { \
1024 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1025 OUT_RING( age ); \
1026 } while (0)
1027
1028 #define RADEON_CLEAR_AGE( age ) do { \
1029 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1030 OUT_RING( age ); \
1031 } while (0)
1032
1033 /* ================================================================
1034 * Ring control
1035 */
1036
1037 #define RADEON_VERBOSE 0
1038
1039 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1040
1041 #define BEGIN_RING( n ) do { \
1042 if ( RADEON_VERBOSE ) { \
1043 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1044 n, __FUNCTION__ ); \
1045 } \
1046 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1047 COMMIT_RING(); \
1048 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1049 } \
1050 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1051 ring = dev_priv->ring.start; \
1052 write = dev_priv->ring.tail; \
1053 mask = dev_priv->ring.tail_mask; \
1054 } while (0)
1055
1056 #define ADVANCE_RING() do { \
1057 if ( RADEON_VERBOSE ) { \
1058 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1059 write, dev_priv->ring.tail ); \
1060 } \
1061 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1062 DRM_ERROR( \
1063 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1064 ((dev_priv->ring.tail + _nr) & mask), \
1065 write, __LINE__); \
1066 } else \
1067 dev_priv->ring.tail = write; \
1068 } while (0)
1069
1070 #define COMMIT_RING() do { \
1071 /* Flush writes to ring */ \
1072 DRM_MEMORYBARRIER(); \
1073 GET_RING_HEAD( dev_priv ); \
1074 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1075 /* read from PCI bus to ensure correct posting */ \
1076 RADEON_READ( RADEON_CP_RB_RPTR ); \
1077 } while (0)
1078
1079 #define OUT_RING( x ) do { \
1080 if ( RADEON_VERBOSE ) { \
1081 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1082 (unsigned int)(x), write ); \
1083 } \
1084 ring[write++] = (x); \
1085 write &= mask; \
1086 } while (0)
1087
1088 #define OUT_RING_REG( reg, val ) do { \
1089 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1090 OUT_RING( val ); \
1091 } while (0)
1092
1093 #define OUT_RING_TABLE( tab, sz ) do { \
1094 int _size = (sz); \
1095 int *_tab = (int *)(tab); \
1096 \
1097 if (write + _size > mask) { \
1098 int _i = (mask+1) - write; \
1099 _size -= _i; \
1100 while (_i > 0 ) { \
1101 *(int *)(ring + write) = *_tab++; \
1102 write++; \
1103 _i--; \
1104 } \
1105 write = 0; \
1106 _tab += _i; \
1107 } \
1108 \
1109 while (_size > 0) { \
1110 *(ring + write) = *_tab++; \
1111 write++; \
1112 _size--; \
1113 } \
1114 write &= mask; \
1115 } while (0)
1116
1117 #endif /* __RADEON_DRV_H__ */
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