2 * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver
4 * Copyright (c) 2005, Advanced Micro Devices, Inc.
6 * Developed with help from the 2.4.30 MMC AU1XXX controller including
7 * the following copyright notices:
8 * Copyright (c) 2003-2004 Embedded Edge, LLC.
9 * Portions Copyright (C) 2002 Embedix, Inc
10 * Copyright 2002 Hewlett-Packard Company
12 * 2.6 version of this driver inspired by:
13 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14 * All Rights Reserved.
15 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16 * All Rights Reserved.
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
24 /* Why is a timer used to detect insert events?
26 * From the AU1100 MMC application guide:
27 * If the Au1100-based design is intended to support both MultiMediaCards
28 * and 1- or 4-data bit SecureDigital cards, then the solution is to
29 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30 * In doing so, a MMC card never enters SPI-mode communications,
31 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32 * (the low to high transition will not occur).
34 * So we use the timer to check the status manually.
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/platform_device.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
44 #include <linux/mmc/host.h>
45 #include <linux/mmc/protocol.h>
47 #include <asm/mach-au1x00/au1000.h>
48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
49 #include <asm/mach-au1x00/au1100_mmc.h>
50 #include <asm/scatterlist.h>
55 #define DRIVER_NAME "au1xxx-mmc"
57 /* Set this to enable special debugging macros */
60 #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
62 #define DBG(fmt, idx, args...)
67 u32 tx_devid
, rx_devid
;
71 } au1xmmc_card_table
[] = {
72 { SD0_BASE
, DSCR_CMD0_SDMS_TX0
, DSCR_CMD0_SDMS_RX0
,
73 BCSR_BOARD_SD0PWR
, BCSR_INT_SD0INSERT
, BCSR_STATUS_SD0WP
},
74 #ifndef CONFIG_MIPS_DB1200
75 { SD1_BASE
, DSCR_CMD0_SDMS_TX1
, DSCR_CMD0_SDMS_RX1
,
76 BCSR_BOARD_DS1PWR
, BCSR_INT_SD1INSERT
, BCSR_STATUS_SD1WP
}
80 #define AU1XMMC_CONTROLLER_COUNT \
81 (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))
83 /* This array stores pointers for the hosts (used by the IRQ handler) */
84 struct au1xmmc_host
*au1xmmc_hosts
[AU1XMMC_CONTROLLER_COUNT
];
88 module_param(dma
, bool, 0);
89 MODULE_PARM_DESC(dma
, "Use DMA engine for data transfers (0 = disabled)");
92 static inline void IRQ_ON(struct au1xmmc_host
*host
, u32 mask
)
94 u32 val
= au_readl(HOST_CONFIG(host
));
96 au_writel(val
, HOST_CONFIG(host
));
100 static inline void FLUSH_FIFO(struct au1xmmc_host
*host
)
102 u32 val
= au_readl(HOST_CONFIG2(host
));
104 au_writel(val
| SD_CONFIG2_FF
, HOST_CONFIG2(host
));
107 /* SEND_STOP will turn off clock control - this re-enables it */
108 val
&= ~SD_CONFIG2_DF
;
110 au_writel(val
, HOST_CONFIG2(host
));
114 static inline void IRQ_OFF(struct au1xmmc_host
*host
, u32 mask
)
116 u32 val
= au_readl(HOST_CONFIG(host
));
118 au_writel(val
, HOST_CONFIG(host
));
122 static inline void SEND_STOP(struct au1xmmc_host
*host
)
125 /* We know the value of CONFIG2, so avoid a read we don't need */
126 u32 mask
= SD_CONFIG2_EN
;
128 WARN_ON(host
->status
!= HOST_S_DATA
);
129 host
->status
= HOST_S_STOP
;
131 au_writel(mask
| SD_CONFIG2_DF
, HOST_CONFIG2(host
));
134 /* Send the stop commmand */
135 au_writel(STOP_CMD
, HOST_CMD(host
));
138 static void au1xmmc_set_power(struct au1xmmc_host
*host
, int state
)
141 u32 val
= au1xmmc_card_table
[host
->id
].bcsrpwr
;
144 if (state
) bcsr
->board
|= val
;
149 static inline int au1xmmc_card_inserted(struct au1xmmc_host
*host
)
151 return (bcsr
->sig_status
& au1xmmc_card_table
[host
->id
].bcsrstatus
)
155 static int au1xmmc_card_readonly(struct mmc_host
*mmc
)
157 struct au1xmmc_host
*host
= mmc_priv(mmc
);
158 return (bcsr
->status
& au1xmmc_card_table
[host
->id
].wpstatus
)
162 static void au1xmmc_finish_request(struct au1xmmc_host
*host
)
165 struct mmc_request
*mrq
= host
->mrq
;
168 host
->flags
&= HOST_F_ACTIVE
;
174 host
->pio
.offset
= 0;
177 host
->status
= HOST_S_IDLE
;
179 bcsr
->disk_leds
|= (1 << 8);
181 mmc_request_done(host
->mmc
, mrq
);
184 static void au1xmmc_tasklet_finish(unsigned long param
)
186 struct au1xmmc_host
*host
= (struct au1xmmc_host
*) param
;
187 au1xmmc_finish_request(host
);
190 static int au1xmmc_send_command(struct au1xmmc_host
*host
, int wait
,
191 struct mmc_command
*cmd
)
194 u32 mmccmd
= (cmd
->opcode
<< SD_CMD_CI_SHIFT
);
196 switch (mmc_resp_type(cmd
)) {
200 mmccmd
|= SD_CMD_RT_1
;
203 mmccmd
|= SD_CMD_RT_1B
;
206 mmccmd
|= SD_CMD_RT_2
;
209 mmccmd
|= SD_CMD_RT_3
;
212 printk(KERN_INFO
"au1xmmc: unhandled response type %02x\n",
214 return MMC_ERR_INVALID
;
217 switch(cmd
->opcode
) {
218 case MMC_READ_SINGLE_BLOCK
:
219 case SD_APP_SEND_SCR
:
220 mmccmd
|= SD_CMD_CT_2
;
222 case MMC_READ_MULTIPLE_BLOCK
:
223 mmccmd
|= SD_CMD_CT_4
;
225 case MMC_WRITE_BLOCK
:
226 mmccmd
|= SD_CMD_CT_1
;
229 case MMC_WRITE_MULTIPLE_BLOCK
:
230 mmccmd
|= SD_CMD_CT_3
;
232 case MMC_STOP_TRANSMISSION
:
233 mmccmd
|= SD_CMD_CT_7
;
237 au_writel(cmd
->arg
, HOST_CMDARG(host
));
241 IRQ_OFF(host
, SD_CONFIG_CR
);
243 au_writel((mmccmd
| SD_CMD_GO
), HOST_CMD(host
));
246 /* Wait for the command to go on the line */
249 if (!(au_readl(HOST_CMD(host
)) & SD_CMD_GO
))
253 /* Wait for the command to come back */
256 u32 status
= au_readl(HOST_STATUS(host
));
258 while(!(status
& SD_STATUS_CR
))
259 status
= au_readl(HOST_STATUS(host
));
261 /* Clear the CR status */
262 au_writel(SD_STATUS_CR
, HOST_STATUS(host
));
264 IRQ_ON(host
, SD_CONFIG_CR
);
270 static void au1xmmc_data_complete(struct au1xmmc_host
*host
, u32 status
)
273 struct mmc_request
*mrq
= host
->mrq
;
274 struct mmc_data
*data
;
277 WARN_ON(host
->status
!= HOST_S_DATA
&& host
->status
!= HOST_S_STOP
);
279 if (host
->mrq
== NULL
)
282 data
= mrq
->cmd
->data
;
285 status
= au_readl(HOST_STATUS(host
));
287 /* The transaction is really over when the SD_STATUS_DB bit is clear */
289 while((host
->flags
& HOST_F_XMIT
) && (status
& SD_STATUS_DB
))
290 status
= au_readl(HOST_STATUS(host
));
292 data
->error
= MMC_ERR_NONE
;
293 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
, host
->dma
.dir
);
295 /* Process any errors */
297 crc
= (status
& (SD_STATUS_WC
| SD_STATUS_RC
));
298 if (host
->flags
& HOST_F_XMIT
)
299 crc
|= ((status
& 0x07) == 0x02) ? 0 : 1;
302 data
->error
= MMC_ERR_BADCRC
;
304 /* Clear the CRC bits */
305 au_writel(SD_STATUS_WC
| SD_STATUS_RC
, HOST_STATUS(host
));
307 data
->bytes_xfered
= 0;
309 if (data
->error
== MMC_ERR_NONE
) {
310 if (host
->flags
& HOST_F_DMA
) {
311 u32 chan
= DMA_CHANNEL(host
);
313 chan_tab_t
*c
= *((chan_tab_t
**) chan
);
314 au1x_dma_chan_t
*cp
= c
->chan_ptr
;
315 data
->bytes_xfered
= cp
->ddma_bytecnt
;
319 (data
->blocks
* data
->blksz
) -
323 au1xmmc_finish_request(host
);
326 static void au1xmmc_tasklet_data(unsigned long param
)
328 struct au1xmmc_host
*host
= (struct au1xmmc_host
*) param
;
330 u32 status
= au_readl(HOST_STATUS(host
));
331 au1xmmc_data_complete(host
, status
);
334 #define AU1XMMC_MAX_TRANSFER 8
336 static void au1xmmc_send_pio(struct au1xmmc_host
*host
)
339 struct mmc_data
*data
= 0;
340 int sg_len
, max
, count
= 0;
341 unsigned char *sg_ptr
;
343 struct scatterlist
*sg
;
345 data
= host
->mrq
->data
;
347 if (!(host
->flags
& HOST_F_XMIT
))
350 /* This is the pointer to the data buffer */
351 sg
= &data
->sg
[host
->pio
.index
];
352 sg_ptr
= page_address(sg
->page
) + sg
->offset
+ host
->pio
.offset
;
354 /* This is the space left inside the buffer */
355 sg_len
= data
->sg
[host
->pio
.index
].length
- host
->pio
.offset
;
357 /* Check to if we need less then the size of the sg_buffer */
359 max
= (sg_len
> host
->pio
.len
) ? host
->pio
.len
: sg_len
;
360 if (max
> AU1XMMC_MAX_TRANSFER
) max
= AU1XMMC_MAX_TRANSFER
;
362 for(count
= 0; count
< max
; count
++ ) {
365 status
= au_readl(HOST_STATUS(host
));
367 if (!(status
& SD_STATUS_TH
))
372 au_writel((unsigned long) val
, HOST_TXPORT(host
));
376 host
->pio
.len
-= count
;
377 host
->pio
.offset
+= count
;
379 if (count
== sg_len
) {
381 host
->pio
.offset
= 0;
384 if (host
->pio
.len
== 0) {
385 IRQ_OFF(host
, SD_CONFIG_TH
);
387 if (host
->flags
& HOST_F_STOP
)
390 tasklet_schedule(&host
->data_task
);
394 static void au1xmmc_receive_pio(struct au1xmmc_host
*host
)
397 struct mmc_data
*data
= 0;
398 int sg_len
= 0, max
= 0, count
= 0;
399 unsigned char *sg_ptr
= 0;
401 struct scatterlist
*sg
;
403 data
= host
->mrq
->data
;
405 if (!(host
->flags
& HOST_F_RECV
))
410 if (host
->pio
.index
< host
->dma
.len
) {
411 sg
= &data
->sg
[host
->pio
.index
];
412 sg_ptr
= page_address(sg
->page
) + sg
->offset
+ host
->pio
.offset
;
414 /* This is the space left inside the buffer */
415 sg_len
= sg_dma_len(&data
->sg
[host
->pio
.index
]) - host
->pio
.offset
;
417 /* Check to if we need less then the size of the sg_buffer */
418 if (sg_len
< max
) max
= sg_len
;
421 if (max
> AU1XMMC_MAX_TRANSFER
)
422 max
= AU1XMMC_MAX_TRANSFER
;
424 for(count
= 0; count
< max
; count
++ ) {
426 status
= au_readl(HOST_STATUS(host
));
428 if (!(status
& SD_STATUS_NE
))
431 if (status
& SD_STATUS_RC
) {
432 DBG("RX CRC Error [%d + %d].\n", host
->id
,
433 host
->pio
.len
, count
);
437 if (status
& SD_STATUS_RO
) {
438 DBG("RX Overrun [%d + %d]\n", host
->id
,
439 host
->pio
.len
, count
);
442 else if (status
& SD_STATUS_RU
) {
443 DBG("RX Underrun [%d + %d]\n", host
->id
,
444 host
->pio
.len
, count
);
448 val
= au_readl(HOST_RXPORT(host
));
451 *sg_ptr
++ = (unsigned char) (val
& 0xFF);
454 host
->pio
.len
-= count
;
455 host
->pio
.offset
+= count
;
457 if (sg_len
&& count
== sg_len
) {
459 host
->pio
.offset
= 0;
462 if (host
->pio
.len
== 0) {
463 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
464 IRQ_OFF(host
, SD_CONFIG_NE
);
466 if (host
->flags
& HOST_F_STOP
)
469 tasklet_schedule(&host
->data_task
);
473 /* static void au1xmmc_cmd_complete
474 This is called when a command has been completed - grab the response
475 and check for errors. Then start the data transfer if it is indicated.
478 static void au1xmmc_cmd_complete(struct au1xmmc_host
*host
, u32 status
)
481 struct mmc_request
*mrq
= host
->mrq
;
482 struct mmc_command
*cmd
;
489 cmd
->error
= MMC_ERR_NONE
;
491 if (cmd
->flags
& MMC_RSP_PRESENT
) {
492 if (cmd
->flags
& MMC_RSP_136
) {
496 r
[0] = au_readl(host
->iobase
+ SD_RESP3
);
497 r
[1] = au_readl(host
->iobase
+ SD_RESP2
);
498 r
[2] = au_readl(host
->iobase
+ SD_RESP1
);
499 r
[3] = au_readl(host
->iobase
+ SD_RESP0
);
501 /* The CRC is omitted from the response, so really
502 * we only got 120 bytes, but the engine expects
503 * 128 bits, so we have to shift things up
506 for(i
= 0; i
< 4; i
++) {
507 cmd
->resp
[i
] = (r
[i
] & 0x00FFFFFF) << 8;
509 cmd
->resp
[i
] |= (r
[i
+ 1] & 0xFF000000) >> 24;
512 /* Techincally, we should be getting all 48 bits of
513 * the response (SD_RESP1 + SD_RESP2), but because
514 * our response omits the CRC, our data ends up
515 * being shifted 8 bits to the right. In this case,
516 * that means that the OSR data starts at bit 31,
517 * so we can just read RESP0 and return that
519 cmd
->resp
[0] = au_readl(host
->iobase
+ SD_RESP0
);
523 /* Figure out errors */
525 if (status
& (SD_STATUS_SC
| SD_STATUS_WC
| SD_STATUS_RC
))
526 cmd
->error
= MMC_ERR_BADCRC
;
528 trans
= host
->flags
& (HOST_F_XMIT
| HOST_F_RECV
);
530 if (!trans
|| cmd
->error
!= MMC_ERR_NONE
) {
532 IRQ_OFF(host
, SD_CONFIG_TH
| SD_CONFIG_RA
|SD_CONFIG_RF
);
533 tasklet_schedule(&host
->finish_task
);
537 host
->status
= HOST_S_DATA
;
539 if (host
->flags
& HOST_F_DMA
) {
540 u32 channel
= DMA_CHANNEL(host
);
542 /* Start the DMA as soon as the buffer gets something in it */
544 if (host
->flags
& HOST_F_RECV
) {
545 u32 mask
= SD_STATUS_DB
| SD_STATUS_NE
;
547 while((status
& mask
) != mask
)
548 status
= au_readl(HOST_STATUS(host
));
551 au1xxx_dbdma_start(channel
);
555 static void au1xmmc_set_clock(struct au1xmmc_host
*host
, int rate
)
558 unsigned int pbus
= get_au1x00_speed();
559 unsigned int divisor
;
563 divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
566 pbus
/= ((au_readl(SYS_POWERCTRL
) & 0x3) + 2);
569 divisor
= ((pbus
/ rate
) / 2) - 1;
571 config
= au_readl(HOST_CONFIG(host
));
573 config
&= ~(SD_CONFIG_DIV
);
574 config
|= (divisor
& SD_CONFIG_DIV
) | SD_CONFIG_DE
;
576 au_writel(config
, HOST_CONFIG(host
));
581 au1xmmc_prepare_data(struct au1xmmc_host
*host
, struct mmc_data
*data
)
584 int datalen
= data
->blocks
* data
->blksz
;
587 host
->flags
|= HOST_F_DMA
;
589 if (data
->flags
& MMC_DATA_READ
)
590 host
->flags
|= HOST_F_RECV
;
592 host
->flags
|= HOST_F_XMIT
;
595 host
->flags
|= HOST_F_STOP
;
597 host
->dma
.dir
= DMA_BIDIRECTIONAL
;
599 host
->dma
.len
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
600 data
->sg_len
, host
->dma
.dir
);
602 if (host
->dma
.len
== 0)
603 return MMC_ERR_TIMEOUT
;
605 au_writel(data
->blksz
- 1, HOST_BLKSIZE(host
));
607 if (host
->flags
& HOST_F_DMA
) {
609 u32 channel
= DMA_CHANNEL(host
);
611 au1xxx_dbdma_stop(channel
);
613 for(i
= 0; i
< host
->dma
.len
; i
++) {
614 u32 ret
= 0, flags
= DDMA_FLAGS_NOIE
;
615 struct scatterlist
*sg
= &data
->sg
[i
];
616 int sg_len
= sg
->length
;
618 int len
= (datalen
> sg_len
) ? sg_len
: datalen
;
620 if (i
== host
->dma
.len
- 1)
621 flags
= DDMA_FLAGS_IE
;
623 if (host
->flags
& HOST_F_XMIT
){
624 ret
= au1xxx_dbdma_put_source_flags(channel
,
625 (void *) (page_address(sg
->page
) +
630 ret
= au1xxx_dbdma_put_dest_flags(channel
,
631 (void *) (page_address(sg
->page
) +
644 host
->pio
.offset
= 0;
645 host
->pio
.len
= datalen
;
647 if (host
->flags
& HOST_F_XMIT
)
648 IRQ_ON(host
, SD_CONFIG_TH
);
650 IRQ_ON(host
, SD_CONFIG_NE
);
651 //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
657 dma_unmap_sg(mmc_dev(host
->mmc
),data
->sg
,data
->sg_len
,host
->dma
.dir
);
658 return MMC_ERR_TIMEOUT
;
661 /* static void au1xmmc_request
662 This actually starts a command or data transaction
665 static void au1xmmc_request(struct mmc_host
* mmc
, struct mmc_request
* mrq
)
668 struct au1xmmc_host
*host
= mmc_priv(mmc
);
669 int ret
= MMC_ERR_NONE
;
671 WARN_ON(irqs_disabled());
672 WARN_ON(host
->status
!= HOST_S_IDLE
);
675 host
->status
= HOST_S_CMD
;
677 bcsr
->disk_leds
&= ~(1 << 8);
681 ret
= au1xmmc_prepare_data(host
, mrq
->data
);
684 if (ret
== MMC_ERR_NONE
)
685 ret
= au1xmmc_send_command(host
, 0, mrq
->cmd
);
687 if (ret
!= MMC_ERR_NONE
) {
688 mrq
->cmd
->error
= ret
;
689 au1xmmc_finish_request(host
);
693 static void au1xmmc_reset_controller(struct au1xmmc_host
*host
)
696 /* Apply the clock */
697 au_writel(SD_ENABLE_CE
, HOST_ENABLE(host
));
700 au_writel(SD_ENABLE_R
| SD_ENABLE_CE
, HOST_ENABLE(host
));
703 au_writel(~0, HOST_STATUS(host
));
706 au_writel(0, HOST_BLKSIZE(host
));
707 au_writel(0x001fffff, HOST_TIMEOUT(host
));
710 au_writel(SD_CONFIG2_EN
, HOST_CONFIG2(host
));
713 au_writel(SD_CONFIG2_EN
| SD_CONFIG2_FF
, HOST_CONFIG2(host
));
716 au_writel(SD_CONFIG2_EN
, HOST_CONFIG2(host
));
719 /* Configure interrupts */
720 au_writel(AU1XMMC_INTERRUPTS
, HOST_CONFIG(host
));
725 static void au1xmmc_set_ios(struct mmc_host
* mmc
, struct mmc_ios
* ios
)
727 struct au1xmmc_host
*host
= mmc_priv(mmc
);
729 if (ios
->power_mode
== MMC_POWER_OFF
)
730 au1xmmc_set_power(host
, 0);
731 else if (ios
->power_mode
== MMC_POWER_ON
) {
732 au1xmmc_set_power(host
, 1);
735 if (ios
->clock
&& ios
->clock
!= host
->clock
) {
736 au1xmmc_set_clock(host
, ios
->clock
);
737 host
->clock
= ios
->clock
;
741 static void au1xmmc_dma_callback(int irq
, void *dev_id
)
743 struct au1xmmc_host
*host
= (struct au1xmmc_host
*) dev_id
;
745 /* Avoid spurious interrupts */
750 if (host
->flags
& HOST_F_STOP
)
753 tasklet_schedule(&host
->data_task
);
756 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
757 #define STATUS_DATA_IN (SD_STATUS_NE)
758 #define STATUS_DATA_OUT (SD_STATUS_TH)
760 static irqreturn_t
au1xmmc_irq(int irq
, void *dev_id
)
766 disable_irq(AU1100_SD_IRQ
);
768 for(i
= 0; i
< AU1XMMC_CONTROLLER_COUNT
; i
++) {
769 struct au1xmmc_host
* host
= au1xmmc_hosts
[i
];
772 status
= au_readl(HOST_STATUS(host
));
774 if (host
->mrq
&& (status
& STATUS_TIMEOUT
)) {
775 if (status
& SD_STATUS_RAT
)
776 host
->mrq
->cmd
->error
= MMC_ERR_TIMEOUT
;
778 else if (status
& SD_STATUS_DT
)
779 host
->mrq
->data
->error
= MMC_ERR_TIMEOUT
;
781 /* In PIO mode, interrupts might still be enabled */
782 IRQ_OFF(host
, SD_CONFIG_NE
| SD_CONFIG_TH
);
784 //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
785 tasklet_schedule(&host
->finish_task
);
788 else if (status
& SD_STATUS_DD
) {
790 /* Sometimes we get a DD before a NE in PIO mode */
792 if (!(host
->flags
& HOST_F_DMA
) &&
793 (status
& SD_STATUS_NE
))
794 au1xmmc_receive_pio(host
);
796 au1xmmc_data_complete(host
, status
);
797 //tasklet_schedule(&host->data_task);
801 else if (status
& (SD_STATUS_CR
)) {
802 if (host
->status
== HOST_S_CMD
)
803 au1xmmc_cmd_complete(host
,status
);
805 else if (!(host
->flags
& HOST_F_DMA
)) {
806 if ((host
->flags
& HOST_F_XMIT
) &&
807 (status
& STATUS_DATA_OUT
))
808 au1xmmc_send_pio(host
);
809 else if ((host
->flags
& HOST_F_RECV
) &&
810 (status
& STATUS_DATA_IN
))
811 au1xmmc_receive_pio(host
);
813 else if (status
& 0x203FBC70) {
814 DBG("Unhandled status %8.8x\n", host
->id
, status
);
818 au_writel(status
, HOST_STATUS(host
));
824 enable_irq(AU1100_SD_IRQ
);
828 static void au1xmmc_poll_event(unsigned long arg
)
830 struct au1xmmc_host
*host
= (struct au1xmmc_host
*) arg
;
832 int card
= au1xmmc_card_inserted(host
);
833 int controller
= (host
->flags
& HOST_F_ACTIVE
) ? 1 : 0;
835 if (card
!= controller
) {
836 host
->flags
&= ~HOST_F_ACTIVE
;
837 if (card
) host
->flags
|= HOST_F_ACTIVE
;
838 mmc_detect_change(host
->mmc
, 0);
841 if (host
->mrq
!= NULL
) {
842 u32 status
= au_readl(HOST_STATUS(host
));
843 DBG("PENDING - %8.8x\n", host
->id
, status
);
846 mod_timer(&host
->timer
, jiffies
+ AU1XMMC_DETECT_TIMEOUT
);
849 static dbdev_tab_t au1xmmc_mem_dbdev
=
851 DSCR_CMD0_ALWAYS
, DEV_FLAGS_ANYUSE
, 0, 8, 0x00000000, 0, 0
854 static void au1xmmc_init_dma(struct au1xmmc_host
*host
)
859 int txid
= au1xmmc_card_table
[host
->id
].tx_devid
;
860 int rxid
= au1xmmc_card_table
[host
->id
].rx_devid
;
862 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
863 of 8 bits. And since devices are shared, we need to create
864 our own to avoid freaking out other devices
867 int memid
= au1xxx_ddma_add_device(&au1xmmc_mem_dbdev
);
869 txchan
= au1xxx_dbdma_chan_alloc(memid
, txid
,
870 au1xmmc_dma_callback
, (void *) host
);
872 rxchan
= au1xxx_dbdma_chan_alloc(rxid
, memid
,
873 au1xmmc_dma_callback
, (void *) host
);
875 au1xxx_dbdma_set_devwidth(txchan
, 8);
876 au1xxx_dbdma_set_devwidth(rxchan
, 8);
878 au1xxx_dbdma_ring_alloc(txchan
, AU1XMMC_DESCRIPTOR_COUNT
);
879 au1xxx_dbdma_ring_alloc(rxchan
, AU1XMMC_DESCRIPTOR_COUNT
);
881 host
->tx_chan
= txchan
;
882 host
->rx_chan
= rxchan
;
885 static const struct mmc_host_ops au1xmmc_ops
= {
886 .request
= au1xmmc_request
,
887 .set_ios
= au1xmmc_set_ios
,
888 .get_ro
= au1xmmc_card_readonly
,
891 static int __devinit
au1xmmc_probe(struct platform_device
*pdev
)
896 /* THe interrupt is shared among all controllers */
897 ret
= request_irq(AU1100_SD_IRQ
, au1xmmc_irq
, IRQF_DISABLED
, "MMC", 0);
900 printk(DRIVER_NAME
"ERROR: Couldn't get int %d: %d\n",
905 disable_irq(AU1100_SD_IRQ
);
907 for(i
= 0; i
< AU1XMMC_CONTROLLER_COUNT
; i
++) {
908 struct mmc_host
*mmc
= mmc_alloc_host(sizeof(struct au1xmmc_host
), &pdev
->dev
);
909 struct au1xmmc_host
*host
= 0;
912 printk(DRIVER_NAME
"ERROR: no mem for host %d\n", i
);
913 au1xmmc_hosts
[i
] = 0;
917 mmc
->ops
= &au1xmmc_ops
;
920 mmc
->f_max
= 24000000;
922 mmc
->max_seg_size
= AU1XMMC_DESCRIPTOR_SIZE
;
923 mmc
->max_phys_segs
= AU1XMMC_DESCRIPTOR_COUNT
;
925 mmc
->max_blk_size
= 2048;
926 mmc
->max_blk_count
= 512;
928 mmc
->ocr_avail
= AU1XMMC_OCR
;
930 host
= mmc_priv(mmc
);
934 host
->iobase
= au1xmmc_card_table
[host
->id
].iobase
;
936 host
->power_mode
= MMC_POWER_OFF
;
938 host
->flags
= au1xmmc_card_inserted(host
) ? HOST_F_ACTIVE
: 0;
939 host
->status
= HOST_S_IDLE
;
941 init_timer(&host
->timer
);
943 host
->timer
.function
= au1xmmc_poll_event
;
944 host
->timer
.data
= (unsigned long) host
;
945 host
->timer
.expires
= jiffies
+ AU1XMMC_DETECT_TIMEOUT
;
947 tasklet_init(&host
->data_task
, au1xmmc_tasklet_data
,
948 (unsigned long) host
);
950 tasklet_init(&host
->finish_task
, au1xmmc_tasklet_finish
,
951 (unsigned long) host
);
953 spin_lock_init(&host
->lock
);
956 au1xmmc_init_dma(host
);
958 au1xmmc_reset_controller(host
);
961 au1xmmc_hosts
[i
] = host
;
963 add_timer(&host
->timer
);
965 printk(KERN_INFO DRIVER_NAME
": MMC Controller %d set up at %8.8X (mode=%s)\n",
966 host
->id
, host
->iobase
, dma
? "dma" : "pio");
969 enable_irq(AU1100_SD_IRQ
);
974 static int __devexit
au1xmmc_remove(struct platform_device
*pdev
)
979 disable_irq(AU1100_SD_IRQ
);
981 for(i
= 0; i
< AU1XMMC_CONTROLLER_COUNT
; i
++) {
982 struct au1xmmc_host
*host
= au1xmmc_hosts
[i
];
985 tasklet_kill(&host
->data_task
);
986 tasklet_kill(&host
->finish_task
);
988 del_timer_sync(&host
->timer
);
989 au1xmmc_set_power(host
, 0);
991 mmc_remove_host(host
->mmc
);
993 au1xxx_dbdma_chan_free(host
->tx_chan
);
994 au1xxx_dbdma_chan_free(host
->rx_chan
);
996 au_writel(0x0, HOST_ENABLE(host
));
1000 free_irq(AU1100_SD_IRQ
, 0);
1004 static struct platform_driver au1xmmc_driver
= {
1005 .probe
= au1xmmc_probe
,
1006 .remove
= au1xmmc_remove
,
1010 .name
= DRIVER_NAME
,
1014 static int __init
au1xmmc_init(void)
1016 return platform_driver_register(&au1xmmc_driver
);
1019 static void __exit
au1xmmc_exit(void)
1021 platform_driver_unregister(&au1xmmc_driver
);
1024 module_init(au1xmmc_init
);
1025 module_exit(au1xmmc_exit
);
1028 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1029 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1030 MODULE_LICENSE("GPL");