?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 2.6.24-rc8
[linux-2.6/kmemtrace.git] / drivers / kvm / svm.c
blob4e04e49a2f1c35f626fa24d3d5d3f1ea5d115869
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
17 #include "kvm_svm.h"
18 #include "x86_emulate.h"
19 #include "irq.h"
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/vmalloc.h>
24 #include <linux/highmem.h>
25 #include <linux/sched.h>
26
27 #include <asm/desc.h>
28
29 MODULE_AUTHOR("Qumranet");
30 MODULE_LICENSE("GPL");
31
32 #define IOPM_ALLOC_ORDER 2
33 #define MSRPM_ALLOC_ORDER 1
34
35 #define DB_VECTOR 1
36 #define UD_VECTOR 6
37 #define GP_VECTOR 13
38
39 #define DR7_GD_MASK (1 << 13)
40 #define DR6_BD_MASK (1 << 13)
41
42 #define SEG_TYPE_LDT 2
43 #define SEG_TYPE_BUSY_TSS16 3
44
45 #define KVM_EFER_LMA (1 << 10)
46 #define KVM_EFER_LME (1 << 8)
47
48 #define SVM_FEATURE_NPT (1 << 0)
49 #define SVM_FEATURE_LBRV (1 << 1)
50 #define SVM_DEATURE_SVML (1 << 2)
51
52 static void kvm_reput_irq(struct vcpu_svm *svm);
53
54 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
55 {
56 return container_of(vcpu, struct vcpu_svm, vcpu);
57 }
58
59 unsigned long iopm_base;
60 unsigned long msrpm_base;
61
62 struct kvm_ldttss_desc {
63 u16 limit0;
64 u16 base0;
65 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
66 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
67 u32 base3;
68 u32 zero1;
69 } __attribute__((packed));
70
71 struct svm_cpu_data {
72 int cpu;
73
74 u64 asid_generation;
75 u32 max_asid;
76 u32 next_asid;
77 struct kvm_ldttss_desc *tss_desc;
78
79 struct page *save_area;
80 };
81
82 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
83 static uint32_t svm_features;
84
85 struct svm_init_data {
86 int cpu;
87 int r;
88 };
89
90 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
91
92 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
93 #define MSRS_RANGE_SIZE 2048
94 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
95
96 #define MAX_INST_SIZE 15
97
98 static inline u32 svm_has(u32 feat)
99 {
100 return svm_features & feat;
101 }
102
103 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
104 {
105 int word_index = __ffs(vcpu->irq_summary);
106 int bit_index = __ffs(vcpu->irq_pending[word_index]);
107 int irq = word_index * BITS_PER_LONG + bit_index;
108
109 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
110 if (!vcpu->irq_pending[word_index])
111 clear_bit(word_index, &vcpu->irq_summary);
112 return irq;
113 }
114
115 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
116 {
117 set_bit(irq, vcpu->irq_pending);
118 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
119 }
120
121 static inline void clgi(void)
122 {
123 asm volatile (SVM_CLGI);
124 }
125
126 static inline void stgi(void)
127 {
128 asm volatile (SVM_STGI);
129 }
130
131 static inline void invlpga(unsigned long addr, u32 asid)
132 {
133 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
134 }
135
136 static inline unsigned long kvm_read_cr2(void)
137 {
138 unsigned long cr2;
139
140 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
141 return cr2;
142 }
143
144 static inline void kvm_write_cr2(unsigned long val)
145 {
146 asm volatile ("mov %0, %%cr2" :: "r" (val));
147 }
148
149 static inline unsigned long read_dr6(void)
150 {
151 unsigned long dr6;
152
153 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
154 return dr6;
155 }
156
157 static inline void write_dr6(unsigned long val)
158 {
159 asm volatile ("mov %0, %%dr6" :: "r" (val));
160 }
161
162 static inline unsigned long read_dr7(void)
163 {
164 unsigned long dr7;
165
166 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
167 return dr7;
168 }
169
170 static inline void write_dr7(unsigned long val)
171 {
172 asm volatile ("mov %0, %%dr7" :: "r" (val));
173 }
174
175 static inline void force_new_asid(struct kvm_vcpu *vcpu)
176 {
177 to_svm(vcpu)->asid_generation--;
178 }
179
180 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
181 {
182 force_new_asid(vcpu);
183 }
184
185 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
186 {
187 if (!(efer & KVM_EFER_LMA))
188 efer &= ~KVM_EFER_LME;
189
190 to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
191 vcpu->shadow_efer = efer;
192 }
193
194 static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
195 {
196 struct vcpu_svm *svm = to_svm(vcpu);
197
198 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
199 SVM_EVTINJ_VALID_ERR |
200 SVM_EVTINJ_TYPE_EXEPT |
201 GP_VECTOR;
202 svm->vmcb->control.event_inj_err = error_code;
203 }
204
205 static void inject_ud(struct kvm_vcpu *vcpu)
206 {
207 to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID |
208 SVM_EVTINJ_TYPE_EXEPT |
209 UD_VECTOR;
210 }
211
212 static int is_page_fault(uint32_t info)
213 {
214 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
215 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
216 }
217
218 static int is_external_interrupt(u32 info)
219 {
220 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
221 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
222 }
223
224 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
225 {
226 struct vcpu_svm *svm = to_svm(vcpu);
227
228 if (!svm->next_rip) {
229 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
230 return;
231 }
232 if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) {
233 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
234 __FUNCTION__,
235 svm->vmcb->save.rip,
236 svm->next_rip);
237 }
238
239 vcpu->rip = svm->vmcb->save.rip = svm->next_rip;
240 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
241
242 vcpu->interrupt_window_open = 1;
243 }
244
245 static int has_svm(void)
246 {
247 uint32_t eax, ebx, ecx, edx;
248
249 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
250 printk(KERN_INFO "has_svm: not amd\n");
251 return 0;
252 }
253
254 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
255 if (eax < SVM_CPUID_FUNC) {
256 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
257 return 0;
258 }
259
260 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
261 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
262 printk(KERN_DEBUG "has_svm: svm not available\n");
263 return 0;
264 }
265 return 1;
266 }
267
268 static void svm_hardware_disable(void *garbage)
269 {
270 struct svm_cpu_data *svm_data
271 = per_cpu(svm_data, raw_smp_processor_id());
272
273 if (svm_data) {
274 uint64_t efer;
275
276 wrmsrl(MSR_VM_HSAVE_PA, 0);
277 rdmsrl(MSR_EFER, efer);
278 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
279 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
280 __free_page(svm_data->save_area);
281 kfree(svm_data);
282 }
283 }
284
285 static void svm_hardware_enable(void *garbage)
286 {
287
288 struct svm_cpu_data *svm_data;
289 uint64_t efer;
290 #ifdef CONFIG_X86_64
291 struct desc_ptr gdt_descr;
292 #else
293 struct Xgt_desc_struct gdt_descr;
294 #endif
295 struct desc_struct *gdt;
296 int me = raw_smp_processor_id();
297
298 if (!has_svm()) {
299 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
300 return;
301 }
302 svm_data = per_cpu(svm_data, me);
303
304 if (!svm_data) {
305 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
306 me);
307 return;
308 }
309
310 svm_data->asid_generation = 1;
311 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
312 svm_data->next_asid = svm_data->max_asid + 1;
313 svm_features = cpuid_edx(SVM_CPUID_FUNC);
314
315 asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
316 gdt = (struct desc_struct *)gdt_descr.address;
317 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
318
319 rdmsrl(MSR_EFER, efer);
320 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
321
322 wrmsrl(MSR_VM_HSAVE_PA,
323 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
324 }
325
326 static int svm_cpu_init(int cpu)
327 {
328 struct svm_cpu_data *svm_data;
329 int r;
330
331 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
332 if (!svm_data)
333 return -ENOMEM;
334 svm_data->cpu = cpu;
335 svm_data->save_area = alloc_page(GFP_KERNEL);
336 r = -ENOMEM;
337 if (!svm_data->save_area)
338 goto err_1;
339
340 per_cpu(svm_data, cpu) = svm_data;
341
342 return 0;
343
344 err_1:
345 kfree(svm_data);
346 return r;
347
348 }
349
350 static void set_msr_interception(u32 *msrpm, unsigned msr,
351 int read, int write)
352 {
353 int i;
354
355 for (i = 0; i < NUM_MSR_MAPS; i++) {
356 if (msr >= msrpm_ranges[i] &&
357 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
358 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
359 msrpm_ranges[i]) * 2;
360
361 u32 *base = msrpm + (msr_offset / 32);
362 u32 msr_shift = msr_offset % 32;
363 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
364 *base = (*base & ~(0x3 << msr_shift)) |
365 (mask << msr_shift);
366 return;
367 }
368 }
369 BUG();
370 }
371
372 static __init int svm_hardware_setup(void)
373 {
374 int cpu;
375 struct page *iopm_pages;
376 struct page *msrpm_pages;
377 void *iopm_va, *msrpm_va;
378 int r;
379
380 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
381
382 if (!iopm_pages)
383 return -ENOMEM;
384
385 iopm_va = page_address(iopm_pages);
386 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
387 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
388 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
389
390
391 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
392
393 r = -ENOMEM;
394 if (!msrpm_pages)
395 goto err_1;
396
397 msrpm_va = page_address(msrpm_pages);
398 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
399 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
400
401 #ifdef CONFIG_X86_64
402 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
403 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
404 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
405 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
406 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
407 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
408 #endif
409 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
410 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
411 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
412 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
413
414 for_each_online_cpu(cpu) {
415 r = svm_cpu_init(cpu);
416 if (r)
417 goto err_2;
418 }
419 return 0;
420
421 err_2:
422 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
423 msrpm_base = 0;
424 err_1:
425 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
426 iopm_base = 0;
427 return r;
428 }
429
430 static __exit void svm_hardware_unsetup(void)
431 {
432 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
433 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
434 iopm_base = msrpm_base = 0;
435 }
436
437 static void init_seg(struct vmcb_seg *seg)
438 {
439 seg->selector = 0;
440 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
441 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
442 seg->limit = 0xffff;
443 seg->base = 0;
444 }
445
446 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
447 {
448 seg->selector = 0;
449 seg->attrib = SVM_SELECTOR_P_MASK | type;
450 seg->limit = 0xffff;
451 seg->base = 0;
452 }
453
454 static void init_vmcb(struct vmcb *vmcb)
455 {
456 struct vmcb_control_area *control = &vmcb->control;
457 struct vmcb_save_area *save = &vmcb->save;
458
459 control->intercept_cr_read = INTERCEPT_CR0_MASK |
460 INTERCEPT_CR3_MASK |
461 INTERCEPT_CR4_MASK;
462
463 control->intercept_cr_write = INTERCEPT_CR0_MASK |
464 INTERCEPT_CR3_MASK |
465 INTERCEPT_CR4_MASK;
466
467 control->intercept_dr_read = INTERCEPT_DR0_MASK |
468 INTERCEPT_DR1_MASK |
469 INTERCEPT_DR2_MASK |
470 INTERCEPT_DR3_MASK;
471
472 control->intercept_dr_write = INTERCEPT_DR0_MASK |
473 INTERCEPT_DR1_MASK |
474 INTERCEPT_DR2_MASK |
475 INTERCEPT_DR3_MASK |
476 INTERCEPT_DR5_MASK |
477 INTERCEPT_DR7_MASK;
478
479 control->intercept_exceptions = 1 << PF_VECTOR;
480
481
482 control->intercept = (1ULL << INTERCEPT_INTR) |
483 (1ULL << INTERCEPT_NMI) |
484 (1ULL << INTERCEPT_SMI) |
485 /*
486 * selective cr0 intercept bug?
487 * 0: 0f 22 d8 mov %eax,%cr3
488 * 3: 0f 20 c0 mov %cr0,%eax
489 * 6: 0d 00 00 00 80 or $0x80000000,%eax
490 * b: 0f 22 c0 mov %eax,%cr0
491 * set cr3 ->interception
492 * get cr0 ->interception
493 * set cr0 -> no interception
494 */
495 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
496 (1ULL << INTERCEPT_CPUID) |
497 (1ULL << INTERCEPT_INVD) |
498 (1ULL << INTERCEPT_HLT) |
499 (1ULL << INTERCEPT_INVLPGA) |
500 (1ULL << INTERCEPT_IOIO_PROT) |
501 (1ULL << INTERCEPT_MSR_PROT) |
502 (1ULL << INTERCEPT_TASK_SWITCH) |
503 (1ULL << INTERCEPT_SHUTDOWN) |
504 (1ULL << INTERCEPT_VMRUN) |
505 (1ULL << INTERCEPT_VMMCALL) |
506 (1ULL << INTERCEPT_VMLOAD) |
507 (1ULL << INTERCEPT_VMSAVE) |
508 (1ULL << INTERCEPT_STGI) |
509 (1ULL << INTERCEPT_CLGI) |
510 (1ULL << INTERCEPT_SKINIT) |
511 (1ULL << INTERCEPT_WBINVD) |
512 (1ULL << INTERCEPT_MONITOR) |
513 (1ULL << INTERCEPT_MWAIT);
514
515 control->iopm_base_pa = iopm_base;
516 control->msrpm_base_pa = msrpm_base;
517 control->tsc_offset = 0;
518 control->int_ctl = V_INTR_MASKING_MASK;
519
520 init_seg(&save->es);
521 init_seg(&save->ss);
522 init_seg(&save->ds);
523 init_seg(&save->fs);
524 init_seg(&save->gs);
525
526 save->cs.selector = 0xf000;
527 /* Executable/Readable Code Segment */
528 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
529 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
530 save->cs.limit = 0xffff;
531 /*
532 * cs.base should really be 0xffff0000, but vmx can't handle that, so
533 * be consistent with it.
534 *
535 * Replace when we have real mode working for vmx.
536 */
537 save->cs.base = 0xf0000;
538
539 save->gdtr.limit = 0xffff;
540 save->idtr.limit = 0xffff;
541
542 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
543 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
544
545 save->efer = MSR_EFER_SVME_MASK;
546
547 save->dr6 = 0xffff0ff0;
548 save->dr7 = 0x400;
549 save->rflags = 2;
550 save->rip = 0x0000fff0;
551
552 /*
553 * cr0 val on cpu init should be 0x60000010, we enable cpu
554 * cache by default. the orderly way is to enable cache in bios.
555 */
556 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
557 save->cr4 = X86_CR4_PAE;
558 /* rdx = ?? */
559 }
560
561 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
562 {
563 struct vcpu_svm *svm = to_svm(vcpu);
564
565 init_vmcb(svm->vmcb);
566
567 if (vcpu->vcpu_id != 0) {
568 svm->vmcb->save.rip = 0;
569 svm->vmcb->save.cs.base = svm->vcpu.sipi_vector << 12;
570 svm->vmcb->save.cs.selector = svm->vcpu.sipi_vector << 8;
571 }
572 }
573
574 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
575 {
576 struct vcpu_svm *svm;
577 struct page *page;
578 int err;
579
580 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
581 if (!svm) {
582 err = -ENOMEM;
583 goto out;
584 }
585
586 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
587 if (err)
588 goto free_svm;
589
590 if (irqchip_in_kernel(kvm)) {
591 err = kvm_create_lapic(&svm->vcpu);
592 if (err < 0)
593 goto free_svm;
594 }
595
596 page = alloc_page(GFP_KERNEL);
597 if (!page) {
598 err = -ENOMEM;
599 goto uninit;
600 }
601
602 svm->vmcb = page_address(page);
603 clear_page(svm->vmcb);
604 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
605 svm->asid_generation = 0;
606 memset(svm->db_regs, 0, sizeof(svm->db_regs));
607 init_vmcb(svm->vmcb);
608
609 fx_init(&svm->vcpu);
610 svm->vcpu.fpu_active = 1;
611 svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
612 if (svm->vcpu.vcpu_id == 0)
613 svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
614
615 return &svm->vcpu;
616
617 uninit:
618 kvm_vcpu_uninit(&svm->vcpu);
619 free_svm:
620 kmem_cache_free(kvm_vcpu_cache, svm);
621 out:
622 return ERR_PTR(err);
623 }
624
625 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
626 {
627 struct vcpu_svm *svm = to_svm(vcpu);
628
629 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
630 kvm_vcpu_uninit(vcpu);
631 kmem_cache_free(kvm_vcpu_cache, svm);
632 }
633
634 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
635 {
636 struct vcpu_svm *svm = to_svm(vcpu);
637 int i;
638
639 if (unlikely(cpu != vcpu->cpu)) {
640 u64 tsc_this, delta;
641
642 /*
643 * Make sure that the guest sees a monotonically
644 * increasing TSC.
645 */
646 rdtscll(tsc_this);
647 delta = vcpu->host_tsc - tsc_this;
648 svm->vmcb->control.tsc_offset += delta;
649 vcpu->cpu = cpu;
650 kvm_migrate_apic_timer(vcpu);
651 }
652
653 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
654 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
655 }
656
657 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
658 {
659 struct vcpu_svm *svm = to_svm(vcpu);
660 int i;
661
662 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
663 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
664
665 rdtscll(vcpu->host_tsc);
666 kvm_put_guest_fpu(vcpu);
667 }
668
669 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
670 {
671 }
672
673 static void svm_cache_regs(struct kvm_vcpu *vcpu)
674 {
675 struct vcpu_svm *svm = to_svm(vcpu);
676
677 vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
678 vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
679 vcpu->rip = svm->vmcb->save.rip;
680 }
681
682 static void svm_decache_regs(struct kvm_vcpu *vcpu)
683 {
684 struct vcpu_svm *svm = to_svm(vcpu);
685 svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
686 svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
687 svm->vmcb->save.rip = vcpu->rip;
688 }
689
690 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
691 {
692 return to_svm(vcpu)->vmcb->save.rflags;
693 }
694
695 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
696 {
697 to_svm(vcpu)->vmcb->save.rflags = rflags;
698 }
699
700 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
701 {
702 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
703
704 switch (seg) {
705 case VCPU_SREG_CS: return &save->cs;
706 case VCPU_SREG_DS: return &save->ds;
707 case VCPU_SREG_ES: return &save->es;
708 case VCPU_SREG_FS: return &save->fs;
709 case VCPU_SREG_GS: return &save->gs;
710 case VCPU_SREG_SS: return &save->ss;
711 case VCPU_SREG_TR: return &save->tr;
712 case VCPU_SREG_LDTR: return &save->ldtr;
713 }
714 BUG();
715 return NULL;
716 }
717
718 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
719 {
720 struct vmcb_seg *s = svm_seg(vcpu, seg);
721
722 return s->base;
723 }
724
725 static void svm_get_segment(struct kvm_vcpu *vcpu,
726 struct kvm_segment *var, int seg)
727 {
728 struct vmcb_seg *s = svm_seg(vcpu, seg);
729
730 var->base = s->base;
731 var->limit = s->limit;
732 var->selector = s->selector;
733 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
734 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
735 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
736 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
737 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
738 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
739 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
740 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
741 var->unusable = !var->present;
742 }
743
744 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
745 {
746 struct vcpu_svm *svm = to_svm(vcpu);
747
748 dt->limit = svm->vmcb->save.idtr.limit;
749 dt->base = svm->vmcb->save.idtr.base;
750 }
751
752 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
753 {
754 struct vcpu_svm *svm = to_svm(vcpu);
755
756 svm->vmcb->save.idtr.limit = dt->limit;
757 svm->vmcb->save.idtr.base = dt->base ;
758 }
759
760 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
761 {
762 struct vcpu_svm *svm = to_svm(vcpu);
763
764 dt->limit = svm->vmcb->save.gdtr.limit;
765 dt->base = svm->vmcb->save.gdtr.base;
766 }
767
768 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
769 {
770 struct vcpu_svm *svm = to_svm(vcpu);
771
772 svm->vmcb->save.gdtr.limit = dt->limit;
773 svm->vmcb->save.gdtr.base = dt->base ;
774 }
775
776 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
777 {
778 }
779
780 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
781 {
782 struct vcpu_svm *svm = to_svm(vcpu);
783
784 #ifdef CONFIG_X86_64
785 if (vcpu->shadow_efer & KVM_EFER_LME) {
786 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
787 vcpu->shadow_efer |= KVM_EFER_LMA;
788 svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
789 }
790
791 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) {
792 vcpu->shadow_efer &= ~KVM_EFER_LMA;
793 svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
794 }
795 }
796 #endif
797 if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
798 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
799 vcpu->fpu_active = 1;
800 }
801
802 vcpu->cr0 = cr0;
803 cr0 |= X86_CR0_PG | X86_CR0_WP;
804 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
805 svm->vmcb->save.cr0 = cr0;
806 }
807
808 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
809 {
810 vcpu->cr4 = cr4;
811 to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
812 }
813
814 static void svm_set_segment(struct kvm_vcpu *vcpu,
815 struct kvm_segment *var, int seg)
816 {
817 struct vcpu_svm *svm = to_svm(vcpu);
818 struct vmcb_seg *s = svm_seg(vcpu, seg);
819
820 s->base = var->base;
821 s->limit = var->limit;
822 s->selector = var->selector;
823 if (var->unusable)
824 s->attrib = 0;
825 else {
826 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
827 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
828 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
829 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
830 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
831 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
832 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
833 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
834 }
835 if (seg == VCPU_SREG_CS)
836 svm->vmcb->save.cpl
837 = (svm->vmcb->save.cs.attrib
838 >> SVM_SELECTOR_DPL_SHIFT) & 3;
839
840 }
841
842 /* FIXME:
843
844 svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
845 svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
846
847 */
848
849 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
850 {
851 return -EOPNOTSUPP;
852 }
853
854 static int svm_get_irq(struct kvm_vcpu *vcpu)
855 {
856 struct vcpu_svm *svm = to_svm(vcpu);
857 u32 exit_int_info = svm->vmcb->control.exit_int_info;
858
859 if (is_external_interrupt(exit_int_info))
860 return exit_int_info & SVM_EVTINJ_VEC_MASK;
861 return -1;
862 }
863
864 static void load_host_msrs(struct kvm_vcpu *vcpu)
865 {
866 #ifdef CONFIG_X86_64
867 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
868 #endif
869 }
870
871 static void save_host_msrs(struct kvm_vcpu *vcpu)
872 {
873 #ifdef CONFIG_X86_64
874 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
875 #endif
876 }
877
878 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
879 {
880 if (svm_data->next_asid > svm_data->max_asid) {
881 ++svm_data->asid_generation;
882 svm_data->next_asid = 1;
883 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
884 }
885
886 svm->vcpu.cpu = svm_data->cpu;
887 svm->asid_generation = svm_data->asid_generation;
888 svm->vmcb->control.asid = svm_data->next_asid++;
889 }
890
891 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
892 {
893 return to_svm(vcpu)->db_regs[dr];
894 }
895
896 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
897 int *exception)
898 {
899 struct vcpu_svm *svm = to_svm(vcpu);
900
901 *exception = 0;
902
903 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
904 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
905 svm->vmcb->save.dr6 |= DR6_BD_MASK;
906 *exception = DB_VECTOR;
907 return;
908 }
909
910 switch (dr) {
911 case 0 ... 3:
912 svm->db_regs[dr] = value;
913 return;
914 case 4 ... 5:
915 if (vcpu->cr4 & X86_CR4_DE) {
916 *exception = UD_VECTOR;
917 return;
918 }
919 case 7: {
920 if (value & ~((1ULL << 32) - 1)) {
921 *exception = GP_VECTOR;
922 return;
923 }
924 svm->vmcb->save.dr7 = value;
925 return;
926 }
927 default:
928 printk(KERN_DEBUG "%s: unexpected dr %u\n",
929 __FUNCTION__, dr);
930 *exception = UD_VECTOR;
931 return;
932 }
933 }
934
935 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
936 {
937 u32 exit_int_info = svm->vmcb->control.exit_int_info;
938 struct kvm *kvm = svm->vcpu.kvm;
939 u64 fault_address;
940 u32 error_code;
941 enum emulation_result er;
942 int r;
943
944 if (!irqchip_in_kernel(kvm) &&
945 is_external_interrupt(exit_int_info))
946 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
947
948 mutex_lock(&kvm->lock);
949
950 fault_address = svm->vmcb->control.exit_info_2;
951 error_code = svm->vmcb->control.exit_info_1;
952 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
953 if (r < 0) {
954 mutex_unlock(&kvm->lock);
955 return r;
956 }
957 if (!r) {
958 mutex_unlock(&kvm->lock);
959 return 1;
960 }
961 er = emulate_instruction(&svm->vcpu, kvm_run, fault_address,
962 error_code);
963 mutex_unlock(&kvm->lock);
964
965 switch (er) {
966 case EMULATE_DONE:
967 return 1;
968 case EMULATE_DO_MMIO:
969 ++svm->vcpu.stat.mmio_exits;
970 return 0;
971 case EMULATE_FAIL:
972 kvm_report_emulation_failure(&svm->vcpu, "pagetable");
973 break;
974 default:
975 BUG();
976 }
977
978 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
979 return 0;
980 }
981
982 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
983 {
984 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
985 if (!(svm->vcpu.cr0 & X86_CR0_TS))
986 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
987 svm->vcpu.fpu_active = 1;
988
989 return 1;
990 }
991
992 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
993 {
994 /*
995 * VMCB is undefined after a SHUTDOWN intercept
996 * so reinitialize it.
997 */
998 clear_page(svm->vmcb);
999 init_vmcb(svm->vmcb);
1000
1001 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1002 return 0;
1003 }
1004
1005 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1006 {
1007 u32 io_info = svm->vmcb->control.exit_info_1; //address size bug?
1008 int size, down, in, string, rep;
1009 unsigned port;
1010
1011 ++svm->vcpu.stat.io_exits;
1012
1013 svm->next_rip = svm->vmcb->control.exit_info_2;
1014
1015 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1016
1017 if (string) {
1018 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO)
1019 return 0;
1020 return 1;
1021 }
1022
1023 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1024 port = io_info >> 16;
1025 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1026 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1027 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1028
1029 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1030 }
1031
1032 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1033 {
1034 return 1;
1035 }
1036
1037 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1038 {
1039 svm->next_rip = svm->vmcb->save.rip + 1;
1040 skip_emulated_instruction(&svm->vcpu);
1041 return kvm_emulate_halt(&svm->vcpu);
1042 }
1043
1044 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1045 {
1046 svm->next_rip = svm->vmcb->save.rip + 3;
1047 skip_emulated_instruction(&svm->vcpu);
1048 return kvm_hypercall(&svm->vcpu, kvm_run);
1049 }
1050
1051 static int invalid_op_interception(struct vcpu_svm *svm,
1052 struct kvm_run *kvm_run)
1053 {
1054 inject_ud(&svm->vcpu);
1055 return 1;
1056 }
1057
1058 static int task_switch_interception(struct vcpu_svm *svm,
1059 struct kvm_run *kvm_run)
1060 {
1061 pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1062 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1063 return 0;
1064 }
1065
1066 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1067 {
1068 svm->next_rip = svm->vmcb->save.rip + 2;
1069 kvm_emulate_cpuid(&svm->vcpu);
1070 return 1;
1071 }
1072
1073 static int emulate_on_interception(struct vcpu_svm *svm,
1074 struct kvm_run *kvm_run)
1075 {
1076 if (emulate_instruction(&svm->vcpu, NULL, 0, 0) != EMULATE_DONE)
1077 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1078 return 1;
1079 }
1080
1081 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1082 {
1083 struct vcpu_svm *svm = to_svm(vcpu);
1084
1085 switch (ecx) {
1086 case MSR_IA32_TIME_STAMP_COUNTER: {
1087 u64 tsc;
1088
1089 rdtscll(tsc);
1090 *data = svm->vmcb->control.tsc_offset + tsc;
1091 break;
1092 }
1093 case MSR_K6_STAR:
1094 *data = svm->vmcb->save.star;
1095 break;
1096 #ifdef CONFIG_X86_64
1097 case MSR_LSTAR:
1098 *data = svm->vmcb->save.lstar;
1099 break;
1100 case MSR_CSTAR:
1101 *data = svm->vmcb->save.cstar;
1102 break;
1103 case MSR_KERNEL_GS_BASE:
1104 *data = svm->vmcb->save.kernel_gs_base;
1105 break;
1106 case MSR_SYSCALL_MASK:
1107 *data = svm->vmcb->save.sfmask;
1108 break;
1109 #endif
1110 case MSR_IA32_SYSENTER_CS:
1111 *data = svm->vmcb->save.sysenter_cs;
1112 break;
1113 case MSR_IA32_SYSENTER_EIP:
1114 *data = svm->vmcb->save.sysenter_eip;
1115 break;
1116 case MSR_IA32_SYSENTER_ESP:
1117 *data = svm->vmcb->save.sysenter_esp;
1118 break;
1119 default:
1120 return kvm_get_msr_common(vcpu, ecx, data);
1121 }
1122 return 0;
1123 }
1124
1125 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1126 {
1127 u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1128 u64 data;
1129
1130 if (svm_get_msr(&svm->vcpu, ecx, &data))
1131 svm_inject_gp(&svm->vcpu, 0);
1132 else {
1133 svm->vmcb->save.rax = data & 0xffffffff;
1134 svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32;
1135 svm->next_rip = svm->vmcb->save.rip + 2;
1136 skip_emulated_instruction(&svm->vcpu);
1137 }
1138 return 1;
1139 }
1140
1141 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1142 {
1143 struct vcpu_svm *svm = to_svm(vcpu);
1144
1145 switch (ecx) {
1146 case MSR_IA32_TIME_STAMP_COUNTER: {
1147 u64 tsc;
1148
1149 rdtscll(tsc);
1150 svm->vmcb->control.tsc_offset = data - tsc;
1151 break;
1152 }
1153 case MSR_K6_STAR:
1154 svm->vmcb->save.star = data;
1155 break;
1156 #ifdef CONFIG_X86_64
1157 case MSR_LSTAR:
1158 svm->vmcb->save.lstar = data;
1159 break;
1160 case MSR_CSTAR:
1161 svm->vmcb->save.cstar = data;
1162 break;
1163 case MSR_KERNEL_GS_BASE:
1164 svm->vmcb->save.kernel_gs_base = data;
1165 break;
1166 case MSR_SYSCALL_MASK:
1167 svm->vmcb->save.sfmask = data;
1168 break;
1169 #endif
1170 case MSR_IA32_SYSENTER_CS:
1171 svm->vmcb->save.sysenter_cs = data;
1172 break;
1173 case MSR_IA32_SYSENTER_EIP:
1174 svm->vmcb->save.sysenter_eip = data;
1175 break;
1176 case MSR_IA32_SYSENTER_ESP:
1177 svm->vmcb->save.sysenter_esp = data;
1178 break;
1179 default:
1180 return kvm_set_msr_common(vcpu, ecx, data);
1181 }
1182 return 0;
1183 }
1184
1185 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1186 {
1187 u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1188 u64 data = (svm->vmcb->save.rax & -1u)
1189 | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32);
1190 svm->next_rip = svm->vmcb->save.rip + 2;
1191 if (svm_set_msr(&svm->vcpu, ecx, data))
1192 svm_inject_gp(&svm->vcpu, 0);
1193 else
1194 skip_emulated_instruction(&svm->vcpu);
1195 return 1;
1196 }
1197
1198 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1199 {
1200 if (svm->vmcb->control.exit_info_1)
1201 return wrmsr_interception(svm, kvm_run);
1202 else
1203 return rdmsr_interception(svm, kvm_run);
1204 }
1205
1206 static int interrupt_window_interception(struct vcpu_svm *svm,
1207 struct kvm_run *kvm_run)
1208 {
1209 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1210 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1211 /*
1212 * If the user space waits to inject interrupts, exit as soon as
1213 * possible
1214 */
1215 if (kvm_run->request_interrupt_window &&
1216 !svm->vcpu.irq_summary) {
1217 ++svm->vcpu.stat.irq_window_exits;
1218 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1219 return 0;
1220 }
1221
1222 return 1;
1223 }
1224
1225 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1226 struct kvm_run *kvm_run) = {
1227 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1228 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1229 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1230 /* for now: */
1231 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1232 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1233 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1234 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1235 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1236 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1237 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1238 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1239 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1240 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1241 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1242 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1243 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1244 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1245 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
1246 [SVM_EXIT_INTR] = nop_on_interception,
1247 [SVM_EXIT_NMI] = nop_on_interception,
1248 [SVM_EXIT_SMI] = nop_on_interception,
1249 [SVM_EXIT_INIT] = nop_on_interception,
1250 [SVM_EXIT_VINTR] = interrupt_window_interception,
1251 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1252 [SVM_EXIT_CPUID] = cpuid_interception,
1253 [SVM_EXIT_INVD] = emulate_on_interception,
1254 [SVM_EXIT_HLT] = halt_interception,
1255 [SVM_EXIT_INVLPG] = emulate_on_interception,
1256 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1257 [SVM_EXIT_IOIO] = io_interception,
1258 [SVM_EXIT_MSR] = msr_interception,
1259 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1260 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1261 [SVM_EXIT_VMRUN] = invalid_op_interception,
1262 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1263 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1264 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1265 [SVM_EXIT_STGI] = invalid_op_interception,
1266 [SVM_EXIT_CLGI] = invalid_op_interception,
1267 [SVM_EXIT_SKINIT] = invalid_op_interception,
1268 [SVM_EXIT_WBINVD] = emulate_on_interception,
1269 [SVM_EXIT_MONITOR] = invalid_op_interception,
1270 [SVM_EXIT_MWAIT] = invalid_op_interception,
1271 };
1272
1273
1274 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1275 {
1276 struct vcpu_svm *svm = to_svm(vcpu);
1277 u32 exit_code = svm->vmcb->control.exit_code;
1278
1279 kvm_reput_irq(svm);
1280
1281 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1282 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1283 kvm_run->fail_entry.hardware_entry_failure_reason
1284 = svm->vmcb->control.exit_code;
1285 return 0;
1286 }
1287
1288 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1289 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1290 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1291 "exit_code 0x%x\n",
1292 __FUNCTION__, svm->vmcb->control.exit_int_info,
1293 exit_code);
1294
1295 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1296 || svm_exit_handlers[exit_code] == 0) {
1297 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1298 kvm_run->hw.hardware_exit_reason = exit_code;
1299 return 0;
1300 }
1301
1302 return svm_exit_handlers[exit_code](svm, kvm_run);
1303 }
1304
1305 static void reload_tss(struct kvm_vcpu *vcpu)
1306 {
1307 int cpu = raw_smp_processor_id();
1308
1309 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1310 svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1311 load_TR_desc();
1312 }
1313
1314 static void pre_svm_run(struct vcpu_svm *svm)
1315 {
1316 int cpu = raw_smp_processor_id();
1317
1318 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1319
1320 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1321 if (svm->vcpu.cpu != cpu ||
1322 svm->asid_generation != svm_data->asid_generation)
1323 new_asid(svm, svm_data);
1324 }
1325
1326
1327 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1328 {
1329 struct vmcb_control_area *control;
1330
1331 control = &svm->vmcb->control;
1332 control->int_vector = irq;
1333 control->int_ctl &= ~V_INTR_PRIO_MASK;
1334 control->int_ctl |= V_IRQ_MASK |
1335 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1336 }
1337
1338 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1339 {
1340 struct vcpu_svm *svm = to_svm(vcpu);
1341
1342 svm_inject_irq(svm, irq);
1343 }
1344
1345 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1346 {
1347 struct vcpu_svm *svm = to_svm(vcpu);
1348 struct vmcb *vmcb = svm->vmcb;
1349 int intr_vector = -1;
1350
1351 kvm_inject_pending_timer_irqs(vcpu);
1352 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1353 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1354 intr_vector = vmcb->control.exit_int_info &
1355 SVM_EVTINJ_VEC_MASK;
1356 vmcb->control.exit_int_info = 0;
1357 svm_inject_irq(svm, intr_vector);
1358 return;
1359 }
1360
1361 if (vmcb->control.int_ctl & V_IRQ_MASK)
1362 return;
1363
1364 if (!kvm_cpu_has_interrupt(vcpu))
1365 return;
1366
1367 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1368 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1369 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1370 /* unable to deliver irq, set pending irq */
1371 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1372 svm_inject_irq(svm, 0x0);
1373 return;
1374 }
1375 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1376 intr_vector = kvm_cpu_get_interrupt(vcpu);
1377 svm_inject_irq(svm, intr_vector);
1378 kvm_timer_intr_post(vcpu, intr_vector);
1379 }
1380
1381 static void kvm_reput_irq(struct vcpu_svm *svm)
1382 {
1383 struct vmcb_control_area *control = &svm->vmcb->control;
1384
1385 if ((control->int_ctl & V_IRQ_MASK)
1386 && !irqchip_in_kernel(svm->vcpu.kvm)) {
1387 control->int_ctl &= ~V_IRQ_MASK;
1388 push_irq(&svm->vcpu, control->int_vector);
1389 }
1390
1391 svm->vcpu.interrupt_window_open =
1392 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1393 }
1394
1395 static void svm_do_inject_vector(struct vcpu_svm *svm)
1396 {
1397 struct kvm_vcpu *vcpu = &svm->vcpu;
1398 int word_index = __ffs(vcpu->irq_summary);
1399 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1400 int irq = word_index * BITS_PER_LONG + bit_index;
1401
1402 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1403 if (!vcpu->irq_pending[word_index])
1404 clear_bit(word_index, &vcpu->irq_summary);
1405 svm_inject_irq(svm, irq);
1406 }
1407
1408 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1409 struct kvm_run *kvm_run)
1410 {
1411 struct vcpu_svm *svm = to_svm(vcpu);
1412 struct vmcb_control_area *control = &svm->vmcb->control;
1413
1414 svm->vcpu.interrupt_window_open =
1415 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1416 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1417
1418 if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary)
1419 /*
1420 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1421 */
1422 svm_do_inject_vector(svm);
1423
1424 /*
1425 * Interrupts blocked. Wait for unblock.
1426 */
1427 if (!svm->vcpu.interrupt_window_open &&
1428 (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) {
1429 control->intercept |= 1ULL << INTERCEPT_VINTR;
1430 } else
1431 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1432 }
1433
1434 static void save_db_regs(unsigned long *db_regs)
1435 {
1436 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1437 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1438 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1439 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1440 }
1441
1442 static void load_db_regs(unsigned long *db_regs)
1443 {
1444 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1445 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1446 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1447 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1448 }
1449
1450 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1451 {
1452 force_new_asid(vcpu);
1453 }
1454
1455 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1456 {
1457 }
1458
1459 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1460 {
1461 struct vcpu_svm *svm = to_svm(vcpu);
1462 u16 fs_selector;
1463 u16 gs_selector;
1464 u16 ldt_selector;
1465
1466 pre_svm_run(svm);
1467
1468 save_host_msrs(vcpu);
1469 fs_selector = read_fs();
1470 gs_selector = read_gs();
1471 ldt_selector = read_ldt();
1472 svm->host_cr2 = kvm_read_cr2();
1473 svm->host_dr6 = read_dr6();
1474 svm->host_dr7 = read_dr7();
1475 svm->vmcb->save.cr2 = vcpu->cr2;
1476
1477 if (svm->vmcb->save.dr7 & 0xff) {
1478 write_dr7(0);
1479 save_db_regs(svm->host_db_regs);
1480 load_db_regs(svm->db_regs);
1481 }
1482
1483 clgi();
1484
1485 local_irq_enable();
1486
1487 asm volatile (
1488 #ifdef CONFIG_X86_64
1489 "push %%rbx; push %%rcx; push %%rdx;"
1490 "push %%rsi; push %%rdi; push %%rbp;"
1491 "push %%r8; push %%r9; push %%r10; push %%r11;"
1492 "push %%r12; push %%r13; push %%r14; push %%r15;"
1493 #else
1494 "push %%ebx; push %%ecx; push %%edx;"
1495 "push %%esi; push %%edi; push %%ebp;"
1496 #endif
1497
1498 #ifdef CONFIG_X86_64
1499 "mov %c[rbx](%[svm]), %%rbx \n\t"
1500 "mov %c[rcx](%[svm]), %%rcx \n\t"
1501 "mov %c[rdx](%[svm]), %%rdx \n\t"
1502 "mov %c[rsi](%[svm]), %%rsi \n\t"
1503 "mov %c[rdi](%[svm]), %%rdi \n\t"
1504 "mov %c[rbp](%[svm]), %%rbp \n\t"
1505 "mov %c[r8](%[svm]), %%r8 \n\t"
1506 "mov %c[r9](%[svm]), %%r9 \n\t"
1507 "mov %c[r10](%[svm]), %%r10 \n\t"
1508 "mov %c[r11](%[svm]), %%r11 \n\t"
1509 "mov %c[r12](%[svm]), %%r12 \n\t"
1510 "mov %c[r13](%[svm]), %%r13 \n\t"
1511 "mov %c[r14](%[svm]), %%r14 \n\t"
1512 "mov %c[r15](%[svm]), %%r15 \n\t"
1513 #else
1514 "mov %c[rbx](%[svm]), %%ebx \n\t"
1515 "mov %c[rcx](%[svm]), %%ecx \n\t"
1516 "mov %c[rdx](%[svm]), %%edx \n\t"
1517 "mov %c[rsi](%[svm]), %%esi \n\t"
1518 "mov %c[rdi](%[svm]), %%edi \n\t"
1519 "mov %c[rbp](%[svm]), %%ebp \n\t"
1520 #endif
1521
1522 #ifdef CONFIG_X86_64
1523 /* Enter guest mode */
1524 "push %%rax \n\t"
1525 "mov %c[vmcb](%[svm]), %%rax \n\t"
1526 SVM_VMLOAD "\n\t"
1527 SVM_VMRUN "\n\t"
1528 SVM_VMSAVE "\n\t"
1529 "pop %%rax \n\t"
1530 #else
1531 /* Enter guest mode */
1532 "push %%eax \n\t"
1533 "mov %c[vmcb](%[svm]), %%eax \n\t"
1534 SVM_VMLOAD "\n\t"
1535 SVM_VMRUN "\n\t"
1536 SVM_VMSAVE "\n\t"
1537 "pop %%eax \n\t"
1538 #endif
1539
1540 /* Save guest registers, load host registers */
1541 #ifdef CONFIG_X86_64
1542 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1543 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1544 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1545 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1546 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1547 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1548 "mov %%r8, %c[r8](%[svm]) \n\t"
1549 "mov %%r9, %c[r9](%[svm]) \n\t"
1550 "mov %%r10, %c[r10](%[svm]) \n\t"
1551 "mov %%r11, %c[r11](%[svm]) \n\t"
1552 "mov %%r12, %c[r12](%[svm]) \n\t"
1553 "mov %%r13, %c[r13](%[svm]) \n\t"
1554 "mov %%r14, %c[r14](%[svm]) \n\t"
1555 "mov %%r15, %c[r15](%[svm]) \n\t"
1556
1557 "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1558 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1559 "pop %%rbp; pop %%rdi; pop %%rsi;"
1560 "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
1561 #else
1562 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1563 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1564 "mov %%edx, %c[rdx](%[svm]) \n\t"
1565 "mov %%esi, %c[rsi](%[svm]) \n\t"
1566 "mov %%edi, %c[rdi](%[svm]) \n\t"
1567 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1568
1569 "pop %%ebp; pop %%edi; pop %%esi;"
1570 "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
1571 #endif
1572 :
1573 : [svm]"a"(svm),
1574 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1575 [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])),
1576 [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])),
1577 [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])),
1578 [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])),
1579 [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])),
1580 [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP]))
1581 #ifdef CONFIG_X86_64
1582 ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])),
1583 [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])),
1584 [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])),
1585 [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])),
1586 [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])),
1587 [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])),
1588 [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])),
1589 [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15]))
1590 #endif
1591 : "cc", "memory" );
1592
1593 if ((svm->vmcb->save.dr7 & 0xff))
1594 load_db_regs(svm->host_db_regs);
1595
1596 vcpu->cr2 = svm->vmcb->save.cr2;
1597
1598 write_dr6(svm->host_dr6);
1599 write_dr7(svm->host_dr7);
1600 kvm_write_cr2(svm->host_cr2);
1601
1602 load_fs(fs_selector);
1603 load_gs(gs_selector);
1604 load_ldt(ldt_selector);
1605 load_host_msrs(vcpu);
1606
1607 reload_tss(vcpu);
1608
1609 local_irq_disable();
1610
1611 stgi();
1612
1613 svm->next_rip = 0;
1614 }
1615
1616 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1617 {
1618 struct vcpu_svm *svm = to_svm(vcpu);
1619
1620 svm->vmcb->save.cr3 = root;
1621 force_new_asid(vcpu);
1622
1623 if (vcpu->fpu_active) {
1624 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1625 svm->vmcb->save.cr0 |= X86_CR0_TS;
1626 vcpu->fpu_active = 0;
1627 }
1628 }
1629
1630 static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1631 unsigned long addr,
1632 uint32_t err_code)
1633 {
1634 struct vcpu_svm *svm = to_svm(vcpu);
1635 uint32_t exit_int_info = svm->vmcb->control.exit_int_info;
1636
1637 ++vcpu->stat.pf_guest;
1638
1639 if (is_page_fault(exit_int_info)) {
1640
1641 svm->vmcb->control.event_inj_err = 0;
1642 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1643 SVM_EVTINJ_VALID_ERR |
1644 SVM_EVTINJ_TYPE_EXEPT |
1645 DF_VECTOR;
1646 return;
1647 }
1648 vcpu->cr2 = addr;
1649 svm->vmcb->save.cr2 = addr;
1650 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1651 SVM_EVTINJ_VALID_ERR |
1652 SVM_EVTINJ_TYPE_EXEPT |
1653 PF_VECTOR;
1654 svm->vmcb->control.event_inj_err = err_code;
1655 }
1656
1657
1658 static int is_disabled(void)
1659 {
1660 u64 vm_cr;
1661
1662 rdmsrl(MSR_VM_CR, vm_cr);
1663 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1664 return 1;
1665
1666 return 0;
1667 }
1668
1669 static void
1670 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1671 {
1672 /*
1673 * Patch in the VMMCALL instruction:
1674 */
1675 hypercall[0] = 0x0f;
1676 hypercall[1] = 0x01;
1677 hypercall[2] = 0xd9;
1678 hypercall[3] = 0xc3;
1679 }
1680
1681 static void svm_check_processor_compat(void *rtn)
1682 {
1683 *(int *)rtn = 0;
1684 }
1685
1686 static struct kvm_x86_ops svm_x86_ops = {
1687 .cpu_has_kvm_support = has_svm,
1688 .disabled_by_bios = is_disabled,
1689 .hardware_setup = svm_hardware_setup,
1690 .hardware_unsetup = svm_hardware_unsetup,
1691 .check_processor_compatibility = svm_check_processor_compat,
1692 .hardware_enable = svm_hardware_enable,
1693 .hardware_disable = svm_hardware_disable,
1694
1695 .vcpu_create = svm_create_vcpu,
1696 .vcpu_free = svm_free_vcpu,
1697 .vcpu_reset = svm_vcpu_reset,
1698
1699 .prepare_guest_switch = svm_prepare_guest_switch,
1700 .vcpu_load = svm_vcpu_load,
1701 .vcpu_put = svm_vcpu_put,
1702 .vcpu_decache = svm_vcpu_decache,
1703
1704 .set_guest_debug = svm_guest_debug,
1705 .get_msr = svm_get_msr,
1706 .set_msr = svm_set_msr,
1707 .get_segment_base = svm_get_segment_base,
1708 .get_segment = svm_get_segment,
1709 .set_segment = svm_set_segment,
1710 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1711 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1712 .set_cr0 = svm_set_cr0,
1713 .set_cr3 = svm_set_cr3,
1714 .set_cr4 = svm_set_cr4,
1715 .set_efer = svm_set_efer,
1716 .get_idt = svm_get_idt,
1717 .set_idt = svm_set_idt,
1718 .get_gdt = svm_get_gdt,
1719 .set_gdt = svm_set_gdt,
1720 .get_dr = svm_get_dr,
1721 .set_dr = svm_set_dr,
1722 .cache_regs = svm_cache_regs,
1723 .decache_regs = svm_decache_regs,
1724 .get_rflags = svm_get_rflags,
1725 .set_rflags = svm_set_rflags,
1726
1727 .tlb_flush = svm_flush_tlb,
1728 .inject_page_fault = svm_inject_page_fault,
1729
1730 .inject_gp = svm_inject_gp,
1731
1732 .run = svm_vcpu_run,
1733 .handle_exit = handle_exit,
1734 .skip_emulated_instruction = skip_emulated_instruction,
1735 .patch_hypercall = svm_patch_hypercall,
1736 .get_irq = svm_get_irq,
1737 .set_irq = svm_set_irq,
1738 .inject_pending_irq = svm_intr_assist,
1739 .inject_pending_vectors = do_interrupt_requests,
1740 };
1741
1742 static int __init svm_init(void)
1743 {
1744 return kvm_init_x86(&svm_x86_ops, sizeof(struct vcpu_svm),
1745 THIS_MODULE);
1746 }
1747
1748 static void __exit svm_exit(void)
1749 {
1750 kvm_exit_x86();
1751 }
1752
1753 module_init(svm_init)
1754 module_exit(svm_exit)
kmemtrace - Kernel memory tracer