2 * include/asm-ppc/mpc85xx.h
6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
8 * Copyright 2004 Freescale Semiconductor, Inc
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
17 #ifndef __ASM_MPC85xx_H__
18 #define __ASM_MPC85xx_H__
20 #include <linux/config.h>
25 #ifdef CONFIG_MPC8540_ADS
26 #include <platforms/85xx/mpc8540_ads.h>
28 #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
29 #include <platforms/85xx/mpc8555_cds.h>
31 #ifdef CONFIG_MPC85xx_CDS
32 #include <platforms/85xx/mpc85xx_cds.h>
34 #ifdef CONFIG_MPC8560_ADS
35 #include <platforms/85xx/mpc8560_ads.h>
38 #include <platforms/85xx/sbc8560.h>
41 #include <platforms/85xx/stx_gp3.h>
43 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
44 defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
45 #include <platforms/85xx/tqm85xx.h>
48 #define _IO_BASE isa_io_base
49 #define _ISA_MEM_BASE isa_mem_base
51 #define PCI_DRAM_OFFSET pci_dram_offset
53 #define PCI_DRAM_OFFSET 0
57 * The "residual" board information structure the boot loader passes
60 extern unsigned char __res
[];
62 /* Offset from CCSRBAR */
63 #define MPC85xx_CPM_OFFSET (0x80000)
64 #define MPC85xx_CPM_SIZE (0x40000)
65 #define MPC85xx_DMA_OFFSET (0x21000)
66 #define MPC85xx_DMA_SIZE (0x01000)
67 #define MPC85xx_DMA0_OFFSET (0x21100)
68 #define MPC85xx_DMA0_SIZE (0x00080)
69 #define MPC85xx_DMA1_OFFSET (0x21180)
70 #define MPC85xx_DMA1_SIZE (0x00080)
71 #define MPC85xx_DMA2_OFFSET (0x21200)
72 #define MPC85xx_DMA2_SIZE (0x00080)
73 #define MPC85xx_DMA3_OFFSET (0x21280)
74 #define MPC85xx_DMA3_SIZE (0x00080)
75 #define MPC85xx_ENET1_OFFSET (0x24000)
76 #define MPC85xx_ENET1_SIZE (0x01000)
77 #define MPC85xx_MIIM_OFFSET (0x24520)
78 #define MPC85xx_MIIM_SIZE (0x00018)
79 #define MPC85xx_ENET2_OFFSET (0x25000)
80 #define MPC85xx_ENET2_SIZE (0x01000)
81 #define MPC85xx_ENET3_OFFSET (0x26000)
82 #define MPC85xx_ENET3_SIZE (0x01000)
83 #define MPC85xx_GUTS_OFFSET (0xe0000)
84 #define MPC85xx_GUTS_SIZE (0x01000)
85 #define MPC85xx_IIC1_OFFSET (0x03000)
86 #define MPC85xx_IIC1_SIZE (0x00100)
87 #define MPC85xx_OPENPIC_OFFSET (0x40000)
88 #define MPC85xx_OPENPIC_SIZE (0x40000)
89 #define MPC85xx_PCI1_OFFSET (0x08000)
90 #define MPC85xx_PCI1_SIZE (0x01000)
91 #define MPC85xx_PCI2_OFFSET (0x09000)
92 #define MPC85xx_PCI2_SIZE (0x01000)
93 #define MPC85xx_PERFMON_OFFSET (0xe1000)
94 #define MPC85xx_PERFMON_SIZE (0x01000)
95 #define MPC85xx_SEC2_OFFSET (0x30000)
96 #define MPC85xx_SEC2_SIZE (0x10000)
97 #define MPC85xx_UART0_OFFSET (0x04500)
98 #define MPC85xx_UART0_SIZE (0x00100)
99 #define MPC85xx_UART1_OFFSET (0x04600)
100 #define MPC85xx_UART1_SIZE (0x00100)
102 #define MPC85xx_CCSRBAR_SIZE (1024*1024)
104 /* Let modules/drivers get at CCSRBAR */
105 extern phys_addr_t
get_ccsrbar(void);
108 #define CCSRBAR get_ccsrbar()
110 #define CCSRBAR BOARD_CCSRBAR
113 enum ppc_sys_devices
{
148 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
149 #define MPC85XX_INTERNAL_IRQ_SENSES \
150 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
151 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
152 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
153 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
154 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
155 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
156 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
157 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
158 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
159 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
160 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
161 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
162 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
163 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
164 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
165 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
166 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
167 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
168 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
169 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
170 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
171 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
172 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
173 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
174 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
175 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
176 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
177 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
178 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
179 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
180 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
181 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
182 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
183 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
184 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
185 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
186 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
187 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
188 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
189 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
190 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
191 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
192 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
193 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
194 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
195 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
196 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
197 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
199 #endif /* CONFIG_85xx */
200 #endif /* __ASM_MPC85xx_H__ */
201 #endif /* __KERNEL__ */