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[ALSA] intel8x0 - Add buggy_semaphore option
[linux-2.6/kmemtrace.git] / drivers / ieee1394 / csr.c
blob149573db91c5a1dc35d727694de54263f0dc96f3
1 /*
2 * IEEE 1394 for Linux
3 *
4 * CSR implementation, iso/bus manager implementation.
5 *
6 * Copyright (C) 1999 Andreas E. Bombe
7 * 2002 Manfred Weihs <weihs@ict.tuwien.ac.at>
8 *
9 * This code is licensed under the GPL. See the file COPYING in the root
10 * directory of the kernel sources for details.
11 *
12 *
13 * Contributions:
14 *
15 * Manfred Weihs <weihs@ict.tuwien.ac.at>
16 * configuration ROM manipulation
17 *
18 */
19
20 #include <linux/string.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/param.h>
24 #include <linux/spinlock.h>
25
26 #include "csr1212.h"
27 #include "ieee1394_types.h"
28 #include "hosts.h"
29 #include "ieee1394.h"
30 #include "highlevel.h"
31 #include "ieee1394_core.h"
32
33 /* Module Parameters */
34 /* this module parameter can be used to disable mapping of the FCP registers */
35
36 static int fcp = 1;
37 module_param(fcp, int, 0444);
38 MODULE_PARM_DESC(fcp, "Map FCP registers (default = 1, disable = 0).");
39
40 static struct csr1212_keyval *node_cap = NULL;
41
42 static void add_host(struct hpsb_host *host);
43 static void remove_host(struct hpsb_host *host);
44 static void host_reset(struct hpsb_host *host);
45 static int read_maps(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
46 u64 addr, size_t length, u16 fl);
47 static int write_fcp(struct hpsb_host *host, int nodeid, int dest,
48 quadlet_t *data, u64 addr, size_t length, u16 flags);
49 static int read_regs(struct hpsb_host *host, int nodeid, quadlet_t *buf,
50 u64 addr, size_t length, u16 flags);
51 static int write_regs(struct hpsb_host *host, int nodeid, int destid,
52 quadlet_t *data, u64 addr, size_t length, u16 flags);
53 static int lock_regs(struct hpsb_host *host, int nodeid, quadlet_t *store,
54 u64 addr, quadlet_t data, quadlet_t arg, int extcode, u16 fl);
55 static int lock64_regs(struct hpsb_host *host, int nodeid, octlet_t * store,
56 u64 addr, octlet_t data, octlet_t arg, int extcode, u16 fl);
57 static int read_config_rom(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
58 u64 addr, size_t length, u16 fl);
59 static u64 allocate_addr_range(u64 size, u32 alignment, void *__host);
60 static void release_addr_range(u64 addr, void *__host);
61
62 static struct hpsb_highlevel csr_highlevel = {
63 .name = "standard registers",
64 .add_host = add_host,
65 .remove_host = remove_host,
66 .host_reset = host_reset,
67 };
68
69 static struct hpsb_address_ops map_ops = {
70 .read = read_maps,
71 };
72
73 static struct hpsb_address_ops fcp_ops = {
74 .write = write_fcp,
75 };
76
77 static struct hpsb_address_ops reg_ops = {
78 .read = read_regs,
79 .write = write_regs,
80 .lock = lock_regs,
81 .lock64 = lock64_regs,
82 };
83
84 static struct hpsb_address_ops config_rom_ops = {
85 .read = read_config_rom,
86 };
87
88 struct csr1212_bus_ops csr_bus_ops = {
89 .allocate_addr_range = allocate_addr_range,
90 .release_addr = release_addr_range,
91 };
92
93
94 static u16 csr_crc16(unsigned *data, int length)
95 {
96 int check=0, i;
97 int shift, sum, next=0;
98
99 for (i = length; i; i--) {
100 for (next = check, shift = 28; shift >= 0; shift -= 4 ) {
101 sum = ((next >> 12) ^ (be32_to_cpu(*data) >> shift)) & 0xf;
102 next = (next << 4) ^ (sum << 12) ^ (sum << 5) ^ (sum);
103 }
104 check = next & 0xffff;
105 data++;
106 }
107
108 return check;
109 }
110
111 static void host_reset(struct hpsb_host *host)
112 {
113 host->csr.state &= 0x300;
114
115 host->csr.bus_manager_id = 0x3f;
116 host->csr.bandwidth_available = 4915;
117 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */
118 host->csr.channels_available_lo = ~0;
119 host->csr.broadcast_channel = 0x80000000 | 31;
120
121 if (host->is_irm) {
122 if (host->driver->hw_csr_reg) {
123 host->driver->hw_csr_reg(host, 2, 0xfffffffe, ~0);
124 }
125 }
126
127 host->csr.node_ids = host->node_id << 16;
128
129 if (!host->is_root) {
130 /* clear cmstr bit */
131 host->csr.state &= ~0x100;
132 }
133
134 host->csr.topology_map[1] =
135 cpu_to_be32(be32_to_cpu(host->csr.topology_map[1]) + 1);
136 host->csr.topology_map[2] = cpu_to_be32(host->node_count << 16
137 | host->selfid_count);
138 host->csr.topology_map[0] =
139 cpu_to_be32((host->selfid_count + 2) << 16
140 | csr_crc16(host->csr.topology_map + 1,
141 host->selfid_count + 2));
142
143 host->csr.speed_map[1] =
144 cpu_to_be32(be32_to_cpu(host->csr.speed_map[1]) + 1);
145 host->csr.speed_map[0] = cpu_to_be32(0x3f1 << 16
146 | csr_crc16(host->csr.speed_map+1,
147 0x3f1));
148 }
149
150 /*
151 * HI == seconds (bits 0:2)
152 * LO == fraction units of 1/8000 of a second, as per 1394 (bits 19:31)
153 *
154 * Convert to units and then to HZ, for comparison to jiffies.
155 *
156 * By default this will end up being 800 units, or 100ms (125usec per
157 * unit).
158 *
159 * NOTE: The spec says 1/8000, but also says we can compute based on 1/8192
160 * like CSR specifies. Should make our math less complex.
161 */
162 static inline void calculate_expire(struct csr_control *csr)
163 {
164 unsigned long units;
165
166 /* Take the seconds, and convert to units */
167 units = (unsigned long)(csr->split_timeout_hi & 0x07) << 13;
168
169 /* Add in the fractional units */
170 units += (unsigned long)(csr->split_timeout_lo >> 19);
171
172 /* Convert to jiffies */
173 csr->expire = (unsigned long)(units * HZ) >> 13UL;
174
175 /* Just to keep from rounding low */
176 csr->expire++;
177
178 HPSB_VERBOSE("CSR: setting expire to %lu, HZ=%u", csr->expire, HZ);
179 }
180
181
182 static void add_host(struct hpsb_host *host)
183 {
184 struct csr1212_keyval *root;
185 quadlet_t bus_info[CSR_BUS_INFO_SIZE];
186
187 hpsb_register_addrspace(&csr_highlevel, host, &reg_ops,
188 CSR_REGISTER_BASE,
189 CSR_REGISTER_BASE + CSR_CONFIG_ROM);
190 hpsb_register_addrspace(&csr_highlevel, host, &config_rom_ops,
191 CSR_REGISTER_BASE + CSR_CONFIG_ROM,
192 CSR_REGISTER_BASE + CSR_CONFIG_ROM_END);
193 if (fcp) {
194 hpsb_register_addrspace(&csr_highlevel, host, &fcp_ops,
195 CSR_REGISTER_BASE + CSR_FCP_COMMAND,
196 CSR_REGISTER_BASE + CSR_FCP_END);
197 }
198 hpsb_register_addrspace(&csr_highlevel, host, &map_ops,
199 CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP,
200 CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP_END);
201 hpsb_register_addrspace(&csr_highlevel, host, &map_ops,
202 CSR_REGISTER_BASE + CSR_SPEED_MAP,
203 CSR_REGISTER_BASE + CSR_SPEED_MAP_END);
204
205 spin_lock_init(&host->csr.lock);
206
207 host->csr.state = 0;
208 host->csr.node_ids = 0;
209 host->csr.split_timeout_hi = 0;
210 host->csr.split_timeout_lo = 800 << 19;
211 calculate_expire(&host->csr);
212 host->csr.cycle_time = 0;
213 host->csr.bus_time = 0;
214 host->csr.bus_manager_id = 0x3f;
215 host->csr.bandwidth_available = 4915;
216 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */
217 host->csr.channels_available_lo = ~0;
218 host->csr.broadcast_channel = 0x80000000 | 31;
219
220 if (host->is_irm) {
221 if (host->driver->hw_csr_reg) {
222 host->driver->hw_csr_reg(host, 2, 0xfffffffe, ~0);
223 }
224 }
225
226 if (host->csr.max_rec >= 9)
227 host->csr.max_rom = 2;
228 else if (host->csr.max_rec >= 5)
229 host->csr.max_rom = 1;
230 else
231 host->csr.max_rom = 0;
232
233 host->csr.generation = 2;
234
235 bus_info[1] = __constant_cpu_to_be32(0x31333934);
236 bus_info[2] = cpu_to_be32((hpsb_disable_irm ? 0 : 1 << CSR_IRMC_SHIFT) |
237 (1 << CSR_CMC_SHIFT) |
238 (1 << CSR_ISC_SHIFT) |
239 (0 << CSR_BMC_SHIFT) |
240 (0 << CSR_PMC_SHIFT) |
241 (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) |
242 (host->csr.max_rec << CSR_MAX_REC_SHIFT) |
243 (host->csr.max_rom << CSR_MAX_ROM_SHIFT) |
244 (host->csr.generation << CSR_GENERATION_SHIFT) |
245 host->csr.lnk_spd);
246
247 bus_info[3] = cpu_to_be32(host->csr.guid_hi);
248 bus_info[4] = cpu_to_be32(host->csr.guid_lo);
249
250 /* The hardware copy of the bus info block will be set later when a
251 * bus reset is issued. */
252
253 csr1212_init_local_csr(host->csr.rom, bus_info, host->csr.max_rom);
254
255 root = host->csr.rom->root_kv;
256
257 if(csr1212_attach_keyval_to_directory(root, node_cap) != CSR1212_SUCCESS) {
258 HPSB_ERR("Failed to attach Node Capabilities to root directory");
259 }
260
261 host->update_config_rom = 1;
262 }
263
264 static void remove_host(struct hpsb_host *host)
265 {
266 quadlet_t bus_info[CSR_BUS_INFO_SIZE];
267
268 bus_info[1] = __constant_cpu_to_be32(0x31333934);
269 bus_info[2] = cpu_to_be32((0 << CSR_IRMC_SHIFT) |
270 (0 << CSR_CMC_SHIFT) |
271 (0 << CSR_ISC_SHIFT) |
272 (0 << CSR_BMC_SHIFT) |
273 (0 << CSR_PMC_SHIFT) |
274 (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) |
275 (host->csr.max_rec << CSR_MAX_REC_SHIFT) |
276 (0 << CSR_MAX_ROM_SHIFT) |
277 (0 << CSR_GENERATION_SHIFT) |
278 host->csr.lnk_spd);
279
280 bus_info[3] = cpu_to_be32(host->csr.guid_hi);
281 bus_info[4] = cpu_to_be32(host->csr.guid_lo);
282
283 csr1212_detach_keyval_from_directory(host->csr.rom->root_kv, node_cap);
284
285 csr1212_init_local_csr(host->csr.rom, bus_info, 0);
286 host->update_config_rom = 1;
287 }
288
289
290 int hpsb_update_config_rom(struct hpsb_host *host, const quadlet_t *new_rom,
291 size_t buffersize, unsigned char rom_version)
292 {
293 unsigned long flags;
294 int ret;
295
296 HPSB_NOTICE("hpsb_update_config_rom() is deprecated");
297
298 spin_lock_irqsave(&host->csr.lock, flags);
299 if (rom_version != host->csr.generation)
300 ret = -1;
301 else if (buffersize > host->csr.rom->cache_head->size)
302 ret = -2;
303 else {
304 /* Just overwrite the generated ConfigROM image with new data,
305 * it can be regenerated later. */
306 memcpy(host->csr.rom->cache_head->data, new_rom, buffersize);
307 host->csr.rom->cache_head->len = buffersize;
308
309 if (host->driver->set_hw_config_rom)
310 host->driver->set_hw_config_rom(host, host->csr.rom->bus_info_data);
311 /* Increment the generation number to keep some sort of sync
312 * with the newer ConfigROM manipulation method. */
313 host->csr.generation++;
314 if (host->csr.generation > 0xf || host->csr.generation < 2)
315 host->csr.generation = 2;
316 ret=0;
317 }
318 spin_unlock_irqrestore(&host->csr.lock, flags);
319 return ret;
320 }
321
322
323 /* Read topology / speed maps and configuration ROM */
324 static int read_maps(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
325 u64 addr, size_t length, u16 fl)
326 {
327 unsigned long flags;
328 int csraddr = addr - CSR_REGISTER_BASE;
329 const char *src;
330
331 spin_lock_irqsave(&host->csr.lock, flags);
332
333 if (csraddr < CSR_SPEED_MAP) {
334 src = ((char *)host->csr.topology_map) + csraddr
335 - CSR_TOPOLOGY_MAP;
336 } else {
337 src = ((char *)host->csr.speed_map) + csraddr - CSR_SPEED_MAP;
338 }
339
340 memcpy(buffer, src, length);
341 spin_unlock_irqrestore(&host->csr.lock, flags);
342 return RCODE_COMPLETE;
343 }
344
345
346 #define out if (--length == 0) break
347
348 static int read_regs(struct hpsb_host *host, int nodeid, quadlet_t *buf,
349 u64 addr, size_t length, u16 flags)
350 {
351 int csraddr = addr - CSR_REGISTER_BASE;
352 int oldcycle;
353 quadlet_t ret;
354
355 if ((csraddr | length) & 0x3)
356 return RCODE_TYPE_ERROR;
357
358 length /= 4;
359
360 switch (csraddr) {
361 case CSR_STATE_CLEAR:
362 *(buf++) = cpu_to_be32(host->csr.state);
363 out;
364 case CSR_STATE_SET:
365 *(buf++) = cpu_to_be32(host->csr.state);
366 out;
367 case CSR_NODE_IDS:
368 *(buf++) = cpu_to_be32(host->csr.node_ids);
369 out;
370
371 case CSR_RESET_START:
372 return RCODE_TYPE_ERROR;
373
374 /* address gap - handled by default below */
375
376 case CSR_SPLIT_TIMEOUT_HI:
377 *(buf++) = cpu_to_be32(host->csr.split_timeout_hi);
378 out;
379 case CSR_SPLIT_TIMEOUT_LO:
380 *(buf++) = cpu_to_be32(host->csr.split_timeout_lo);
381 out;
382
383 /* address gap */
384 return RCODE_ADDRESS_ERROR;
385
386 case CSR_CYCLE_TIME:
387 oldcycle = host->csr.cycle_time;
388 host->csr.cycle_time =
389 host->driver->devctl(host, GET_CYCLE_COUNTER, 0);
390
391 if (oldcycle > host->csr.cycle_time) {
392 /* cycle time wrapped around */
393 host->csr.bus_time += 1 << 7;
394 }
395 *(buf++) = cpu_to_be32(host->csr.cycle_time);
396 out;
397 case CSR_BUS_TIME:
398 oldcycle = host->csr.cycle_time;
399 host->csr.cycle_time =
400 host->driver->devctl(host, GET_CYCLE_COUNTER, 0);
401
402 if (oldcycle > host->csr.cycle_time) {
403 /* cycle time wrapped around */
404 host->csr.bus_time += (1 << 7);
405 }
406 *(buf++) = cpu_to_be32(host->csr.bus_time
407 | (host->csr.cycle_time >> 25));
408 out;
409
410 /* address gap */
411 return RCODE_ADDRESS_ERROR;
412
413 case CSR_BUSY_TIMEOUT:
414 /* not yet implemented */
415 return RCODE_ADDRESS_ERROR;
416
417 case CSR_BUS_MANAGER_ID:
418 if (host->driver->hw_csr_reg)
419 ret = host->driver->hw_csr_reg(host, 0, 0, 0);
420 else
421 ret = host->csr.bus_manager_id;
422
423 *(buf++) = cpu_to_be32(ret);
424 out;
425 case CSR_BANDWIDTH_AVAILABLE:
426 if (host->driver->hw_csr_reg)
427 ret = host->driver->hw_csr_reg(host, 1, 0, 0);
428 else
429 ret = host->csr.bandwidth_available;
430
431 *(buf++) = cpu_to_be32(ret);
432 out;
433 case CSR_CHANNELS_AVAILABLE_HI:
434 if (host->driver->hw_csr_reg)
435 ret = host->driver->hw_csr_reg(host, 2, 0, 0);
436 else
437 ret = host->csr.channels_available_hi;
438
439 *(buf++) = cpu_to_be32(ret);
440 out;
441 case CSR_CHANNELS_AVAILABLE_LO:
442 if (host->driver->hw_csr_reg)
443 ret = host->driver->hw_csr_reg(host, 3, 0, 0);
444 else
445 ret = host->csr.channels_available_lo;
446
447 *(buf++) = cpu_to_be32(ret);
448 out;
449
450 case CSR_BROADCAST_CHANNEL:
451 *(buf++) = cpu_to_be32(host->csr.broadcast_channel);
452 out;
453
454 /* address gap to end - fall through to default */
455 default:
456 return RCODE_ADDRESS_ERROR;
457 }
458
459 return RCODE_COMPLETE;
460 }
461
462 static int write_regs(struct hpsb_host *host, int nodeid, int destid,
463 quadlet_t *data, u64 addr, size_t length, u16 flags)
464 {
465 int csraddr = addr - CSR_REGISTER_BASE;
466
467 if ((csraddr | length) & 0x3)
468 return RCODE_TYPE_ERROR;
469
470 length /= 4;
471
472 switch (csraddr) {
473 case CSR_STATE_CLEAR:
474 /* FIXME FIXME FIXME */
475 printk("doh, someone wants to mess with state clear\n");
476 out;
477 case CSR_STATE_SET:
478 printk("doh, someone wants to mess with state set\n");
479 out;
480
481 case CSR_NODE_IDS:
482 host->csr.node_ids &= NODE_MASK << 16;
483 host->csr.node_ids |= be32_to_cpu(*(data++)) & (BUS_MASK << 16);
484 host->node_id = host->csr.node_ids >> 16;
485 host->driver->devctl(host, SET_BUS_ID, host->node_id >> 6);
486 out;
487
488 case CSR_RESET_START:
489 /* FIXME - perform command reset */
490 out;
491
492 /* address gap */
493 return RCODE_ADDRESS_ERROR;
494
495 case CSR_SPLIT_TIMEOUT_HI:
496 host->csr.split_timeout_hi =
497 be32_to_cpu(*(data++)) & 0x00000007;
498 calculate_expire(&host->csr);
499 out;
500 case CSR_SPLIT_TIMEOUT_LO:
501 host->csr.split_timeout_lo =
502 be32_to_cpu(*(data++)) & 0xfff80000;
503 calculate_expire(&host->csr);
504 out;
505
506 /* address gap */
507 return RCODE_ADDRESS_ERROR;
508
509 case CSR_CYCLE_TIME:
510 /* should only be set by cycle start packet, automatically */
511 host->csr.cycle_time = be32_to_cpu(*data);
512 host->driver->devctl(host, SET_CYCLE_COUNTER,
513 be32_to_cpu(*(data++)));
514 out;
515 case CSR_BUS_TIME:
516 host->csr.bus_time = be32_to_cpu(*(data++)) & 0xffffff80;
517 out;
518
519 /* address gap */
520 return RCODE_ADDRESS_ERROR;
521
522 case CSR_BUSY_TIMEOUT:
523 /* not yet implemented */
524 return RCODE_ADDRESS_ERROR;
525
526 case CSR_BUS_MANAGER_ID:
527 case CSR_BANDWIDTH_AVAILABLE:
528 case CSR_CHANNELS_AVAILABLE_HI:
529 case CSR_CHANNELS_AVAILABLE_LO:
530 /* these are not writable, only lockable */
531 return RCODE_TYPE_ERROR;
532
533 case CSR_BROADCAST_CHANNEL:
534 /* only the valid bit can be written */
535 host->csr.broadcast_channel = (host->csr.broadcast_channel & ~0x40000000)
536 | (be32_to_cpu(*data) & 0x40000000);
537 out;
538
539 /* address gap to end - fall through */
540 default:
541 return RCODE_ADDRESS_ERROR;
542 }
543
544 return RCODE_COMPLETE;
545 }
546
547 #undef out
548
549
550 static int lock_regs(struct hpsb_host *host, int nodeid, quadlet_t *store,
551 u64 addr, quadlet_t data, quadlet_t arg, int extcode, u16 fl)
552 {
553 int csraddr = addr - CSR_REGISTER_BASE;
554 unsigned long flags;
555 quadlet_t *regptr = NULL;
556
557 if (csraddr & 0x3)
558 return RCODE_TYPE_ERROR;
559
560 if (csraddr < CSR_BUS_MANAGER_ID || csraddr > CSR_CHANNELS_AVAILABLE_LO
561 || extcode != EXTCODE_COMPARE_SWAP)
562 goto unsupported_lockreq;
563
564 data = be32_to_cpu(data);
565 arg = be32_to_cpu(arg);
566
567 /* Is somebody releasing the broadcast_channel on us? */
568 if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x1)) {
569 /* Note: this is may not be the right way to handle
570 * the problem, so we should look into the proper way
571 * eventually. */
572 HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release "
573 "broadcast channel 31. Ignoring.",
574 NODE_BUS_ARGS(host, nodeid));
575
576 data &= ~0x1; /* keep broadcast channel allocated */
577 }
578
579 if (host->driver->hw_csr_reg) {
580 quadlet_t old;
581
582 old = host->driver->
583 hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2,
584 data, arg);
585
586 *store = cpu_to_be32(old);
587 return RCODE_COMPLETE;
588 }
589
590 spin_lock_irqsave(&host->csr.lock, flags);
591
592 switch (csraddr) {
593 case CSR_BUS_MANAGER_ID:
594 regptr = &host->csr.bus_manager_id;
595 *store = cpu_to_be32(*regptr);
596 if (*regptr == arg)
597 *regptr = data;
598 break;
599
600 case CSR_BANDWIDTH_AVAILABLE:
601 {
602 quadlet_t bandwidth;
603 quadlet_t old;
604 quadlet_t new;
605
606 regptr = &host->csr.bandwidth_available;
607 old = *regptr;
608
609 /* bandwidth available algorithm adapted from IEEE 1394a-2000 spec */
610 if (arg > 0x1fff) {
611 *store = cpu_to_be32(old); /* change nothing */
612 break;
613 }
614 data &= 0x1fff;
615 if (arg >= data) {
616 /* allocate bandwidth */
617 bandwidth = arg - data;
618 if (old >= bandwidth) {
619 new = old - bandwidth;
620 *store = cpu_to_be32(arg);
621 *regptr = new;
622 } else {
623 *store = cpu_to_be32(old);
624 }
625 } else {
626 /* deallocate bandwidth */
627 bandwidth = data - arg;
628 if (old + bandwidth < 0x2000) {
629 new = old + bandwidth;
630 *store = cpu_to_be32(arg);
631 *regptr = new;
632 } else {
633 *store = cpu_to_be32(old);
634 }
635 }
636 break;
637 }
638
639 case CSR_CHANNELS_AVAILABLE_HI:
640 {
641 /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */
642 quadlet_t affected_channels = arg ^ data;
643
644 regptr = &host->csr.channels_available_hi;
645
646 if ((arg & affected_channels) == (*regptr & affected_channels)) {
647 *regptr ^= affected_channels;
648 *store = cpu_to_be32(arg);
649 } else {
650 *store = cpu_to_be32(*regptr);
651 }
652
653 break;
654 }
655
656 case CSR_CHANNELS_AVAILABLE_LO:
657 {
658 /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */
659 quadlet_t affected_channels = arg ^ data;
660
661 regptr = &host->csr.channels_available_lo;
662
663 if ((arg & affected_channels) == (*regptr & affected_channels)) {
664 *regptr ^= affected_channels;
665 *store = cpu_to_be32(arg);
666 } else {
667 *store = cpu_to_be32(*regptr);
668 }
669 break;
670 }
671 }
672
673 spin_unlock_irqrestore(&host->csr.lock, flags);
674
675 return RCODE_COMPLETE;
676
677 unsupported_lockreq:
678 switch (csraddr) {
679 case CSR_STATE_CLEAR:
680 case CSR_STATE_SET:
681 case CSR_RESET_START:
682 case CSR_NODE_IDS:
683 case CSR_SPLIT_TIMEOUT_HI:
684 case CSR_SPLIT_TIMEOUT_LO:
685 case CSR_CYCLE_TIME:
686 case CSR_BUS_TIME:
687 case CSR_BROADCAST_CHANNEL:
688 return RCODE_TYPE_ERROR;
689
690 case CSR_BUSY_TIMEOUT:
691 /* not yet implemented - fall through */
692 default:
693 return RCODE_ADDRESS_ERROR;
694 }
695 }
696
697 static int lock64_regs(struct hpsb_host *host, int nodeid, octlet_t * store,
698 u64 addr, octlet_t data, octlet_t arg, int extcode, u16 fl)
699 {
700 int csraddr = addr - CSR_REGISTER_BASE;
701 unsigned long flags;
702
703 data = be64_to_cpu(data);
704 arg = be64_to_cpu(arg);
705
706 if (csraddr & 0x3)
707 return RCODE_TYPE_ERROR;
708
709 if (csraddr != CSR_CHANNELS_AVAILABLE
710 || extcode != EXTCODE_COMPARE_SWAP)
711 goto unsupported_lock64req;
712
713 /* Is somebody releasing the broadcast_channel on us? */
714 if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x100000000ULL)) {
715 /* Note: this is may not be the right way to handle
716 * the problem, so we should look into the proper way
717 * eventually. */
718 HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release "
719 "broadcast channel 31. Ignoring.",
720 NODE_BUS_ARGS(host, nodeid));
721
722 data &= ~0x100000000ULL; /* keep broadcast channel allocated */
723 }
724
725 if (host->driver->hw_csr_reg) {
726 quadlet_t data_hi, data_lo;
727 quadlet_t arg_hi, arg_lo;
728 quadlet_t old_hi, old_lo;
729
730 data_hi = data >> 32;
731 data_lo = data & 0xFFFFFFFF;
732 arg_hi = arg >> 32;
733 arg_lo = arg & 0xFFFFFFFF;
734
735 old_hi = host->driver->hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2,
736 data_hi, arg_hi);
737
738 old_lo = host->driver->hw_csr_reg(host, ((csraddr + 4) - CSR_BUS_MANAGER_ID) >> 2,
739 data_lo, arg_lo);
740
741 *store = cpu_to_be64(((octlet_t)old_hi << 32) | old_lo);
742 } else {
743 octlet_t old;
744 octlet_t affected_channels = arg ^ data;
745
746 spin_lock_irqsave(&host->csr.lock, flags);
747
748 old = ((octlet_t)host->csr.channels_available_hi << 32) | host->csr.channels_available_lo;
749
750 if ((arg & affected_channels) == (old & affected_channels)) {
751 host->csr.channels_available_hi ^= (affected_channels >> 32);
752 host->csr.channels_available_lo ^= (affected_channels & 0xffffffff);
753 *store = cpu_to_be64(arg);
754 } else {
755 *store = cpu_to_be64(old);
756 }
757
758 spin_unlock_irqrestore(&host->csr.lock, flags);
759 }
760
761 /* Is somebody erroneously releasing the broadcast_channel on us? */
762 if (host->csr.channels_available_hi & 0x1)
763 host->csr.channels_available_hi &= ~0x1;
764
765 return RCODE_COMPLETE;
766
767 unsupported_lock64req:
768 switch (csraddr) {
769 case CSR_STATE_CLEAR:
770 case CSR_STATE_SET:
771 case CSR_RESET_START:
772 case CSR_NODE_IDS:
773 case CSR_SPLIT_TIMEOUT_HI:
774 case CSR_SPLIT_TIMEOUT_LO:
775 case CSR_CYCLE_TIME:
776 case CSR_BUS_TIME:
777 case CSR_BUS_MANAGER_ID:
778 case CSR_BROADCAST_CHANNEL:
779 case CSR_BUSY_TIMEOUT:
780 case CSR_BANDWIDTH_AVAILABLE:
781 return RCODE_TYPE_ERROR;
782
783 default:
784 return RCODE_ADDRESS_ERROR;
785 }
786 }
787
788 static int write_fcp(struct hpsb_host *host, int nodeid, int dest,
789 quadlet_t *data, u64 addr, size_t length, u16 flags)
790 {
791 int csraddr = addr - CSR_REGISTER_BASE;
792
793 if (length > 512)
794 return RCODE_TYPE_ERROR;
795
796 switch (csraddr) {
797 case CSR_FCP_COMMAND:
798 highlevel_fcp_request(host, nodeid, 0, (u8 *)data, length);
799 break;
800 case CSR_FCP_RESPONSE:
801 highlevel_fcp_request(host, nodeid, 1, (u8 *)data, length);
802 break;
803 default:
804 return RCODE_TYPE_ERROR;
805 }
806
807 return RCODE_COMPLETE;
808 }
809
810 static int read_config_rom(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
811 u64 addr, size_t length, u16 fl)
812 {
813 u32 offset = addr - CSR1212_REGISTER_SPACE_BASE;
814
815 if (csr1212_read(host->csr.rom, offset, buffer, length) == CSR1212_SUCCESS)
816 return RCODE_COMPLETE;
817 else
818 return RCODE_ADDRESS_ERROR;
819 }
820
821 static u64 allocate_addr_range(u64 size, u32 alignment, void *__host)
822 {
823 struct hpsb_host *host = (struct hpsb_host*)__host;
824
825 return hpsb_allocate_and_register_addrspace(&csr_highlevel,
826 host,
827 &config_rom_ops,
828 size, alignment,
829 CSR1212_UNITS_SPACE_BASE,
830 CSR1212_UNITS_SPACE_END);
831 }
832
833 static void release_addr_range(u64 addr, void *__host)
834 {
835 struct hpsb_host *host = (struct hpsb_host*)__host;
836 hpsb_unregister_addrspace(&csr_highlevel, host, addr);
837 }
838
839
840 int init_csr(void)
841 {
842 node_cap = csr1212_new_immediate(CSR1212_KV_ID_NODE_CAPABILITIES, 0x0083c0);
843 if (!node_cap) {
844 HPSB_ERR("Failed to allocate memory for Node Capabilties ConfigROM entry!");
845 return -ENOMEM;
846 }
847
848 hpsb_register_highlevel(&csr_highlevel);
849
850 return 0;
851 }
852
853 void cleanup_csr(void)
854 {
855 if (node_cap)
856 csr1212_release_keyval(node_cap);
857 hpsb_unregister_highlevel(&csr_highlevel);
858 }
kmemtrace - Kernel memory tracer