include/asm-powerpc/io.h

   1 #ifndef _ASM_POWERPC_IO_H
   2 #define _ASM_POWERPC_IO_H
   3 #ifdef __KERNEL__
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 /* Check of existence of legacy devices */
  13 extern int check_legacy_ioport(unsigned long base_port);
  14 #define I8042_DATA_REG  0x60
  15 #define FDC_BASE        0x3f0
  16 /* only relevant for PReP */
  17 #define _PIDXR          0x279
  18 #define _PNPWRP         0xa79
  19 #define PNPBIOS_BASE    0xf000
  20
  21 #include <linux/device.h>
  22 #include <linux/io.h>
  23
  24 #include <linux/compiler.h>
  25 #include <asm/page.h>
  26 #include <asm/byteorder.h>
  27 #include <asm/synch.h>
  28 #include <asm/delay.h>
  29 #include <asm/mmu.h>
  30
  31 #include <asm-generic/iomap.h>
  32
  33 #ifdef CONFIG_PPC64
  34 #include <asm/paca.h>
  35 #endif
  36
  37 #define SIO_CONFIG_RA   0x398
  38 #define SIO_CONFIG_RD   0x399
  39
  40 #define SLOW_DOWN_IO
  41
  42 /* 32 bits uses slightly different variables for the various IO
  43  * bases. Most of this file only uses _IO_BASE though which we
  44  * define properly based on the platform
  45  */
  46 #ifndef CONFIG_PCI
  47 #define _IO_BASE        0
  48 #define _ISA_MEM_BASE   0
  49 #define PCI_DRAM_OFFSET 0
  50 #elif defined(CONFIG_PPC32)
  51 #define _IO_BASE        isa_io_base
  52 #define _ISA_MEM_BASE   isa_mem_base
  53 #define PCI_DRAM_OFFSET pci_dram_offset
  54 #else
  55 #define _IO_BASE        pci_io_base
  56 #define _ISA_MEM_BASE   isa_mem_base
  57 #define PCI_DRAM_OFFSET 0
  58 #endif
  59
  60 extern unsigned long isa_io_base;
  61 extern unsigned long pci_io_base;
  62 extern unsigned long pci_dram_offset;
  63
  64 extern resource_size_t isa_mem_base;
  65
  66 #if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
  67 #error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
  68 #endif
  69
  70 /*
  71  *
  72  * Low level MMIO accessors
  73  *
  74  * This provides the non-bus specific accessors to MMIO. Those are PowerPC
  75  * specific and thus shouldn't be used in generic code. The accessors
  76  * provided here are:
  77  *
  78  *      in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
  79  *      out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
  80  *      _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
  81  *
  82  * Those operate directly on a kernel virtual address. Note that the prototype
  83  * for the out_* accessors has the arguments in opposite order from the usual
  84  * linux PCI accessors. Unlike those, they take the address first and the value
  85  * next.
  86  *
  87  * Note: I might drop the _ns suffix on the stream operations soon as it is
  88  * simply normal for stream operations to not swap in the first place.
  89  *
  90  */
  91
  92 #ifdef CONFIG_PPC64
  93 #define IO_SET_SYNC_FLAG()      do { local_paca->io_sync = 1; } while(0)
  94 #else
  95 #define IO_SET_SYNC_FLAG()
  96 #endif
  97
  98 #define DEF_MMIO_IN(name, type, insn)                                   \
  99 static inline type name(const volatile type __iomem *addr)              \
 100 {                                                                       \
 101         type ret;                                                       \
 102         __asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync"           \
 103                 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory");     \
 104         return ret;                                                     \
 105 }
 106
 107 #define DEF_MMIO_OUT(name, type, insn)                                  \
 108 static inline void name(volatile type __iomem *addr, type val)          \
 109 {                                                                       \
 110         __asm__ __volatile__("sync;" insn                               \
 111                 : "=m" (*addr) : "r" (val), "r" (addr) : "memory");     \
 112         IO_SET_SYNC_FLAG();                                             \
 113 }
 114
 115
 116 #define DEF_MMIO_IN_BE(name, size, insn) \
 117         DEF_MMIO_IN(name, u##size, __stringify(insn)"%U2%X2 %0,%2")
 118 #define DEF_MMIO_IN_LE(name, size, insn) \
 119         DEF_MMIO_IN(name, u##size, __stringify(insn)" %0,0,%1")
 120
 121 #define DEF_MMIO_OUT_BE(name, size, insn) \
 122         DEF_MMIO_OUT(name, u##size, __stringify(insn)"%U0%X0 %1,%0")
 123 #define DEF_MMIO_OUT_LE(name, size, insn) \
 124         DEF_MMIO_OUT(name, u##size, __stringify(insn)" %1,0,%2")
 125
 126 DEF_MMIO_IN_BE(in_8,     8, lbz);
 127 DEF_MMIO_IN_BE(in_be16, 16, lhz);
 128 DEF_MMIO_IN_BE(in_be32, 32, lwz);
 129 DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
 130 DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
 131
 132 DEF_MMIO_OUT_BE(out_8,     8, stb);
 133 DEF_MMIO_OUT_BE(out_be16, 16, sth);
 134 DEF_MMIO_OUT_BE(out_be32, 32, stw);
 135 DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
 136 DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
 137
 138 #ifdef __powerpc64__
 139 DEF_MMIO_OUT_BE(out_be64, 64, std);
 140 DEF_MMIO_IN_BE(in_be64, 64, ld);
 141
 142 /* There is no asm instructions for 64 bits reverse loads and stores */
 143 static inline u64 in_le64(const volatile u64 __iomem *addr)
 144 {
 145         return swab64(in_be64(addr));
 146 }
 147
 148 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
 149 {
 150         out_be64(addr, swab64(val));
 151 }
 152 #endif /* __powerpc64__ */
 153
 154 /*
 155  * Low level IO stream instructions are defined out of line for now
 156  */
 157 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
 158 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
 159 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
 160 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
 161 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
 162 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
 163
 164 /* The _ns naming is historical and will be removed. For now, just #define
 165  * the non _ns equivalent names
 166  */
 167 #define _insw   _insw_ns
 168 #define _insl   _insl_ns
 169 #define _outsw  _outsw_ns
 170 #define _outsl  _outsl_ns
 171
 172
 173 /*
 174  * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
 175  */
 176
 177 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
 178 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
 179                            unsigned long n);
 180 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
 181                          unsigned long n);
 182
 183 /*
 184  *
 185  * PCI and standard ISA accessors
 186  *
 187  * Those are globally defined linux accessors for devices on PCI or ISA
 188  * busses. They follow the Linux defined semantics. The current implementation
 189  * for PowerPC is as close as possible to the x86 version of these, and thus
 190  * provides fairly heavy weight barriers for the non-raw versions
 191  *
 192  * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
 193  * allowing the platform to provide its own implementation of some or all
 194  * of the accessors.
 195  */
 196
 197 /*
 198  * Include the EEH definitions when EEH is enabled only so they don't get
 199  * in the way when building for 32 bits
 200  */
 201 #ifdef CONFIG_EEH
 202 #include <asm/eeh.h>
 203 #endif
 204
 205 /* Shortcut to the MMIO argument pointer */
 206 #define PCI_IO_ADDR     volatile void __iomem *
 207
 208 /* Indirect IO address tokens:
 209  *
 210  * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
 211  * on all IOs. (Note that this is all 64 bits only for now)
 212  *
 213  * To help platforms who may need to differenciate MMIO addresses in
 214  * their hooks, a bitfield is reserved for use by the platform near the
 215  * top of MMIO addresses (not PIO, those have to cope the hard way).
 216  *
 217  * This bit field is 12 bits and is at the top of the IO virtual
 218  * addresses PCI_IO_INDIRECT_TOKEN_MASK.
 219  *
 220  * The kernel virtual space is thus:
 221  *
 222  *  0xD000000000000000          : vmalloc
 223  *  0xD000080000000000          : PCI PHB IO space
 224  *  0xD000080080000000          : ioremap
 225  *  0xD0000fffffffffff          : end of ioremap region
 226  *
 227  * Since the top 4 bits are reserved as the region ID, we use thus
 228  * the next 12 bits and keep 4 bits available for the future if the
 229  * virtual address space is ever to be extended.
 230  *
 231  * The direct IO mapping operations will then mask off those bits
 232  * before doing the actual access, though that only happen when
 233  * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
 234  * mechanism
 235  */
 236
 237 #ifdef CONFIG_PPC_INDIRECT_IO
 238 #define PCI_IO_IND_TOKEN_MASK   0x0fff000000000000ul
 239 #define PCI_IO_IND_TOKEN_SHIFT  48
 240 #define PCI_FIX_ADDR(addr)                                              \
 241         ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
 242 #define PCI_GET_ADDR_TOKEN(addr)                                        \
 243         (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >>             \
 244                 PCI_IO_IND_TOKEN_SHIFT)
 245 #define PCI_SET_ADDR_TOKEN(addr, token)                                 \
 246 do {                                                                    \
 247         unsigned long __a = (unsigned long)(addr);                      \
 248         __a &= ~PCI_IO_IND_TOKEN_MASK;                                  \
 249         __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;      \
 250         (addr) = (void __iomem *)__a;                                   \
 251 } while(0)
 252 #else
 253 #define PCI_FIX_ADDR(addr) (addr)
 254 #endif
 255
 256
 257 /*
 258  * Non ordered and non-swapping "raw" accessors
 259  */
 260
 261 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
 262 {
 263         return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
 264 }
 265 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
 266 {
 267         return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
 268 }
 269 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
 270 {
 271         return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
 272 }
 273 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
 274 {
 275         *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
 276 }
 277 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
 278 {
 279         *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
 280 }
 281 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
 282 {
 283         *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
 284 }
 285
 286 #ifdef __powerpc64__
 287 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
 288 {
 289         return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
 290 }
 291 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
 292 {
 293         *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
 294 }
 295 #endif /* __powerpc64__ */
 296
 297 /*
 298  *
 299  * PCI PIO and MMIO accessors.
 300  *
 301  *
 302  * On 32 bits, PIO operations have a recovery mechanism in case they trigger
 303  * machine checks (which they occasionally do when probing non existing
 304  * IO ports on some platforms, like PowerMac and 8xx).
 305  * I always found it to be of dubious reliability and I am tempted to get
 306  * rid of it one of these days. So if you think it's important to keep it,
 307  * please voice up asap. We never had it for 64 bits and I do not intend
 308  * to port it over
 309  */
 310
 311 #ifdef CONFIG_PPC32
 312
 313 #define __do_in_asm(name, op)                           \
 314 static inline unsigned int name(unsigned int port)      \
 315 {                                                       \
 316         unsigned int x;                                 \
 317         __asm__ __volatile__(                           \
 318                 "sync\n"                                \
 319                 "0:"    op "    %0,0,%1\n"              \
 320                 "1:     twi     0,%0,0\n"               \
 321                 "2:     isync\n"                        \
 322                 "3:     nop\n"                          \
 323                 "4:\n"                                  \
 324                 ".section .fixup,\"ax\"\n"              \
 325                 "5:     li      %0,-1\n"                \
 326                 "       b       4b\n"                   \
 327                 ".previous\n"                           \
 328                 ".section __ex_table,\"a\"\n"           \
 329                 "       .align  2\n"                    \
 330                 "       .long   0b,5b\n"                \
 331                 "       .long   1b,5b\n"                \
 332                 "       .long   2b,5b\n"                \
 333                 "       .long   3b,5b\n"                \
 334                 ".previous"                             \
 335                 : "=&r" (x)                             \
 336                 : "r" (port + _IO_BASE)                 \
 337                 : "memory");                            \
 338         return x;                                       \
 339 }
 340
 341 #define __do_out_asm(name, op)                          \
 342 static inline void name(unsigned int val, unsigned int port) \
 343 {                                                       \
 344         __asm__ __volatile__(                           \
 345                 "sync\n"                                \
 346                 "0:" op " %0,0,%1\n"                    \
 347                 "1:     sync\n"                         \
 348                 "2:\n"                                  \
 349                 ".section __ex_table,\"a\"\n"           \
 350                 "       .align  2\n"                    \
 351                 "       .long   0b,2b\n"                \
 352                 "       .long   1b,2b\n"                \
 353                 ".previous"                             \
 354                 : : "r" (val), "r" (port + _IO_BASE)    \
 355                 : "memory");                            \
 356 }
 357
 358 __do_in_asm(_rec_inb, "lbzx")
 359 __do_in_asm(_rec_inw, "lhbrx")
 360 __do_in_asm(_rec_inl, "lwbrx")
 361 __do_out_asm(_rec_outb, "stbx")
 362 __do_out_asm(_rec_outw, "sthbrx")
 363 __do_out_asm(_rec_outl, "stwbrx")
 364
 365 #endif /* CONFIG_PPC32 */
 366
 367 /* The "__do_*" operations below provide the actual "base" implementation
 368  * for each of the defined acccessor. Some of them use the out_* functions
 369  * directly, some of them still use EEH, though we might change that in the
 370  * future. Those macros below provide the necessary argument swapping and
 371  * handling of the IO base for PIO.
 372  *
 373  * They are themselves used by the macros that define the actual accessors
 374  * and can be used by the hooks if any.
 375  *
 376  * Note that PIO operations are always defined in terms of their corresonding
 377  * MMIO operations. That allows platforms like iSeries who want to modify the
 378  * behaviour of both to only hook on the MMIO version and get both. It's also
 379  * possible to hook directly at the toplevel PIO operation if they have to
 380  * be handled differently
 381  */
 382 #define __do_writeb(val, addr)  out_8(PCI_FIX_ADDR(addr), val)
 383 #define __do_writew(val, addr)  out_le16(PCI_FIX_ADDR(addr), val)
 384 #define __do_writel(val, addr)  out_le32(PCI_FIX_ADDR(addr), val)
 385 #define __do_writeq(val, addr)  out_le64(PCI_FIX_ADDR(addr), val)
 386 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
 387 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
 388 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
 389
 390 #ifdef CONFIG_EEH
 391 #define __do_readb(addr)        eeh_readb(PCI_FIX_ADDR(addr))
 392 #define __do_readw(addr)        eeh_readw(PCI_FIX_ADDR(addr))
 393 #define __do_readl(addr)        eeh_readl(PCI_FIX_ADDR(addr))
 394 #define __do_readq(addr)        eeh_readq(PCI_FIX_ADDR(addr))
 395 #define __do_readw_be(addr)     eeh_readw_be(PCI_FIX_ADDR(addr))
 396 #define __do_readl_be(addr)     eeh_readl_be(PCI_FIX_ADDR(addr))
 397 #define __do_readq_be(addr)     eeh_readq_be(PCI_FIX_ADDR(addr))
 398 #else /* CONFIG_EEH */
 399 #define __do_readb(addr)        in_8(PCI_FIX_ADDR(addr))
 400 #define __do_readw(addr)        in_le16(PCI_FIX_ADDR(addr))
 401 #define __do_readl(addr)        in_le32(PCI_FIX_ADDR(addr))
 402 #define __do_readq(addr)        in_le64(PCI_FIX_ADDR(addr))
 403 #define __do_readw_be(addr)     in_be16(PCI_FIX_ADDR(addr))
 404 #define __do_readl_be(addr)     in_be32(PCI_FIX_ADDR(addr))
 405 #define __do_readq_be(addr)     in_be64(PCI_FIX_ADDR(addr))
 406 #endif /* !defined(CONFIG_EEH) */
 407
 408 #ifdef CONFIG_PPC32
 409 #define __do_outb(val, port)    _rec_outb(val, port)
 410 #define __do_outw(val, port)    _rec_outw(val, port)
 411 #define __do_outl(val, port)    _rec_outl(val, port)
 412 #define __do_inb(port)          _rec_inb(port)
 413 #define __do_inw(port)          _rec_inw(port)
 414 #define __do_inl(port)          _rec_inl(port)
 415 #else /* CONFIG_PPC32 */
 416 #define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
 417 #define __do_outw(val, port)    writew(val,(PCI_IO_ADDR)_IO_BASE+port);
 418 #define __do_outl(val, port)    writel(val,(PCI_IO_ADDR)_IO_BASE+port);
 419 #define __do_inb(port)          readb((PCI_IO_ADDR)_IO_BASE + port);
 420 #define __do_inw(port)          readw((PCI_IO_ADDR)_IO_BASE + port);
 421 #define __do_inl(port)          readl((PCI_IO_ADDR)_IO_BASE + port);
 422 #endif /* !CONFIG_PPC32 */
 423
 424 #ifdef CONFIG_EEH
 425 #define __do_readsb(a, b, n)    eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
 426 #define __do_readsw(a, b, n)    eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
 427 #define __do_readsl(a, b, n)    eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
 428 #else /* CONFIG_EEH */
 429 #define __do_readsb(a, b, n)    _insb(PCI_FIX_ADDR(a), (b), (n))
 430 #define __do_readsw(a, b, n)    _insw(PCI_FIX_ADDR(a), (b), (n))
 431 #define __do_readsl(a, b, n)    _insl(PCI_FIX_ADDR(a), (b), (n))
 432 #endif /* !CONFIG_EEH */
 433 #define __do_writesb(a, b, n)   _outsb(PCI_FIX_ADDR(a),(b),(n))
 434 #define __do_writesw(a, b, n)   _outsw(PCI_FIX_ADDR(a),(b),(n))
 435 #define __do_writesl(a, b, n)   _outsl(PCI_FIX_ADDR(a),(b),(n))
 436
 437 #define __do_insb(p, b, n)      readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 438 #define __do_insw(p, b, n)      readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 439 #define __do_insl(p, b, n)      readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 440 #define __do_outsb(p, b, n)     writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 441 #define __do_outsw(p, b, n)     writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 442 #define __do_outsl(p, b, n)     writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 443
 444 #define __do_memset_io(addr, c, n)      \
 445                                 _memset_io(PCI_FIX_ADDR(addr), c, n)
 446 #define __do_memcpy_toio(dst, src, n)   \
 447                                 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
 448
 449 #ifdef CONFIG_EEH
 450 #define __do_memcpy_fromio(dst, src, n) \
 451                                 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
 452 #else /* CONFIG_EEH */
 453 #define __do_memcpy_fromio(dst, src, n) \
 454                                 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
 455 #endif /* !CONFIG_EEH */
 456
 457 #ifdef CONFIG_PPC_INDIRECT_IO
 458 #define DEF_PCI_HOOK(x)         x
 459 #else
 460 #define DEF_PCI_HOOK(x)         NULL
 461 #endif
 462
 463 /* Structure containing all the hooks */
 464 extern struct ppc_pci_io {
 465
 466 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)    ret (*name) at;
 467 #define DEF_PCI_AC_NORET(name, at, al, space, aa)       void (*name) at;
 468
 469 #include <asm/io-defs.h>
 470
 471 #undef DEF_PCI_AC_RET
 472 #undef DEF_PCI_AC_NORET
 473
 474 } ppc_pci_io;
 475
 476 /* The inline wrappers */
 477 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)            \
 478 static inline ret name at                                       \
 479 {                                                               \
 480         if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
 481                 return ppc_pci_io.name al;                      \
 482         return __do_##name al;                                  \
 483 }
 484
 485 #define DEF_PCI_AC_NORET(name, at, al, space, aa)               \
 486 static inline void name at                                      \
 487 {                                                               \
 488         if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
 489                 ppc_pci_io.name al;                             \
 490         else                                                    \
 491                 __do_##name al;                                 \
 492 }
 493
 494 #include <asm/io-defs.h>
 495
 496 #undef DEF_PCI_AC_RET
 497 #undef DEF_PCI_AC_NORET
 498
 499 /* Some drivers check for the presence of readq & writeq with
 500  * a #ifdef, so we make them happy here.
 501  */
 502 #ifdef __powerpc64__
 503 #define readq   readq
 504 #define writeq  writeq
 505 #endif
 506
 507 /*
 508  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 509  * access
 510  */
 511 #define xlate_dev_mem_ptr(p)    __va(p)
 512
 513 /*
 514  * Convert a virtual cached pointer to an uncached pointer
 515  */
 516 #define xlate_dev_kmem_ptr(p)   p
 517
 518 /*
 519  * We don't do relaxed operations yet, at least not with this semantic
 520  */
 521 #define readb_relaxed(addr) readb(addr)
 522 #define readw_relaxed(addr) readw(addr)
 523 #define readl_relaxed(addr) readl(addr)
 524 #define readq_relaxed(addr) readq(addr)
 525
 526 #ifdef CONFIG_PPC32
 527 #define mmiowb()
 528 #else
 529 /*
 530  * Enforce synchronisation of stores vs. spin_unlock
 531  * (this does it explicitly, though our implementation of spin_unlock
 532  * does it implicitely too)
 533  */
 534 static inline void mmiowb(void)
 535 {
 536         unsigned long tmp;
 537
 538         __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
 539         : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
 540         : "memory");
 541 }
 542 #endif /* !CONFIG_PPC32 */
 543
 544 static inline void iosync(void)
 545 {
 546         __asm__ __volatile__ ("sync" : : : "memory");
 547 }
 548
 549 /* Enforce in-order execution of data I/O.
 550  * No distinction between read/write on PPC; use eieio for all three.
 551  * Those are fairly week though. They don't provide a barrier between
 552  * MMIO and cacheable storage nor do they provide a barrier vs. locks,
 553  * they only provide barriers between 2 __raw MMIO operations and
 554  * possibly break write combining.
 555  */
 556 #define iobarrier_rw() eieio()
 557 #define iobarrier_r()  eieio()
 558 #define iobarrier_w()  eieio()
 559
 560
 561 /*
 562  * output pause versions need a delay at least for the
 563  * w83c105 ide controller in a p610.
 564  */
 565 #define inb_p(port)             inb(port)
 566 #define outb_p(val, port)       (udelay(1), outb((val), (port)))
 567 #define inw_p(port)             inw(port)
 568 #define outw_p(val, port)       (udelay(1), outw((val), (port)))
 569 #define inl_p(port)             inl(port)
 570 #define outl_p(val, port)       (udelay(1), outl((val), (port)))
 571
 572
 573 #define IO_SPACE_LIMIT ~(0UL)
 574
 575
 576 /**
 577  * ioremap     -   map bus memory into CPU space
 578  * @address:   bus address of the memory
 579  * @size:      size of the resource to map
 580  *
 581  * ioremap performs a platform specific sequence of operations to
 582  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 583  * writew/writel functions and the other mmio helpers. The returned
 584  * address is not guaranteed to be usable directly as a virtual
 585  * address.
 586  *
 587  * We provide a few variations of it:
 588  *
 589  * * ioremap is the standard one and provides non-cacheable guarded mappings
 590  *   and can be hooked by the platform via ppc_md
 591  *
 592  * * ioremap_flags allows to specify the page flags as an argument and can
 593  *   also be hooked by the platform via ppc_md
 594  *
 595  * * ioremap_nocache is identical to ioremap
 596  *
 597  * * iounmap undoes such a mapping and can be hooked
 598  *
 599  * * __ioremap_at (and the pending __iounmap_at) are low level functions to
 600  *   create hand-made mappings for use only by the PCI code and cannot
 601  *   currently be hooked. Must be page aligned.
 602  *
 603  * * __ioremap is the low level implementation used by ioremap and
 604  *   ioremap_flags and cannot be hooked (but can be used by a hook on one
 605  *   of the previous ones)
 606  *
 607  * * __iounmap, is the low level implementation used by iounmap and cannot
 608  *   be hooked (but can be used by a hook on iounmap)
 609  *
 610  */
 611 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
 612 extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,
 613                                    unsigned long flags);
 614 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
 615 extern void iounmap(volatile void __iomem *addr);
 616
 617 extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
 618                                unsigned long flags);
 619 extern void __iounmap(volatile void __iomem *addr);
 620
 621 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
 622                                    unsigned long size, unsigned long flags);
 623 extern void __iounmap_at(void *ea, unsigned long size);
 624
 625 /*
 626  * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
 627  * which needs some additional definitions here. They basically allow PIO
 628  * space overall to be 1GB. This will work as long as we never try to use
 629  * iomap to map MMIO below 1GB which should be fine on ppc64
 630  */
 631 #define HAVE_ARCH_PIO_SIZE              1
 632 #define PIO_OFFSET                      0x00000000UL
 633 #define PIO_MASK                        (FULL_IO_SIZE - 1)
 634 #define PIO_RESERVED                    (FULL_IO_SIZE)
 635
 636 #define mmio_read16be(addr)             readw_be(addr)
 637 #define mmio_read32be(addr)             readl_be(addr)
 638 #define mmio_write16be(val, addr)       writew_be(val, addr)
 639 #define mmio_write32be(val, addr)       writel_be(val, addr)
 640 #define mmio_insb(addr, dst, count)     readsb(addr, dst, count)
 641 #define mmio_insw(addr, dst, count)     readsw(addr, dst, count)
 642 #define mmio_insl(addr, dst, count)     readsl(addr, dst, count)
 643 #define mmio_outsb(addr, src, count)    writesb(addr, src, count)
 644 #define mmio_outsw(addr, src, count)    writesw(addr, src, count)
 645 #define mmio_outsl(addr, src, count)    writesl(addr, src, count)
 646
 647 /**
 648  *      virt_to_phys    -       map virtual addresses to physical
 649  *      @address: address to remap
 650  *
 651  *      The returned physical address is the physical (CPU) mapping for
 652  *      the memory address given. It is only valid to use this function on
 653  *      addresses directly mapped or allocated via kmalloc.
 654  *
 655  *      This function does not give bus mappings for DMA transfers. In
 656  *      almost all conceivable cases a device driver should not be using
 657  *      this function
 658  */
 659 static inline unsigned long virt_to_phys(volatile void * address)
 660 {
 661         return __pa((unsigned long)address);
 662 }
 663
 664 /**
 665  *      phys_to_virt    -       map physical address to virtual
 666  *      @address: address to remap
 667  *
 668  *      The returned virtual address is a current CPU mapping for
 669  *      the memory address given. It is only valid to use this function on
 670  *      addresses that have a kernel mapping
 671  *
 672  *      This function does not handle bus mappings for DMA transfers. In
 673  *      almost all conceivable cases a device driver should not be using
 674  *      this function
 675  */
 676 static inline void * phys_to_virt(unsigned long address)
 677 {
 678         return (void *)__va(address);
 679 }
 680
 681 /*
 682  * Change "struct page" to physical address.
 683  */
 684 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 685
 686 /* We do NOT want virtual merging, it would put too much pressure on
 687  * our iommu allocator. Instead, we want drivers to be smart enough
 688  * to coalesce sglists that happen to have been mapped in a contiguous
 689  * way by the iommu
 690  */
 691 #define BIO_VMERGE_BOUNDARY     0
 692
 693 /*
 694  * 32 bits still uses virt_to_bus() for it's implementation of DMA
 695  * mappings se we have to keep it defined here. We also have some old
 696  * drivers (shame shame shame) that use bus_to_virt() and haven't been
 697  * fixed yet so I need to define it here.
 698  */
 699 #ifdef CONFIG_PPC32
 700
 701 static inline unsigned long virt_to_bus(volatile void * address)
 702 {
 703         if (address == NULL)
 704                 return 0;
 705         return __pa(address) + PCI_DRAM_OFFSET;
 706 }
 707
 708 static inline void * bus_to_virt(unsigned long address)
 709 {
 710         if (address == 0)
 711                 return NULL;
 712         return __va(address - PCI_DRAM_OFFSET);
 713 }
 714
 715 #define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
 716
 717 #endif /* CONFIG_PPC32 */
 718
 719 /* access ports */
 720 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
 721 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
 722
 723 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
 724 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
 725
 726 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
 727 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
 728
 729 /* Clear and set bits in one shot.  These macros can be used to clear and
 730  * set multiple bits in a register using a single read-modify-write.  These
 731  * macros can also be used to set a multiple-bit bit pattern using a mask,
 732  * by specifying the mask in the 'clear' parameter and the new bit pattern
 733  * in the 'set' parameter.
 734  */
 735
 736 #define clrsetbits(type, addr, clear, set) \
 737         out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
 738
 739 #ifdef __powerpc64__
 740 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
 741 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
 742 #endif
 743
 744 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
 745 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
 746
 747 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
 748 #define clrsetbits_le16(addr, clear, set) clrsetbits(le32, addr, clear, set)
 749
 750 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
 751
 752 void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset,
 753                                 size_t size, unsigned long flags);
 754
 755 #endif /* __KERNEL__ */
 756
 757 #endif /* _ASM_POWERPC_IO_H */