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kmemtrace: SLOB hooks.
[linux-2.6/kmemtrace.git] / drivers / net / s2io.c
blobae7b697456b4c88245ec36e6599efb17e6dc280f
1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 *
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
29 *
30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
55 ************************************************************************/
56
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/skbuff.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/stddef.h>
70 #include <linux/ioctl.h>
71 #include <linux/timex.h>
72 #include <linux/ethtool.h>
73 #include <linux/workqueue.h>
74 #include <linux/if_vlan.h>
75 #include <linux/ip.h>
76 #include <linux/tcp.h>
77 #include <net/tcp.h>
78
79 #include <asm/system.h>
80 #include <asm/uaccess.h>
81 #include <asm/io.h>
82 #include <asm/div64.h>
83 #include <asm/irq.h>
84
85 /* local include */
86 #include "s2io.h"
87 #include "s2io-regs.h"
88
89 #define DRV_VERSION "2.0.26.24"
90
91 /* S2io Driver name & version. */
92 static char s2io_driver_name[] = "Neterion";
93 static char s2io_driver_version[] = DRV_VERSION;
94
95 static int rxd_size[2] = {32,48};
96 static int rxd_count[2] = {127,85};
97
98 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
99 {
100 int ret;
101
102 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
103 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
104
105 return ret;
106 }
107
108 /*
109 * Cards with following subsystem_id have a link state indication
110 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
111 * macro below identifies these cards given the subsystem_id.
112 */
113 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
114 (dev_type == XFRAME_I_DEVICE) ? \
115 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
116 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
117
118 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
119 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
120
121 static inline int is_s2io_card_up(const struct s2io_nic * sp)
122 {
123 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
124 }
125
126 /* Ethtool related variables and Macros. */
127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128 "Register test\t(offline)",
129 "Eeprom test\t(offline)",
130 "Link test\t(online)",
131 "RLDRAM test\t(offline)",
132 "BIST Test\t(offline)"
133 };
134
135 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
136 {"tmac_frms"},
137 {"tmac_data_octets"},
138 {"tmac_drop_frms"},
139 {"tmac_mcst_frms"},
140 {"tmac_bcst_frms"},
141 {"tmac_pause_ctrl_frms"},
142 {"tmac_ttl_octets"},
143 {"tmac_ucst_frms"},
144 {"tmac_nucst_frms"},
145 {"tmac_any_err_frms"},
146 {"tmac_ttl_less_fb_octets"},
147 {"tmac_vld_ip_octets"},
148 {"tmac_vld_ip"},
149 {"tmac_drop_ip"},
150 {"tmac_icmp"},
151 {"tmac_rst_tcp"},
152 {"tmac_tcp"},
153 {"tmac_udp"},
154 {"rmac_vld_frms"},
155 {"rmac_data_octets"},
156 {"rmac_fcs_err_frms"},
157 {"rmac_drop_frms"},
158 {"rmac_vld_mcst_frms"},
159 {"rmac_vld_bcst_frms"},
160 {"rmac_in_rng_len_err_frms"},
161 {"rmac_out_rng_len_err_frms"},
162 {"rmac_long_frms"},
163 {"rmac_pause_ctrl_frms"},
164 {"rmac_unsup_ctrl_frms"},
165 {"rmac_ttl_octets"},
166 {"rmac_accepted_ucst_frms"},
167 {"rmac_accepted_nucst_frms"},
168 {"rmac_discarded_frms"},
169 {"rmac_drop_events"},
170 {"rmac_ttl_less_fb_octets"},
171 {"rmac_ttl_frms"},
172 {"rmac_usized_frms"},
173 {"rmac_osized_frms"},
174 {"rmac_frag_frms"},
175 {"rmac_jabber_frms"},
176 {"rmac_ttl_64_frms"},
177 {"rmac_ttl_65_127_frms"},
178 {"rmac_ttl_128_255_frms"},
179 {"rmac_ttl_256_511_frms"},
180 {"rmac_ttl_512_1023_frms"},
181 {"rmac_ttl_1024_1518_frms"},
182 {"rmac_ip"},
183 {"rmac_ip_octets"},
184 {"rmac_hdr_err_ip"},
185 {"rmac_drop_ip"},
186 {"rmac_icmp"},
187 {"rmac_tcp"},
188 {"rmac_udp"},
189 {"rmac_err_drp_udp"},
190 {"rmac_xgmii_err_sym"},
191 {"rmac_frms_q0"},
192 {"rmac_frms_q1"},
193 {"rmac_frms_q2"},
194 {"rmac_frms_q3"},
195 {"rmac_frms_q4"},
196 {"rmac_frms_q5"},
197 {"rmac_frms_q6"},
198 {"rmac_frms_q7"},
199 {"rmac_full_q0"},
200 {"rmac_full_q1"},
201 {"rmac_full_q2"},
202 {"rmac_full_q3"},
203 {"rmac_full_q4"},
204 {"rmac_full_q5"},
205 {"rmac_full_q6"},
206 {"rmac_full_q7"},
207 {"rmac_pause_cnt"},
208 {"rmac_xgmii_data_err_cnt"},
209 {"rmac_xgmii_ctrl_err_cnt"},
210 {"rmac_accepted_ip"},
211 {"rmac_err_tcp"},
212 {"rd_req_cnt"},
213 {"new_rd_req_cnt"},
214 {"new_rd_req_rtry_cnt"},
215 {"rd_rtry_cnt"},
216 {"wr_rtry_rd_ack_cnt"},
217 {"wr_req_cnt"},
218 {"new_wr_req_cnt"},
219 {"new_wr_req_rtry_cnt"},
220 {"wr_rtry_cnt"},
221 {"wr_disc_cnt"},
222 {"rd_rtry_wr_ack_cnt"},
223 {"txp_wr_cnt"},
224 {"txd_rd_cnt"},
225 {"txd_wr_cnt"},
226 {"rxd_rd_cnt"},
227 {"rxd_wr_cnt"},
228 {"txf_rd_cnt"},
229 {"rxf_wr_cnt"}
230 };
231
232 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
233 {"rmac_ttl_1519_4095_frms"},
234 {"rmac_ttl_4096_8191_frms"},
235 {"rmac_ttl_8192_max_frms"},
236 {"rmac_ttl_gt_max_frms"},
237 {"rmac_osized_alt_frms"},
238 {"rmac_jabber_alt_frms"},
239 {"rmac_gt_max_alt_frms"},
240 {"rmac_vlan_frms"},
241 {"rmac_len_discard"},
242 {"rmac_fcs_discard"},
243 {"rmac_pf_discard"},
244 {"rmac_da_discard"},
245 {"rmac_red_discard"},
246 {"rmac_rts_discard"},
247 {"rmac_ingm_full_discard"},
248 {"link_fault_cnt"}
249 };
250
251 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
252 {"\n DRIVER STATISTICS"},
253 {"single_bit_ecc_errs"},
254 {"double_bit_ecc_errs"},
255 {"parity_err_cnt"},
256 {"serious_err_cnt"},
257 {"soft_reset_cnt"},
258 {"fifo_full_cnt"},
259 {"ring_0_full_cnt"},
260 {"ring_1_full_cnt"},
261 {"ring_2_full_cnt"},
262 {"ring_3_full_cnt"},
263 {"ring_4_full_cnt"},
264 {"ring_5_full_cnt"},
265 {"ring_6_full_cnt"},
266 {"ring_7_full_cnt"},
267 {"alarm_transceiver_temp_high"},
268 {"alarm_transceiver_temp_low"},
269 {"alarm_laser_bias_current_high"},
270 {"alarm_laser_bias_current_low"},
271 {"alarm_laser_output_power_high"},
272 {"alarm_laser_output_power_low"},
273 {"warn_transceiver_temp_high"},
274 {"warn_transceiver_temp_low"},
275 {"warn_laser_bias_current_high"},
276 {"warn_laser_bias_current_low"},
277 {"warn_laser_output_power_high"},
278 {"warn_laser_output_power_low"},
279 {"lro_aggregated_pkts"},
280 {"lro_flush_both_count"},
281 {"lro_out_of_sequence_pkts"},
282 {"lro_flush_due_to_max_pkts"},
283 {"lro_avg_aggr_pkts"},
284 {"mem_alloc_fail_cnt"},
285 {"pci_map_fail_cnt"},
286 {"watchdog_timer_cnt"},
287 {"mem_allocated"},
288 {"mem_freed"},
289 {"link_up_cnt"},
290 {"link_down_cnt"},
291 {"link_up_time"},
292 {"link_down_time"},
293 {"tx_tcode_buf_abort_cnt"},
294 {"tx_tcode_desc_abort_cnt"},
295 {"tx_tcode_parity_err_cnt"},
296 {"tx_tcode_link_loss_cnt"},
297 {"tx_tcode_list_proc_err_cnt"},
298 {"rx_tcode_parity_err_cnt"},
299 {"rx_tcode_abort_cnt"},
300 {"rx_tcode_parity_abort_cnt"},
301 {"rx_tcode_rda_fail_cnt"},
302 {"rx_tcode_unkn_prot_cnt"},
303 {"rx_tcode_fcs_err_cnt"},
304 {"rx_tcode_buf_size_err_cnt"},
305 {"rx_tcode_rxd_corrupt_cnt"},
306 {"rx_tcode_unkn_err_cnt"},
307 {"tda_err_cnt"},
308 {"pfc_err_cnt"},
309 {"pcc_err_cnt"},
310 {"tti_err_cnt"},
311 {"tpa_err_cnt"},
312 {"sm_err_cnt"},
313 {"lso_err_cnt"},
314 {"mac_tmac_err_cnt"},
315 {"mac_rmac_err_cnt"},
316 {"xgxs_txgxs_err_cnt"},
317 {"xgxs_rxgxs_err_cnt"},
318 {"rc_err_cnt"},
319 {"prc_pcix_err_cnt"},
320 {"rpa_err_cnt"},
321 {"rda_err_cnt"},
322 {"rti_err_cnt"},
323 {"mc_err_cnt"}
324 };
325
326 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
327 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
328 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
329
330 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
331 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
332
333 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
334 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
335
336 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
337 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
338
339 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
340 init_timer(&timer); \
341 timer.function = handle; \
342 timer.data = (unsigned long) arg; \
343 mod_timer(&timer, (jiffies + exp)) \
344
345 /* copy mac addr to def_mac_addr array */
346 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
347 {
348 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
349 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
350 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
351 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
352 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
353 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
354 }
355 /* Add the vlan */
356 static void s2io_vlan_rx_register(struct net_device *dev,
357 struct vlan_group *grp)
358 {
359 int i;
360 struct s2io_nic *nic = dev->priv;
361 unsigned long flags[MAX_TX_FIFOS];
362 struct mac_info *mac_control = &nic->mac_control;
363 struct config_param *config = &nic->config;
364
365 for (i = 0; i < config->tx_fifo_num; i++)
366 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
367
368 nic->vlgrp = grp;
369 for (i = config->tx_fifo_num - 1; i >= 0; i--)
370 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
371 flags[i]);
372 }
373
374 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
375 static int vlan_strip_flag;
376
377 /* Unregister the vlan */
378 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
379 {
380 int i;
381 struct s2io_nic *nic = dev->priv;
382 unsigned long flags[MAX_TX_FIFOS];
383 struct mac_info *mac_control = &nic->mac_control;
384 struct config_param *config = &nic->config;
385
386 for (i = 0; i < config->tx_fifo_num; i++)
387 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
388
389 if (nic->vlgrp)
390 vlan_group_set_device(nic->vlgrp, vid, NULL);
391
392 for (i = config->tx_fifo_num - 1; i >= 0; i--)
393 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
394 flags[i]);
395 }
396
397 /*
398 * Constants to be programmed into the Xena's registers, to configure
399 * the XAUI.
400 */
401
402 #define END_SIGN 0x0
403 static const u64 herc_act_dtx_cfg[] = {
404 /* Set address */
405 0x8000051536750000ULL, 0x80000515367500E0ULL,
406 /* Write data */
407 0x8000051536750004ULL, 0x80000515367500E4ULL,
408 /* Set address */
409 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
410 /* Write data */
411 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
412 /* Set address */
413 0x801205150D440000ULL, 0x801205150D4400E0ULL,
414 /* Write data */
415 0x801205150D440004ULL, 0x801205150D4400E4ULL,
416 /* Set address */
417 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
418 /* Write data */
419 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
420 /* Done */
421 END_SIGN
422 };
423
424 static const u64 xena_dtx_cfg[] = {
425 /* Set address */
426 0x8000051500000000ULL, 0x80000515000000E0ULL,
427 /* Write data */
428 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
429 /* Set address */
430 0x8001051500000000ULL, 0x80010515000000E0ULL,
431 /* Write data */
432 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
433 /* Set address */
434 0x8002051500000000ULL, 0x80020515000000E0ULL,
435 /* Write data */
436 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
437 END_SIGN
438 };
439
440 /*
441 * Constants for Fixing the MacAddress problem seen mostly on
442 * Alpha machines.
443 */
444 static const u64 fix_mac[] = {
445 0x0060000000000000ULL, 0x0060600000000000ULL,
446 0x0040600000000000ULL, 0x0000600000000000ULL,
447 0x0020600000000000ULL, 0x0060600000000000ULL,
448 0x0020600000000000ULL, 0x0060600000000000ULL,
449 0x0020600000000000ULL, 0x0060600000000000ULL,
450 0x0020600000000000ULL, 0x0060600000000000ULL,
451 0x0020600000000000ULL, 0x0060600000000000ULL,
452 0x0020600000000000ULL, 0x0060600000000000ULL,
453 0x0020600000000000ULL, 0x0060600000000000ULL,
454 0x0020600000000000ULL, 0x0060600000000000ULL,
455 0x0020600000000000ULL, 0x0060600000000000ULL,
456 0x0020600000000000ULL, 0x0060600000000000ULL,
457 0x0020600000000000ULL, 0x0000600000000000ULL,
458 0x0040600000000000ULL, 0x0060600000000000ULL,
459 END_SIGN
460 };
461
462 MODULE_LICENSE("GPL");
463 MODULE_VERSION(DRV_VERSION);
464
465
466 /* Module Loadable parameters. */
467 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
468 S2IO_PARM_INT(rx_ring_num, 1);
469 S2IO_PARM_INT(multiq, 0);
470 S2IO_PARM_INT(rx_ring_mode, 1);
471 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
472 S2IO_PARM_INT(rmac_pause_time, 0x100);
473 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
474 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
475 S2IO_PARM_INT(shared_splits, 0);
476 S2IO_PARM_INT(tmac_util_period, 5);
477 S2IO_PARM_INT(rmac_util_period, 5);
478 S2IO_PARM_INT(l3l4hdr_size, 128);
479 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
480 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
481 /* Frequency of Rx desc syncs expressed as power of 2 */
482 S2IO_PARM_INT(rxsync_frequency, 3);
483 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
484 S2IO_PARM_INT(intr_type, 2);
485 /* Large receive offload feature */
486 static unsigned int lro_enable;
487 module_param_named(lro, lro_enable, uint, 0);
488
489 /* Max pkts to be aggregated by LRO at one time. If not specified,
490 * aggregation happens until we hit max IP pkt size(64K)
491 */
492 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
493 S2IO_PARM_INT(indicate_max_pkts, 0);
494
495 S2IO_PARM_INT(napi, 1);
496 S2IO_PARM_INT(ufo, 0);
497 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
498
499 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
500 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
501 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
502 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
503 static unsigned int rts_frm_len[MAX_RX_RINGS] =
504 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
505
506 module_param_array(tx_fifo_len, uint, NULL, 0);
507 module_param_array(rx_ring_sz, uint, NULL, 0);
508 module_param_array(rts_frm_len, uint, NULL, 0);
509
510 /*
511 * S2IO device table.
512 * This table lists all the devices that this driver supports.
513 */
514 static struct pci_device_id s2io_tbl[] __devinitdata = {
515 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
516 PCI_ANY_ID, PCI_ANY_ID},
517 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
518 PCI_ANY_ID, PCI_ANY_ID},
519 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
520 PCI_ANY_ID, PCI_ANY_ID},
521 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
522 PCI_ANY_ID, PCI_ANY_ID},
523 {0,}
524 };
525
526 MODULE_DEVICE_TABLE(pci, s2io_tbl);
527
528 static struct pci_error_handlers s2io_err_handler = {
529 .error_detected = s2io_io_error_detected,
530 .slot_reset = s2io_io_slot_reset,
531 .resume = s2io_io_resume,
532 };
533
534 static struct pci_driver s2io_driver = {
535 .name = "S2IO",
536 .id_table = s2io_tbl,
537 .probe = s2io_init_nic,
538 .remove = __devexit_p(s2io_rem_nic),
539 .err_handler = &s2io_err_handler,
540 };
541
542 /* A simplifier macro used both by init and free shared_mem Fns(). */
543 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
544
545 /* netqueue manipulation helper functions */
546 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
547 {
548 int i;
549 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
550 if (sp->config.multiq) {
551 for (i = 0; i < sp->config.tx_fifo_num; i++)
552 netif_stop_subqueue(sp->dev, i);
553 } else
554 #endif
555 {
556 for (i = 0; i < sp->config.tx_fifo_num; i++)
557 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
558 netif_stop_queue(sp->dev);
559 }
560 }
561
562 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
563 {
564 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
565 if (sp->config.multiq)
566 netif_stop_subqueue(sp->dev, fifo_no);
567 else
568 #endif
569 {
570 sp->mac_control.fifos[fifo_no].queue_state =
571 FIFO_QUEUE_STOP;
572 netif_stop_queue(sp->dev);
573 }
574 }
575
576 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
577 {
578 int i;
579 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
580 if (sp->config.multiq) {
581 for (i = 0; i < sp->config.tx_fifo_num; i++)
582 netif_start_subqueue(sp->dev, i);
583 } else
584 #endif
585 {
586 for (i = 0; i < sp->config.tx_fifo_num; i++)
587 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
588 netif_start_queue(sp->dev);
589 }
590 }
591
592 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
593 {
594 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
595 if (sp->config.multiq)
596 netif_start_subqueue(sp->dev, fifo_no);
597 else
598 #endif
599 {
600 sp->mac_control.fifos[fifo_no].queue_state =
601 FIFO_QUEUE_START;
602 netif_start_queue(sp->dev);
603 }
604 }
605
606 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
607 {
608 int i;
609 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
610 if (sp->config.multiq) {
611 for (i = 0; i < sp->config.tx_fifo_num; i++)
612 netif_wake_subqueue(sp->dev, i);
613 } else
614 #endif
615 {
616 for (i = 0; i < sp->config.tx_fifo_num; i++)
617 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
618 netif_wake_queue(sp->dev);
619 }
620 }
621
622 static inline void s2io_wake_tx_queue(
623 struct fifo_info *fifo, int cnt, u8 multiq)
624 {
625
626 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
627 if (multiq) {
628 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
629 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
630 } else
631 #endif
632 if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
633 if (netif_queue_stopped(fifo->dev)) {
634 fifo->queue_state = FIFO_QUEUE_START;
635 netif_wake_queue(fifo->dev);
636 }
637 }
638 }
639
640 /**
641 * init_shared_mem - Allocation and Initialization of Memory
642 * @nic: Device private variable.
643 * Description: The function allocates all the memory areas shared
644 * between the NIC and the driver. This includes Tx descriptors,
645 * Rx descriptors and the statistics block.
646 */
647
648 static int init_shared_mem(struct s2io_nic *nic)
649 {
650 u32 size;
651 void *tmp_v_addr, *tmp_v_addr_next;
652 dma_addr_t tmp_p_addr, tmp_p_addr_next;
653 struct RxD_block *pre_rxd_blk = NULL;
654 int i, j, blk_cnt;
655 int lst_size, lst_per_page;
656 struct net_device *dev = nic->dev;
657 unsigned long tmp;
658 struct buffAdd *ba;
659
660 struct mac_info *mac_control;
661 struct config_param *config;
662 unsigned long long mem_allocated = 0;
663
664 mac_control = &nic->mac_control;
665 config = &nic->config;
666
667
668 /* Allocation and initialization of TXDLs in FIOFs */
669 size = 0;
670 for (i = 0; i < config->tx_fifo_num; i++) {
671 size += config->tx_cfg[i].fifo_len;
672 }
673 if (size > MAX_AVAILABLE_TXDS) {
674 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
675 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
676 return -EINVAL;
677 }
678
679 size = 0;
680 for (i = 0; i < config->tx_fifo_num; i++) {
681 size = config->tx_cfg[i].fifo_len;
682 /*
683 * Legal values are from 2 to 8192
684 */
685 if (size < 2) {
686 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
687 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
688 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
689 "are 2 to 8192\n");
690 return -EINVAL;
691 }
692 }
693
694 lst_size = (sizeof(struct TxD) * config->max_txds);
695 lst_per_page = PAGE_SIZE / lst_size;
696
697 for (i = 0; i < config->tx_fifo_num; i++) {
698 int fifo_len = config->tx_cfg[i].fifo_len;
699 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
700 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
701 GFP_KERNEL);
702 if (!mac_control->fifos[i].list_info) {
703 DBG_PRINT(INFO_DBG,
704 "Malloc failed for list_info\n");
705 return -ENOMEM;
706 }
707 mem_allocated += list_holder_size;
708 }
709 for (i = 0; i < config->tx_fifo_num; i++) {
710 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
711 lst_per_page);
712 mac_control->fifos[i].tx_curr_put_info.offset = 0;
713 mac_control->fifos[i].tx_curr_put_info.fifo_len =
714 config->tx_cfg[i].fifo_len - 1;
715 mac_control->fifos[i].tx_curr_get_info.offset = 0;
716 mac_control->fifos[i].tx_curr_get_info.fifo_len =
717 config->tx_cfg[i].fifo_len - 1;
718 mac_control->fifos[i].fifo_no = i;
719 mac_control->fifos[i].nic = nic;
720 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
721 mac_control->fifos[i].dev = dev;
722
723 for (j = 0; j < page_num; j++) {
724 int k = 0;
725 dma_addr_t tmp_p;
726 void *tmp_v;
727 tmp_v = pci_alloc_consistent(nic->pdev,
728 PAGE_SIZE, &tmp_p);
729 if (!tmp_v) {
730 DBG_PRINT(INFO_DBG,
731 "pci_alloc_consistent ");
732 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
733 return -ENOMEM;
734 }
735 /* If we got a zero DMA address(can happen on
736 * certain platforms like PPC), reallocate.
737 * Store virtual address of page we don't want,
738 * to be freed later.
739 */
740 if (!tmp_p) {
741 mac_control->zerodma_virt_addr = tmp_v;
742 DBG_PRINT(INIT_DBG,
743 "%s: Zero DMA address for TxDL. ", dev->name);
744 DBG_PRINT(INIT_DBG,
745 "Virtual address %p\n", tmp_v);
746 tmp_v = pci_alloc_consistent(nic->pdev,
747 PAGE_SIZE, &tmp_p);
748 if (!tmp_v) {
749 DBG_PRINT(INFO_DBG,
750 "pci_alloc_consistent ");
751 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
752 return -ENOMEM;
753 }
754 mem_allocated += PAGE_SIZE;
755 }
756 while (k < lst_per_page) {
757 int l = (j * lst_per_page) + k;
758 if (l == config->tx_cfg[i].fifo_len)
759 break;
760 mac_control->fifos[i].list_info[l].list_virt_addr =
761 tmp_v + (k * lst_size);
762 mac_control->fifos[i].list_info[l].list_phy_addr =
763 tmp_p + (k * lst_size);
764 k++;
765 }
766 }
767 }
768
769 for (i = 0; i < config->tx_fifo_num; i++) {
770 size = config->tx_cfg[i].fifo_len;
771 mac_control->fifos[i].ufo_in_band_v
772 = kcalloc(size, sizeof(u64), GFP_KERNEL);
773 if (!mac_control->fifos[i].ufo_in_band_v)
774 return -ENOMEM;
775 mem_allocated += (size * sizeof(u64));
776 }
777
778 /* Allocation and initialization of RXDs in Rings */
779 size = 0;
780 for (i = 0; i < config->rx_ring_num; i++) {
781 if (config->rx_cfg[i].num_rxd %
782 (rxd_count[nic->rxd_mode] + 1)) {
783 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
784 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
785 i);
786 DBG_PRINT(ERR_DBG, "RxDs per Block");
787 return FAILURE;
788 }
789 size += config->rx_cfg[i].num_rxd;
790 mac_control->rings[i].block_count =
791 config->rx_cfg[i].num_rxd /
792 (rxd_count[nic->rxd_mode] + 1 );
793 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
794 mac_control->rings[i].block_count;
795 }
796 if (nic->rxd_mode == RXD_MODE_1)
797 size = (size * (sizeof(struct RxD1)));
798 else
799 size = (size * (sizeof(struct RxD3)));
800
801 for (i = 0; i < config->rx_ring_num; i++) {
802 mac_control->rings[i].rx_curr_get_info.block_index = 0;
803 mac_control->rings[i].rx_curr_get_info.offset = 0;
804 mac_control->rings[i].rx_curr_get_info.ring_len =
805 config->rx_cfg[i].num_rxd - 1;
806 mac_control->rings[i].rx_curr_put_info.block_index = 0;
807 mac_control->rings[i].rx_curr_put_info.offset = 0;
808 mac_control->rings[i].rx_curr_put_info.ring_len =
809 config->rx_cfg[i].num_rxd - 1;
810 mac_control->rings[i].nic = nic;
811 mac_control->rings[i].ring_no = i;
812 mac_control->rings[i].lro = lro_enable;
813
814 blk_cnt = config->rx_cfg[i].num_rxd /
815 (rxd_count[nic->rxd_mode] + 1);
816 /* Allocating all the Rx blocks */
817 for (j = 0; j < blk_cnt; j++) {
818 struct rx_block_info *rx_blocks;
819 int l;
820
821 rx_blocks = &mac_control->rings[i].rx_blocks[j];
822 size = SIZE_OF_BLOCK; //size is always page size
823 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
824 &tmp_p_addr);
825 if (tmp_v_addr == NULL) {
826 /*
827 * In case of failure, free_shared_mem()
828 * is called, which should free any
829 * memory that was alloced till the
830 * failure happened.
831 */
832 rx_blocks->block_virt_addr = tmp_v_addr;
833 return -ENOMEM;
834 }
835 mem_allocated += size;
836 memset(tmp_v_addr, 0, size);
837 rx_blocks->block_virt_addr = tmp_v_addr;
838 rx_blocks->block_dma_addr = tmp_p_addr;
839 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
840 rxd_count[nic->rxd_mode],
841 GFP_KERNEL);
842 if (!rx_blocks->rxds)
843 return -ENOMEM;
844 mem_allocated +=
845 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
846 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
847 rx_blocks->rxds[l].virt_addr =
848 rx_blocks->block_virt_addr +
849 (rxd_size[nic->rxd_mode] * l);
850 rx_blocks->rxds[l].dma_addr =
851 rx_blocks->block_dma_addr +
852 (rxd_size[nic->rxd_mode] * l);
853 }
854 }
855 /* Interlinking all Rx Blocks */
856 for (j = 0; j < blk_cnt; j++) {
857 tmp_v_addr =
858 mac_control->rings[i].rx_blocks[j].block_virt_addr;
859 tmp_v_addr_next =
860 mac_control->rings[i].rx_blocks[(j + 1) %
861 blk_cnt].block_virt_addr;
862 tmp_p_addr =
863 mac_control->rings[i].rx_blocks[j].block_dma_addr;
864 tmp_p_addr_next =
865 mac_control->rings[i].rx_blocks[(j + 1) %
866 blk_cnt].block_dma_addr;
867
868 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
869 pre_rxd_blk->reserved_2_pNext_RxD_block =
870 (unsigned long) tmp_v_addr_next;
871 pre_rxd_blk->pNext_RxD_Blk_physical =
872 (u64) tmp_p_addr_next;
873 }
874 }
875 if (nic->rxd_mode == RXD_MODE_3B) {
876 /*
877 * Allocation of Storages for buffer addresses in 2BUFF mode
878 * and the buffers as well.
879 */
880 for (i = 0; i < config->rx_ring_num; i++) {
881 blk_cnt = config->rx_cfg[i].num_rxd /
882 (rxd_count[nic->rxd_mode]+ 1);
883 mac_control->rings[i].ba =
884 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
885 GFP_KERNEL);
886 if (!mac_control->rings[i].ba)
887 return -ENOMEM;
888 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
889 for (j = 0; j < blk_cnt; j++) {
890 int k = 0;
891 mac_control->rings[i].ba[j] =
892 kmalloc((sizeof(struct buffAdd) *
893 (rxd_count[nic->rxd_mode] + 1)),
894 GFP_KERNEL);
895 if (!mac_control->rings[i].ba[j])
896 return -ENOMEM;
897 mem_allocated += (sizeof(struct buffAdd) * \
898 (rxd_count[nic->rxd_mode] + 1));
899 while (k != rxd_count[nic->rxd_mode]) {
900 ba = &mac_control->rings[i].ba[j][k];
901
902 ba->ba_0_org = (void *) kmalloc
903 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
904 if (!ba->ba_0_org)
905 return -ENOMEM;
906 mem_allocated +=
907 (BUF0_LEN + ALIGN_SIZE);
908 tmp = (unsigned long)ba->ba_0_org;
909 tmp += ALIGN_SIZE;
910 tmp &= ~((unsigned long) ALIGN_SIZE);
911 ba->ba_0 = (void *) tmp;
912
913 ba->ba_1_org = (void *) kmalloc
914 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
915 if (!ba->ba_1_org)
916 return -ENOMEM;
917 mem_allocated
918 += (BUF1_LEN + ALIGN_SIZE);
919 tmp = (unsigned long) ba->ba_1_org;
920 tmp += ALIGN_SIZE;
921 tmp &= ~((unsigned long) ALIGN_SIZE);
922 ba->ba_1 = (void *) tmp;
923 k++;
924 }
925 }
926 }
927 }
928
929 /* Allocation and initialization of Statistics block */
930 size = sizeof(struct stat_block);
931 mac_control->stats_mem = pci_alloc_consistent
932 (nic->pdev, size, &mac_control->stats_mem_phy);
933
934 if (!mac_control->stats_mem) {
935 /*
936 * In case of failure, free_shared_mem() is called, which
937 * should free any memory that was alloced till the
938 * failure happened.
939 */
940 return -ENOMEM;
941 }
942 mem_allocated += size;
943 mac_control->stats_mem_sz = size;
944
945 tmp_v_addr = mac_control->stats_mem;
946 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
947 memset(tmp_v_addr, 0, size);
948 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
949 (unsigned long long) tmp_p_addr);
950 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
951 return SUCCESS;
952 }
953
954 /**
955 * free_shared_mem - Free the allocated Memory
956 * @nic: Device private variable.
957 * Description: This function is to free all memory locations allocated by
958 * the init_shared_mem() function and return it to the kernel.
959 */
960
961 static void free_shared_mem(struct s2io_nic *nic)
962 {
963 int i, j, blk_cnt, size;
964 void *tmp_v_addr;
965 dma_addr_t tmp_p_addr;
966 struct mac_info *mac_control;
967 struct config_param *config;
968 int lst_size, lst_per_page;
969 struct net_device *dev;
970 int page_num = 0;
971
972 if (!nic)
973 return;
974
975 dev = nic->dev;
976
977 mac_control = &nic->mac_control;
978 config = &nic->config;
979
980 lst_size = (sizeof(struct TxD) * config->max_txds);
981 lst_per_page = PAGE_SIZE / lst_size;
982
983 for (i = 0; i < config->tx_fifo_num; i++) {
984 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
985 lst_per_page);
986 for (j = 0; j < page_num; j++) {
987 int mem_blks = (j * lst_per_page);
988 if (!mac_control->fifos[i].list_info)
989 return;
990 if (!mac_control->fifos[i].list_info[mem_blks].
991 list_virt_addr)
992 break;
993 pci_free_consistent(nic->pdev, PAGE_SIZE,
994 mac_control->fifos[i].
995 list_info[mem_blks].
996 list_virt_addr,
997 mac_control->fifos[i].
998 list_info[mem_blks].
999 list_phy_addr);
1000 nic->mac_control.stats_info->sw_stat.mem_freed
1001 += PAGE_SIZE;
1002 }
1003 /* If we got a zero DMA address during allocation,
1004 * free the page now
1005 */
1006 if (mac_control->zerodma_virt_addr) {
1007 pci_free_consistent(nic->pdev, PAGE_SIZE,
1008 mac_control->zerodma_virt_addr,
1009 (dma_addr_t)0);
1010 DBG_PRINT(INIT_DBG,
1011 "%s: Freeing TxDL with zero DMA addr. ",
1012 dev->name);
1013 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
1014 mac_control->zerodma_virt_addr);
1015 nic->mac_control.stats_info->sw_stat.mem_freed
1016 += PAGE_SIZE;
1017 }
1018 kfree(mac_control->fifos[i].list_info);
1019 nic->mac_control.stats_info->sw_stat.mem_freed +=
1020 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1021 }
1022
1023 size = SIZE_OF_BLOCK;
1024 for (i = 0; i < config->rx_ring_num; i++) {
1025 blk_cnt = mac_control->rings[i].block_count;
1026 for (j = 0; j < blk_cnt; j++) {
1027 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
1028 block_virt_addr;
1029 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
1030 block_dma_addr;
1031 if (tmp_v_addr == NULL)
1032 break;
1033 pci_free_consistent(nic->pdev, size,
1034 tmp_v_addr, tmp_p_addr);
1035 nic->mac_control.stats_info->sw_stat.mem_freed += size;
1036 kfree(mac_control->rings[i].rx_blocks[j].rxds);
1037 nic->mac_control.stats_info->sw_stat.mem_freed +=
1038 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1039 }
1040 }
1041
1042 if (nic->rxd_mode == RXD_MODE_3B) {
1043 /* Freeing buffer storage addresses in 2BUFF mode. */
1044 for (i = 0; i < config->rx_ring_num; i++) {
1045 blk_cnt = config->rx_cfg[i].num_rxd /
1046 (rxd_count[nic->rxd_mode] + 1);
1047 for (j = 0; j < blk_cnt; j++) {
1048 int k = 0;
1049 if (!mac_control->rings[i].ba[j])
1050 continue;
1051 while (k != rxd_count[nic->rxd_mode]) {
1052 struct buffAdd *ba =
1053 &mac_control->rings[i].ba[j][k];
1054 kfree(ba->ba_0_org);
1055 nic->mac_control.stats_info->sw_stat.\
1056 mem_freed += (BUF0_LEN + ALIGN_SIZE);
1057 kfree(ba->ba_1_org);
1058 nic->mac_control.stats_info->sw_stat.\
1059 mem_freed += (BUF1_LEN + ALIGN_SIZE);
1060 k++;
1061 }
1062 kfree(mac_control->rings[i].ba[j]);
1063 nic->mac_control.stats_info->sw_stat.mem_freed +=
1064 (sizeof(struct buffAdd) *
1065 (rxd_count[nic->rxd_mode] + 1));
1066 }
1067 kfree(mac_control->rings[i].ba);
1068 nic->mac_control.stats_info->sw_stat.mem_freed +=
1069 (sizeof(struct buffAdd *) * blk_cnt);
1070 }
1071 }
1072
1073 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1074 if (mac_control->fifos[i].ufo_in_band_v) {
1075 nic->mac_control.stats_info->sw_stat.mem_freed
1076 += (config->tx_cfg[i].fifo_len * sizeof(u64));
1077 kfree(mac_control->fifos[i].ufo_in_band_v);
1078 }
1079 }
1080
1081 if (mac_control->stats_mem) {
1082 nic->mac_control.stats_info->sw_stat.mem_freed +=
1083 mac_control->stats_mem_sz;
1084 pci_free_consistent(nic->pdev,
1085 mac_control->stats_mem_sz,
1086 mac_control->stats_mem,
1087 mac_control->stats_mem_phy);
1088 }
1089 }
1090
1091 /**
1092 * s2io_verify_pci_mode -
1093 */
1094
1095 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1096 {
1097 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1098 register u64 val64 = 0;
1099 int mode;
1100
1101 val64 = readq(&bar0->pci_mode);
1102 mode = (u8)GET_PCI_MODE(val64);
1103
1104 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1105 return -1; /* Unknown PCI mode */
1106 return mode;
1107 }
1108
1109 #define NEC_VENID 0x1033
1110 #define NEC_DEVID 0x0125
1111 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1112 {
1113 struct pci_dev *tdev = NULL;
1114 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1115 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1116 if (tdev->bus == s2io_pdev->bus->parent) {
1117 pci_dev_put(tdev);
1118 return 1;
1119 }
1120 }
1121 }
1122 return 0;
1123 }
1124
1125 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1126 /**
1127 * s2io_print_pci_mode -
1128 */
1129 static int s2io_print_pci_mode(struct s2io_nic *nic)
1130 {
1131 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1132 register u64 val64 = 0;
1133 int mode;
1134 struct config_param *config = &nic->config;
1135
1136 val64 = readq(&bar0->pci_mode);
1137 mode = (u8)GET_PCI_MODE(val64);
1138
1139 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1140 return -1; /* Unknown PCI mode */
1141
1142 config->bus_speed = bus_speed[mode];
1143
1144 if (s2io_on_nec_bridge(nic->pdev)) {
1145 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1146 nic->dev->name);
1147 return mode;
1148 }
1149
1150 if (val64 & PCI_MODE_32_BITS) {
1151 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1152 } else {
1153 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1154 }
1155
1156 switch(mode) {
1157 case PCI_MODE_PCI_33:
1158 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1159 break;
1160 case PCI_MODE_PCI_66:
1161 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1162 break;
1163 case PCI_MODE_PCIX_M1_66:
1164 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1165 break;
1166 case PCI_MODE_PCIX_M1_100:
1167 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1168 break;
1169 case PCI_MODE_PCIX_M1_133:
1170 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1171 break;
1172 case PCI_MODE_PCIX_M2_66:
1173 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1174 break;
1175 case PCI_MODE_PCIX_M2_100:
1176 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1177 break;
1178 case PCI_MODE_PCIX_M2_133:
1179 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1180 break;
1181 default:
1182 return -1; /* Unsupported bus speed */
1183 }
1184
1185 return mode;
1186 }
1187
1188 /**
1189 * init_tti - Initialization transmit traffic interrupt scheme
1190 * @nic: device private variable
1191 * @link: link status (UP/DOWN) used to enable/disable continuous
1192 * transmit interrupts
1193 * Description: The function configures transmit traffic interrupts
1194 * Return Value: SUCCESS on success and
1195 * '-1' on failure
1196 */
1197
1198 static int init_tti(struct s2io_nic *nic, int link)
1199 {
1200 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1201 register u64 val64 = 0;
1202 int i;
1203 struct config_param *config;
1204
1205 config = &nic->config;
1206
1207 for (i = 0; i < config->tx_fifo_num; i++) {
1208 /*
1209 * TTI Initialization. Default Tx timer gets us about
1210 * 250 interrupts per sec. Continuous interrupts are enabled
1211 * by default.
1212 */
1213 if (nic->device_type == XFRAME_II_DEVICE) {
1214 int count = (nic->config.bus_speed * 125)/2;
1215 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1216 } else
1217 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1218
1219 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1220 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1221 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1222 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1223 if (i == 0)
1224 if (use_continuous_tx_intrs && (link == LINK_UP))
1225 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1226 writeq(val64, &bar0->tti_data1_mem);
1227
1228 if (nic->config.intr_type == MSI_X) {
1229 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1230 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1231 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1232 TTI_DATA2_MEM_TX_UFC_D(0x300);
1233 } else {
1234 if ((nic->config.tx_steering_type ==
1235 TX_DEFAULT_STEERING) &&
1236 (config->tx_fifo_num > 1) &&
1237 (i >= nic->udp_fifo_idx) &&
1238 (i < (nic->udp_fifo_idx +
1239 nic->total_udp_fifos)))
1240 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1241 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1242 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1243 TTI_DATA2_MEM_TX_UFC_D(0x120);
1244 else
1245 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1246 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1247 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1248 TTI_DATA2_MEM_TX_UFC_D(0x80);
1249 }
1250
1251 writeq(val64, &bar0->tti_data2_mem);
1252
1253 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1254 TTI_CMD_MEM_OFFSET(i);
1255 writeq(val64, &bar0->tti_command_mem);
1256
1257 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1258 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1259 return FAILURE;
1260 }
1261
1262 return SUCCESS;
1263 }
1264
1265 /**
1266 * init_nic - Initialization of hardware
1267 * @nic: device private variable
1268 * Description: The function sequentially configures every block
1269 * of the H/W from their reset values.
1270 * Return Value: SUCCESS on success and
1271 * '-1' on failure (endian settings incorrect).
1272 */
1273
1274 static int init_nic(struct s2io_nic *nic)
1275 {
1276 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1277 struct net_device *dev = nic->dev;
1278 register u64 val64 = 0;
1279 void __iomem *add;
1280 u32 time;
1281 int i, j;
1282 struct mac_info *mac_control;
1283 struct config_param *config;
1284 int dtx_cnt = 0;
1285 unsigned long long mem_share;
1286 int mem_size;
1287
1288 mac_control = &nic->mac_control;
1289 config = &nic->config;
1290
1291 /* to set the swapper controle on the card */
1292 if(s2io_set_swapper(nic)) {
1293 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1294 return -EIO;
1295 }
1296
1297 /*
1298 * Herc requires EOI to be removed from reset before XGXS, so..
1299 */
1300 if (nic->device_type & XFRAME_II_DEVICE) {
1301 val64 = 0xA500000000ULL;
1302 writeq(val64, &bar0->sw_reset);
1303 msleep(500);
1304 val64 = readq(&bar0->sw_reset);
1305 }
1306
1307 /* Remove XGXS from reset state */
1308 val64 = 0;
1309 writeq(val64, &bar0->sw_reset);
1310 msleep(500);
1311 val64 = readq(&bar0->sw_reset);
1312
1313 /* Ensure that it's safe to access registers by checking
1314 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1315 */
1316 if (nic->device_type == XFRAME_II_DEVICE) {
1317 for (i = 0; i < 50; i++) {
1318 val64 = readq(&bar0->adapter_status);
1319 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1320 break;
1321 msleep(10);
1322 }
1323 if (i == 50)
1324 return -ENODEV;
1325 }
1326
1327 /* Enable Receiving broadcasts */
1328 add = &bar0->mac_cfg;
1329 val64 = readq(&bar0->mac_cfg);
1330 val64 |= MAC_RMAC_BCAST_ENABLE;
1331 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1332 writel((u32) val64, add);
1333 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1334 writel((u32) (val64 >> 32), (add + 4));
1335
1336 /* Read registers in all blocks */
1337 val64 = readq(&bar0->mac_int_mask);
1338 val64 = readq(&bar0->mc_int_mask);
1339 val64 = readq(&bar0->xgxs_int_mask);
1340
1341 /* Set MTU */
1342 val64 = dev->mtu;
1343 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1344
1345 if (nic->device_type & XFRAME_II_DEVICE) {
1346 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1347 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1348 &bar0->dtx_control, UF);
1349 if (dtx_cnt & 0x1)
1350 msleep(1); /* Necessary!! */
1351 dtx_cnt++;
1352 }
1353 } else {
1354 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1355 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1356 &bar0->dtx_control, UF);
1357 val64 = readq(&bar0->dtx_control);
1358 dtx_cnt++;
1359 }
1360 }
1361
1362 /* Tx DMA Initialization */
1363 val64 = 0;
1364 writeq(val64, &bar0->tx_fifo_partition_0);
1365 writeq(val64, &bar0->tx_fifo_partition_1);
1366 writeq(val64, &bar0->tx_fifo_partition_2);
1367 writeq(val64, &bar0->tx_fifo_partition_3);
1368
1369
1370 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1371 val64 |=
1372 vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1373 13) | vBIT(config->tx_cfg[i].fifo_priority,
1374 ((j * 32) + 5), 3);
1375
1376 if (i == (config->tx_fifo_num - 1)) {
1377 if (i % 2 == 0)
1378 i++;
1379 }
1380
1381 switch (i) {
1382 case 1:
1383 writeq(val64, &bar0->tx_fifo_partition_0);
1384 val64 = 0;
1385 j = 0;
1386 break;
1387 case 3:
1388 writeq(val64, &bar0->tx_fifo_partition_1);
1389 val64 = 0;
1390 j = 0;
1391 break;
1392 case 5:
1393 writeq(val64, &bar0->tx_fifo_partition_2);
1394 val64 = 0;
1395 j = 0;
1396 break;
1397 case 7:
1398 writeq(val64, &bar0->tx_fifo_partition_3);
1399 val64 = 0;
1400 j = 0;
1401 break;
1402 default:
1403 j++;
1404 break;
1405 }
1406 }
1407
1408 /*
1409 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1410 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1411 */
1412 if ((nic->device_type == XFRAME_I_DEVICE) &&
1413 (nic->pdev->revision < 4))
1414 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1415
1416 val64 = readq(&bar0->tx_fifo_partition_0);
1417 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1418 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1419
1420 /*
1421 * Initialization of Tx_PA_CONFIG register to ignore packet
1422 * integrity checking.
1423 */
1424 val64 = readq(&bar0->tx_pa_cfg);
1425 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1426 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1427 writeq(val64, &bar0->tx_pa_cfg);
1428
1429 /* Rx DMA intialization. */
1430 val64 = 0;
1431 for (i = 0; i < config->rx_ring_num; i++) {
1432 val64 |=
1433 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1434 3);
1435 }
1436 writeq(val64, &bar0->rx_queue_priority);
1437
1438 /*
1439 * Allocating equal share of memory to all the
1440 * configured Rings.
1441 */
1442 val64 = 0;
1443 if (nic->device_type & XFRAME_II_DEVICE)
1444 mem_size = 32;
1445 else
1446 mem_size = 64;
1447
1448 for (i = 0; i < config->rx_ring_num; i++) {
1449 switch (i) {
1450 case 0:
1451 mem_share = (mem_size / config->rx_ring_num +
1452 mem_size % config->rx_ring_num);
1453 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1454 continue;
1455 case 1:
1456 mem_share = (mem_size / config->rx_ring_num);
1457 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1458 continue;
1459 case 2:
1460 mem_share = (mem_size / config->rx_ring_num);
1461 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1462 continue;
1463 case 3:
1464 mem_share = (mem_size / config->rx_ring_num);
1465 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1466 continue;
1467 case 4:
1468 mem_share = (mem_size / config->rx_ring_num);
1469 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1470 continue;
1471 case 5:
1472 mem_share = (mem_size / config->rx_ring_num);
1473 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1474 continue;
1475 case 6:
1476 mem_share = (mem_size / config->rx_ring_num);
1477 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1478 continue;
1479 case 7:
1480 mem_share = (mem_size / config->rx_ring_num);
1481 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1482 continue;
1483 }
1484 }
1485 writeq(val64, &bar0->rx_queue_cfg);
1486
1487 /*
1488 * Filling Tx round robin registers
1489 * as per the number of FIFOs for equal scheduling priority
1490 */
1491 switch (config->tx_fifo_num) {
1492 case 1:
1493 val64 = 0x0;
1494 writeq(val64, &bar0->tx_w_round_robin_0);
1495 writeq(val64, &bar0->tx_w_round_robin_1);
1496 writeq(val64, &bar0->tx_w_round_robin_2);
1497 writeq(val64, &bar0->tx_w_round_robin_3);
1498 writeq(val64, &bar0->tx_w_round_robin_4);
1499 break;
1500 case 2:
1501 val64 = 0x0001000100010001ULL;
1502 writeq(val64, &bar0->tx_w_round_robin_0);
1503 writeq(val64, &bar0->tx_w_round_robin_1);
1504 writeq(val64, &bar0->tx_w_round_robin_2);
1505 writeq(val64, &bar0->tx_w_round_robin_3);
1506 val64 = 0x0001000100000000ULL;
1507 writeq(val64, &bar0->tx_w_round_robin_4);
1508 break;
1509 case 3:
1510 val64 = 0x0001020001020001ULL;
1511 writeq(val64, &bar0->tx_w_round_robin_0);
1512 val64 = 0x0200010200010200ULL;
1513 writeq(val64, &bar0->tx_w_round_robin_1);
1514 val64 = 0x0102000102000102ULL;
1515 writeq(val64, &bar0->tx_w_round_robin_2);
1516 val64 = 0x0001020001020001ULL;
1517 writeq(val64, &bar0->tx_w_round_robin_3);
1518 val64 = 0x0200010200000000ULL;
1519 writeq(val64, &bar0->tx_w_round_robin_4);
1520 break;
1521 case 4:
1522 val64 = 0x0001020300010203ULL;
1523 writeq(val64, &bar0->tx_w_round_robin_0);
1524 writeq(val64, &bar0->tx_w_round_robin_1);
1525 writeq(val64, &bar0->tx_w_round_robin_2);
1526 writeq(val64, &bar0->tx_w_round_robin_3);
1527 val64 = 0x0001020300000000ULL;
1528 writeq(val64, &bar0->tx_w_round_robin_4);
1529 break;
1530 case 5:
1531 val64 = 0x0001020304000102ULL;
1532 writeq(val64, &bar0->tx_w_round_robin_0);
1533 val64 = 0x0304000102030400ULL;
1534 writeq(val64, &bar0->tx_w_round_robin_1);
1535 val64 = 0x0102030400010203ULL;
1536 writeq(val64, &bar0->tx_w_round_robin_2);
1537 val64 = 0x0400010203040001ULL;
1538 writeq(val64, &bar0->tx_w_round_robin_3);
1539 val64 = 0x0203040000000000ULL;
1540 writeq(val64, &bar0->tx_w_round_robin_4);
1541 break;
1542 case 6:
1543 val64 = 0x0001020304050001ULL;
1544 writeq(val64, &bar0->tx_w_round_robin_0);
1545 val64 = 0x0203040500010203ULL;
1546 writeq(val64, &bar0->tx_w_round_robin_1);
1547 val64 = 0x0405000102030405ULL;
1548 writeq(val64, &bar0->tx_w_round_robin_2);
1549 val64 = 0x0001020304050001ULL;
1550 writeq(val64, &bar0->tx_w_round_robin_3);
1551 val64 = 0x0203040500000000ULL;
1552 writeq(val64, &bar0->tx_w_round_robin_4);
1553 break;
1554 case 7:
1555 val64 = 0x0001020304050600ULL;
1556 writeq(val64, &bar0->tx_w_round_robin_0);
1557 val64 = 0x0102030405060001ULL;
1558 writeq(val64, &bar0->tx_w_round_robin_1);
1559 val64 = 0x0203040506000102ULL;
1560 writeq(val64, &bar0->tx_w_round_robin_2);
1561 val64 = 0x0304050600010203ULL;
1562 writeq(val64, &bar0->tx_w_round_robin_3);
1563 val64 = 0x0405060000000000ULL;
1564 writeq(val64, &bar0->tx_w_round_robin_4);
1565 break;
1566 case 8:
1567 val64 = 0x0001020304050607ULL;
1568 writeq(val64, &bar0->tx_w_round_robin_0);
1569 writeq(val64, &bar0->tx_w_round_robin_1);
1570 writeq(val64, &bar0->tx_w_round_robin_2);
1571 writeq(val64, &bar0->tx_w_round_robin_3);
1572 val64 = 0x0001020300000000ULL;
1573 writeq(val64, &bar0->tx_w_round_robin_4);
1574 break;
1575 }
1576
1577 /* Enable all configured Tx FIFO partitions */
1578 val64 = readq(&bar0->tx_fifo_partition_0);
1579 val64 |= (TX_FIFO_PARTITION_EN);
1580 writeq(val64, &bar0->tx_fifo_partition_0);
1581
1582 /* Filling the Rx round robin registers as per the
1583 * number of Rings and steering based on QoS with
1584 * equal priority.
1585 */
1586 switch (config->rx_ring_num) {
1587 case 1:
1588 val64 = 0x0;
1589 writeq(val64, &bar0->rx_w_round_robin_0);
1590 writeq(val64, &bar0->rx_w_round_robin_1);
1591 writeq(val64, &bar0->rx_w_round_robin_2);
1592 writeq(val64, &bar0->rx_w_round_robin_3);
1593 writeq(val64, &bar0->rx_w_round_robin_4);
1594
1595 val64 = 0x8080808080808080ULL;
1596 writeq(val64, &bar0->rts_qos_steering);
1597 break;
1598 case 2:
1599 val64 = 0x0001000100010001ULL;
1600 writeq(val64, &bar0->rx_w_round_robin_0);
1601 writeq(val64, &bar0->rx_w_round_robin_1);
1602 writeq(val64, &bar0->rx_w_round_robin_2);
1603 writeq(val64, &bar0->rx_w_round_robin_3);
1604 val64 = 0x0001000100000000ULL;
1605 writeq(val64, &bar0->rx_w_round_robin_4);
1606
1607 val64 = 0x8080808040404040ULL;
1608 writeq(val64, &bar0->rts_qos_steering);
1609 break;
1610 case 3:
1611 val64 = 0x0001020001020001ULL;
1612 writeq(val64, &bar0->rx_w_round_robin_0);
1613 val64 = 0x0200010200010200ULL;
1614 writeq(val64, &bar0->rx_w_round_robin_1);
1615 val64 = 0x0102000102000102ULL;
1616 writeq(val64, &bar0->rx_w_round_robin_2);
1617 val64 = 0x0001020001020001ULL;
1618 writeq(val64, &bar0->rx_w_round_robin_3);
1619 val64 = 0x0200010200000000ULL;
1620 writeq(val64, &bar0->rx_w_round_robin_4);
1621
1622 val64 = 0x8080804040402020ULL;
1623 writeq(val64, &bar0->rts_qos_steering);
1624 break;
1625 case 4:
1626 val64 = 0x0001020300010203ULL;
1627 writeq(val64, &bar0->rx_w_round_robin_0);
1628 writeq(val64, &bar0->rx_w_round_robin_1);
1629 writeq(val64, &bar0->rx_w_round_robin_2);
1630 writeq(val64, &bar0->rx_w_round_robin_3);
1631 val64 = 0x0001020300000000ULL;
1632 writeq(val64, &bar0->rx_w_round_robin_4);
1633
1634 val64 = 0x8080404020201010ULL;
1635 writeq(val64, &bar0->rts_qos_steering);
1636 break;
1637 case 5:
1638 val64 = 0x0001020304000102ULL;
1639 writeq(val64, &bar0->rx_w_round_robin_0);
1640 val64 = 0x0304000102030400ULL;
1641 writeq(val64, &bar0->rx_w_round_robin_1);
1642 val64 = 0x0102030400010203ULL;
1643 writeq(val64, &bar0->rx_w_round_robin_2);
1644 val64 = 0x0400010203040001ULL;
1645 writeq(val64, &bar0->rx_w_round_robin_3);
1646 val64 = 0x0203040000000000ULL;
1647 writeq(val64, &bar0->rx_w_round_robin_4);
1648
1649 val64 = 0x8080404020201008ULL;
1650 writeq(val64, &bar0->rts_qos_steering);
1651 break;
1652 case 6:
1653 val64 = 0x0001020304050001ULL;
1654 writeq(val64, &bar0->rx_w_round_robin_0);
1655 val64 = 0x0203040500010203ULL;
1656 writeq(val64, &bar0->rx_w_round_robin_1);
1657 val64 = 0x0405000102030405ULL;
1658 writeq(val64, &bar0->rx_w_round_robin_2);
1659 val64 = 0x0001020304050001ULL;
1660 writeq(val64, &bar0->rx_w_round_robin_3);
1661 val64 = 0x0203040500000000ULL;
1662 writeq(val64, &bar0->rx_w_round_robin_4);
1663
1664 val64 = 0x8080404020100804ULL;
1665 writeq(val64, &bar0->rts_qos_steering);
1666 break;
1667 case 7:
1668 val64 = 0x0001020304050600ULL;
1669 writeq(val64, &bar0->rx_w_round_robin_0);
1670 val64 = 0x0102030405060001ULL;
1671 writeq(val64, &bar0->rx_w_round_robin_1);
1672 val64 = 0x0203040506000102ULL;
1673 writeq(val64, &bar0->rx_w_round_robin_2);
1674 val64 = 0x0304050600010203ULL;
1675 writeq(val64, &bar0->rx_w_round_robin_3);
1676 val64 = 0x0405060000000000ULL;
1677 writeq(val64, &bar0->rx_w_round_robin_4);
1678
1679 val64 = 0x8080402010080402ULL;
1680 writeq(val64, &bar0->rts_qos_steering);
1681 break;
1682 case 8:
1683 val64 = 0x0001020304050607ULL;
1684 writeq(val64, &bar0->rx_w_round_robin_0);
1685 writeq(val64, &bar0->rx_w_round_robin_1);
1686 writeq(val64, &bar0->rx_w_round_robin_2);
1687 writeq(val64, &bar0->rx_w_round_robin_3);
1688 val64 = 0x0001020300000000ULL;
1689 writeq(val64, &bar0->rx_w_round_robin_4);
1690
1691 val64 = 0x8040201008040201ULL;
1692 writeq(val64, &bar0->rts_qos_steering);
1693 break;
1694 }
1695
1696 /* UDP Fix */
1697 val64 = 0;
1698 for (i = 0; i < 8; i++)
1699 writeq(val64, &bar0->rts_frm_len_n[i]);
1700
1701 /* Set the default rts frame length for the rings configured */
1702 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1703 for (i = 0 ; i < config->rx_ring_num ; i++)
1704 writeq(val64, &bar0->rts_frm_len_n[i]);
1705
1706 /* Set the frame length for the configured rings
1707 * desired by the user
1708 */
1709 for (i = 0; i < config->rx_ring_num; i++) {
1710 /* If rts_frm_len[i] == 0 then it is assumed that user not
1711 * specified frame length steering.
1712 * If the user provides the frame length then program
1713 * the rts_frm_len register for those values or else
1714 * leave it as it is.
1715 */
1716 if (rts_frm_len[i] != 0) {
1717 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1718 &bar0->rts_frm_len_n[i]);
1719 }
1720 }
1721
1722 /* Disable differentiated services steering logic */
1723 for (i = 0; i < 64; i++) {
1724 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1725 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1726 dev->name);
1727 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1728 return -ENODEV;
1729 }
1730 }
1731
1732 /* Program statistics memory */
1733 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1734
1735 if (nic->device_type == XFRAME_II_DEVICE) {
1736 val64 = STAT_BC(0x320);
1737 writeq(val64, &bar0->stat_byte_cnt);
1738 }
1739
1740 /*
1741 * Initializing the sampling rate for the device to calculate the
1742 * bandwidth utilization.
1743 */
1744 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1745 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1746 writeq(val64, &bar0->mac_link_util);
1747
1748 /*
1749 * Initializing the Transmit and Receive Traffic Interrupt
1750 * Scheme.
1751 */
1752
1753 /* Initialize TTI */
1754 if (SUCCESS != init_tti(nic, nic->last_link_state))
1755 return -ENODEV;
1756
1757 /* RTI Initialization */
1758 if (nic->device_type == XFRAME_II_DEVICE) {
1759 /*
1760 * Programmed to generate Apprx 500 Intrs per
1761 * second
1762 */
1763 int count = (nic->config.bus_speed * 125)/4;
1764 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1765 } else
1766 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1767 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1768 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1769 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1770
1771 writeq(val64, &bar0->rti_data1_mem);
1772
1773 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1774 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1775 if (nic->config.intr_type == MSI_X)
1776 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1777 RTI_DATA2_MEM_RX_UFC_D(0x40));
1778 else
1779 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1780 RTI_DATA2_MEM_RX_UFC_D(0x80));
1781 writeq(val64, &bar0->rti_data2_mem);
1782
1783 for (i = 0; i < config->rx_ring_num; i++) {
1784 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1785 | RTI_CMD_MEM_OFFSET(i);
1786 writeq(val64, &bar0->rti_command_mem);
1787
1788 /*
1789 * Once the operation completes, the Strobe bit of the
1790 * command register will be reset. We poll for this
1791 * particular condition. We wait for a maximum of 500ms
1792 * for the operation to complete, if it's not complete
1793 * by then we return error.
1794 */
1795 time = 0;
1796 while (TRUE) {
1797 val64 = readq(&bar0->rti_command_mem);
1798 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1799 break;
1800
1801 if (time > 10) {
1802 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1803 dev->name);
1804 return -ENODEV;
1805 }
1806 time++;
1807 msleep(50);
1808 }
1809 }
1810
1811 /*
1812 * Initializing proper values as Pause threshold into all
1813 * the 8 Queues on Rx side.
1814 */
1815 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1816 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1817
1818 /* Disable RMAC PAD STRIPPING */
1819 add = &bar0->mac_cfg;
1820 val64 = readq(&bar0->mac_cfg);
1821 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1822 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1823 writel((u32) (val64), add);
1824 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1825 writel((u32) (val64 >> 32), (add + 4));
1826 val64 = readq(&bar0->mac_cfg);
1827
1828 /* Enable FCS stripping by adapter */
1829 add = &bar0->mac_cfg;
1830 val64 = readq(&bar0->mac_cfg);
1831 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1832 if (nic->device_type == XFRAME_II_DEVICE)
1833 writeq(val64, &bar0->mac_cfg);
1834 else {
1835 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1836 writel((u32) (val64), add);
1837 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1838 writel((u32) (val64 >> 32), (add + 4));
1839 }
1840
1841 /*
1842 * Set the time value to be inserted in the pause frame
1843 * generated by xena.
1844 */
1845 val64 = readq(&bar0->rmac_pause_cfg);
1846 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1847 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1848 writeq(val64, &bar0->rmac_pause_cfg);
1849
1850 /*
1851 * Set the Threshold Limit for Generating the pause frame
1852 * If the amount of data in any Queue exceeds ratio of
1853 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1854 * pause frame is generated
1855 */
1856 val64 = 0;
1857 for (i = 0; i < 4; i++) {
1858 val64 |=
1859 (((u64) 0xFF00 | nic->mac_control.
1860 mc_pause_threshold_q0q3)
1861 << (i * 2 * 8));
1862 }
1863 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1864
1865 val64 = 0;
1866 for (i = 0; i < 4; i++) {
1867 val64 |=
1868 (((u64) 0xFF00 | nic->mac_control.
1869 mc_pause_threshold_q4q7)
1870 << (i * 2 * 8));
1871 }
1872 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1873
1874 /*
1875 * TxDMA will stop Read request if the number of read split has
1876 * exceeded the limit pointed by shared_splits
1877 */
1878 val64 = readq(&bar0->pic_control);
1879 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1880 writeq(val64, &bar0->pic_control);
1881
1882 if (nic->config.bus_speed == 266) {
1883 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1884 writeq(0x0, &bar0->read_retry_delay);
1885 writeq(0x0, &bar0->write_retry_delay);
1886 }
1887
1888 /*
1889 * Programming the Herc to split every write transaction
1890 * that does not start on an ADB to reduce disconnects.
1891 */
1892 if (nic->device_type == XFRAME_II_DEVICE) {
1893 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1894 MISC_LINK_STABILITY_PRD(3);
1895 writeq(val64, &bar0->misc_control);
1896 val64 = readq(&bar0->pic_control2);
1897 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1898 writeq(val64, &bar0->pic_control2);
1899 }
1900 if (strstr(nic->product_name, "CX4")) {
1901 val64 = TMAC_AVG_IPG(0x17);
1902 writeq(val64, &bar0->tmac_avg_ipg);
1903 }
1904
1905 return SUCCESS;
1906 }
1907 #define LINK_UP_DOWN_INTERRUPT 1
1908 #define MAC_RMAC_ERR_TIMER 2
1909
1910 static int s2io_link_fault_indication(struct s2io_nic *nic)
1911 {
1912 if (nic->config.intr_type != INTA)
1913 return MAC_RMAC_ERR_TIMER;
1914 if (nic->device_type == XFRAME_II_DEVICE)
1915 return LINK_UP_DOWN_INTERRUPT;
1916 else
1917 return MAC_RMAC_ERR_TIMER;
1918 }
1919
1920 /**
1921 * do_s2io_write_bits - update alarm bits in alarm register
1922 * @value: alarm bits
1923 * @flag: interrupt status
1924 * @addr: address value
1925 * Description: update alarm bits in alarm register
1926 * Return Value:
1927 * NONE.
1928 */
1929 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1930 {
1931 u64 temp64;
1932
1933 temp64 = readq(addr);
1934
1935 if(flag == ENABLE_INTRS)
1936 temp64 &= ~((u64) value);
1937 else
1938 temp64 |= ((u64) value);
1939 writeq(temp64, addr);
1940 }
1941
1942 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1943 {
1944 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1945 register u64 gen_int_mask = 0;
1946
1947 if (mask & TX_DMA_INTR) {
1948
1949 gen_int_mask |= TXDMA_INT_M;
1950
1951 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1952 TXDMA_PCC_INT | TXDMA_TTI_INT |
1953 TXDMA_LSO_INT | TXDMA_TPA_INT |
1954 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1955
1956 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1957 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1958 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1959 &bar0->pfc_err_mask);
1960
1961 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1962 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1963 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1964
1965 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1966 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1967 PCC_N_SERR | PCC_6_COF_OV_ERR |
1968 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1969 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1970 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1971
1972 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1973 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1974
1975 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1976 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1977 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1978 flag, &bar0->lso_err_mask);
1979
1980 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1981 flag, &bar0->tpa_err_mask);
1982
1983 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1984
1985 }
1986
1987 if (mask & TX_MAC_INTR) {
1988 gen_int_mask |= TXMAC_INT_M;
1989 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1990 &bar0->mac_int_mask);
1991 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1992 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1993 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1994 flag, &bar0->mac_tmac_err_mask);
1995 }
1996
1997 if (mask & TX_XGXS_INTR) {
1998 gen_int_mask |= TXXGXS_INT_M;
1999 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
2000 &bar0->xgxs_int_mask);
2001 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
2002 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
2003 flag, &bar0->xgxs_txgxs_err_mask);
2004 }
2005
2006 if (mask & RX_DMA_INTR) {
2007 gen_int_mask |= RXDMA_INT_M;
2008 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
2009 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
2010 flag, &bar0->rxdma_int_mask);
2011 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
2012 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
2013 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
2014 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
2015 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
2016 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
2017 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
2018 &bar0->prc_pcix_err_mask);
2019 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
2020 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2021 &bar0->rpa_err_mask);
2022 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2023 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2024 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2025 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
2026 flag, &bar0->rda_err_mask);
2027 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2028 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2029 flag, &bar0->rti_err_mask);
2030 }
2031
2032 if (mask & RX_MAC_INTR) {
2033 gen_int_mask |= RXMAC_INT_M;
2034 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2035 &bar0->mac_int_mask);
2036 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2037 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2038 RMAC_DOUBLE_ECC_ERR |
2039 RMAC_LINK_STATE_CHANGE_INT,
2040 flag, &bar0->mac_rmac_err_mask);
2041 }
2042
2043 if (mask & RX_XGXS_INTR)
2044 {
2045 gen_int_mask |= RXXGXS_INT_M;
2046 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2047 &bar0->xgxs_int_mask);
2048 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2049 &bar0->xgxs_rxgxs_err_mask);
2050 }
2051
2052 if (mask & MC_INTR) {
2053 gen_int_mask |= MC_INT_M;
2054 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2055 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2056 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2057 &bar0->mc_err_mask);
2058 }
2059 nic->general_int_mask = gen_int_mask;
2060
2061 /* Remove this line when alarm interrupts are enabled */
2062 nic->general_int_mask = 0;
2063 }
2064 /**
2065 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2066 * @nic: device private variable,
2067 * @mask: A mask indicating which Intr block must be modified and,
2068 * @flag: A flag indicating whether to enable or disable the Intrs.
2069 * Description: This function will either disable or enable the interrupts
2070 * depending on the flag argument. The mask argument can be used to
2071 * enable/disable any Intr block.
2072 * Return Value: NONE.
2073 */
2074
2075 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2076 {
2077 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2078 register u64 temp64 = 0, intr_mask = 0;
2079
2080 intr_mask = nic->general_int_mask;
2081
2082 /* Top level interrupt classification */
2083 /* PIC Interrupts */
2084 if (mask & TX_PIC_INTR) {
2085 /* Enable PIC Intrs in the general intr mask register */
2086 intr_mask |= TXPIC_INT_M;
2087 if (flag == ENABLE_INTRS) {
2088 /*
2089 * If Hercules adapter enable GPIO otherwise
2090 * disable all PCIX, Flash, MDIO, IIC and GPIO
2091 * interrupts for now.
2092 * TODO
2093 */
2094 if (s2io_link_fault_indication(nic) ==
2095 LINK_UP_DOWN_INTERRUPT ) {
2096 do_s2io_write_bits(PIC_INT_GPIO, flag,
2097 &bar0->pic_int_mask);
2098 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2099 &bar0->gpio_int_mask);
2100 } else
2101 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2102 } else if (flag == DISABLE_INTRS) {
2103 /*
2104 * Disable PIC Intrs in the general
2105 * intr mask register
2106 */
2107 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2108 }
2109 }
2110
2111 /* Tx traffic interrupts */
2112 if (mask & TX_TRAFFIC_INTR) {
2113 intr_mask |= TXTRAFFIC_INT_M;
2114 if (flag == ENABLE_INTRS) {
2115 /*
2116 * Enable all the Tx side interrupts
2117 * writing 0 Enables all 64 TX interrupt levels
2118 */
2119 writeq(0x0, &bar0->tx_traffic_mask);
2120 } else if (flag == DISABLE_INTRS) {
2121 /*
2122 * Disable Tx Traffic Intrs in the general intr mask
2123 * register.
2124 */
2125 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2126 }
2127 }
2128
2129 /* Rx traffic interrupts */
2130 if (mask & RX_TRAFFIC_INTR) {
2131 intr_mask |= RXTRAFFIC_INT_M;
2132 if (flag == ENABLE_INTRS) {
2133 /* writing 0 Enables all 8 RX interrupt levels */
2134 writeq(0x0, &bar0->rx_traffic_mask);
2135 } else if (flag == DISABLE_INTRS) {
2136 /*
2137 * Disable Rx Traffic Intrs in the general intr mask
2138 * register.
2139 */
2140 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2141 }
2142 }
2143
2144 temp64 = readq(&bar0->general_int_mask);
2145 if (flag == ENABLE_INTRS)
2146 temp64 &= ~((u64) intr_mask);
2147 else
2148 temp64 = DISABLE_ALL_INTRS;
2149 writeq(temp64, &bar0->general_int_mask);
2150
2151 nic->general_int_mask = readq(&bar0->general_int_mask);
2152 }
2153
2154 /**
2155 * verify_pcc_quiescent- Checks for PCC quiescent state
2156 * Return: 1 If PCC is quiescence
2157 * 0 If PCC is not quiescence
2158 */
2159 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2160 {
2161 int ret = 0, herc;
2162 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2163 u64 val64 = readq(&bar0->adapter_status);
2164
2165 herc = (sp->device_type == XFRAME_II_DEVICE);
2166
2167 if (flag == FALSE) {
2168 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2169 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2170 ret = 1;
2171 } else {
2172 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2173 ret = 1;
2174 }
2175 } else {
2176 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2177 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2178 ADAPTER_STATUS_RMAC_PCC_IDLE))
2179 ret = 1;
2180 } else {
2181 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2182 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2183 ret = 1;
2184 }
2185 }
2186
2187 return ret;
2188 }
2189 /**
2190 * verify_xena_quiescence - Checks whether the H/W is ready
2191 * Description: Returns whether the H/W is ready to go or not. Depending
2192 * on whether adapter enable bit was written or not the comparison
2193 * differs and the calling function passes the input argument flag to
2194 * indicate this.
2195 * Return: 1 If xena is quiescence
2196 * 0 If Xena is not quiescence
2197 */
2198
2199 static int verify_xena_quiescence(struct s2io_nic *sp)
2200 {
2201 int mode;
2202 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2203 u64 val64 = readq(&bar0->adapter_status);
2204 mode = s2io_verify_pci_mode(sp);
2205
2206 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2207 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2208 return 0;
2209 }
2210 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2211 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2212 return 0;
2213 }
2214 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2215 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2216 return 0;
2217 }
2218 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2219 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2220 return 0;
2221 }
2222 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2223 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2224 return 0;
2225 }
2226 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2227 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2228 return 0;
2229 }
2230 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2231 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2232 return 0;
2233 }
2234 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2235 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2236 return 0;
2237 }
2238
2239 /*
2240 * In PCI 33 mode, the P_PLL is not used, and therefore,
2241 * the the P_PLL_LOCK bit in the adapter_status register will
2242 * not be asserted.
2243 */
2244 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2245 sp->device_type == XFRAME_II_DEVICE && mode !=
2246 PCI_MODE_PCI_33) {
2247 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2248 return 0;
2249 }
2250 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2251 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2252 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2253 return 0;
2254 }
2255 return 1;
2256 }
2257
2258 /**
2259 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2260 * @sp: Pointer to device specifc structure
2261 * Description :
2262 * New procedure to clear mac address reading problems on Alpha platforms
2263 *
2264 */
2265
2266 static void fix_mac_address(struct s2io_nic * sp)
2267 {
2268 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2269 u64 val64;
2270 int i = 0;
2271
2272 while (fix_mac[i] != END_SIGN) {
2273 writeq(fix_mac[i++], &bar0->gpio_control);
2274 udelay(10);
2275 val64 = readq(&bar0->gpio_control);
2276 }
2277 }
2278
2279 /**
2280 * start_nic - Turns the device on
2281 * @nic : device private variable.
2282 * Description:
2283 * This function actually turns the device on. Before this function is
2284 * called,all Registers are configured from their reset states
2285 * and shared memory is allocated but the NIC is still quiescent. On
2286 * calling this function, the device interrupts are cleared and the NIC is
2287 * literally switched on by writing into the adapter control register.
2288 * Return Value:
2289 * SUCCESS on success and -1 on failure.
2290 */
2291
2292 static int start_nic(struct s2io_nic *nic)
2293 {
2294 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2295 struct net_device *dev = nic->dev;
2296 register u64 val64 = 0;
2297 u16 subid, i;
2298 struct mac_info *mac_control;
2299 struct config_param *config;
2300
2301 mac_control = &nic->mac_control;
2302 config = &nic->config;
2303
2304 /* PRC Initialization and configuration */
2305 for (i = 0; i < config->rx_ring_num; i++) {
2306 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2307 &bar0->prc_rxd0_n[i]);
2308
2309 val64 = readq(&bar0->prc_ctrl_n[i]);
2310 if (nic->rxd_mode == RXD_MODE_1)
2311 val64 |= PRC_CTRL_RC_ENABLED;
2312 else
2313 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2314 if (nic->device_type == XFRAME_II_DEVICE)
2315 val64 |= PRC_CTRL_GROUP_READS;
2316 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2317 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2318 writeq(val64, &bar0->prc_ctrl_n[i]);
2319 }
2320
2321 if (nic->rxd_mode == RXD_MODE_3B) {
2322 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2323 val64 = readq(&bar0->rx_pa_cfg);
2324 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2325 writeq(val64, &bar0->rx_pa_cfg);
2326 }
2327
2328 if (vlan_tag_strip == 0) {
2329 val64 = readq(&bar0->rx_pa_cfg);
2330 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2331 writeq(val64, &bar0->rx_pa_cfg);
2332 vlan_strip_flag = 0;
2333 }
2334
2335 /*
2336 * Enabling MC-RLDRAM. After enabling the device, we timeout
2337 * for around 100ms, which is approximately the time required
2338 * for the device to be ready for operation.
2339 */
2340 val64 = readq(&bar0->mc_rldram_mrs);
2341 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2342 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2343 val64 = readq(&bar0->mc_rldram_mrs);
2344
2345 msleep(100); /* Delay by around 100 ms. */
2346
2347 /* Enabling ECC Protection. */
2348 val64 = readq(&bar0->adapter_control);
2349 val64 &= ~ADAPTER_ECC_EN;
2350 writeq(val64, &bar0->adapter_control);
2351
2352 /*
2353 * Verify if the device is ready to be enabled, if so enable
2354 * it.
2355 */
2356 val64 = readq(&bar0->adapter_status);
2357 if (!verify_xena_quiescence(nic)) {
2358 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2359 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2360 (unsigned long long) val64);
2361 return FAILURE;
2362 }
2363
2364 /*
2365 * With some switches, link might be already up at this point.
2366 * Because of this weird behavior, when we enable laser,
2367 * we may not get link. We need to handle this. We cannot
2368 * figure out which switch is misbehaving. So we are forced to
2369 * make a global change.
2370 */
2371
2372 /* Enabling Laser. */
2373 val64 = readq(&bar0->adapter_control);
2374 val64 |= ADAPTER_EOI_TX_ON;
2375 writeq(val64, &bar0->adapter_control);
2376
2377 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2378 /*
2379 * Dont see link state interrupts initally on some switches,
2380 * so directly scheduling the link state task here.
2381 */
2382 schedule_work(&nic->set_link_task);
2383 }
2384 /* SXE-002: Initialize link and activity LED */
2385 subid = nic->pdev->subsystem_device;
2386 if (((subid & 0xFF) >= 0x07) &&
2387 (nic->device_type == XFRAME_I_DEVICE)) {
2388 val64 = readq(&bar0->gpio_control);
2389 val64 |= 0x0000800000000000ULL;
2390 writeq(val64, &bar0->gpio_control);
2391 val64 = 0x0411040400000000ULL;
2392 writeq(val64, (void __iomem *)bar0 + 0x2700);
2393 }
2394
2395 return SUCCESS;
2396 }
2397 /**
2398 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2399 */
2400 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2401 TxD *txdlp, int get_off)
2402 {
2403 struct s2io_nic *nic = fifo_data->nic;
2404 struct sk_buff *skb;
2405 struct TxD *txds;
2406 u16 j, frg_cnt;
2407
2408 txds = txdlp;
2409 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2410 pci_unmap_single(nic->pdev, (dma_addr_t)
2411 txds->Buffer_Pointer, sizeof(u64),
2412 PCI_DMA_TODEVICE);
2413 txds++;
2414 }
2415
2416 skb = (struct sk_buff *) ((unsigned long)
2417 txds->Host_Control);
2418 if (!skb) {
2419 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2420 return NULL;
2421 }
2422 pci_unmap_single(nic->pdev, (dma_addr_t)
2423 txds->Buffer_Pointer,
2424 skb->len - skb->data_len,
2425 PCI_DMA_TODEVICE);
2426 frg_cnt = skb_shinfo(skb)->nr_frags;
2427 if (frg_cnt) {
2428 txds++;
2429 for (j = 0; j < frg_cnt; j++, txds++) {
2430 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2431 if (!txds->Buffer_Pointer)
2432 break;
2433 pci_unmap_page(nic->pdev, (dma_addr_t)
2434 txds->Buffer_Pointer,
2435 frag->size, PCI_DMA_TODEVICE);
2436 }
2437 }
2438 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2439 return(skb);
2440 }
2441
2442 /**
2443 * free_tx_buffers - Free all queued Tx buffers
2444 * @nic : device private variable.
2445 * Description:
2446 * Free all queued Tx buffers.
2447 * Return Value: void
2448 */
2449
2450 static void free_tx_buffers(struct s2io_nic *nic)
2451 {
2452 struct net_device *dev = nic->dev;
2453 struct sk_buff *skb;
2454 struct TxD *txdp;
2455 int i, j;
2456 struct mac_info *mac_control;
2457 struct config_param *config;
2458 int cnt = 0;
2459
2460 mac_control = &nic->mac_control;
2461 config = &nic->config;
2462
2463 for (i = 0; i < config->tx_fifo_num; i++) {
2464 unsigned long flags;
2465 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
2466 for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
2467 txdp = (struct TxD *) \
2468 mac_control->fifos[i].list_info[j].list_virt_addr;
2469 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2470 if (skb) {
2471 nic->mac_control.stats_info->sw_stat.mem_freed
2472 += skb->truesize;
2473 dev_kfree_skb(skb);
2474 cnt++;
2475 }
2476 }
2477 DBG_PRINT(INTR_DBG,
2478 "%s:forcibly freeing %d skbs on FIFO%d\n",
2479 dev->name, cnt, i);
2480 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2481 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2482 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
2483 }
2484 }
2485
2486 /**
2487 * stop_nic - To stop the nic
2488 * @nic ; device private variable.
2489 * Description:
2490 * This function does exactly the opposite of what the start_nic()
2491 * function does. This function is called to stop the device.
2492 * Return Value:
2493 * void.
2494 */
2495
2496 static void stop_nic(struct s2io_nic *nic)
2497 {
2498 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2499 register u64 val64 = 0;
2500 u16 interruptible;
2501 struct mac_info *mac_control;
2502 struct config_param *config;
2503
2504 mac_control = &nic->mac_control;
2505 config = &nic->config;
2506
2507 /* Disable all interrupts */
2508 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2509 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2510 interruptible |= TX_PIC_INTR;
2511 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2512
2513 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2514 val64 = readq(&bar0->adapter_control);
2515 val64 &= ~(ADAPTER_CNTL_EN);
2516 writeq(val64, &bar0->adapter_control);
2517 }
2518
2519 /**
2520 * fill_rx_buffers - Allocates the Rx side skbs
2521 * @ring_info: per ring structure
2522 * Description:
2523 * The function allocates Rx side skbs and puts the physical
2524 * address of these buffers into the RxD buffer pointers, so that the NIC
2525 * can DMA the received frame into these locations.
2526 * The NIC supports 3 receive modes, viz
2527 * 1. single buffer,
2528 * 2. three buffer and
2529 * 3. Five buffer modes.
2530 * Each mode defines how many fragments the received frame will be split
2531 * up into by the NIC. The frame is split into L3 header, L4 Header,
2532 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2533 * is split into 3 fragments. As of now only single buffer mode is
2534 * supported.
2535 * Return Value:
2536 * SUCCESS on success or an appropriate -ve value on failure.
2537 */
2538
2539 static int fill_rx_buffers(struct ring_info *ring)
2540 {
2541 struct sk_buff *skb;
2542 struct RxD_t *rxdp;
2543 int off, size, block_no, block_no1;
2544 u32 alloc_tab = 0;
2545 u32 alloc_cnt;
2546 u64 tmp;
2547 struct buffAdd *ba;
2548 struct RxD_t *first_rxdp = NULL;
2549 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2550 int rxd_index = 0;
2551 struct RxD1 *rxdp1;
2552 struct RxD3 *rxdp3;
2553 struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
2554
2555 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2556
2557 block_no1 = ring->rx_curr_get_info.block_index;
2558 while (alloc_tab < alloc_cnt) {
2559 block_no = ring->rx_curr_put_info.block_index;
2560
2561 off = ring->rx_curr_put_info.offset;
2562
2563 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2564
2565 rxd_index = off + 1;
2566 if (block_no)
2567 rxd_index += (block_no * ring->rxd_count);
2568
2569 if ((block_no == block_no1) &&
2570 (off == ring->rx_curr_get_info.offset) &&
2571 (rxdp->Host_Control)) {
2572 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2573 ring->dev->name);
2574 DBG_PRINT(INTR_DBG, " info equated\n");
2575 goto end;
2576 }
2577 if (off && (off == ring->rxd_count)) {
2578 ring->rx_curr_put_info.block_index++;
2579 if (ring->rx_curr_put_info.block_index ==
2580 ring->block_count)
2581 ring->rx_curr_put_info.block_index = 0;
2582 block_no = ring->rx_curr_put_info.block_index;
2583 off = 0;
2584 ring->rx_curr_put_info.offset = off;
2585 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2586 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2587 ring->dev->name, rxdp);
2588
2589 }
2590
2591 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2592 ((ring->rxd_mode == RXD_MODE_3B) &&
2593 (rxdp->Control_2 & s2BIT(0)))) {
2594 ring->rx_curr_put_info.offset = off;
2595 goto end;
2596 }
2597 /* calculate size of skb based on ring mode */
2598 size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2599 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2600 if (ring->rxd_mode == RXD_MODE_1)
2601 size += NET_IP_ALIGN;
2602 else
2603 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2604
2605 /* allocate skb */
2606 skb = dev_alloc_skb(size);
2607 if(!skb) {
2608 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
2609 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2610 if (first_rxdp) {
2611 wmb();
2612 first_rxdp->Control_1 |= RXD_OWN_XENA;
2613 }
2614 stats->mem_alloc_fail_cnt++;
2615
2616 return -ENOMEM ;
2617 }
2618 stats->mem_allocated += skb->truesize;
2619
2620 if (ring->rxd_mode == RXD_MODE_1) {
2621 /* 1 buffer mode - normal operation mode */
2622 rxdp1 = (struct RxD1*)rxdp;
2623 memset(rxdp, 0, sizeof(struct RxD1));
2624 skb_reserve(skb, NET_IP_ALIGN);
2625 rxdp1->Buffer0_ptr = pci_map_single
2626 (ring->pdev, skb->data, size - NET_IP_ALIGN,
2627 PCI_DMA_FROMDEVICE);
2628 if(pci_dma_mapping_error(rxdp1->Buffer0_ptr))
2629 goto pci_map_failed;
2630
2631 rxdp->Control_2 =
2632 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2633 rxdp->Host_Control = (unsigned long) (skb);
2634 } else if (ring->rxd_mode == RXD_MODE_3B) {
2635 /*
2636 * 2 buffer mode -
2637 * 2 buffer mode provides 128
2638 * byte aligned receive buffers.
2639 */
2640
2641 rxdp3 = (struct RxD3*)rxdp;
2642 /* save buffer pointers to avoid frequent dma mapping */
2643 Buffer0_ptr = rxdp3->Buffer0_ptr;
2644 Buffer1_ptr = rxdp3->Buffer1_ptr;
2645 memset(rxdp, 0, sizeof(struct RxD3));
2646 /* restore the buffer pointers for dma sync*/
2647 rxdp3->Buffer0_ptr = Buffer0_ptr;
2648 rxdp3->Buffer1_ptr = Buffer1_ptr;
2649
2650 ba = &ring->ba[block_no][off];
2651 skb_reserve(skb, BUF0_LEN);
2652 tmp = (u64)(unsigned long) skb->data;
2653 tmp += ALIGN_SIZE;
2654 tmp &= ~ALIGN_SIZE;
2655 skb->data = (void *) (unsigned long)tmp;
2656 skb_reset_tail_pointer(skb);
2657
2658 /* AK: check is wrong. 0 can be valid dma address */
2659 if (!(rxdp3->Buffer0_ptr))
2660 rxdp3->Buffer0_ptr =
2661 pci_map_single(ring->pdev, ba->ba_0,
2662 BUF0_LEN, PCI_DMA_FROMDEVICE);
2663 else
2664 pci_dma_sync_single_for_device(ring->pdev,
2665 (dma_addr_t) rxdp3->Buffer0_ptr,
2666 BUF0_LEN, PCI_DMA_FROMDEVICE);
2667 if (pci_dma_mapping_error(rxdp3->Buffer0_ptr))
2668 goto pci_map_failed;
2669
2670 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2671 if (ring->rxd_mode == RXD_MODE_3B) {
2672 /* Two buffer mode */
2673
2674 /*
2675 * Buffer2 will have L3/L4 header plus
2676 * L4 payload
2677 */
2678 rxdp3->Buffer2_ptr = pci_map_single
2679 (ring->pdev, skb->data, ring->mtu + 4,
2680 PCI_DMA_FROMDEVICE);
2681
2682 if (pci_dma_mapping_error(rxdp3->Buffer2_ptr))
2683 goto pci_map_failed;
2684
2685 /* AK: check is wrong */
2686 if (!rxdp3->Buffer1_ptr)
2687 rxdp3->Buffer1_ptr =
2688 pci_map_single(ring->pdev,
2689 ba->ba_1, BUF1_LEN,
2690 PCI_DMA_FROMDEVICE);
2691
2692 if (pci_dma_mapping_error(rxdp3->Buffer1_ptr)) {
2693 pci_unmap_single
2694 (ring->pdev,
2695 (dma_addr_t)(unsigned long)
2696 skb->data,
2697 ring->mtu + 4,
2698 PCI_DMA_FROMDEVICE);
2699 goto pci_map_failed;
2700 }
2701 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2702 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2703 (ring->mtu + 4);
2704 }
2705 rxdp->Control_2 |= s2BIT(0);
2706 rxdp->Host_Control = (unsigned long) (skb);
2707 }
2708 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2709 rxdp->Control_1 |= RXD_OWN_XENA;
2710 off++;
2711 if (off == (ring->rxd_count + 1))
2712 off = 0;
2713 ring->rx_curr_put_info.offset = off;
2714
2715 rxdp->Control_2 |= SET_RXD_MARKER;
2716 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2717 if (first_rxdp) {
2718 wmb();
2719 first_rxdp->Control_1 |= RXD_OWN_XENA;
2720 }
2721 first_rxdp = rxdp;
2722 }
2723 ring->rx_bufs_left += 1;
2724 alloc_tab++;
2725 }
2726
2727 end:
2728 /* Transfer ownership of first descriptor to adapter just before
2729 * exiting. Before that, use memory barrier so that ownership
2730 * and other fields are seen by adapter correctly.
2731 */
2732 if (first_rxdp) {
2733 wmb();
2734 first_rxdp->Control_1 |= RXD_OWN_XENA;
2735 }
2736
2737 return SUCCESS;
2738 pci_map_failed:
2739 stats->pci_map_fail_cnt++;
2740 stats->mem_freed += skb->truesize;
2741 dev_kfree_skb_irq(skb);
2742 return -ENOMEM;
2743 }
2744
2745 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2746 {
2747 struct net_device *dev = sp->dev;
2748 int j;
2749 struct sk_buff *skb;
2750 struct RxD_t *rxdp;
2751 struct mac_info *mac_control;
2752 struct buffAdd *ba;
2753 struct RxD1 *rxdp1;
2754 struct RxD3 *rxdp3;
2755
2756 mac_control = &sp->mac_control;
2757 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2758 rxdp = mac_control->rings[ring_no].
2759 rx_blocks[blk].rxds[j].virt_addr;
2760 skb = (struct sk_buff *)
2761 ((unsigned long) rxdp->Host_Control);
2762 if (!skb) {
2763 continue;
2764 }
2765 if (sp->rxd_mode == RXD_MODE_1) {
2766 rxdp1 = (struct RxD1*)rxdp;
2767 pci_unmap_single(sp->pdev, (dma_addr_t)
2768 rxdp1->Buffer0_ptr,
2769 dev->mtu +
2770 HEADER_ETHERNET_II_802_3_SIZE
2771 + HEADER_802_2_SIZE +
2772 HEADER_SNAP_SIZE,
2773 PCI_DMA_FROMDEVICE);
2774 memset(rxdp, 0, sizeof(struct RxD1));
2775 } else if(sp->rxd_mode == RXD_MODE_3B) {
2776 rxdp3 = (struct RxD3*)rxdp;
2777 ba = &mac_control->rings[ring_no].
2778 ba[blk][j];
2779 pci_unmap_single(sp->pdev, (dma_addr_t)
2780 rxdp3->Buffer0_ptr,
2781 BUF0_LEN,
2782 PCI_DMA_FROMDEVICE);
2783 pci_unmap_single(sp->pdev, (dma_addr_t)
2784 rxdp3->Buffer1_ptr,
2785 BUF1_LEN,
2786 PCI_DMA_FROMDEVICE);
2787 pci_unmap_single(sp->pdev, (dma_addr_t)
2788 rxdp3->Buffer2_ptr,
2789 dev->mtu + 4,
2790 PCI_DMA_FROMDEVICE);
2791 memset(rxdp, 0, sizeof(struct RxD3));
2792 }
2793 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2794 dev_kfree_skb(skb);
2795 mac_control->rings[ring_no].rx_bufs_left -= 1;
2796 }
2797 }
2798
2799 /**
2800 * free_rx_buffers - Frees all Rx buffers
2801 * @sp: device private variable.
2802 * Description:
2803 * This function will free all Rx buffers allocated by host.
2804 * Return Value:
2805 * NONE.
2806 */
2807
2808 static void free_rx_buffers(struct s2io_nic *sp)
2809 {
2810 struct net_device *dev = sp->dev;
2811 int i, blk = 0, buf_cnt = 0;
2812 struct mac_info *mac_control;
2813 struct config_param *config;
2814
2815 mac_control = &sp->mac_control;
2816 config = &sp->config;
2817
2818 for (i = 0; i < config->rx_ring_num; i++) {
2819 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2820 free_rxd_blk(sp,i,blk);
2821
2822 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2823 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2824 mac_control->rings[i].rx_curr_put_info.offset = 0;
2825 mac_control->rings[i].rx_curr_get_info.offset = 0;
2826 mac_control->rings[i].rx_bufs_left = 0;
2827 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2828 dev->name, buf_cnt, i);
2829 }
2830 }
2831
2832 static int s2io_chk_rx_buffers(struct ring_info *ring)
2833 {
2834 if (fill_rx_buffers(ring) == -ENOMEM) {
2835 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2836 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2837 }
2838 return 0;
2839 }
2840
2841 /**
2842 * s2io_poll - Rx interrupt handler for NAPI support
2843 * @napi : pointer to the napi structure.
2844 * @budget : The number of packets that were budgeted to be processed
2845 * during one pass through the 'Poll" function.
2846 * Description:
2847 * Comes into picture only if NAPI support has been incorporated. It does
2848 * the same thing that rx_intr_handler does, but not in a interrupt context
2849 * also It will process only a given number of packets.
2850 * Return value:
2851 * 0 on success and 1 if there are No Rx packets to be processed.
2852 */
2853
2854 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2855 {
2856 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2857 struct net_device *dev = ring->dev;
2858 struct config_param *config;
2859 struct mac_info *mac_control;
2860 int pkts_processed = 0;
2861 u8 __iomem *addr = NULL;
2862 u8 val8 = 0;
2863 struct s2io_nic *nic = dev->priv;
2864 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2865 int budget_org = budget;
2866
2867 config = &nic->config;
2868 mac_control = &nic->mac_control;
2869
2870 if (unlikely(!is_s2io_card_up(nic)))
2871 return 0;
2872
2873 pkts_processed = rx_intr_handler(ring, budget);
2874 s2io_chk_rx_buffers(ring);
2875
2876 if (pkts_processed < budget_org) {
2877 netif_rx_complete(dev, napi);
2878 /*Re Enable MSI-Rx Vector*/
2879 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2880 addr += 7 - ring->ring_no;
2881 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2882 writeb(val8, addr);
2883 val8 = readb(addr);
2884 }
2885 return pkts_processed;
2886 }
2887 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2888 {
2889 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2890 struct ring_info *ring;
2891 struct net_device *dev = nic->dev;
2892 struct config_param *config;
2893 struct mac_info *mac_control;
2894 int pkts_processed = 0;
2895 int ring_pkts_processed, i;
2896 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2897 int budget_org = budget;
2898
2899 config = &nic->config;
2900 mac_control = &nic->mac_control;
2901
2902 if (unlikely(!is_s2io_card_up(nic)))
2903 return 0;
2904
2905 for (i = 0; i < config->rx_ring_num; i++) {
2906 ring = &mac_control->rings[i];
2907 ring_pkts_processed = rx_intr_handler(ring, budget);
2908 s2io_chk_rx_buffers(ring);
2909 pkts_processed += ring_pkts_processed;
2910 budget -= ring_pkts_processed;
2911 if (budget <= 0)
2912 break;
2913 }
2914 if (pkts_processed < budget_org) {
2915 netif_rx_complete(dev, napi);
2916 /* Re enable the Rx interrupts for the ring */
2917 writeq(0, &bar0->rx_traffic_mask);
2918 readl(&bar0->rx_traffic_mask);
2919 }
2920 return pkts_processed;
2921 }
2922
2923 #ifdef CONFIG_NET_POLL_CONTROLLER
2924 /**
2925 * s2io_netpoll - netpoll event handler entry point
2926 * @dev : pointer to the device structure.
2927 * Description:
2928 * This function will be called by upper layer to check for events on the
2929 * interface in situations where interrupts are disabled. It is used for
2930 * specific in-kernel networking tasks, such as remote consoles and kernel
2931 * debugging over the network (example netdump in RedHat).
2932 */
2933 static void s2io_netpoll(struct net_device *dev)
2934 {
2935 struct s2io_nic *nic = dev->priv;
2936 struct mac_info *mac_control;
2937 struct config_param *config;
2938 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2939 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2940 int i;
2941
2942 if (pci_channel_offline(nic->pdev))
2943 return;
2944
2945 disable_irq(dev->irq);
2946
2947 mac_control = &nic->mac_control;
2948 config = &nic->config;
2949
2950 writeq(val64, &bar0->rx_traffic_int);
2951 writeq(val64, &bar0->tx_traffic_int);
2952
2953 /* we need to free up the transmitted skbufs or else netpoll will
2954 * run out of skbs and will fail and eventually netpoll application such
2955 * as netdump will fail.
2956 */
2957 for (i = 0; i < config->tx_fifo_num; i++)
2958 tx_intr_handler(&mac_control->fifos[i]);
2959
2960 /* check for received packet and indicate up to network */
2961 for (i = 0; i < config->rx_ring_num; i++)
2962 rx_intr_handler(&mac_control->rings[i], 0);
2963
2964 for (i = 0; i < config->rx_ring_num; i++) {
2965 if (fill_rx_buffers(&mac_control->rings[i]) == -ENOMEM) {
2966 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2967 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2968 break;
2969 }
2970 }
2971 enable_irq(dev->irq);
2972 return;
2973 }
2974 #endif
2975
2976 /**
2977 * rx_intr_handler - Rx interrupt handler
2978 * @ring_info: per ring structure.
2979 * @budget: budget for napi processing.
2980 * Description:
2981 * If the interrupt is because of a received frame or if the
2982 * receive ring contains fresh as yet un-processed frames,this function is
2983 * called. It picks out the RxD at which place the last Rx processing had
2984 * stopped and sends the skb to the OSM's Rx handler and then increments
2985 * the offset.
2986 * Return Value:
2987 * No. of napi packets processed.
2988 */
2989 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2990 {
2991 int get_block, put_block;
2992 struct rx_curr_get_info get_info, put_info;
2993 struct RxD_t *rxdp;
2994 struct sk_buff *skb;
2995 int pkt_cnt = 0, napi_pkts = 0;
2996 int i;
2997 struct RxD1* rxdp1;
2998 struct RxD3* rxdp3;
2999
3000 get_info = ring_data->rx_curr_get_info;
3001 get_block = get_info.block_index;
3002 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
3003 put_block = put_info.block_index;
3004 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
3005
3006 while (RXD_IS_UP2DT(rxdp)) {
3007 /*
3008 * If your are next to put index then it's
3009 * FIFO full condition
3010 */
3011 if ((get_block == put_block) &&
3012 (get_info.offset + 1) == put_info.offset) {
3013 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
3014 ring_data->dev->name);
3015 break;
3016 }
3017 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
3018 if (skb == NULL) {
3019 DBG_PRINT(ERR_DBG, "%s: The skb is ",
3020 ring_data->dev->name);
3021 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
3022 return 0;
3023 }
3024 if (ring_data->rxd_mode == RXD_MODE_1) {
3025 rxdp1 = (struct RxD1*)rxdp;
3026 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3027 rxdp1->Buffer0_ptr,
3028 ring_data->mtu +
3029 HEADER_ETHERNET_II_802_3_SIZE +
3030 HEADER_802_2_SIZE +
3031 HEADER_SNAP_SIZE,
3032 PCI_DMA_FROMDEVICE);
3033 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3034 rxdp3 = (struct RxD3*)rxdp;
3035 pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t)
3036 rxdp3->Buffer0_ptr,
3037 BUF0_LEN, PCI_DMA_FROMDEVICE);
3038 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3039 rxdp3->Buffer2_ptr,
3040 ring_data->mtu + 4,
3041 PCI_DMA_FROMDEVICE);
3042 }
3043 prefetch(skb->data);
3044 rx_osm_handler(ring_data, rxdp);
3045 get_info.offset++;
3046 ring_data->rx_curr_get_info.offset = get_info.offset;
3047 rxdp = ring_data->rx_blocks[get_block].
3048 rxds[get_info.offset].virt_addr;
3049 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3050 get_info.offset = 0;
3051 ring_data->rx_curr_get_info.offset = get_info.offset;
3052 get_block++;
3053 if (get_block == ring_data->block_count)
3054 get_block = 0;
3055 ring_data->rx_curr_get_info.block_index = get_block;
3056 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3057 }
3058
3059 if (ring_data->nic->config.napi) {
3060 budget--;
3061 napi_pkts++;
3062 if (!budget)
3063 break;
3064 }
3065 pkt_cnt++;
3066 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3067 break;
3068 }
3069 if (ring_data->lro) {
3070 /* Clear all LRO sessions before exiting */
3071 for (i=0; i<MAX_LRO_SESSIONS; i++) {
3072 struct lro *lro = &ring_data->lro0_n[i];
3073 if (lro->in_use) {
3074 update_L3L4_header(ring_data->nic, lro);
3075 queue_rx_frame(lro->parent, lro->vlan_tag);
3076 clear_lro_session(lro);
3077 }
3078 }
3079 }
3080 return(napi_pkts);
3081 }
3082
3083 /**
3084 * tx_intr_handler - Transmit interrupt handler
3085 * @nic : device private variable
3086 * Description:
3087 * If an interrupt was raised to indicate DMA complete of the
3088 * Tx packet, this function is called. It identifies the last TxD
3089 * whose buffer was freed and frees all skbs whose data have already
3090 * DMA'ed into the NICs internal memory.
3091 * Return Value:
3092 * NONE
3093 */
3094
3095 static void tx_intr_handler(struct fifo_info *fifo_data)
3096 {
3097 struct s2io_nic *nic = fifo_data->nic;
3098 struct tx_curr_get_info get_info, put_info;
3099 struct sk_buff *skb = NULL;
3100 struct TxD *txdlp;
3101 int pkt_cnt = 0;
3102 unsigned long flags = 0;
3103 u8 err_mask;
3104
3105 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3106 return;
3107
3108 get_info = fifo_data->tx_curr_get_info;
3109 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3110 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
3111 list_virt_addr;
3112 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3113 (get_info.offset != put_info.offset) &&
3114 (txdlp->Host_Control)) {
3115 /* Check for TxD errors */
3116 if (txdlp->Control_1 & TXD_T_CODE) {
3117 unsigned long long err;
3118 err = txdlp->Control_1 & TXD_T_CODE;
3119 if (err & 0x1) {
3120 nic->mac_control.stats_info->sw_stat.
3121 parity_err_cnt++;
3122 }
3123
3124 /* update t_code statistics */
3125 err_mask = err >> 48;
3126 switch(err_mask) {
3127 case 2:
3128 nic->mac_control.stats_info->sw_stat.
3129 tx_buf_abort_cnt++;
3130 break;
3131
3132 case 3:
3133 nic->mac_control.stats_info->sw_stat.
3134 tx_desc_abort_cnt++;
3135 break;
3136
3137 case 7:
3138 nic->mac_control.stats_info->sw_stat.
3139 tx_parity_err_cnt++;
3140 break;
3141
3142 case 10:
3143 nic->mac_control.stats_info->sw_stat.
3144 tx_link_loss_cnt++;
3145 break;
3146
3147 case 15:
3148 nic->mac_control.stats_info->sw_stat.
3149 tx_list_proc_err_cnt++;
3150 break;
3151 }
3152 }
3153
3154 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3155 if (skb == NULL) {
3156 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3157 DBG_PRINT(ERR_DBG, "%s: Null skb ",
3158 __FUNCTION__);
3159 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3160 return;
3161 }
3162 pkt_cnt++;
3163
3164 /* Updating the statistics block */
3165 nic->stats.tx_bytes += skb->len;
3166 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
3167 dev_kfree_skb_irq(skb);
3168
3169 get_info.offset++;
3170 if (get_info.offset == get_info.fifo_len + 1)
3171 get_info.offset = 0;
3172 txdlp = (struct TxD *) fifo_data->list_info
3173 [get_info.offset].list_virt_addr;
3174 fifo_data->tx_curr_get_info.offset =
3175 get_info.offset;
3176 }
3177
3178 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3179
3180 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3181 }
3182
3183 /**
3184 * s2io_mdio_write - Function to write in to MDIO registers
3185 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3186 * @addr : address value
3187 * @value : data value
3188 * @dev : pointer to net_device structure
3189 * Description:
3190 * This function is used to write values to the MDIO registers
3191 * NONE
3192 */
3193 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3194 {
3195 u64 val64 = 0x0;
3196 struct s2io_nic *sp = dev->priv;
3197 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3198
3199 //address transaction
3200 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3201 | MDIO_MMD_DEV_ADDR(mmd_type)
3202 | MDIO_MMS_PRT_ADDR(0x0);
3203 writeq(val64, &bar0->mdio_control);
3204 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3205 writeq(val64, &bar0->mdio_control);
3206 udelay(100);
3207
3208 //Data transaction
3209 val64 = 0x0;
3210 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3211 | MDIO_MMD_DEV_ADDR(mmd_type)
3212 | MDIO_MMS_PRT_ADDR(0x0)
3213 | MDIO_MDIO_DATA(value)
3214 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3215 writeq(val64, &bar0->mdio_control);
3216 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3217 writeq(val64, &bar0->mdio_control);
3218 udelay(100);
3219
3220 val64 = 0x0;
3221 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3222 | MDIO_MMD_DEV_ADDR(mmd_type)
3223 | MDIO_MMS_PRT_ADDR(0x0)
3224 | MDIO_OP(MDIO_OP_READ_TRANS);
3225 writeq(val64, &bar0->mdio_control);
3226 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3227 writeq(val64, &bar0->mdio_control);
3228 udelay(100);
3229
3230 }
3231
3232 /**
3233 * s2io_mdio_read - Function to write in to MDIO registers
3234 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3235 * @addr : address value
3236 * @dev : pointer to net_device structure
3237 * Description:
3238 * This function is used to read values to the MDIO registers
3239 * NONE
3240 */
3241 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3242 {
3243 u64 val64 = 0x0;
3244 u64 rval64 = 0x0;
3245 struct s2io_nic *sp = dev->priv;
3246 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3247
3248 /* address transaction */
3249 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3250 | MDIO_MMD_DEV_ADDR(mmd_type)
3251 | MDIO_MMS_PRT_ADDR(0x0);
3252 writeq(val64, &bar0->mdio_control);
3253 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3254 writeq(val64, &bar0->mdio_control);
3255 udelay(100);
3256
3257 /* Data transaction */
3258 val64 = 0x0;
3259 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3260 | MDIO_MMD_DEV_ADDR(mmd_type)
3261 | MDIO_MMS_PRT_ADDR(0x0)
3262 | MDIO_OP(MDIO_OP_READ_TRANS);
3263 writeq(val64, &bar0->mdio_control);
3264 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3265 writeq(val64, &bar0->mdio_control);
3266 udelay(100);
3267
3268 /* Read the value from regs */
3269 rval64 = readq(&bar0->mdio_control);
3270 rval64 = rval64 & 0xFFFF0000;
3271 rval64 = rval64 >> 16;
3272 return rval64;
3273 }
3274 /**
3275 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3276 * @counter : couter value to be updated
3277 * @flag : flag to indicate the status
3278 * @type : counter type
3279 * Description:
3280 * This function is to check the status of the xpak counters value
3281 * NONE
3282 */
3283
3284 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3285 {
3286 u64 mask = 0x3;
3287 u64 val64;
3288 int i;
3289 for(i = 0; i <index; i++)
3290 mask = mask << 0x2;
3291
3292 if(flag > 0)
3293 {
3294 *counter = *counter + 1;
3295 val64 = *regs_stat & mask;
3296 val64 = val64 >> (index * 0x2);
3297 val64 = val64 + 1;
3298 if(val64 == 3)
3299 {
3300 switch(type)
3301 {
3302 case 1:
3303 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3304 "service. Excessive temperatures may "
3305 "result in premature transceiver "
3306 "failure \n");
3307 break;
3308 case 2:
3309 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3310 "service Excessive bias currents may "
3311 "indicate imminent laser diode "
3312 "failure \n");
3313 break;
3314 case 3:
3315 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3316 "service Excessive laser output "
3317 "power may saturate far-end "
3318 "receiver\n");
3319 break;
3320 default:
3321 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3322 "type \n");
3323 }
3324 val64 = 0x0;
3325 }
3326 val64 = val64 << (index * 0x2);
3327 *regs_stat = (*regs_stat & (~mask)) | (val64);
3328
3329 } else {
3330 *regs_stat = *regs_stat & (~mask);
3331 }
3332 }
3333
3334 /**
3335 * s2io_updt_xpak_counter - Function to update the xpak counters
3336 * @dev : pointer to net_device struct
3337 * Description:
3338 * This function is to upate the status of the xpak counters value
3339 * NONE
3340 */
3341 static void s2io_updt_xpak_counter(struct net_device *dev)
3342 {
3343 u16 flag = 0x0;
3344 u16 type = 0x0;
3345 u16 val16 = 0x0;
3346 u64 val64 = 0x0;
3347 u64 addr = 0x0;
3348
3349 struct s2io_nic *sp = dev->priv;
3350 struct stat_block *stat_info = sp->mac_control.stats_info;
3351
3352 /* Check the communication with the MDIO slave */
3353 addr = 0x0000;
3354 val64 = 0x0;
3355 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3356 if((val64 == 0xFFFF) || (val64 == 0x0000))
3357 {
3358 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3359 "Returned %llx\n", (unsigned long long)val64);
3360 return;
3361 }
3362
3363 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3364 if(val64 != 0x2040)
3365 {
3366 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3367 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3368 (unsigned long long)val64);
3369 return;
3370 }
3371
3372 /* Loading the DOM register to MDIO register */
3373 addr = 0xA100;
3374 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3375 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3376
3377 /* Reading the Alarm flags */
3378 addr = 0xA070;
3379 val64 = 0x0;
3380 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3381
3382 flag = CHECKBIT(val64, 0x7);
3383 type = 1;
3384 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3385 &stat_info->xpak_stat.xpak_regs_stat,
3386 0x0, flag, type);
3387
3388 if(CHECKBIT(val64, 0x6))
3389 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3390
3391 flag = CHECKBIT(val64, 0x3);
3392 type = 2;
3393 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3394 &stat_info->xpak_stat.xpak_regs_stat,
3395 0x2, flag, type);
3396
3397 if(CHECKBIT(val64, 0x2))
3398 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3399
3400 flag = CHECKBIT(val64, 0x1);
3401 type = 3;
3402 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3403 &stat_info->xpak_stat.xpak_regs_stat,
3404 0x4, flag, type);
3405
3406 if(CHECKBIT(val64, 0x0))
3407 stat_info->xpak_stat.alarm_laser_output_power_low++;
3408
3409 /* Reading the Warning flags */
3410 addr = 0xA074;
3411 val64 = 0x0;
3412 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3413
3414 if(CHECKBIT(val64, 0x7))
3415 stat_info->xpak_stat.warn_transceiver_temp_high++;
3416
3417 if(CHECKBIT(val64, 0x6))
3418 stat_info->xpak_stat.warn_transceiver_temp_low++;
3419
3420 if(CHECKBIT(val64, 0x3))
3421 stat_info->xpak_stat.warn_laser_bias_current_high++;
3422
3423 if(CHECKBIT(val64, 0x2))
3424 stat_info->xpak_stat.warn_laser_bias_current_low++;
3425
3426 if(CHECKBIT(val64, 0x1))
3427 stat_info->xpak_stat.warn_laser_output_power_high++;
3428
3429 if(CHECKBIT(val64, 0x0))
3430 stat_info->xpak_stat.warn_laser_output_power_low++;
3431 }
3432
3433 /**
3434 * wait_for_cmd_complete - waits for a command to complete.
3435 * @sp : private member of the device structure, which is a pointer to the
3436 * s2io_nic structure.
3437 * Description: Function that waits for a command to Write into RMAC
3438 * ADDR DATA registers to be completed and returns either success or
3439 * error depending on whether the command was complete or not.
3440 * Return value:
3441 * SUCCESS on success and FAILURE on failure.
3442 */
3443
3444 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3445 int bit_state)
3446 {
3447 int ret = FAILURE, cnt = 0, delay = 1;
3448 u64 val64;
3449
3450 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3451 return FAILURE;
3452
3453 do {
3454 val64 = readq(addr);
3455 if (bit_state == S2IO_BIT_RESET) {
3456 if (!(val64 & busy_bit)) {
3457 ret = SUCCESS;
3458 break;
3459 }
3460 } else {
3461 if (!(val64 & busy_bit)) {
3462 ret = SUCCESS;
3463 break;
3464 }
3465 }
3466
3467 if(in_interrupt())
3468 mdelay(delay);
3469 else
3470 msleep(delay);
3471
3472 if (++cnt >= 10)
3473 delay = 50;
3474 } while (cnt < 20);
3475 return ret;
3476 }
3477 /*
3478 * check_pci_device_id - Checks if the device id is supported
3479 * @id : device id
3480 * Description: Function to check if the pci device id is supported by driver.
3481 * Return value: Actual device id if supported else PCI_ANY_ID
3482 */
3483 static u16 check_pci_device_id(u16 id)
3484 {
3485 switch (id) {
3486 case PCI_DEVICE_ID_HERC_WIN:
3487 case PCI_DEVICE_ID_HERC_UNI:
3488 return XFRAME_II_DEVICE;
3489 case PCI_DEVICE_ID_S2IO_UNI:
3490 case PCI_DEVICE_ID_S2IO_WIN:
3491 return XFRAME_I_DEVICE;
3492 default:
3493 return PCI_ANY_ID;
3494 }
3495 }
3496
3497 /**
3498 * s2io_reset - Resets the card.
3499 * @sp : private member of the device structure.
3500 * Description: Function to Reset the card. This function then also
3501 * restores the previously saved PCI configuration space registers as
3502 * the card reset also resets the configuration space.
3503 * Return value:
3504 * void.
3505 */
3506
3507 static void s2io_reset(struct s2io_nic * sp)
3508 {
3509 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3510 u64 val64;
3511 u16 subid, pci_cmd;
3512 int i;
3513 u16 val16;
3514 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3515 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3516
3517 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3518 __FUNCTION__, sp->dev->name);
3519
3520 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3521 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3522
3523 val64 = SW_RESET_ALL;
3524 writeq(val64, &bar0->sw_reset);
3525 if (strstr(sp->product_name, "CX4")) {
3526 msleep(750);
3527 }
3528 msleep(250);
3529 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3530
3531 /* Restore the PCI state saved during initialization. */
3532 pci_restore_state(sp->pdev);
3533 pci_read_config_word(sp->pdev, 0x2, &val16);
3534 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3535 break;
3536 msleep(200);
3537 }
3538
3539 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3540 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3541 }
3542
3543 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3544
3545 s2io_init_pci(sp);
3546
3547 /* Set swapper to enable I/O register access */
3548 s2io_set_swapper(sp);
3549
3550 /* restore mac_addr entries */
3551 do_s2io_restore_unicast_mc(sp);
3552
3553 /* Restore the MSIX table entries from local variables */
3554 restore_xmsi_data(sp);
3555
3556 /* Clear certain PCI/PCI-X fields after reset */
3557 if (sp->device_type == XFRAME_II_DEVICE) {
3558 /* Clear "detected parity error" bit */
3559 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3560
3561 /* Clearing PCIX Ecc status register */
3562 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3563
3564 /* Clearing PCI_STATUS error reflected here */
3565 writeq(s2BIT(62), &bar0->txpic_int_reg);
3566 }
3567
3568 /* Reset device statistics maintained by OS */
3569 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3570
3571 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3572 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3573 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3574 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3575 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3576 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3577 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3578 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3579 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3580 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3581 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3582 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3583 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3584 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3585 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3586 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3587 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3588 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3589 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3590
3591 /* SXE-002: Configure link and activity LED to turn it off */
3592 subid = sp->pdev->subsystem_device;
3593 if (((subid & 0xFF) >= 0x07) &&
3594 (sp->device_type == XFRAME_I_DEVICE)) {
3595 val64 = readq(&bar0->gpio_control);
3596 val64 |= 0x0000800000000000ULL;
3597 writeq(val64, &bar0->gpio_control);
3598 val64 = 0x0411040400000000ULL;
3599 writeq(val64, (void __iomem *)bar0 + 0x2700);
3600 }
3601
3602 /*
3603 * Clear spurious ECC interrupts that would have occured on
3604 * XFRAME II cards after reset.
3605 */
3606 if (sp->device_type == XFRAME_II_DEVICE) {
3607 val64 = readq(&bar0->pcc_err_reg);
3608 writeq(val64, &bar0->pcc_err_reg);
3609 }
3610
3611 sp->device_enabled_once = FALSE;
3612 }
3613
3614 /**
3615 * s2io_set_swapper - to set the swapper controle on the card
3616 * @sp : private member of the device structure,
3617 * pointer to the s2io_nic structure.
3618 * Description: Function to set the swapper control on the card
3619 * correctly depending on the 'endianness' of the system.
3620 * Return value:
3621 * SUCCESS on success and FAILURE on failure.
3622 */
3623
3624 static int s2io_set_swapper(struct s2io_nic * sp)
3625 {
3626 struct net_device *dev = sp->dev;
3627 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3628 u64 val64, valt, valr;
3629
3630 /*
3631 * Set proper endian settings and verify the same by reading
3632 * the PIF Feed-back register.
3633 */
3634
3635 val64 = readq(&bar0->pif_rd_swapper_fb);
3636 if (val64 != 0x0123456789ABCDEFULL) {
3637 int i = 0;
3638 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3639 0x8100008181000081ULL, /* FE=1, SE=0 */
3640 0x4200004242000042ULL, /* FE=0, SE=1 */
3641 0}; /* FE=0, SE=0 */
3642
3643 while(i<4) {
3644 writeq(value[i], &bar0->swapper_ctrl);
3645 val64 = readq(&bar0->pif_rd_swapper_fb);
3646 if (val64 == 0x0123456789ABCDEFULL)
3647 break;
3648 i++;
3649 }
3650 if (i == 4) {
3651 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3652 dev->name);
3653 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3654 (unsigned long long) val64);
3655 return FAILURE;
3656 }
3657 valr = value[i];
3658 } else {
3659 valr = readq(&bar0->swapper_ctrl);
3660 }
3661
3662 valt = 0x0123456789ABCDEFULL;
3663 writeq(valt, &bar0->xmsi_address);
3664 val64 = readq(&bar0->xmsi_address);
3665
3666 if(val64 != valt) {
3667 int i = 0;
3668 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3669 0x0081810000818100ULL, /* FE=1, SE=0 */
3670 0x0042420000424200ULL, /* FE=0, SE=1 */
3671 0}; /* FE=0, SE=0 */
3672
3673 while(i<4) {
3674 writeq((value[i] | valr), &bar0->swapper_ctrl);
3675 writeq(valt, &bar0->xmsi_address);
3676 val64 = readq(&bar0->xmsi_address);
3677 if(val64 == valt)
3678 break;
3679 i++;
3680 }
3681 if(i == 4) {
3682 unsigned long long x = val64;
3683 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3684 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3685 return FAILURE;
3686 }
3687 }
3688 val64 = readq(&bar0->swapper_ctrl);
3689 val64 &= 0xFFFF000000000000ULL;
3690
3691 #ifdef __BIG_ENDIAN
3692 /*
3693 * The device by default set to a big endian format, so a
3694 * big endian driver need not set anything.
3695 */
3696 val64 |= (SWAPPER_CTRL_TXP_FE |
3697 SWAPPER_CTRL_TXP_SE |
3698 SWAPPER_CTRL_TXD_R_FE |
3699 SWAPPER_CTRL_TXD_W_FE |
3700 SWAPPER_CTRL_TXF_R_FE |
3701 SWAPPER_CTRL_RXD_R_FE |
3702 SWAPPER_CTRL_RXD_W_FE |
3703 SWAPPER_CTRL_RXF_W_FE |
3704 SWAPPER_CTRL_XMSI_FE |
3705 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3706 if (sp->config.intr_type == INTA)
3707 val64 |= SWAPPER_CTRL_XMSI_SE;
3708 writeq(val64, &bar0->swapper_ctrl);
3709 #else
3710 /*
3711 * Initially we enable all bits to make it accessible by the
3712 * driver, then we selectively enable only those bits that
3713 * we want to set.
3714 */
3715 val64 |= (SWAPPER_CTRL_TXP_FE |
3716 SWAPPER_CTRL_TXP_SE |
3717 SWAPPER_CTRL_TXD_R_FE |
3718 SWAPPER_CTRL_TXD_R_SE |
3719 SWAPPER_CTRL_TXD_W_FE |
3720 SWAPPER_CTRL_TXD_W_SE |
3721 SWAPPER_CTRL_TXF_R_FE |
3722 SWAPPER_CTRL_RXD_R_FE |
3723 SWAPPER_CTRL_RXD_R_SE |
3724 SWAPPER_CTRL_RXD_W_FE |
3725 SWAPPER_CTRL_RXD_W_SE |
3726 SWAPPER_CTRL_RXF_W_FE |
3727 SWAPPER_CTRL_XMSI_FE |
3728 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3729 if (sp->config.intr_type == INTA)
3730 val64 |= SWAPPER_CTRL_XMSI_SE;
3731 writeq(val64, &bar0->swapper_ctrl);
3732 #endif
3733 val64 = readq(&bar0->swapper_ctrl);
3734
3735 /*
3736 * Verifying if endian settings are accurate by reading a
3737 * feedback register.
3738 */
3739 val64 = readq(&bar0->pif_rd_swapper_fb);
3740 if (val64 != 0x0123456789ABCDEFULL) {
3741 /* Endian settings are incorrect, calls for another dekko. */
3742 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3743 dev->name);
3744 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3745 (unsigned long long) val64);
3746 return FAILURE;
3747 }
3748
3749 return SUCCESS;
3750 }
3751
3752 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3753 {
3754 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3755 u64 val64;
3756 int ret = 0, cnt = 0;
3757
3758 do {
3759 val64 = readq(&bar0->xmsi_access);
3760 if (!(val64 & s2BIT(15)))
3761 break;
3762 mdelay(1);
3763 cnt++;
3764 } while(cnt < 5);
3765 if (cnt == 5) {
3766 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3767 ret = 1;
3768 }
3769
3770 return ret;
3771 }
3772
3773 static void restore_xmsi_data(struct s2io_nic *nic)
3774 {
3775 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3776 u64 val64;
3777 int i, msix_index;
3778
3779
3780 if (nic->device_type == XFRAME_I_DEVICE)
3781 return;
3782
3783 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3784 msix_index = (i) ? ((i-1) * 8 + 1): 0;
3785 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3786 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3787 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3788 writeq(val64, &bar0->xmsi_access);
3789 if (wait_for_msix_trans(nic, msix_index)) {
3790 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3791 continue;
3792 }
3793 }
3794 }
3795
3796 static void store_xmsi_data(struct s2io_nic *nic)
3797 {
3798 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3799 u64 val64, addr, data;
3800 int i, msix_index;
3801
3802 if (nic->device_type == XFRAME_I_DEVICE)
3803 return;
3804
3805 /* Store and display */
3806 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3807 msix_index = (i) ? ((i-1) * 8 + 1): 0;
3808 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3809 writeq(val64, &bar0->xmsi_access);
3810 if (wait_for_msix_trans(nic, msix_index)) {
3811 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3812 continue;
3813 }
3814 addr = readq(&bar0->xmsi_address);
3815 data = readq(&bar0->xmsi_data);
3816 if (addr && data) {
3817 nic->msix_info[i].addr = addr;
3818 nic->msix_info[i].data = data;
3819 }
3820 }
3821 }
3822
3823 static int s2io_enable_msi_x(struct s2io_nic *nic)
3824 {
3825 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3826 u64 rx_mat;
3827 u16 msi_control; /* Temp variable */
3828 int ret, i, j, msix_indx = 1;
3829
3830 nic->entries = kmalloc(nic->num_entries * sizeof(struct msix_entry),
3831 GFP_KERNEL);
3832 if (!nic->entries) {
3833 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3834 __FUNCTION__);
3835 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3836 return -ENOMEM;
3837 }
3838 nic->mac_control.stats_info->sw_stat.mem_allocated
3839 += (nic->num_entries * sizeof(struct msix_entry));
3840
3841 memset(nic->entries, 0, nic->num_entries * sizeof(struct msix_entry));
3842
3843 nic->s2io_entries =
3844 kmalloc(nic->num_entries * sizeof(struct s2io_msix_entry),
3845 GFP_KERNEL);
3846 if (!nic->s2io_entries) {
3847 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3848 __FUNCTION__);
3849 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3850 kfree(nic->entries);
3851 nic->mac_control.stats_info->sw_stat.mem_freed
3852 += (nic->num_entries * sizeof(struct msix_entry));
3853 return -ENOMEM;
3854 }
3855 nic->mac_control.stats_info->sw_stat.mem_allocated
3856 += (nic->num_entries * sizeof(struct s2io_msix_entry));
3857 memset(nic->s2io_entries, 0,
3858 nic->num_entries * sizeof(struct s2io_msix_entry));
3859
3860 nic->entries[0].entry = 0;
3861 nic->s2io_entries[0].entry = 0;
3862 nic->s2io_entries[0].in_use = MSIX_FLG;
3863 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3864 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3865
3866 for (i = 1; i < nic->num_entries; i++) {
3867 nic->entries[i].entry = ((i - 1) * 8) + 1;
3868 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3869 nic->s2io_entries[i].arg = NULL;
3870 nic->s2io_entries[i].in_use = 0;
3871 }
3872
3873 rx_mat = readq(&bar0->rx_mat);
3874 for (j = 0; j < nic->config.rx_ring_num; j++) {
3875 rx_mat |= RX_MAT_SET(j, msix_indx);
3876 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3877 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3878 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3879 msix_indx += 8;
3880 }
3881 writeq(rx_mat, &bar0->rx_mat);
3882 readq(&bar0->rx_mat);
3883
3884 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3885 /* We fail init if error or we get less vectors than min required */
3886 if (ret) {
3887 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3888 kfree(nic->entries);
3889 nic->mac_control.stats_info->sw_stat.mem_freed
3890 += (nic->num_entries * sizeof(struct msix_entry));
3891 kfree(nic->s2io_entries);
3892 nic->mac_control.stats_info->sw_stat.mem_freed
3893 += (nic->num_entries * sizeof(struct s2io_msix_entry));
3894 nic->entries = NULL;
3895 nic->s2io_entries = NULL;
3896 return -ENOMEM;
3897 }
3898
3899 /*
3900 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3901 * in the herc NIC. (Temp change, needs to be removed later)
3902 */
3903 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3904 msi_control |= 0x1; /* Enable MSI */
3905 pci_write_config_word(nic->pdev, 0x42, msi_control);
3906
3907 return 0;
3908 }
3909
3910 /* Handle software interrupt used during MSI(X) test */
3911 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3912 {
3913 struct s2io_nic *sp = dev_id;
3914
3915 sp->msi_detected = 1;
3916 wake_up(&sp->msi_wait);
3917
3918 return IRQ_HANDLED;
3919 }
3920
3921 /* Test interrupt path by forcing a a software IRQ */
3922 static int s2io_test_msi(struct s2io_nic *sp)
3923 {
3924 struct pci_dev *pdev = sp->pdev;
3925 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3926 int err;
3927 u64 val64, saved64;
3928
3929 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3930 sp->name, sp);
3931 if (err) {
3932 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3933 sp->dev->name, pci_name(pdev), pdev->irq);
3934 return err;
3935 }
3936
3937 init_waitqueue_head (&sp->msi_wait);
3938 sp->msi_detected = 0;
3939
3940 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3941 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3942 val64 |= SCHED_INT_CTRL_TIMER_EN;
3943 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3944 writeq(val64, &bar0->scheduled_int_ctrl);
3945
3946 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3947
3948 if (!sp->msi_detected) {
3949 /* MSI(X) test failed, go back to INTx mode */
3950 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3951 "using MSI(X) during test\n", sp->dev->name,
3952 pci_name(pdev));
3953
3954 err = -EOPNOTSUPP;
3955 }
3956
3957 free_irq(sp->entries[1].vector, sp);
3958
3959 writeq(saved64, &bar0->scheduled_int_ctrl);
3960
3961 return err;
3962 }
3963
3964 static void remove_msix_isr(struct s2io_nic *sp)
3965 {
3966 int i;
3967 u16 msi_control;
3968
3969 for (i = 0; i < sp->num_entries; i++) {
3970 if (sp->s2io_entries[i].in_use ==
3971 MSIX_REGISTERED_SUCCESS) {
3972 int vector = sp->entries[i].vector;
3973 void *arg = sp->s2io_entries[i].arg;
3974 free_irq(vector, arg);
3975 }
3976 }
3977
3978 kfree(sp->entries);
3979 kfree(sp->s2io_entries);
3980 sp->entries = NULL;
3981 sp->s2io_entries = NULL;
3982
3983 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3984 msi_control &= 0xFFFE; /* Disable MSI */
3985 pci_write_config_word(sp->pdev, 0x42, msi_control);
3986
3987 pci_disable_msix(sp->pdev);
3988 }
3989
3990 static void remove_inta_isr(struct s2io_nic *sp)
3991 {
3992 struct net_device *dev = sp->dev;
3993
3994 free_irq(sp->pdev->irq, dev);
3995 }
3996
3997 /* ********************************************************* *
3998 * Functions defined below concern the OS part of the driver *
3999 * ********************************************************* */
4000
4001 /**
4002 * s2io_open - open entry point of the driver
4003 * @dev : pointer to the device structure.
4004 * Description:
4005 * This function is the open entry point of the driver. It mainly calls a
4006 * function to allocate Rx buffers and inserts them into the buffer
4007 * descriptors and then enables the Rx part of the NIC.
4008 * Return value:
4009 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4010 * file on failure.
4011 */
4012
4013 static int s2io_open(struct net_device *dev)
4014 {
4015 struct s2io_nic *sp = dev->priv;
4016 int err = 0;
4017
4018 /*
4019 * Make sure you have link off by default every time
4020 * Nic is initialized
4021 */
4022 netif_carrier_off(dev);
4023 sp->last_link_state = 0;
4024
4025 /* Initialize H/W and enable interrupts */
4026 err = s2io_card_up(sp);
4027 if (err) {
4028 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4029 dev->name);
4030 goto hw_init_failed;
4031 }
4032
4033 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
4034 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4035 s2io_card_down(sp);
4036 err = -ENODEV;
4037 goto hw_init_failed;
4038 }
4039 s2io_start_all_tx_queue(sp);
4040 return 0;
4041
4042 hw_init_failed:
4043 if (sp->config.intr_type == MSI_X) {
4044 if (sp->entries) {
4045 kfree(sp->entries);
4046 sp->mac_control.stats_info->sw_stat.mem_freed
4047 += (sp->num_entries * sizeof(struct msix_entry));
4048 }
4049 if (sp->s2io_entries) {
4050 kfree(sp->s2io_entries);
4051 sp->mac_control.stats_info->sw_stat.mem_freed
4052 += (sp->num_entries * sizeof(struct s2io_msix_entry));
4053 }
4054 }
4055 return err;
4056 }
4057
4058 /**
4059 * s2io_close -close entry point of the driver
4060 * @dev : device pointer.
4061 * Description:
4062 * This is the stop entry point of the driver. It needs to undo exactly
4063 * whatever was done by the open entry point,thus it's usually referred to
4064 * as the close function.Among other things this function mainly stops the
4065 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4066 * Return value:
4067 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4068 * file on failure.
4069 */
4070
4071 static int s2io_close(struct net_device *dev)
4072 {
4073 struct s2io_nic *sp = dev->priv;
4074 struct config_param *config = &sp->config;
4075 u64 tmp64;
4076 int offset;
4077
4078 /* Return if the device is already closed *
4079 * Can happen when s2io_card_up failed in change_mtu *
4080 */
4081 if (!is_s2io_card_up(sp))
4082 return 0;
4083
4084 s2io_stop_all_tx_queue(sp);
4085 /* delete all populated mac entries */
4086 for (offset = 1; offset < config->max_mc_addr; offset++) {
4087 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4088 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4089 do_s2io_delete_unicast_mc(sp, tmp64);
4090 }
4091
4092 s2io_card_down(sp);
4093
4094 return 0;
4095 }
4096
4097 /**
4098 * s2io_xmit - Tx entry point of te driver
4099 * @skb : the socket buffer containing the Tx data.
4100 * @dev : device pointer.
4101 * Description :
4102 * This function is the Tx entry point of the driver. S2IO NIC supports
4103 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4104 * NOTE: when device cant queue the pkt,just the trans_start variable will
4105 * not be upadted.
4106 * Return value:
4107 * 0 on success & 1 on failure.
4108 */
4109
4110 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4111 {
4112 struct s2io_nic *sp = dev->priv;
4113 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4114 register u64 val64;
4115 struct TxD *txdp;
4116 struct TxFIFO_element __iomem *tx_fifo;
4117 unsigned long flags = 0;
4118 u16 vlan_tag = 0;
4119 struct fifo_info *fifo = NULL;
4120 struct mac_info *mac_control;
4121 struct config_param *config;
4122 int do_spin_lock = 1;
4123 int offload_type;
4124 int enable_per_list_interrupt = 0;
4125 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
4126
4127 mac_control = &sp->mac_control;
4128 config = &sp->config;
4129
4130 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4131
4132 if (unlikely(skb->len <= 0)) {
4133 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4134 dev_kfree_skb_any(skb);
4135 return 0;
4136 }
4137
4138 if (!is_s2io_card_up(sp)) {
4139 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4140 dev->name);
4141 dev_kfree_skb(skb);
4142 return 0;
4143 }
4144
4145 queue = 0;
4146 if (sp->vlgrp && vlan_tx_tag_present(skb))
4147 vlan_tag = vlan_tx_tag_get(skb);
4148 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4149 if (skb->protocol == htons(ETH_P_IP)) {
4150 struct iphdr *ip;
4151 struct tcphdr *th;
4152 ip = ip_hdr(skb);
4153
4154 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4155 th = (struct tcphdr *)(((unsigned char *)ip) +
4156 ip->ihl*4);
4157
4158 if (ip->protocol == IPPROTO_TCP) {
4159 queue_len = sp->total_tcp_fifos;
4160 queue = (ntohs(th->source) +
4161 ntohs(th->dest)) &
4162 sp->fifo_selector[queue_len - 1];
4163 if (queue >= queue_len)
4164 queue = queue_len - 1;
4165 } else if (ip->protocol == IPPROTO_UDP) {
4166 queue_len = sp->total_udp_fifos;
4167 queue = (ntohs(th->source) +
4168 ntohs(th->dest)) &
4169 sp->fifo_selector[queue_len - 1];
4170 if (queue >= queue_len)
4171 queue = queue_len - 1;
4172 queue += sp->udp_fifo_idx;
4173 if (skb->len > 1024)
4174 enable_per_list_interrupt = 1;
4175 do_spin_lock = 0;
4176 }
4177 }
4178 }
4179 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4180 /* get fifo number based on skb->priority value */
4181 queue = config->fifo_mapping
4182 [skb->priority & (MAX_TX_FIFOS - 1)];
4183 fifo = &mac_control->fifos[queue];
4184
4185 if (do_spin_lock)
4186 spin_lock_irqsave(&fifo->tx_lock, flags);
4187 else {
4188 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4189 return NETDEV_TX_LOCKED;
4190 }
4191
4192 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
4193 if (sp->config.multiq) {
4194 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4195 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4196 return NETDEV_TX_BUSY;
4197 }
4198 } else
4199 #endif
4200 if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4201 if (netif_queue_stopped(dev)) {
4202 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4203 return NETDEV_TX_BUSY;
4204 }
4205 }
4206
4207 put_off = (u16) fifo->tx_curr_put_info.offset;
4208 get_off = (u16) fifo->tx_curr_get_info.offset;
4209 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
4210
4211 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4212 /* Avoid "put" pointer going beyond "get" pointer */
4213 if (txdp->Host_Control ||
4214 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4215 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4216 s2io_stop_tx_queue(sp, fifo->fifo_no);
4217 dev_kfree_skb(skb);
4218 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4219 return 0;
4220 }
4221
4222 offload_type = s2io_offload_type(skb);
4223 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4224 txdp->Control_1 |= TXD_TCP_LSO_EN;
4225 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4226 }
4227 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4228 txdp->Control_2 |=
4229 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4230 TXD_TX_CKO_UDP_EN);
4231 }
4232 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4233 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4234 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4235 if (enable_per_list_interrupt)
4236 if (put_off & (queue_len >> 5))
4237 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4238 if (vlan_tag) {
4239 txdp->Control_2 |= TXD_VLAN_ENABLE;
4240 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4241 }
4242
4243 frg_len = skb->len - skb->data_len;
4244 if (offload_type == SKB_GSO_UDP) {
4245 int ufo_size;
4246
4247 ufo_size = s2io_udp_mss(skb);
4248 ufo_size &= ~7;
4249 txdp->Control_1 |= TXD_UFO_EN;
4250 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4251 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4252 #ifdef __BIG_ENDIAN
4253 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4254 fifo->ufo_in_band_v[put_off] =
4255 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4256 #else
4257 fifo->ufo_in_band_v[put_off] =
4258 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4259 #endif
4260 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4261 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4262 fifo->ufo_in_band_v,
4263 sizeof(u64), PCI_DMA_TODEVICE);
4264 if (pci_dma_mapping_error(txdp->Buffer_Pointer))
4265 goto pci_map_failed;
4266 txdp++;
4267 }
4268
4269 txdp->Buffer_Pointer = pci_map_single
4270 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4271 if (pci_dma_mapping_error(txdp->Buffer_Pointer))
4272 goto pci_map_failed;
4273
4274 txdp->Host_Control = (unsigned long) skb;
4275 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4276 if (offload_type == SKB_GSO_UDP)
4277 txdp->Control_1 |= TXD_UFO_EN;
4278
4279 frg_cnt = skb_shinfo(skb)->nr_frags;
4280 /* For fragmented SKB. */
4281 for (i = 0; i < frg_cnt; i++) {
4282 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4283 /* A '0' length fragment will be ignored */
4284 if (!frag->size)
4285 continue;
4286 txdp++;
4287 txdp->Buffer_Pointer = (u64) pci_map_page
4288 (sp->pdev, frag->page, frag->page_offset,
4289 frag->size, PCI_DMA_TODEVICE);
4290 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4291 if (offload_type == SKB_GSO_UDP)
4292 txdp->Control_1 |= TXD_UFO_EN;
4293 }
4294 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4295
4296 if (offload_type == SKB_GSO_UDP)
4297 frg_cnt++; /* as Txd0 was used for inband header */
4298
4299 tx_fifo = mac_control->tx_FIFO_start[queue];
4300 val64 = fifo->list_info[put_off].list_phy_addr;
4301 writeq(val64, &tx_fifo->TxDL_Pointer);
4302
4303 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4304 TX_FIFO_LAST_LIST);
4305 if (offload_type)
4306 val64 |= TX_FIFO_SPECIAL_FUNC;
4307
4308 writeq(val64, &tx_fifo->List_Control);
4309
4310 mmiowb();
4311
4312 put_off++;
4313 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4314 put_off = 0;
4315 fifo->tx_curr_put_info.offset = put_off;
4316
4317 /* Avoid "put" pointer going beyond "get" pointer */
4318 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4319 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4320 DBG_PRINT(TX_DBG,
4321 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4322 put_off, get_off);
4323 s2io_stop_tx_queue(sp, fifo->fifo_no);
4324 }
4325 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4326 dev->trans_start = jiffies;
4327 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4328
4329 if (sp->config.intr_type == MSI_X)
4330 tx_intr_handler(fifo);
4331
4332 return 0;
4333 pci_map_failed:
4334 stats->pci_map_fail_cnt++;
4335 s2io_stop_tx_queue(sp, fifo->fifo_no);
4336 stats->mem_freed += skb->truesize;
4337 dev_kfree_skb(skb);
4338 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4339 return 0;
4340 }
4341
4342 static void
4343 s2io_alarm_handle(unsigned long data)
4344 {
4345 struct s2io_nic *sp = (struct s2io_nic *)data;
4346 struct net_device *dev = sp->dev;
4347
4348 s2io_handle_errors(dev);
4349 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4350 }
4351
4352 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4353 {
4354 struct ring_info *ring = (struct ring_info *)dev_id;
4355 struct s2io_nic *sp = ring->nic;
4356 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4357 struct net_device *dev = sp->dev;
4358
4359 if (unlikely(!is_s2io_card_up(sp)))
4360 return IRQ_HANDLED;
4361
4362 if (sp->config.napi) {
4363 u8 __iomem *addr = NULL;
4364 u8 val8 = 0;
4365
4366 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4367 addr += (7 - ring->ring_no);
4368 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4369 writeb(val8, addr);
4370 val8 = readb(addr);
4371 netif_rx_schedule(dev, &ring->napi);
4372 } else {
4373 rx_intr_handler(ring, 0);
4374 s2io_chk_rx_buffers(ring);
4375 }
4376
4377 return IRQ_HANDLED;
4378 }
4379
4380 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4381 {
4382 int i;
4383 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4384 struct s2io_nic *sp = fifos->nic;
4385 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4386 struct config_param *config = &sp->config;
4387 u64 reason;
4388
4389 if (unlikely(!is_s2io_card_up(sp)))
4390 return IRQ_NONE;
4391
4392 reason = readq(&bar0->general_int_status);
4393 if (unlikely(reason == S2IO_MINUS_ONE))
4394 /* Nothing much can be done. Get out */
4395 return IRQ_HANDLED;
4396
4397 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4398
4399 if (reason & GEN_INTR_TXTRAFFIC)
4400 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4401
4402 for (i = 0; i < config->tx_fifo_num; i++)
4403 tx_intr_handler(&fifos[i]);
4404
4405 writeq(sp->general_int_mask, &bar0->general_int_mask);
4406 readl(&bar0->general_int_status);
4407
4408 return IRQ_HANDLED;
4409 }
4410
4411 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4412 {
4413 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4414 u64 val64;
4415
4416 val64 = readq(&bar0->pic_int_status);
4417 if (val64 & PIC_INT_GPIO) {
4418 val64 = readq(&bar0->gpio_int_reg);
4419 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4420 (val64 & GPIO_INT_REG_LINK_UP)) {
4421 /*
4422 * This is unstable state so clear both up/down
4423 * interrupt and adapter to re-evaluate the link state.
4424 */
4425 val64 |= GPIO_INT_REG_LINK_DOWN;
4426 val64 |= GPIO_INT_REG_LINK_UP;
4427 writeq(val64, &bar0->gpio_int_reg);
4428 val64 = readq(&bar0->gpio_int_mask);
4429 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4430 GPIO_INT_MASK_LINK_DOWN);
4431 writeq(val64, &bar0->gpio_int_mask);
4432 }
4433 else if (val64 & GPIO_INT_REG_LINK_UP) {
4434 val64 = readq(&bar0->adapter_status);
4435 /* Enable Adapter */
4436 val64 = readq(&bar0->adapter_control);
4437 val64 |= ADAPTER_CNTL_EN;
4438 writeq(val64, &bar0->adapter_control);
4439 val64 |= ADAPTER_LED_ON;
4440 writeq(val64, &bar0->adapter_control);
4441 if (!sp->device_enabled_once)
4442 sp->device_enabled_once = 1;
4443
4444 s2io_link(sp, LINK_UP);
4445 /*
4446 * unmask link down interrupt and mask link-up
4447 * intr
4448 */
4449 val64 = readq(&bar0->gpio_int_mask);
4450 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4451 val64 |= GPIO_INT_MASK_LINK_UP;
4452 writeq(val64, &bar0->gpio_int_mask);
4453
4454 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4455 val64 = readq(&bar0->adapter_status);
4456 s2io_link(sp, LINK_DOWN);
4457 /* Link is down so unmaks link up interrupt */
4458 val64 = readq(&bar0->gpio_int_mask);
4459 val64 &= ~GPIO_INT_MASK_LINK_UP;
4460 val64 |= GPIO_INT_MASK_LINK_DOWN;
4461 writeq(val64, &bar0->gpio_int_mask);
4462
4463 /* turn off LED */
4464 val64 = readq(&bar0->adapter_control);
4465 val64 = val64 &(~ADAPTER_LED_ON);
4466 writeq(val64, &bar0->adapter_control);
4467 }
4468 }
4469 val64 = readq(&bar0->gpio_int_mask);
4470 }
4471
4472 /**
4473 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4474 * @value: alarm bits
4475 * @addr: address value
4476 * @cnt: counter variable
4477 * Description: Check for alarm and increment the counter
4478 * Return Value:
4479 * 1 - if alarm bit set
4480 * 0 - if alarm bit is not set
4481 */
4482 static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
4483 unsigned long long *cnt)
4484 {
4485 u64 val64;
4486 val64 = readq(addr);
4487 if ( val64 & value ) {
4488 writeq(val64, addr);
4489 (*cnt)++;
4490 return 1;
4491 }
4492 return 0;
4493
4494 }
4495
4496 /**
4497 * s2io_handle_errors - Xframe error indication handler
4498 * @nic: device private variable
4499 * Description: Handle alarms such as loss of link, single or
4500 * double ECC errors, critical and serious errors.
4501 * Return Value:
4502 * NONE
4503 */
4504 static void s2io_handle_errors(void * dev_id)
4505 {
4506 struct net_device *dev = (struct net_device *) dev_id;
4507 struct s2io_nic *sp = dev->priv;
4508 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4509 u64 temp64 = 0,val64=0;
4510 int i = 0;
4511
4512 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4513 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4514
4515 if (!is_s2io_card_up(sp))
4516 return;
4517
4518 if (pci_channel_offline(sp->pdev))
4519 return;
4520
4521 memset(&sw_stat->ring_full_cnt, 0,
4522 sizeof(sw_stat->ring_full_cnt));
4523
4524 /* Handling the XPAK counters update */
4525 if(stats->xpak_timer_count < 72000) {
4526 /* waiting for an hour */
4527 stats->xpak_timer_count++;
4528 } else {
4529 s2io_updt_xpak_counter(dev);
4530 /* reset the count to zero */
4531 stats->xpak_timer_count = 0;
4532 }
4533
4534 /* Handling link status change error Intr */
4535 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4536 val64 = readq(&bar0->mac_rmac_err_reg);
4537 writeq(val64, &bar0->mac_rmac_err_reg);
4538 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4539 schedule_work(&sp->set_link_task);
4540 }
4541
4542 /* In case of a serious error, the device will be Reset. */
4543 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4544 &sw_stat->serious_err_cnt))
4545 goto reset;
4546
4547 /* Check for data parity error */
4548 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4549 &sw_stat->parity_err_cnt))
4550 goto reset;
4551
4552 /* Check for ring full counter */
4553 if (sp->device_type == XFRAME_II_DEVICE) {
4554 val64 = readq(&bar0->ring_bump_counter1);
4555 for (i=0; i<4; i++) {
4556 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4557 temp64 >>= 64 - ((i+1)*16);
4558 sw_stat->ring_full_cnt[i] += temp64;
4559 }
4560
4561 val64 = readq(&bar0->ring_bump_counter2);
4562 for (i=0; i<4; i++) {
4563 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4564 temp64 >>= 64 - ((i+1)*16);
4565 sw_stat->ring_full_cnt[i+4] += temp64;
4566 }
4567 }
4568
4569 val64 = readq(&bar0->txdma_int_status);
4570 /*check for pfc_err*/
4571 if (val64 & TXDMA_PFC_INT) {
4572 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4573 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4574 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4575 &sw_stat->pfc_err_cnt))
4576 goto reset;
4577 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4578 &sw_stat->pfc_err_cnt);
4579 }
4580
4581 /*check for tda_err*/
4582 if (val64 & TXDMA_TDA_INT) {
4583 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4584 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4585 &sw_stat->tda_err_cnt))
4586 goto reset;
4587 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4588 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4589 }
4590 /*check for pcc_err*/
4591 if (val64 & TXDMA_PCC_INT) {
4592 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4593 | PCC_N_SERR | PCC_6_COF_OV_ERR
4594 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4595 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4596 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4597 &sw_stat->pcc_err_cnt))
4598 goto reset;
4599 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4600 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4601 }
4602
4603 /*check for tti_err*/
4604 if (val64 & TXDMA_TTI_INT) {
4605 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4606 &sw_stat->tti_err_cnt))
4607 goto reset;
4608 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4609 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4610 }
4611
4612 /*check for lso_err*/
4613 if (val64 & TXDMA_LSO_INT) {
4614 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4615 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4616 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4617 goto reset;
4618 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4619 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4620 }
4621
4622 /*check for tpa_err*/
4623 if (val64 & TXDMA_TPA_INT) {
4624 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4625 &sw_stat->tpa_err_cnt))
4626 goto reset;
4627 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4628 &sw_stat->tpa_err_cnt);
4629 }
4630
4631 /*check for sm_err*/
4632 if (val64 & TXDMA_SM_INT) {
4633 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4634 &sw_stat->sm_err_cnt))
4635 goto reset;
4636 }
4637
4638 val64 = readq(&bar0->mac_int_status);
4639 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4640 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4641 &bar0->mac_tmac_err_reg,
4642 &sw_stat->mac_tmac_err_cnt))
4643 goto reset;
4644 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4645 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4646 &bar0->mac_tmac_err_reg,
4647 &sw_stat->mac_tmac_err_cnt);
4648 }
4649
4650 val64 = readq(&bar0->xgxs_int_status);
4651 if (val64 & XGXS_INT_STATUS_TXGXS) {
4652 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4653 &bar0->xgxs_txgxs_err_reg,
4654 &sw_stat->xgxs_txgxs_err_cnt))
4655 goto reset;
4656 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4657 &bar0->xgxs_txgxs_err_reg,
4658 &sw_stat->xgxs_txgxs_err_cnt);
4659 }
4660
4661 val64 = readq(&bar0->rxdma_int_status);
4662 if (val64 & RXDMA_INT_RC_INT_M) {
4663 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4664 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4665 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4666 goto reset;
4667 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4668 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4669 &sw_stat->rc_err_cnt);
4670 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4671 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4672 &sw_stat->prc_pcix_err_cnt))
4673 goto reset;
4674 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4675 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4676 &sw_stat->prc_pcix_err_cnt);
4677 }
4678
4679 if (val64 & RXDMA_INT_RPA_INT_M) {
4680 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4681 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4682 goto reset;
4683 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4684 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4685 }
4686
4687 if (val64 & RXDMA_INT_RDA_INT_M) {
4688 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4689 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4690 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4691 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4692 goto reset;
4693 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4694 | RDA_MISC_ERR | RDA_PCIX_ERR,
4695 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4696 }
4697
4698 if (val64 & RXDMA_INT_RTI_INT_M) {
4699 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4700 &sw_stat->rti_err_cnt))
4701 goto reset;
4702 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4703 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4704 }
4705
4706 val64 = readq(&bar0->mac_int_status);
4707 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4708 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4709 &bar0->mac_rmac_err_reg,
4710 &sw_stat->mac_rmac_err_cnt))
4711 goto reset;
4712 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4713 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4714 &sw_stat->mac_rmac_err_cnt);
4715 }
4716
4717 val64 = readq(&bar0->xgxs_int_status);
4718 if (val64 & XGXS_INT_STATUS_RXGXS) {
4719 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4720 &bar0->xgxs_rxgxs_err_reg,
4721 &sw_stat->xgxs_rxgxs_err_cnt))
4722 goto reset;
4723 }
4724
4725 val64 = readq(&bar0->mc_int_status);
4726 if(val64 & MC_INT_STATUS_MC_INT) {
4727 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4728 &sw_stat->mc_err_cnt))
4729 goto reset;
4730
4731 /* Handling Ecc errors */
4732 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4733 writeq(val64, &bar0->mc_err_reg);
4734 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4735 sw_stat->double_ecc_errs++;
4736 if (sp->device_type != XFRAME_II_DEVICE) {
4737 /*
4738 * Reset XframeI only if critical error
4739 */
4740 if (val64 &
4741 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4742 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4743 goto reset;
4744 }
4745 } else
4746 sw_stat->single_ecc_errs++;
4747 }
4748 }
4749 return;
4750
4751 reset:
4752 s2io_stop_all_tx_queue(sp);
4753 schedule_work(&sp->rst_timer_task);
4754 sw_stat->soft_reset_cnt++;
4755 return;
4756 }
4757
4758 /**
4759 * s2io_isr - ISR handler of the device .
4760 * @irq: the irq of the device.
4761 * @dev_id: a void pointer to the dev structure of the NIC.
4762 * Description: This function is the ISR handler of the device. It
4763 * identifies the reason for the interrupt and calls the relevant
4764 * service routines. As a contongency measure, this ISR allocates the
4765 * recv buffers, if their numbers are below the panic value which is
4766 * presently set to 25% of the original number of rcv buffers allocated.
4767 * Return value:
4768 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4769 * IRQ_NONE: will be returned if interrupt is not from our device
4770 */
4771 static irqreturn_t s2io_isr(int irq, void *dev_id)
4772 {
4773 struct net_device *dev = (struct net_device *) dev_id;
4774 struct s2io_nic *sp = dev->priv;
4775 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4776 int i;
4777 u64 reason = 0;
4778 struct mac_info *mac_control;
4779 struct config_param *config;
4780
4781 /* Pretend we handled any irq's from a disconnected card */
4782 if (pci_channel_offline(sp->pdev))
4783 return IRQ_NONE;
4784
4785 if (!is_s2io_card_up(sp))
4786 return IRQ_NONE;
4787
4788 mac_control = &sp->mac_control;
4789 config = &sp->config;
4790
4791 /*
4792 * Identify the cause for interrupt and call the appropriate
4793 * interrupt handler. Causes for the interrupt could be;
4794 * 1. Rx of packet.
4795 * 2. Tx complete.
4796 * 3. Link down.
4797 */
4798 reason = readq(&bar0->general_int_status);
4799
4800 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4801 /* Nothing much can be done. Get out */
4802 return IRQ_HANDLED;
4803 }
4804
4805 if (reason & (GEN_INTR_RXTRAFFIC |
4806 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4807 {
4808 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4809
4810 if (config->napi) {
4811 if (reason & GEN_INTR_RXTRAFFIC) {
4812 netif_rx_schedule(dev, &sp->napi);
4813 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4814 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4815 readl(&bar0->rx_traffic_int);
4816 }
4817 } else {
4818 /*
4819 * rx_traffic_int reg is an R1 register, writing all 1's
4820 * will ensure that the actual interrupt causing bit
4821 * get's cleared and hence a read can be avoided.
4822 */
4823 if (reason & GEN_INTR_RXTRAFFIC)
4824 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4825
4826 for (i = 0; i < config->rx_ring_num; i++)
4827 rx_intr_handler(&mac_control->rings[i], 0);
4828 }
4829
4830 /*
4831 * tx_traffic_int reg is an R1 register, writing all 1's
4832 * will ensure that the actual interrupt causing bit get's
4833 * cleared and hence a read can be avoided.
4834 */
4835 if (reason & GEN_INTR_TXTRAFFIC)
4836 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4837
4838 for (i = 0; i < config->tx_fifo_num; i++)
4839 tx_intr_handler(&mac_control->fifos[i]);
4840
4841 if (reason & GEN_INTR_TXPIC)
4842 s2io_txpic_intr_handle(sp);
4843
4844 /*
4845 * Reallocate the buffers from the interrupt handler itself.
4846 */
4847 if (!config->napi) {
4848 for (i = 0; i < config->rx_ring_num; i++)
4849 s2io_chk_rx_buffers(&mac_control->rings[i]);
4850 }
4851 writeq(sp->general_int_mask, &bar0->general_int_mask);
4852 readl(&bar0->general_int_status);
4853
4854 return IRQ_HANDLED;
4855
4856 }
4857 else if (!reason) {
4858 /* The interrupt was not raised by us */
4859 return IRQ_NONE;
4860 }
4861
4862 return IRQ_HANDLED;
4863 }
4864
4865 /**
4866 * s2io_updt_stats -
4867 */
4868 static void s2io_updt_stats(struct s2io_nic *sp)
4869 {
4870 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4871 u64 val64;
4872 int cnt = 0;
4873
4874 if (is_s2io_card_up(sp)) {
4875 /* Apprx 30us on a 133 MHz bus */
4876 val64 = SET_UPDT_CLICKS(10) |
4877 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4878 writeq(val64, &bar0->stat_cfg);
4879 do {
4880 udelay(100);
4881 val64 = readq(&bar0->stat_cfg);
4882 if (!(val64 & s2BIT(0)))
4883 break;
4884 cnt++;
4885 if (cnt == 5)
4886 break; /* Updt failed */
4887 } while(1);
4888 }
4889 }
4890
4891 /**
4892 * s2io_get_stats - Updates the device statistics structure.
4893 * @dev : pointer to the device structure.
4894 * Description:
4895 * This function updates the device statistics structure in the s2io_nic
4896 * structure and returns a pointer to the same.
4897 * Return value:
4898 * pointer to the updated net_device_stats structure.
4899 */
4900
4901 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4902 {
4903 struct s2io_nic *sp = dev->priv;
4904 struct mac_info *mac_control;
4905 struct config_param *config;
4906 int i;
4907
4908
4909 mac_control = &sp->mac_control;
4910 config = &sp->config;
4911
4912 /* Configure Stats for immediate updt */
4913 s2io_updt_stats(sp);
4914
4915 sp->stats.tx_packets =
4916 le32_to_cpu(mac_control->stats_info->tmac_frms);
4917 sp->stats.tx_errors =
4918 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4919 sp->stats.rx_errors =
4920 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4921 sp->stats.multicast =
4922 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4923 sp->stats.rx_length_errors =
4924 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4925
4926 /* collect per-ring rx_packets and rx_bytes */
4927 sp->stats.rx_packets = sp->stats.rx_bytes = 0;
4928 for (i = 0; i < config->rx_ring_num; i++) {
4929 sp->stats.rx_packets += mac_control->rings[i].rx_packets;
4930 sp->stats.rx_bytes += mac_control->rings[i].rx_bytes;
4931 }
4932
4933 return (&sp->stats);
4934 }
4935
4936 /**
4937 * s2io_set_multicast - entry point for multicast address enable/disable.
4938 * @dev : pointer to the device structure
4939 * Description:
4940 * This function is a driver entry point which gets called by the kernel
4941 * whenever multicast addresses must be enabled/disabled. This also gets
4942 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4943 * determine, if multicast address must be enabled or if promiscuous mode
4944 * is to be disabled etc.
4945 * Return value:
4946 * void.
4947 */
4948
4949 static void s2io_set_multicast(struct net_device *dev)
4950 {
4951 int i, j, prev_cnt;
4952 struct dev_mc_list *mclist;
4953 struct s2io_nic *sp = dev->priv;
4954 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4955 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4956 0xfeffffffffffULL;
4957 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4958 void __iomem *add;
4959 struct config_param *config = &sp->config;
4960
4961 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4962 /* Enable all Multicast addresses */
4963 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4964 &bar0->rmac_addr_data0_mem);
4965 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4966 &bar0->rmac_addr_data1_mem);
4967 val64 = RMAC_ADDR_CMD_MEM_WE |
4968 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4969 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4970 writeq(val64, &bar0->rmac_addr_cmd_mem);
4971 /* Wait till command completes */
4972 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4973 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4974 S2IO_BIT_RESET);
4975
4976 sp->m_cast_flg = 1;
4977 sp->all_multi_pos = config->max_mc_addr - 1;
4978 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4979 /* Disable all Multicast addresses */
4980 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4981 &bar0->rmac_addr_data0_mem);
4982 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4983 &bar0->rmac_addr_data1_mem);
4984 val64 = RMAC_ADDR_CMD_MEM_WE |
4985 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4986 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4987 writeq(val64, &bar0->rmac_addr_cmd_mem);
4988 /* Wait till command completes */
4989 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4990 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4991 S2IO_BIT_RESET);
4992
4993 sp->m_cast_flg = 0;
4994 sp->all_multi_pos = 0;
4995 }
4996
4997 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4998 /* Put the NIC into promiscuous mode */
4999 add = &bar0->mac_cfg;
5000 val64 = readq(&bar0->mac_cfg);
5001 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5002
5003 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5004 writel((u32) val64, add);
5005 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5006 writel((u32) (val64 >> 32), (add + 4));
5007
5008 if (vlan_tag_strip != 1) {
5009 val64 = readq(&bar0->rx_pa_cfg);
5010 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5011 writeq(val64, &bar0->rx_pa_cfg);
5012 vlan_strip_flag = 0;
5013 }
5014
5015 val64 = readq(&bar0->mac_cfg);
5016 sp->promisc_flg = 1;
5017 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5018 dev->name);
5019 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5020 /* Remove the NIC from promiscuous mode */
5021 add = &bar0->mac_cfg;
5022 val64 = readq(&bar0->mac_cfg);
5023 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5024
5025 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5026 writel((u32) val64, add);
5027 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5028 writel((u32) (val64 >> 32), (add + 4));
5029
5030 if (vlan_tag_strip != 0) {
5031 val64 = readq(&bar0->rx_pa_cfg);
5032 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5033 writeq(val64, &bar0->rx_pa_cfg);
5034 vlan_strip_flag = 1;
5035 }
5036
5037 val64 = readq(&bar0->mac_cfg);
5038 sp->promisc_flg = 0;
5039 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
5040 dev->name);
5041 }
5042
5043 /* Update individual M_CAST address list */
5044 if ((!sp->m_cast_flg) && dev->mc_count) {
5045 if (dev->mc_count >
5046 (config->max_mc_addr - config->max_mac_addr)) {
5047 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5048 dev->name);
5049 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5050 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5051 return;
5052 }
5053
5054 prev_cnt = sp->mc_addr_count;
5055 sp->mc_addr_count = dev->mc_count;
5056
5057 /* Clear out the previous list of Mc in the H/W. */
5058 for (i = 0; i < prev_cnt; i++) {
5059 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5060 &bar0->rmac_addr_data0_mem);
5061 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5062 &bar0->rmac_addr_data1_mem);
5063 val64 = RMAC_ADDR_CMD_MEM_WE |
5064 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5065 RMAC_ADDR_CMD_MEM_OFFSET
5066 (config->mc_start_offset + i);
5067 writeq(val64, &bar0->rmac_addr_cmd_mem);
5068
5069 /* Wait for command completes */
5070 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5071 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5072 S2IO_BIT_RESET)) {
5073 DBG_PRINT(ERR_DBG, "%s: Adding ",
5074 dev->name);
5075 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5076 return;
5077 }
5078 }
5079
5080 /* Create the new Rx filter list and update the same in H/W. */
5081 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5082 i++, mclist = mclist->next) {
5083 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5084 ETH_ALEN);
5085 mac_addr = 0;
5086 for (j = 0; j < ETH_ALEN; j++) {
5087 mac_addr |= mclist->dmi_addr[j];
5088 mac_addr <<= 8;
5089 }
5090 mac_addr >>= 8;
5091 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5092 &bar0->rmac_addr_data0_mem);
5093 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5094 &bar0->rmac_addr_data1_mem);
5095 val64 = RMAC_ADDR_CMD_MEM_WE |
5096 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5097 RMAC_ADDR_CMD_MEM_OFFSET
5098 (i + config->mc_start_offset);
5099 writeq(val64, &bar0->rmac_addr_cmd_mem);
5100
5101 /* Wait for command completes */
5102 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5103 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5104 S2IO_BIT_RESET)) {
5105 DBG_PRINT(ERR_DBG, "%s: Adding ",
5106 dev->name);
5107 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5108 return;
5109 }
5110 }
5111 }
5112 }
5113
5114 /* read from CAM unicast & multicast addresses and store it in
5115 * def_mac_addr structure
5116 */
5117 void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5118 {
5119 int offset;
5120 u64 mac_addr = 0x0;
5121 struct config_param *config = &sp->config;
5122
5123 /* store unicast & multicast mac addresses */
5124 for (offset = 0; offset < config->max_mc_addr; offset++) {
5125 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5126 /* if read fails disable the entry */
5127 if (mac_addr == FAILURE)
5128 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5129 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5130 }
5131 }
5132
5133 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5134 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5135 {
5136 int offset;
5137 struct config_param *config = &sp->config;
5138 /* restore unicast mac address */
5139 for (offset = 0; offset < config->max_mac_addr; offset++)
5140 do_s2io_prog_unicast(sp->dev,
5141 sp->def_mac_addr[offset].mac_addr);
5142
5143 /* restore multicast mac address */
5144 for (offset = config->mc_start_offset;
5145 offset < config->max_mc_addr; offset++)
5146 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5147 }
5148
5149 /* add a multicast MAC address to CAM */
5150 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5151 {
5152 int i;
5153 u64 mac_addr = 0;
5154 struct config_param *config = &sp->config;
5155
5156 for (i = 0; i < ETH_ALEN; i++) {
5157 mac_addr <<= 8;
5158 mac_addr |= addr[i];
5159 }
5160 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5161 return SUCCESS;
5162
5163 /* check if the multicast mac already preset in CAM */
5164 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5165 u64 tmp64;
5166 tmp64 = do_s2io_read_unicast_mc(sp, i);
5167 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5168 break;
5169
5170 if (tmp64 == mac_addr)
5171 return SUCCESS;
5172 }
5173 if (i == config->max_mc_addr) {
5174 DBG_PRINT(ERR_DBG,
5175 "CAM full no space left for multicast MAC\n");
5176 return FAILURE;
5177 }
5178 /* Update the internal structure with this new mac address */
5179 do_s2io_copy_mac_addr(sp, i, mac_addr);
5180
5181 return (do_s2io_add_mac(sp, mac_addr, i));
5182 }
5183
5184 /* add MAC address to CAM */
5185 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5186 {
5187 u64 val64;
5188 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5189
5190 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5191 &bar0->rmac_addr_data0_mem);
5192
5193 val64 =
5194 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5195 RMAC_ADDR_CMD_MEM_OFFSET(off);
5196 writeq(val64, &bar0->rmac_addr_cmd_mem);
5197
5198 /* Wait till command completes */
5199 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5200 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5201 S2IO_BIT_RESET)) {
5202 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5203 return FAILURE;
5204 }
5205 return SUCCESS;
5206 }
5207 /* deletes a specified unicast/multicast mac entry from CAM */
5208 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5209 {
5210 int offset;
5211 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5212 struct config_param *config = &sp->config;
5213
5214 for (offset = 1;
5215 offset < config->max_mc_addr; offset++) {
5216 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5217 if (tmp64 == addr) {
5218 /* disable the entry by writing 0xffffffffffffULL */
5219 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5220 return FAILURE;
5221 /* store the new mac list from CAM */
5222 do_s2io_store_unicast_mc(sp);
5223 return SUCCESS;
5224 }
5225 }
5226 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5227 (unsigned long long)addr);
5228 return FAILURE;
5229 }
5230
5231 /* read mac entries from CAM */
5232 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5233 {
5234 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5235 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5236
5237 /* read mac addr */
5238 val64 =
5239 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5240 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5241 writeq(val64, &bar0->rmac_addr_cmd_mem);
5242
5243 /* Wait till command completes */
5244 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5245 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5246 S2IO_BIT_RESET)) {
5247 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5248 return FAILURE;
5249 }
5250 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5251 return (tmp64 >> 16);
5252 }
5253
5254 /**
5255 * s2io_set_mac_addr driver entry point
5256 */
5257
5258 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5259 {
5260 struct sockaddr *addr = p;
5261
5262 if (!is_valid_ether_addr(addr->sa_data))
5263 return -EINVAL;
5264
5265 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5266
5267 /* store the MAC address in CAM */
5268 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5269 }
5270 /**
5271 * do_s2io_prog_unicast - Programs the Xframe mac address
5272 * @dev : pointer to the device structure.
5273 * @addr: a uchar pointer to the new mac address which is to be set.
5274 * Description : This procedure will program the Xframe to receive
5275 * frames with new Mac Address
5276 * Return value: SUCCESS on success and an appropriate (-)ve integer
5277 * as defined in errno.h file on failure.
5278 */
5279
5280 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5281 {
5282 struct s2io_nic *sp = dev->priv;
5283 register u64 mac_addr = 0, perm_addr = 0;
5284 int i;
5285 u64 tmp64;
5286 struct config_param *config = &sp->config;
5287
5288 /*
5289 * Set the new MAC address as the new unicast filter and reflect this
5290 * change on the device address registered with the OS. It will be
5291 * at offset 0.
5292 */
5293 for (i = 0; i < ETH_ALEN; i++) {
5294 mac_addr <<= 8;
5295 mac_addr |= addr[i];
5296 perm_addr <<= 8;
5297 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5298 }
5299
5300 /* check if the dev_addr is different than perm_addr */
5301 if (mac_addr == perm_addr)
5302 return SUCCESS;
5303
5304 /* check if the mac already preset in CAM */
5305 for (i = 1; i < config->max_mac_addr; i++) {
5306 tmp64 = do_s2io_read_unicast_mc(sp, i);
5307 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5308 break;
5309
5310 if (tmp64 == mac_addr) {
5311 DBG_PRINT(INFO_DBG,
5312 "MAC addr:0x%llx already present in CAM\n",
5313 (unsigned long long)mac_addr);
5314 return SUCCESS;
5315 }
5316 }
5317 if (i == config->max_mac_addr) {
5318 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5319 return FAILURE;
5320 }
5321 /* Update the internal structure with this new mac address */
5322 do_s2io_copy_mac_addr(sp, i, mac_addr);
5323 return (do_s2io_add_mac(sp, mac_addr, i));
5324 }
5325
5326 /**
5327 * s2io_ethtool_sset - Sets different link parameters.
5328 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5329 * @info: pointer to the structure with parameters given by ethtool to set
5330 * link information.
5331 * Description:
5332 * The function sets different link parameters provided by the user onto
5333 * the NIC.
5334 * Return value:
5335 * 0 on success.
5336 */
5337
5338 static int s2io_ethtool_sset(struct net_device *dev,
5339 struct ethtool_cmd *info)
5340 {
5341 struct s2io_nic *sp = dev->priv;
5342 if ((info->autoneg == AUTONEG_ENABLE) ||
5343 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5344 return -EINVAL;
5345 else {
5346 s2io_close(sp->dev);
5347 s2io_open(sp->dev);
5348 }
5349
5350 return 0;
5351 }
5352
5353 /**
5354 * s2io_ethtol_gset - Return link specific information.
5355 * @sp : private member of the device structure, pointer to the
5356 * s2io_nic structure.
5357 * @info : pointer to the structure with parameters given by ethtool
5358 * to return link information.
5359 * Description:
5360 * Returns link specific information like speed, duplex etc.. to ethtool.
5361 * Return value :
5362 * return 0 on success.
5363 */
5364
5365 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5366 {
5367 struct s2io_nic *sp = dev->priv;
5368 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5369 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5370 info->port = PORT_FIBRE;
5371
5372 /* info->transceiver */
5373 info->transceiver = XCVR_EXTERNAL;
5374
5375 if (netif_carrier_ok(sp->dev)) {
5376 info->speed = 10000;
5377 info->duplex = DUPLEX_FULL;
5378 } else {
5379 info->speed = -1;
5380 info->duplex = -1;
5381 }
5382
5383 info->autoneg = AUTONEG_DISABLE;
5384 return 0;
5385 }
5386
5387 /**
5388 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5389 * @sp : private member of the device structure, which is a pointer to the
5390 * s2io_nic structure.
5391 * @info : pointer to the structure with parameters given by ethtool to
5392 * return driver information.
5393 * Description:
5394 * Returns driver specefic information like name, version etc.. to ethtool.
5395 * Return value:
5396 * void
5397 */
5398
5399 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5400 struct ethtool_drvinfo *info)
5401 {
5402 struct s2io_nic *sp = dev->priv;
5403
5404 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5405 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5406 strncpy(info->fw_version, "", sizeof(info->fw_version));
5407 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5408 info->regdump_len = XENA_REG_SPACE;
5409 info->eedump_len = XENA_EEPROM_SPACE;
5410 }
5411
5412 /**
5413 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5414 * @sp: private member of the device structure, which is a pointer to the
5415 * s2io_nic structure.
5416 * @regs : pointer to the structure with parameters given by ethtool for
5417 * dumping the registers.
5418 * @reg_space: The input argumnet into which all the registers are dumped.
5419 * Description:
5420 * Dumps the entire register space of xFrame NIC into the user given
5421 * buffer area.
5422 * Return value :
5423 * void .
5424 */
5425
5426 static void s2io_ethtool_gregs(struct net_device *dev,
5427 struct ethtool_regs *regs, void *space)
5428 {
5429 int i;
5430 u64 reg;
5431 u8 *reg_space = (u8 *) space;
5432 struct s2io_nic *sp = dev->priv;
5433
5434 regs->len = XENA_REG_SPACE;
5435 regs->version = sp->pdev->subsystem_device;
5436
5437 for (i = 0; i < regs->len; i += 8) {
5438 reg = readq(sp->bar0 + i);
5439 memcpy((reg_space + i), &reg, 8);
5440 }
5441 }
5442
5443 /**
5444 * s2io_phy_id - timer function that alternates adapter LED.
5445 * @data : address of the private member of the device structure, which
5446 * is a pointer to the s2io_nic structure, provided as an u32.
5447 * Description: This is actually the timer function that alternates the
5448 * adapter LED bit of the adapter control bit to set/reset every time on
5449 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5450 * once every second.
5451 */
5452 static void s2io_phy_id(unsigned long data)
5453 {
5454 struct s2io_nic *sp = (struct s2io_nic *) data;
5455 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5456 u64 val64 = 0;
5457 u16 subid;
5458
5459 subid = sp->pdev->subsystem_device;
5460 if ((sp->device_type == XFRAME_II_DEVICE) ||
5461 ((subid & 0xFF) >= 0x07)) {
5462 val64 = readq(&bar0->gpio_control);
5463 val64 ^= GPIO_CTRL_GPIO_0;
5464 writeq(val64, &bar0->gpio_control);
5465 } else {
5466 val64 = readq(&bar0->adapter_control);
5467 val64 ^= ADAPTER_LED_ON;
5468 writeq(val64, &bar0->adapter_control);
5469 }
5470
5471 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5472 }
5473
5474 /**
5475 * s2io_ethtool_idnic - To physically identify the nic on the system.
5476 * @sp : private member of the device structure, which is a pointer to the
5477 * s2io_nic structure.
5478 * @id : pointer to the structure with identification parameters given by
5479 * ethtool.
5480 * Description: Used to physically identify the NIC on the system.
5481 * The Link LED will blink for a time specified by the user for
5482 * identification.
5483 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5484 * identification is possible only if it's link is up.
5485 * Return value:
5486 * int , returns 0 on success
5487 */
5488
5489 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5490 {
5491 u64 val64 = 0, last_gpio_ctrl_val;
5492 struct s2io_nic *sp = dev->priv;
5493 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5494 u16 subid;
5495
5496 subid = sp->pdev->subsystem_device;
5497 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5498 if ((sp->device_type == XFRAME_I_DEVICE) &&
5499 ((subid & 0xFF) < 0x07)) {
5500 val64 = readq(&bar0->adapter_control);
5501 if (!(val64 & ADAPTER_CNTL_EN)) {
5502 printk(KERN_ERR
5503 "Adapter Link down, cannot blink LED\n");
5504 return -EFAULT;
5505 }
5506 }
5507 if (sp->id_timer.function == NULL) {
5508 init_timer(&sp->id_timer);
5509 sp->id_timer.function = s2io_phy_id;
5510 sp->id_timer.data = (unsigned long) sp;
5511 }
5512 mod_timer(&sp->id_timer, jiffies);
5513 if (data)
5514 msleep_interruptible(data * HZ);
5515 else
5516 msleep_interruptible(MAX_FLICKER_TIME);
5517 del_timer_sync(&sp->id_timer);
5518
5519 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5520 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5521 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5522 }
5523
5524 return 0;
5525 }
5526
5527 static void s2io_ethtool_gringparam(struct net_device *dev,
5528 struct ethtool_ringparam *ering)
5529 {
5530 struct s2io_nic *sp = dev->priv;
5531 int i,tx_desc_count=0,rx_desc_count=0;
5532
5533 if (sp->rxd_mode == RXD_MODE_1)
5534 ering->rx_max_pending = MAX_RX_DESC_1;
5535 else if (sp->rxd_mode == RXD_MODE_3B)
5536 ering->rx_max_pending = MAX_RX_DESC_2;
5537
5538 ering->tx_max_pending = MAX_TX_DESC;
5539 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5540 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5541
5542 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5543 ering->tx_pending = tx_desc_count;
5544 rx_desc_count = 0;
5545 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5546 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5547
5548 ering->rx_pending = rx_desc_count;
5549
5550 ering->rx_mini_max_pending = 0;
5551 ering->rx_mini_pending = 0;
5552 if(sp->rxd_mode == RXD_MODE_1)
5553 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5554 else if (sp->rxd_mode == RXD_MODE_3B)
5555 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5556 ering->rx_jumbo_pending = rx_desc_count;
5557 }
5558
5559 /**
5560 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5561 * @sp : private member of the device structure, which is a pointer to the
5562 * s2io_nic structure.
5563 * @ep : pointer to the structure with pause parameters given by ethtool.
5564 * Description:
5565 * Returns the Pause frame generation and reception capability of the NIC.
5566 * Return value:
5567 * void
5568 */
5569 static void s2io_ethtool_getpause_data(struct net_device *dev,
5570 struct ethtool_pauseparam *ep)
5571 {
5572 u64 val64;
5573 struct s2io_nic *sp = dev->priv;
5574 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5575
5576 val64 = readq(&bar0->rmac_pause_cfg);
5577 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5578 ep->tx_pause = TRUE;
5579 if (val64 & RMAC_PAUSE_RX_ENABLE)
5580 ep->rx_pause = TRUE;
5581 ep->autoneg = FALSE;
5582 }
5583
5584 /**
5585 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5586 * @sp : private member of the device structure, which is a pointer to the
5587 * s2io_nic structure.
5588 * @ep : pointer to the structure with pause parameters given by ethtool.
5589 * Description:
5590 * It can be used to set or reset Pause frame generation or reception
5591 * support of the NIC.
5592 * Return value:
5593 * int, returns 0 on Success
5594 */
5595
5596 static int s2io_ethtool_setpause_data(struct net_device *dev,
5597 struct ethtool_pauseparam *ep)
5598 {
5599 u64 val64;
5600 struct s2io_nic *sp = dev->priv;
5601 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5602
5603 val64 = readq(&bar0->rmac_pause_cfg);
5604 if (ep->tx_pause)
5605 val64 |= RMAC_PAUSE_GEN_ENABLE;
5606 else
5607 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5608 if (ep->rx_pause)
5609 val64 |= RMAC_PAUSE_RX_ENABLE;
5610 else
5611 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5612 writeq(val64, &bar0->rmac_pause_cfg);
5613 return 0;
5614 }
5615
5616 /**
5617 * read_eeprom - reads 4 bytes of data from user given offset.
5618 * @sp : private member of the device structure, which is a pointer to the
5619 * s2io_nic structure.
5620 * @off : offset at which the data must be written
5621 * @data : Its an output parameter where the data read at the given
5622 * offset is stored.
5623 * Description:
5624 * Will read 4 bytes of data from the user given offset and return the
5625 * read data.
5626 * NOTE: Will allow to read only part of the EEPROM visible through the
5627 * I2C bus.
5628 * Return value:
5629 * -1 on failure and 0 on success.
5630 */
5631
5632 #define S2IO_DEV_ID 5
5633 static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
5634 {
5635 int ret = -1;
5636 u32 exit_cnt = 0;
5637 u64 val64;
5638 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5639
5640 if (sp->device_type == XFRAME_I_DEVICE) {
5641 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5642 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5643 I2C_CONTROL_CNTL_START;
5644 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5645
5646 while (exit_cnt < 5) {
5647 val64 = readq(&bar0->i2c_control);
5648 if (I2C_CONTROL_CNTL_END(val64)) {
5649 *data = I2C_CONTROL_GET_DATA(val64);
5650 ret = 0;
5651 break;
5652 }
5653 msleep(50);
5654 exit_cnt++;
5655 }
5656 }
5657
5658 if (sp->device_type == XFRAME_II_DEVICE) {
5659 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5660 SPI_CONTROL_BYTECNT(0x3) |
5661 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5662 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5663 val64 |= SPI_CONTROL_REQ;
5664 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5665 while (exit_cnt < 5) {
5666 val64 = readq(&bar0->spi_control);
5667 if (val64 & SPI_CONTROL_NACK) {
5668 ret = 1;
5669 break;
5670 } else if (val64 & SPI_CONTROL_DONE) {
5671 *data = readq(&bar0->spi_data);
5672 *data &= 0xffffff;
5673 ret = 0;
5674 break;
5675 }
5676 msleep(50);
5677 exit_cnt++;
5678 }
5679 }
5680 return ret;
5681 }
5682
5683 /**
5684 * write_eeprom - actually writes the relevant part of the data value.
5685 * @sp : private member of the device structure, which is a pointer to the
5686 * s2io_nic structure.
5687 * @off : offset at which the data must be written
5688 * @data : The data that is to be written
5689 * @cnt : Number of bytes of the data that are actually to be written into
5690 * the Eeprom. (max of 3)
5691 * Description:
5692 * Actually writes the relevant part of the data value into the Eeprom
5693 * through the I2C bus.
5694 * Return value:
5695 * 0 on success, -1 on failure.
5696 */
5697
5698 static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
5699 {
5700 int exit_cnt = 0, ret = -1;
5701 u64 val64;
5702 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5703
5704 if (sp->device_type == XFRAME_I_DEVICE) {
5705 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5706 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5707 I2C_CONTROL_CNTL_START;
5708 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5709
5710 while (exit_cnt < 5) {
5711 val64 = readq(&bar0->i2c_control);
5712 if (I2C_CONTROL_CNTL_END(val64)) {
5713 if (!(val64 & I2C_CONTROL_NACK))
5714 ret = 0;
5715 break;
5716 }
5717 msleep(50);
5718 exit_cnt++;
5719 }
5720 }
5721
5722 if (sp->device_type == XFRAME_II_DEVICE) {
5723 int write_cnt = (cnt == 8) ? 0 : cnt;
5724 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5725
5726 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5727 SPI_CONTROL_BYTECNT(write_cnt) |
5728 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5729 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5730 val64 |= SPI_CONTROL_REQ;
5731 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5732 while (exit_cnt < 5) {
5733 val64 = readq(&bar0->spi_control);
5734 if (val64 & SPI_CONTROL_NACK) {
5735 ret = 1;
5736 break;
5737 } else if (val64 & SPI_CONTROL_DONE) {
5738 ret = 0;
5739 break;
5740 }
5741 msleep(50);
5742 exit_cnt++;
5743 }
5744 }
5745 return ret;
5746 }
5747 static void s2io_vpd_read(struct s2io_nic *nic)
5748 {
5749 u8 *vpd_data;
5750 u8 data;
5751 int i=0, cnt, fail = 0;
5752 int vpd_addr = 0x80;
5753
5754 if (nic->device_type == XFRAME_II_DEVICE) {
5755 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5756 vpd_addr = 0x80;
5757 }
5758 else {
5759 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5760 vpd_addr = 0x50;
5761 }
5762 strcpy(nic->serial_num, "NOT AVAILABLE");
5763
5764 vpd_data = kmalloc(256, GFP_KERNEL);
5765 if (!vpd_data) {
5766 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5767 return;
5768 }
5769 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5770
5771 for (i = 0; i < 256; i +=4 ) {
5772 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5773 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5774 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5775 for (cnt = 0; cnt <5; cnt++) {
5776 msleep(2);
5777 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5778 if (data == 0x80)
5779 break;
5780 }
5781 if (cnt >= 5) {
5782 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5783 fail = 1;
5784 break;
5785 }
5786 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5787 (u32 *)&vpd_data[i]);
5788 }
5789
5790 if(!fail) {
5791 /* read serial number of adapter */
5792 for (cnt = 0; cnt < 256; cnt++) {
5793 if ((vpd_data[cnt] == 'S') &&
5794 (vpd_data[cnt+1] == 'N') &&
5795 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5796 memset(nic->serial_num, 0, VPD_STRING_LEN);
5797 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5798 vpd_data[cnt+2]);
5799 break;
5800 }
5801 }
5802 }
5803
5804 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5805 memset(nic->product_name, 0, vpd_data[1]);
5806 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5807 }
5808 kfree(vpd_data);
5809 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5810 }
5811
5812 /**
5813 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5814 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5815 * @eeprom : pointer to the user level structure provided by ethtool,
5816 * containing all relevant information.
5817 * @data_buf : user defined value to be written into Eeprom.
5818 * Description: Reads the values stored in the Eeprom at given offset
5819 * for a given length. Stores these values int the input argument data
5820 * buffer 'data_buf' and returns these to the caller (ethtool.)
5821 * Return value:
5822 * int 0 on success
5823 */
5824
5825 static int s2io_ethtool_geeprom(struct net_device *dev,
5826 struct ethtool_eeprom *eeprom, u8 * data_buf)
5827 {
5828 u32 i, valid;
5829 u64 data;
5830 struct s2io_nic *sp = dev->priv;
5831
5832 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5833
5834 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5835 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5836
5837 for (i = 0; i < eeprom->len; i += 4) {
5838 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5839 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5840 return -EFAULT;
5841 }
5842 valid = INV(data);
5843 memcpy((data_buf + i), &valid, 4);
5844 }
5845 return 0;
5846 }
5847
5848 /**
5849 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5850 * @sp : private member of the device structure, which is a pointer to the
5851 * s2io_nic structure.
5852 * @eeprom : pointer to the user level structure provided by ethtool,
5853 * containing all relevant information.
5854 * @data_buf ; user defined value to be written into Eeprom.
5855 * Description:
5856 * Tries to write the user provided value in the Eeprom, at the offset
5857 * given by the user.
5858 * Return value:
5859 * 0 on success, -EFAULT on failure.
5860 */
5861
5862 static int s2io_ethtool_seeprom(struct net_device *dev,
5863 struct ethtool_eeprom *eeprom,
5864 u8 * data_buf)
5865 {
5866 int len = eeprom->len, cnt = 0;
5867 u64 valid = 0, data;
5868 struct s2io_nic *sp = dev->priv;
5869
5870 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5871 DBG_PRINT(ERR_DBG,
5872 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5873 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5874 eeprom->magic);
5875 return -EFAULT;
5876 }
5877
5878 while (len) {
5879 data = (u32) data_buf[cnt] & 0x000000FF;
5880 if (data) {
5881 valid = (u32) (data << 24);
5882 } else
5883 valid = data;
5884
5885 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5886 DBG_PRINT(ERR_DBG,
5887 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5888 DBG_PRINT(ERR_DBG,
5889 "write into the specified offset\n");
5890 return -EFAULT;
5891 }
5892 cnt++;
5893 len--;
5894 }
5895
5896 return 0;
5897 }
5898
5899 /**
5900 * s2io_register_test - reads and writes into all clock domains.
5901 * @sp : private member of the device structure, which is a pointer to the
5902 * s2io_nic structure.
5903 * @data : variable that returns the result of each of the test conducted b
5904 * by the driver.
5905 * Description:
5906 * Read and write into all clock domains. The NIC has 3 clock domains,
5907 * see that registers in all the three regions are accessible.
5908 * Return value:
5909 * 0 on success.
5910 */
5911
5912 static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5913 {
5914 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5915 u64 val64 = 0, exp_val;
5916 int fail = 0;
5917
5918 val64 = readq(&bar0->pif_rd_swapper_fb);
5919 if (val64 != 0x123456789abcdefULL) {
5920 fail = 1;
5921 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5922 }
5923
5924 val64 = readq(&bar0->rmac_pause_cfg);
5925 if (val64 != 0xc000ffff00000000ULL) {
5926 fail = 1;
5927 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5928 }
5929
5930 val64 = readq(&bar0->rx_queue_cfg);
5931 if (sp->device_type == XFRAME_II_DEVICE)
5932 exp_val = 0x0404040404040404ULL;
5933 else
5934 exp_val = 0x0808080808080808ULL;
5935 if (val64 != exp_val) {
5936 fail = 1;
5937 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5938 }
5939
5940 val64 = readq(&bar0->xgxs_efifo_cfg);
5941 if (val64 != 0x000000001923141EULL) {
5942 fail = 1;
5943 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5944 }
5945
5946 val64 = 0x5A5A5A5A5A5A5A5AULL;
5947 writeq(val64, &bar0->xmsi_data);
5948 val64 = readq(&bar0->xmsi_data);
5949 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5950 fail = 1;
5951 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5952 }
5953
5954 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5955 writeq(val64, &bar0->xmsi_data);
5956 val64 = readq(&bar0->xmsi_data);
5957 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5958 fail = 1;
5959 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5960 }
5961
5962 *data = fail;
5963 return fail;
5964 }
5965
5966 /**
5967 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5968 * @sp : private member of the device structure, which is a pointer to the
5969 * s2io_nic structure.
5970 * @data:variable that returns the result of each of the test conducted by
5971 * the driver.
5972 * Description:
5973 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5974 * register.
5975 * Return value:
5976 * 0 on success.
5977 */
5978
5979 static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5980 {
5981 int fail = 0;
5982 u64 ret_data, org_4F0, org_7F0;
5983 u8 saved_4F0 = 0, saved_7F0 = 0;
5984 struct net_device *dev = sp->dev;
5985
5986 /* Test Write Error at offset 0 */
5987 /* Note that SPI interface allows write access to all areas
5988 * of EEPROM. Hence doing all negative testing only for Xframe I.
5989 */
5990 if (sp->device_type == XFRAME_I_DEVICE)
5991 if (!write_eeprom(sp, 0, 0, 3))
5992 fail = 1;
5993
5994 /* Save current values at offsets 0x4F0 and 0x7F0 */
5995 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5996 saved_4F0 = 1;
5997 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5998 saved_7F0 = 1;
5999
6000 /* Test Write at offset 4f0 */
6001 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
6002 fail = 1;
6003 if (read_eeprom(sp, 0x4F0, &ret_data))
6004 fail = 1;
6005
6006 if (ret_data != 0x012345) {
6007 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6008 "Data written %llx Data read %llx\n",
6009 dev->name, (unsigned long long)0x12345,
6010 (unsigned long long)ret_data);
6011 fail = 1;
6012 }
6013
6014 /* Reset the EEPROM data go FFFF */
6015 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6016
6017 /* Test Write Request Error at offset 0x7c */
6018 if (sp->device_type == XFRAME_I_DEVICE)
6019 if (!write_eeprom(sp, 0x07C, 0, 3))
6020 fail = 1;
6021
6022 /* Test Write Request at offset 0x7f0 */
6023 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6024 fail = 1;
6025 if (read_eeprom(sp, 0x7F0, &ret_data))
6026 fail = 1;
6027
6028 if (ret_data != 0x012345) {
6029 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6030 "Data written %llx Data read %llx\n",
6031 dev->name, (unsigned long long)0x12345,
6032 (unsigned long long)ret_data);
6033 fail = 1;
6034 }
6035
6036 /* Reset the EEPROM data go FFFF */
6037 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6038
6039 if (sp->device_type == XFRAME_I_DEVICE) {
6040 /* Test Write Error at offset 0x80 */
6041 if (!write_eeprom(sp, 0x080, 0, 3))
6042 fail = 1;
6043
6044 /* Test Write Error at offset 0xfc */
6045 if (!write_eeprom(sp, 0x0FC, 0, 3))
6046 fail = 1;
6047
6048 /* Test Write Error at offset 0x100 */
6049 if (!write_eeprom(sp, 0x100, 0, 3))
6050 fail = 1;
6051
6052 /* Test Write Error at offset 4ec */
6053 if (!write_eeprom(sp, 0x4EC, 0, 3))
6054 fail = 1;
6055 }
6056
6057 /* Restore values at offsets 0x4F0 and 0x7F0 */
6058 if (saved_4F0)
6059 write_eeprom(sp, 0x4F0, org_4F0, 3);
6060 if (saved_7F0)
6061 write_eeprom(sp, 0x7F0, org_7F0, 3);
6062
6063 *data = fail;
6064 return fail;
6065 }
6066
6067 /**
6068 * s2io_bist_test - invokes the MemBist test of the card .
6069 * @sp : private member of the device structure, which is a pointer to the
6070 * s2io_nic structure.
6071 * @data:variable that returns the result of each of the test conducted by
6072 * the driver.
6073 * Description:
6074 * This invokes the MemBist test of the card. We give around
6075 * 2 secs time for the Test to complete. If it's still not complete
6076 * within this peiod, we consider that the test failed.
6077 * Return value:
6078 * 0 on success and -1 on failure.
6079 */
6080
6081 static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
6082 {
6083 u8 bist = 0;
6084 int cnt = 0, ret = -1;
6085
6086 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6087 bist |= PCI_BIST_START;
6088 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6089
6090 while (cnt < 20) {
6091 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6092 if (!(bist & PCI_BIST_START)) {
6093 *data = (bist & PCI_BIST_CODE_MASK);
6094 ret = 0;
6095 break;
6096 }
6097 msleep(100);
6098 cnt++;
6099 }
6100
6101 return ret;
6102 }
6103
6104 /**
6105 * s2io-link_test - verifies the link state of the nic
6106 * @sp ; private member of the device structure, which is a pointer to the
6107 * s2io_nic structure.
6108 * @data: variable that returns the result of each of the test conducted by
6109 * the driver.
6110 * Description:
6111 * The function verifies the link state of the NIC and updates the input
6112 * argument 'data' appropriately.
6113 * Return value:
6114 * 0 on success.
6115 */
6116
6117 static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
6118 {
6119 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6120 u64 val64;
6121
6122 val64 = readq(&bar0->adapter_status);
6123 if(!(LINK_IS_UP(val64)))
6124 *data = 1;
6125 else
6126 *data = 0;
6127
6128 return *data;
6129 }
6130
6131 /**
6132 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6133 * @sp - private member of the device structure, which is a pointer to the
6134 * s2io_nic structure.
6135 * @data - variable that returns the result of each of the test
6136 * conducted by the driver.
6137 * Description:
6138 * This is one of the offline test that tests the read and write
6139 * access to the RldRam chip on the NIC.
6140 * Return value:
6141 * 0 on success.
6142 */
6143
6144 static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
6145 {
6146 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6147 u64 val64;
6148 int cnt, iteration = 0, test_fail = 0;
6149
6150 val64 = readq(&bar0->adapter_control);
6151 val64 &= ~ADAPTER_ECC_EN;
6152 writeq(val64, &bar0->adapter_control);
6153
6154 val64 = readq(&bar0->mc_rldram_test_ctrl);
6155 val64 |= MC_RLDRAM_TEST_MODE;
6156 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6157
6158 val64 = readq(&bar0->mc_rldram_mrs);
6159 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6160 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6161
6162 val64 |= MC_RLDRAM_MRS_ENABLE;
6163 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6164
6165 while (iteration < 2) {
6166 val64 = 0x55555555aaaa0000ULL;
6167 if (iteration == 1) {
6168 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6169 }
6170 writeq(val64, &bar0->mc_rldram_test_d0);
6171
6172 val64 = 0xaaaa5a5555550000ULL;
6173 if (iteration == 1) {
6174 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6175 }
6176 writeq(val64, &bar0->mc_rldram_test_d1);
6177
6178 val64 = 0x55aaaaaaaa5a0000ULL;
6179 if (iteration == 1) {
6180 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6181 }
6182 writeq(val64, &bar0->mc_rldram_test_d2);
6183
6184 val64 = (u64) (0x0000003ffffe0100ULL);
6185 writeq(val64, &bar0->mc_rldram_test_add);
6186
6187 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6188 MC_RLDRAM_TEST_GO;
6189 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6190
6191 for (cnt = 0; cnt < 5; cnt++) {
6192 val64 = readq(&bar0->mc_rldram_test_ctrl);
6193 if (val64 & MC_RLDRAM_TEST_DONE)
6194 break;
6195 msleep(200);
6196 }
6197
6198 if (cnt == 5)
6199 break;
6200
6201 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6202 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6203
6204 for (cnt = 0; cnt < 5; cnt++) {
6205 val64 = readq(&bar0->mc_rldram_test_ctrl);
6206 if (val64 & MC_RLDRAM_TEST_DONE)
6207 break;
6208 msleep(500);
6209 }
6210
6211 if (cnt == 5)
6212 break;
6213
6214 val64 = readq(&bar0->mc_rldram_test_ctrl);
6215 if (!(val64 & MC_RLDRAM_TEST_PASS))
6216 test_fail = 1;
6217
6218 iteration++;
6219 }
6220
6221 *data = test_fail;
6222
6223 /* Bring the adapter out of test mode */
6224 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6225
6226 return test_fail;
6227 }
6228
6229 /**
6230 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6231 * @sp : private member of the device structure, which is a pointer to the
6232 * s2io_nic structure.
6233 * @ethtest : pointer to a ethtool command specific structure that will be
6234 * returned to the user.
6235 * @data : variable that returns the result of each of the test
6236 * conducted by the driver.
6237 * Description:
6238 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6239 * the health of the card.
6240 * Return value:
6241 * void
6242 */
6243
6244 static void s2io_ethtool_test(struct net_device *dev,
6245 struct ethtool_test *ethtest,
6246 uint64_t * data)
6247 {
6248 struct s2io_nic *sp = dev->priv;
6249 int orig_state = netif_running(sp->dev);
6250
6251 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6252 /* Offline Tests. */
6253 if (orig_state)
6254 s2io_close(sp->dev);
6255
6256 if (s2io_register_test(sp, &data[0]))
6257 ethtest->flags |= ETH_TEST_FL_FAILED;
6258
6259 s2io_reset(sp);
6260
6261 if (s2io_rldram_test(sp, &data[3]))
6262 ethtest->flags |= ETH_TEST_FL_FAILED;
6263
6264 s2io_reset(sp);
6265
6266 if (s2io_eeprom_test(sp, &data[1]))
6267 ethtest->flags |= ETH_TEST_FL_FAILED;
6268
6269 if (s2io_bist_test(sp, &data[4]))
6270 ethtest->flags |= ETH_TEST_FL_FAILED;
6271
6272 if (orig_state)
6273 s2io_open(sp->dev);
6274
6275 data[2] = 0;
6276 } else {
6277 /* Online Tests. */
6278 if (!orig_state) {
6279 DBG_PRINT(ERR_DBG,
6280 "%s: is not up, cannot run test\n",
6281 dev->name);
6282 data[0] = -1;
6283 data[1] = -1;
6284 data[2] = -1;
6285 data[3] = -1;
6286 data[4] = -1;
6287 }
6288
6289 if (s2io_link_test(sp, &data[2]))
6290 ethtest->flags |= ETH_TEST_FL_FAILED;
6291
6292 data[0] = 0;
6293 data[1] = 0;
6294 data[3] = 0;
6295 data[4] = 0;
6296 }
6297 }
6298
6299 static void s2io_get_ethtool_stats(struct net_device *dev,
6300 struct ethtool_stats *estats,
6301 u64 * tmp_stats)
6302 {
6303 int i = 0, k;
6304 struct s2io_nic *sp = dev->priv;
6305 struct stat_block *stat_info = sp->mac_control.stats_info;
6306
6307 s2io_updt_stats(sp);
6308 tmp_stats[i++] =
6309 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6310 le32_to_cpu(stat_info->tmac_frms);
6311 tmp_stats[i++] =
6312 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6313 le32_to_cpu(stat_info->tmac_data_octets);
6314 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
6315 tmp_stats[i++] =
6316 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6317 le32_to_cpu(stat_info->tmac_mcst_frms);
6318 tmp_stats[i++] =
6319 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6320 le32_to_cpu(stat_info->tmac_bcst_frms);
6321 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
6322 tmp_stats[i++] =
6323 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6324 le32_to_cpu(stat_info->tmac_ttl_octets);
6325 tmp_stats[i++] =
6326 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6327 le32_to_cpu(stat_info->tmac_ucst_frms);
6328 tmp_stats[i++] =
6329 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6330 le32_to_cpu(stat_info->tmac_nucst_frms);
6331 tmp_stats[i++] =
6332 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6333 le32_to_cpu(stat_info->tmac_any_err_frms);
6334 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
6335 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
6336 tmp_stats[i++] =
6337 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6338 le32_to_cpu(stat_info->tmac_vld_ip);
6339 tmp_stats[i++] =
6340 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6341 le32_to_cpu(stat_info->tmac_drop_ip);
6342 tmp_stats[i++] =
6343 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6344 le32_to_cpu(stat_info->tmac_icmp);
6345 tmp_stats[i++] =
6346 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6347 le32_to_cpu(stat_info->tmac_rst_tcp);
6348 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
6349 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6350 le32_to_cpu(stat_info->tmac_udp);
6351 tmp_stats[i++] =
6352 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6353 le32_to_cpu(stat_info->rmac_vld_frms);
6354 tmp_stats[i++] =
6355 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6356 le32_to_cpu(stat_info->rmac_data_octets);
6357 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6358 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
6359 tmp_stats[i++] =
6360 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6361 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6362 tmp_stats[i++] =
6363 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6364 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
6365 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
6366 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
6367 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6368 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
6369 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6370 tmp_stats[i++] =
6371 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6372 le32_to_cpu(stat_info->rmac_ttl_octets);
6373 tmp_stats[i++] =
6374 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6375 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6376 tmp_stats[i++] =
6377 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6378 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
6379 tmp_stats[i++] =
6380 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6381 le32_to_cpu(stat_info->rmac_discarded_frms);
6382 tmp_stats[i++] =
6383 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6384 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6385 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6386 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
6387 tmp_stats[i++] =
6388 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6389 le32_to_cpu(stat_info->rmac_usized_frms);
6390 tmp_stats[i++] =
6391 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6392 le32_to_cpu(stat_info->rmac_osized_frms);
6393 tmp_stats[i++] =
6394 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6395 le32_to_cpu(stat_info->rmac_frag_frms);
6396 tmp_stats[i++] =
6397 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6398 le32_to_cpu(stat_info->rmac_jabber_frms);
6399 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6400 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6401 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6402 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6403 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6404 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6405 tmp_stats[i++] =
6406 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
6407 le32_to_cpu(stat_info->rmac_ip);
6408 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6409 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
6410 tmp_stats[i++] =
6411 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
6412 le32_to_cpu(stat_info->rmac_drop_ip);
6413 tmp_stats[i++] =
6414 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
6415 le32_to_cpu(stat_info->rmac_icmp);
6416 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
6417 tmp_stats[i++] =
6418 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
6419 le32_to_cpu(stat_info->rmac_udp);
6420 tmp_stats[i++] =
6421 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6422 le32_to_cpu(stat_info->rmac_err_drp_udp);
6423 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6424 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6425 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6426 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6427 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6428 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6429 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6430 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6431 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6432 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6433 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6434 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6435 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6436 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6437 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6438 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6439 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
6440 tmp_stats[i++] =
6441 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6442 le32_to_cpu(stat_info->rmac_pause_cnt);
6443 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6444 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
6445 tmp_stats[i++] =
6446 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6447 le32_to_cpu(stat_info->rmac_accepted_ip);
6448 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
6449 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6450 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6451 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6452 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6453 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6454 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6455 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6456 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6457 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6458 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6459 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6460 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6461 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6462 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6463 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6464 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6465 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6466 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
6467
6468 /* Enhanced statistics exist only for Hercules */
6469 if(sp->device_type == XFRAME_II_DEVICE) {
6470 tmp_stats[i++] =
6471 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6472 tmp_stats[i++] =
6473 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6474 tmp_stats[i++] =
6475 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6476 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6477 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6478 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6479 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6480 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6481 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6482 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6483 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6484 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6485 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6486 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6487 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6488 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6489 }
6490
6491 tmp_stats[i++] = 0;
6492 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6493 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
6494 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6495 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6496 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6497 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
6498 for (k = 0; k < MAX_RX_RINGS; k++)
6499 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
6500 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6501 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6502 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6503 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6504 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6505 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6506 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6507 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6508 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6509 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6510 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6511 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
6512 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6513 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6514 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6515 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
6516 if (stat_info->sw_stat.num_aggregations) {
6517 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6518 int count = 0;
6519 /*
6520 * Since 64-bit divide does not work on all platforms,
6521 * do repeated subtraction.
6522 */
6523 while (tmp >= stat_info->sw_stat.num_aggregations) {
6524 tmp -= stat_info->sw_stat.num_aggregations;
6525 count++;
6526 }
6527 tmp_stats[i++] = count;
6528 }
6529 else
6530 tmp_stats[i++] = 0;
6531 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
6532 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
6533 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
6534 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6535 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6536 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6537 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6538 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6539 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6540
6541 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6542 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6543 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6544 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6545 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6546
6547 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6548 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6549 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6550 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6551 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6552 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6553 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6554 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6555 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
6556 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6557 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6558 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6559 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6560 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6561 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6562 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6563 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6564 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6565 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6566 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6567 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6568 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6569 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6570 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6571 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6572 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
6573 }
6574
6575 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6576 {
6577 return (XENA_REG_SPACE);
6578 }
6579
6580
6581 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
6582 {
6583 struct s2io_nic *sp = dev->priv;
6584
6585 return (sp->rx_csum);
6586 }
6587
6588 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6589 {
6590 struct s2io_nic *sp = dev->priv;
6591
6592 if (data)
6593 sp->rx_csum = 1;
6594 else
6595 sp->rx_csum = 0;
6596
6597 return 0;
6598 }
6599
6600 static int s2io_get_eeprom_len(struct net_device *dev)
6601 {
6602 return (XENA_EEPROM_SPACE);
6603 }
6604
6605 static int s2io_get_sset_count(struct net_device *dev, int sset)
6606 {
6607 struct s2io_nic *sp = dev->priv;
6608
6609 switch (sset) {
6610 case ETH_SS_TEST:
6611 return S2IO_TEST_LEN;
6612 case ETH_SS_STATS:
6613 switch(sp->device_type) {
6614 case XFRAME_I_DEVICE:
6615 return XFRAME_I_STAT_LEN;
6616 case XFRAME_II_DEVICE:
6617 return XFRAME_II_STAT_LEN;
6618 default:
6619 return 0;
6620 }
6621 default:
6622 return -EOPNOTSUPP;
6623 }
6624 }
6625
6626 static void s2io_ethtool_get_strings(struct net_device *dev,
6627 u32 stringset, u8 * data)
6628 {
6629 int stat_size = 0;
6630 struct s2io_nic *sp = dev->priv;
6631
6632 switch (stringset) {
6633 case ETH_SS_TEST:
6634 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6635 break;
6636 case ETH_SS_STATS:
6637 stat_size = sizeof(ethtool_xena_stats_keys);
6638 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6639 if(sp->device_type == XFRAME_II_DEVICE) {
6640 memcpy(data + stat_size,
6641 &ethtool_enhanced_stats_keys,
6642 sizeof(ethtool_enhanced_stats_keys));
6643 stat_size += sizeof(ethtool_enhanced_stats_keys);
6644 }
6645
6646 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6647 sizeof(ethtool_driver_stats_keys));
6648 }
6649 }
6650
6651 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6652 {
6653 if (data)
6654 dev->features |= NETIF_F_IP_CSUM;
6655 else
6656 dev->features &= ~NETIF_F_IP_CSUM;
6657
6658 return 0;
6659 }
6660
6661 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6662 {
6663 return (dev->features & NETIF_F_TSO) != 0;
6664 }
6665 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6666 {
6667 if (data)
6668 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6669 else
6670 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6671
6672 return 0;
6673 }
6674
6675 static const struct ethtool_ops netdev_ethtool_ops = {
6676 .get_settings = s2io_ethtool_gset,
6677 .set_settings = s2io_ethtool_sset,
6678 .get_drvinfo = s2io_ethtool_gdrvinfo,
6679 .get_regs_len = s2io_ethtool_get_regs_len,
6680 .get_regs = s2io_ethtool_gregs,
6681 .get_link = ethtool_op_get_link,
6682 .get_eeprom_len = s2io_get_eeprom_len,
6683 .get_eeprom = s2io_ethtool_geeprom,
6684 .set_eeprom = s2io_ethtool_seeprom,
6685 .get_ringparam = s2io_ethtool_gringparam,
6686 .get_pauseparam = s2io_ethtool_getpause_data,
6687 .set_pauseparam = s2io_ethtool_setpause_data,
6688 .get_rx_csum = s2io_ethtool_get_rx_csum,
6689 .set_rx_csum = s2io_ethtool_set_rx_csum,
6690 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6691 .set_sg = ethtool_op_set_sg,
6692 .get_tso = s2io_ethtool_op_get_tso,
6693 .set_tso = s2io_ethtool_op_set_tso,
6694 .set_ufo = ethtool_op_set_ufo,
6695 .self_test = s2io_ethtool_test,
6696 .get_strings = s2io_ethtool_get_strings,
6697 .phys_id = s2io_ethtool_idnic,
6698 .get_ethtool_stats = s2io_get_ethtool_stats,
6699 .get_sset_count = s2io_get_sset_count,
6700 };
6701
6702 /**
6703 * s2io_ioctl - Entry point for the Ioctl
6704 * @dev : Device pointer.
6705 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6706 * a proprietary structure used to pass information to the driver.
6707 * @cmd : This is used to distinguish between the different commands that
6708 * can be passed to the IOCTL functions.
6709 * Description:
6710 * Currently there are no special functionality supported in IOCTL, hence
6711 * function always return EOPNOTSUPPORTED
6712 */
6713
6714 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6715 {
6716 return -EOPNOTSUPP;
6717 }
6718
6719 /**
6720 * s2io_change_mtu - entry point to change MTU size for the device.
6721 * @dev : device pointer.
6722 * @new_mtu : the new MTU size for the device.
6723 * Description: A driver entry point to change MTU size for the device.
6724 * Before changing the MTU the device must be stopped.
6725 * Return value:
6726 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6727 * file on failure.
6728 */
6729
6730 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6731 {
6732 struct s2io_nic *sp = dev->priv;
6733 int ret = 0;
6734
6735 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6736 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6737 dev->name);
6738 return -EPERM;
6739 }
6740
6741 dev->mtu = new_mtu;
6742 if (netif_running(dev)) {
6743 s2io_stop_all_tx_queue(sp);
6744 s2io_card_down(sp);
6745 ret = s2io_card_up(sp);
6746 if (ret) {
6747 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6748 __FUNCTION__);
6749 return ret;
6750 }
6751 s2io_wake_all_tx_queue(sp);
6752 } else { /* Device is down */
6753 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6754 u64 val64 = new_mtu;
6755
6756 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6757 }
6758
6759 return ret;
6760 }
6761
6762 /**
6763 * s2io_set_link - Set the LInk status
6764 * @data: long pointer to device private structue
6765 * Description: Sets the link status for the adapter
6766 */
6767
6768 static void s2io_set_link(struct work_struct *work)
6769 {
6770 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
6771 struct net_device *dev = nic->dev;
6772 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6773 register u64 val64;
6774 u16 subid;
6775
6776 rtnl_lock();
6777
6778 if (!netif_running(dev))
6779 goto out_unlock;
6780
6781 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6782 /* The card is being reset, no point doing anything */
6783 goto out_unlock;
6784 }
6785
6786 subid = nic->pdev->subsystem_device;
6787 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6788 /*
6789 * Allow a small delay for the NICs self initiated
6790 * cleanup to complete.
6791 */
6792 msleep(100);
6793 }
6794
6795 val64 = readq(&bar0->adapter_status);
6796 if (LINK_IS_UP(val64)) {
6797 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6798 if (verify_xena_quiescence(nic)) {
6799 val64 = readq(&bar0->adapter_control);
6800 val64 |= ADAPTER_CNTL_EN;
6801 writeq(val64, &bar0->adapter_control);
6802 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6803 nic->device_type, subid)) {
6804 val64 = readq(&bar0->gpio_control);
6805 val64 |= GPIO_CTRL_GPIO_0;
6806 writeq(val64, &bar0->gpio_control);
6807 val64 = readq(&bar0->gpio_control);
6808 } else {
6809 val64 |= ADAPTER_LED_ON;
6810 writeq(val64, &bar0->adapter_control);
6811 }
6812 nic->device_enabled_once = TRUE;
6813 } else {
6814 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6815 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6816 s2io_stop_all_tx_queue(nic);
6817 }
6818 }
6819 val64 = readq(&bar0->adapter_control);
6820 val64 |= ADAPTER_LED_ON;
6821 writeq(val64, &bar0->adapter_control);
6822 s2io_link(nic, LINK_UP);
6823 } else {
6824 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6825 subid)) {
6826 val64 = readq(&bar0->gpio_control);
6827 val64 &= ~GPIO_CTRL_GPIO_0;
6828 writeq(val64, &bar0->gpio_control);
6829 val64 = readq(&bar0->gpio_control);
6830 }
6831 /* turn off LED */
6832 val64 = readq(&bar0->adapter_control);
6833 val64 = val64 &(~ADAPTER_LED_ON);
6834 writeq(val64, &bar0->adapter_control);
6835 s2io_link(nic, LINK_DOWN);
6836 }
6837 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6838
6839 out_unlock:
6840 rtnl_unlock();
6841 }
6842
6843 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6844 struct buffAdd *ba,
6845 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6846 u64 *temp2, int size)
6847 {
6848 struct net_device *dev = sp->dev;
6849 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6850
6851 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6852 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6853 /* allocate skb */
6854 if (*skb) {
6855 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6856 /*
6857 * As Rx frame are not going to be processed,
6858 * using same mapped address for the Rxd
6859 * buffer pointer
6860 */
6861 rxdp1->Buffer0_ptr = *temp0;
6862 } else {
6863 *skb = dev_alloc_skb(size);
6864 if (!(*skb)) {
6865 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6866 DBG_PRINT(INFO_DBG, "memory to allocate ");
6867 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6868 sp->mac_control.stats_info->sw_stat. \
6869 mem_alloc_fail_cnt++;
6870 return -ENOMEM ;
6871 }
6872 sp->mac_control.stats_info->sw_stat.mem_allocated
6873 += (*skb)->truesize;
6874 /* storing the mapped addr in a temp variable
6875 * such it will be used for next rxd whose
6876 * Host Control is NULL
6877 */
6878 rxdp1->Buffer0_ptr = *temp0 =
6879 pci_map_single( sp->pdev, (*skb)->data,
6880 size - NET_IP_ALIGN,
6881 PCI_DMA_FROMDEVICE);
6882 if (pci_dma_mapping_error(rxdp1->Buffer0_ptr))
6883 goto memalloc_failed;
6884 rxdp->Host_Control = (unsigned long) (*skb);
6885 }
6886 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6887 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6888 /* Two buffer Mode */
6889 if (*skb) {
6890 rxdp3->Buffer2_ptr = *temp2;
6891 rxdp3->Buffer0_ptr = *temp0;
6892 rxdp3->Buffer1_ptr = *temp1;
6893 } else {
6894 *skb = dev_alloc_skb(size);
6895 if (!(*skb)) {
6896 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6897 DBG_PRINT(INFO_DBG, "memory to allocate ");
6898 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6899 sp->mac_control.stats_info->sw_stat. \
6900 mem_alloc_fail_cnt++;
6901 return -ENOMEM;
6902 }
6903 sp->mac_control.stats_info->sw_stat.mem_allocated
6904 += (*skb)->truesize;
6905 rxdp3->Buffer2_ptr = *temp2 =
6906 pci_map_single(sp->pdev, (*skb)->data,
6907 dev->mtu + 4,
6908 PCI_DMA_FROMDEVICE);
6909 if (pci_dma_mapping_error(rxdp3->Buffer2_ptr))
6910 goto memalloc_failed;
6911 rxdp3->Buffer0_ptr = *temp0 =
6912 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6913 PCI_DMA_FROMDEVICE);
6914 if (pci_dma_mapping_error(rxdp3->Buffer0_ptr)) {
6915 pci_unmap_single (sp->pdev,
6916 (dma_addr_t)rxdp3->Buffer2_ptr,
6917 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6918 goto memalloc_failed;
6919 }
6920 rxdp->Host_Control = (unsigned long) (*skb);
6921
6922 /* Buffer-1 will be dummy buffer not used */
6923 rxdp3->Buffer1_ptr = *temp1 =
6924 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6925 PCI_DMA_FROMDEVICE);
6926 if (pci_dma_mapping_error(rxdp3->Buffer1_ptr)) {
6927 pci_unmap_single (sp->pdev,
6928 (dma_addr_t)rxdp3->Buffer0_ptr,
6929 BUF0_LEN, PCI_DMA_FROMDEVICE);
6930 pci_unmap_single (sp->pdev,
6931 (dma_addr_t)rxdp3->Buffer2_ptr,
6932 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6933 goto memalloc_failed;
6934 }
6935 }
6936 }
6937 return 0;
6938 memalloc_failed:
6939 stats->pci_map_fail_cnt++;
6940 stats->mem_freed += (*skb)->truesize;
6941 dev_kfree_skb(*skb);
6942 return -ENOMEM;
6943 }
6944
6945 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6946 int size)
6947 {
6948 struct net_device *dev = sp->dev;
6949 if (sp->rxd_mode == RXD_MODE_1) {
6950 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6951 } else if (sp->rxd_mode == RXD_MODE_3B) {
6952 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6953 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6954 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6955 }
6956 }
6957
6958 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6959 {
6960 int i, j, k, blk_cnt = 0, size;
6961 struct mac_info * mac_control = &sp->mac_control;
6962 struct config_param *config = &sp->config;
6963 struct net_device *dev = sp->dev;
6964 struct RxD_t *rxdp = NULL;
6965 struct sk_buff *skb = NULL;
6966 struct buffAdd *ba = NULL;
6967 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6968
6969 /* Calculate the size based on ring mode */
6970 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6971 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6972 if (sp->rxd_mode == RXD_MODE_1)
6973 size += NET_IP_ALIGN;
6974 else if (sp->rxd_mode == RXD_MODE_3B)
6975 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6976
6977 for (i = 0; i < config->rx_ring_num; i++) {
6978 blk_cnt = config->rx_cfg[i].num_rxd /
6979 (rxd_count[sp->rxd_mode] +1);
6980
6981 for (j = 0; j < blk_cnt; j++) {
6982 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6983 rxdp = mac_control->rings[i].
6984 rx_blocks[j].rxds[k].virt_addr;
6985 if(sp->rxd_mode == RXD_MODE_3B)
6986 ba = &mac_control->rings[i].ba[j][k];
6987 if (set_rxd_buffer_pointer(sp, rxdp, ba,
6988 &skb,(u64 *)&temp0_64,
6989 (u64 *)&temp1_64,
6990 (u64 *)&temp2_64,
6991 size) == ENOMEM) {
6992 return 0;
6993 }
6994
6995 set_rxd_buffer_size(sp, rxdp, size);
6996 wmb();
6997 /* flip the Ownership bit to Hardware */
6998 rxdp->Control_1 |= RXD_OWN_XENA;
6999 }
7000 }
7001 }
7002 return 0;
7003
7004 }
7005
7006 static int s2io_add_isr(struct s2io_nic * sp)
7007 {
7008 int ret = 0;
7009 struct net_device *dev = sp->dev;
7010 int err = 0;
7011
7012 if (sp->config.intr_type == MSI_X)
7013 ret = s2io_enable_msi_x(sp);
7014 if (ret) {
7015 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7016 sp->config.intr_type = INTA;
7017 }
7018
7019 /* Store the values of the MSIX table in the struct s2io_nic structure */
7020 store_xmsi_data(sp);
7021
7022 /* After proper initialization of H/W, register ISR */
7023 if (sp->config.intr_type == MSI_X) {
7024 int i, msix_rx_cnt = 0;
7025
7026 for (i = 0; i < sp->num_entries; i++) {
7027 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7028 if (sp->s2io_entries[i].type ==
7029 MSIX_RING_TYPE) {
7030 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7031 dev->name, i);
7032 err = request_irq(sp->entries[i].vector,
7033 s2io_msix_ring_handle, 0,
7034 sp->desc[i],
7035 sp->s2io_entries[i].arg);
7036 } else if (sp->s2io_entries[i].type ==
7037 MSIX_ALARM_TYPE) {
7038 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7039 dev->name, i);
7040 err = request_irq(sp->entries[i].vector,
7041 s2io_msix_fifo_handle, 0,
7042 sp->desc[i],
7043 sp->s2io_entries[i].arg);
7044
7045 }
7046 /* if either data or addr is zero print it. */
7047 if (!(sp->msix_info[i].addr &&
7048 sp->msix_info[i].data)) {
7049 DBG_PRINT(ERR_DBG,
7050 "%s @Addr:0x%llx Data:0x%llx\n",
7051 sp->desc[i],
7052 (unsigned long long)
7053 sp->msix_info[i].addr,
7054 (unsigned long long)
7055 ntohl(sp->msix_info[i].data));
7056 } else
7057 msix_rx_cnt++;
7058 if (err) {
7059 remove_msix_isr(sp);
7060
7061 DBG_PRINT(ERR_DBG,
7062 "%s:MSI-X-%d registration "
7063 "failed\n", dev->name, i);
7064
7065 DBG_PRINT(ERR_DBG,
7066 "%s: Defaulting to INTA\n",
7067 dev->name);
7068 sp->config.intr_type = INTA;
7069 break;
7070 }
7071 sp->s2io_entries[i].in_use =
7072 MSIX_REGISTERED_SUCCESS;
7073 }
7074 }
7075 if (!err) {
7076 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
7077 --msix_rx_cnt);
7078 DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
7079 " through alarm vector\n");
7080 }
7081 }
7082 if (sp->config.intr_type == INTA) {
7083 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
7084 sp->name, dev);
7085 if (err) {
7086 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7087 dev->name);
7088 return -1;
7089 }
7090 }
7091 return 0;
7092 }
7093 static void s2io_rem_isr(struct s2io_nic * sp)
7094 {
7095 if (sp->config.intr_type == MSI_X)
7096 remove_msix_isr(sp);
7097 else
7098 remove_inta_isr(sp);
7099 }
7100
7101 static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
7102 {
7103 int cnt = 0;
7104 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7105 register u64 val64 = 0;
7106 struct config_param *config;
7107 config = &sp->config;
7108
7109 if (!is_s2io_card_up(sp))
7110 return;
7111
7112 del_timer_sync(&sp->alarm_timer);
7113 /* If s2io_set_link task is executing, wait till it completes. */
7114 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
7115 msleep(50);
7116 }
7117 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7118
7119 /* Disable napi */
7120 if (sp->config.napi) {
7121 int off = 0;
7122 if (config->intr_type == MSI_X) {
7123 for (; off < sp->config.rx_ring_num; off++)
7124 napi_disable(&sp->mac_control.rings[off].napi);
7125 }
7126 else
7127 napi_disable(&sp->napi);
7128 }
7129
7130 /* disable Tx and Rx traffic on the NIC */
7131 if (do_io)
7132 stop_nic(sp);
7133
7134 s2io_rem_isr(sp);
7135
7136 /* Check if the device is Quiescent and then Reset the NIC */
7137 while(do_io) {
7138 /* As per the HW requirement we need to replenish the
7139 * receive buffer to avoid the ring bump. Since there is
7140 * no intention of processing the Rx frame at this pointwe are
7141 * just settting the ownership bit of rxd in Each Rx
7142 * ring to HW and set the appropriate buffer size
7143 * based on the ring mode
7144 */
7145 rxd_owner_bit_reset(sp);
7146
7147 val64 = readq(&bar0->adapter_status);
7148 if (verify_xena_quiescence(sp)) {
7149 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
7150 break;
7151 }
7152
7153 msleep(50);
7154 cnt++;
7155 if (cnt == 10) {
7156 DBG_PRINT(ERR_DBG,
7157 "s2io_close:Device not Quiescent ");
7158 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7159 (unsigned long long) val64);
7160 break;
7161 }
7162 }
7163 if (do_io)
7164 s2io_reset(sp);
7165
7166 /* Free all Tx buffers */
7167 free_tx_buffers(sp);
7168
7169 /* Free all Rx buffers */
7170 free_rx_buffers(sp);
7171
7172 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7173 }
7174
7175 static void s2io_card_down(struct s2io_nic * sp)
7176 {
7177 do_s2io_card_down(sp, 1);
7178 }
7179
7180 static int s2io_card_up(struct s2io_nic * sp)
7181 {
7182 int i, ret = 0;
7183 struct mac_info *mac_control;
7184 struct config_param *config;
7185 struct net_device *dev = (struct net_device *) sp->dev;
7186 u16 interruptible;
7187
7188 /* Initialize the H/W I/O registers */
7189 ret = init_nic(sp);
7190 if (ret != 0) {
7191 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7192 dev->name);
7193 if (ret != -EIO)
7194 s2io_reset(sp);
7195 return ret;
7196 }
7197
7198 /*
7199 * Initializing the Rx buffers. For now we are considering only 1
7200 * Rx ring and initializing buffers into 30 Rx blocks
7201 */
7202 mac_control = &sp->mac_control;
7203 config = &sp->config;
7204
7205 for (i = 0; i < config->rx_ring_num; i++) {
7206 mac_control->rings[i].mtu = dev->mtu;
7207 ret = fill_rx_buffers(&mac_control->rings[i]);
7208 if (ret) {
7209 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7210 dev->name);
7211 s2io_reset(sp);
7212 free_rx_buffers(sp);
7213 return -ENOMEM;
7214 }
7215 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7216 mac_control->rings[i].rx_bufs_left);
7217 }
7218
7219 /* Initialise napi */
7220 if (config->napi) {
7221 int i;
7222 if (config->intr_type == MSI_X) {
7223 for (i = 0; i < sp->config.rx_ring_num; i++)
7224 napi_enable(&sp->mac_control.rings[i].napi);
7225 } else {
7226 napi_enable(&sp->napi);
7227 }
7228 }
7229
7230 /* Maintain the state prior to the open */
7231 if (sp->promisc_flg)
7232 sp->promisc_flg = 0;
7233 if (sp->m_cast_flg) {
7234 sp->m_cast_flg = 0;
7235 sp->all_multi_pos= 0;
7236 }
7237
7238 /* Setting its receive mode */
7239 s2io_set_multicast(dev);
7240
7241 if (sp->lro) {
7242 /* Initialize max aggregatable pkts per session based on MTU */
7243 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7244 /* Check if we can use(if specified) user provided value */
7245 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7246 sp->lro_max_aggr_per_sess = lro_max_pkts;
7247 }
7248
7249 /* Enable Rx Traffic and interrupts on the NIC */
7250 if (start_nic(sp)) {
7251 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7252 s2io_reset(sp);
7253 free_rx_buffers(sp);
7254 return -ENODEV;
7255 }
7256
7257 /* Add interrupt service routine */
7258 if (s2io_add_isr(sp) != 0) {
7259 if (sp->config.intr_type == MSI_X)
7260 s2io_rem_isr(sp);
7261 s2io_reset(sp);
7262 free_rx_buffers(sp);
7263 return -ENODEV;
7264 }
7265
7266 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7267
7268 /* Enable select interrupts */
7269 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7270 if (sp->config.intr_type != INTA)
7271 en_dis_able_nic_intrs(sp, TX_TRAFFIC_INTR, ENABLE_INTRS);
7272 else {
7273 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7274 interruptible |= TX_PIC_INTR;
7275 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7276 }
7277
7278 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7279 return 0;
7280 }
7281
7282 /**
7283 * s2io_restart_nic - Resets the NIC.
7284 * @data : long pointer to the device private structure
7285 * Description:
7286 * This function is scheduled to be run by the s2io_tx_watchdog
7287 * function after 0.5 secs to reset the NIC. The idea is to reduce
7288 * the run time of the watch dog routine which is run holding a
7289 * spin lock.
7290 */
7291
7292 static void s2io_restart_nic(struct work_struct *work)
7293 {
7294 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7295 struct net_device *dev = sp->dev;
7296
7297 rtnl_lock();
7298
7299 if (!netif_running(dev))
7300 goto out_unlock;
7301
7302 s2io_card_down(sp);
7303 if (s2io_card_up(sp)) {
7304 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7305 dev->name);
7306 }
7307 s2io_wake_all_tx_queue(sp);
7308 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7309 dev->name);
7310 out_unlock:
7311 rtnl_unlock();
7312 }
7313
7314 /**
7315 * s2io_tx_watchdog - Watchdog for transmit side.
7316 * @dev : Pointer to net device structure
7317 * Description:
7318 * This function is triggered if the Tx Queue is stopped
7319 * for a pre-defined amount of time when the Interface is still up.
7320 * If the Interface is jammed in such a situation, the hardware is
7321 * reset (by s2io_close) and restarted again (by s2io_open) to
7322 * overcome any problem that might have been caused in the hardware.
7323 * Return value:
7324 * void
7325 */
7326
7327 static void s2io_tx_watchdog(struct net_device *dev)
7328 {
7329 struct s2io_nic *sp = dev->priv;
7330
7331 if (netif_carrier_ok(dev)) {
7332 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
7333 schedule_work(&sp->rst_timer_task);
7334 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
7335 }
7336 }
7337
7338 /**
7339 * rx_osm_handler - To perform some OS related operations on SKB.
7340 * @sp: private member of the device structure,pointer to s2io_nic structure.
7341 * @skb : the socket buffer pointer.
7342 * @len : length of the packet
7343 * @cksum : FCS checksum of the frame.
7344 * @ring_no : the ring from which this RxD was extracted.
7345 * Description:
7346 * This function is called by the Rx interrupt serivce routine to perform
7347 * some OS related operations on the SKB before passing it to the upper
7348 * layers. It mainly checks if the checksum is OK, if so adds it to the
7349 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7350 * to the upper layer. If the checksum is wrong, it increments the Rx
7351 * packet error count, frees the SKB and returns error.
7352 * Return value:
7353 * SUCCESS on success and -1 on failure.
7354 */
7355 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7356 {
7357 struct s2io_nic *sp = ring_data->nic;
7358 struct net_device *dev = (struct net_device *) ring_data->dev;
7359 struct sk_buff *skb = (struct sk_buff *)
7360 ((unsigned long) rxdp->Host_Control);
7361 int ring_no = ring_data->ring_no;
7362 u16 l3_csum, l4_csum;
7363 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7364 struct lro *lro;
7365 u8 err_mask;
7366
7367 skb->dev = dev;
7368
7369 if (err) {
7370 /* Check for parity error */
7371 if (err & 0x1) {
7372 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7373 }
7374 err_mask = err >> 48;
7375 switch(err_mask) {
7376 case 1:
7377 sp->mac_control.stats_info->sw_stat.
7378 rx_parity_err_cnt++;
7379 break;
7380
7381 case 2:
7382 sp->mac_control.stats_info->sw_stat.
7383 rx_abort_cnt++;
7384 break;
7385
7386 case 3:
7387 sp->mac_control.stats_info->sw_stat.
7388 rx_parity_abort_cnt++;
7389 break;
7390
7391 case 4:
7392 sp->mac_control.stats_info->sw_stat.
7393 rx_rda_fail_cnt++;
7394 break;
7395
7396 case 5:
7397 sp->mac_control.stats_info->sw_stat.
7398 rx_unkn_prot_cnt++;
7399 break;
7400
7401 case 6:
7402 sp->mac_control.stats_info->sw_stat.
7403 rx_fcs_err_cnt++;
7404 break;
7405
7406 case 7:
7407 sp->mac_control.stats_info->sw_stat.
7408 rx_buf_size_err_cnt++;
7409 break;
7410
7411 case 8:
7412 sp->mac_control.stats_info->sw_stat.
7413 rx_rxd_corrupt_cnt++;
7414 break;
7415
7416 case 15:
7417 sp->mac_control.stats_info->sw_stat.
7418 rx_unkn_err_cnt++;
7419 break;
7420 }
7421 /*
7422 * Drop the packet if bad transfer code. Exception being
7423 * 0x5, which could be due to unsupported IPv6 extension header.
7424 * In this case, we let stack handle the packet.
7425 * Note that in this case, since checksum will be incorrect,
7426 * stack will validate the same.
7427 */
7428 if (err_mask != 0x5) {
7429 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7430 dev->name, err_mask);
7431 sp->stats.rx_crc_errors++;
7432 sp->mac_control.stats_info->sw_stat.mem_freed
7433 += skb->truesize;
7434 dev_kfree_skb(skb);
7435 ring_data->rx_bufs_left -= 1;
7436 rxdp->Host_Control = 0;
7437 return 0;
7438 }
7439 }
7440
7441 /* Updating statistics */
7442 ring_data->rx_packets++;
7443 rxdp->Host_Control = 0;
7444 if (sp->rxd_mode == RXD_MODE_1) {
7445 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7446
7447 ring_data->rx_bytes += len;
7448 skb_put(skb, len);
7449
7450 } else if (sp->rxd_mode == RXD_MODE_3B) {
7451 int get_block = ring_data->rx_curr_get_info.block_index;
7452 int get_off = ring_data->rx_curr_get_info.offset;
7453 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7454 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7455 unsigned char *buff = skb_push(skb, buf0_len);
7456
7457 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7458 ring_data->rx_bytes += buf0_len + buf2_len;
7459 memcpy(buff, ba->ba_0, buf0_len);
7460 skb_put(skb, buf2_len);
7461 }
7462
7463 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!ring_data->lro) ||
7464 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7465 (sp->rx_csum)) {
7466 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7467 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7468 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7469 /*
7470 * NIC verifies if the Checksum of the received
7471 * frame is Ok or not and accordingly returns
7472 * a flag in the RxD.
7473 */
7474 skb->ip_summed = CHECKSUM_UNNECESSARY;
7475 if (ring_data->lro) {
7476 u32 tcp_len;
7477 u8 *tcp;
7478 int ret = 0;
7479
7480 ret = s2io_club_tcp_session(ring_data,
7481 skb->data, &tcp, &tcp_len, &lro,
7482 rxdp, sp);
7483 switch (ret) {
7484 case 3: /* Begin anew */
7485 lro->parent = skb;
7486 goto aggregate;
7487 case 1: /* Aggregate */
7488 {
7489 lro_append_pkt(sp, lro,
7490 skb, tcp_len);
7491 goto aggregate;
7492 }
7493 case 4: /* Flush session */
7494 {
7495 lro_append_pkt(sp, lro,
7496 skb, tcp_len);
7497 queue_rx_frame(lro->parent,
7498 lro->vlan_tag);
7499 clear_lro_session(lro);
7500 sp->mac_control.stats_info->
7501 sw_stat.flush_max_pkts++;
7502 goto aggregate;
7503 }
7504 case 2: /* Flush both */
7505 lro->parent->data_len =
7506 lro->frags_len;
7507 sp->mac_control.stats_info->
7508 sw_stat.sending_both++;
7509 queue_rx_frame(lro->parent,
7510 lro->vlan_tag);
7511 clear_lro_session(lro);
7512 goto send_up;
7513 case 0: /* sessions exceeded */
7514 case -1: /* non-TCP or not
7515 * L2 aggregatable
7516 */
7517 case 5: /*
7518 * First pkt in session not
7519 * L3/L4 aggregatable
7520 */
7521 break;
7522 default:
7523 DBG_PRINT(ERR_DBG,
7524 "%s: Samadhana!!\n",
7525 __FUNCTION__);
7526 BUG();
7527 }
7528 }
7529 } else {
7530 /*
7531 * Packet with erroneous checksum, let the
7532 * upper layers deal with it.
7533 */
7534 skb->ip_summed = CHECKSUM_NONE;
7535 }
7536 } else
7537 skb->ip_summed = CHECKSUM_NONE;
7538
7539 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7540 send_up:
7541 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7542 dev->last_rx = jiffies;
7543 aggregate:
7544 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7545 return SUCCESS;
7546 }
7547
7548 /**
7549 * s2io_link - stops/starts the Tx queue.
7550 * @sp : private member of the device structure, which is a pointer to the
7551 * s2io_nic structure.
7552 * @link : inidicates whether link is UP/DOWN.
7553 * Description:
7554 * This function stops/starts the Tx queue depending on whether the link
7555 * status of the NIC is is down or up. This is called by the Alarm
7556 * interrupt handler whenever a link change interrupt comes up.
7557 * Return value:
7558 * void.
7559 */
7560
7561 static void s2io_link(struct s2io_nic * sp, int link)
7562 {
7563 struct net_device *dev = (struct net_device *) sp->dev;
7564
7565 if (link != sp->last_link_state) {
7566 init_tti(sp, link);
7567 if (link == LINK_DOWN) {
7568 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7569 s2io_stop_all_tx_queue(sp);
7570 netif_carrier_off(dev);
7571 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
7572 sp->mac_control.stats_info->sw_stat.link_up_time =
7573 jiffies - sp->start_time;
7574 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
7575 } else {
7576 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7577 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7578 sp->mac_control.stats_info->sw_stat.link_down_time =
7579 jiffies - sp->start_time;
7580 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
7581 netif_carrier_on(dev);
7582 s2io_wake_all_tx_queue(sp);
7583 }
7584 }
7585 sp->last_link_state = link;
7586 sp->start_time = jiffies;
7587 }
7588
7589 /**
7590 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7591 * @sp : private member of the device structure, which is a pointer to the
7592 * s2io_nic structure.
7593 * Description:
7594 * This function initializes a few of the PCI and PCI-X configuration registers
7595 * with recommended values.
7596 * Return value:
7597 * void
7598 */
7599
7600 static void s2io_init_pci(struct s2io_nic * sp)
7601 {
7602 u16 pci_cmd = 0, pcix_cmd = 0;
7603
7604 /* Enable Data Parity Error Recovery in PCI-X command register. */
7605 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7606 &(pcix_cmd));
7607 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7608 (pcix_cmd | 1));
7609 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7610 &(pcix_cmd));
7611
7612 /* Set the PErr Response bit in PCI command register. */
7613 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7614 pci_write_config_word(sp->pdev, PCI_COMMAND,
7615 (pci_cmd | PCI_COMMAND_PARITY));
7616 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7617 }
7618
7619 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7620 u8 *dev_multiq)
7621 {
7622 if ((tx_fifo_num > MAX_TX_FIFOS) ||
7623 (tx_fifo_num < 1)) {
7624 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7625 "(%d) not supported\n", tx_fifo_num);
7626
7627 if (tx_fifo_num < 1)
7628 tx_fifo_num = 1;
7629 else
7630 tx_fifo_num = MAX_TX_FIFOS;
7631
7632 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7633 DBG_PRINT(ERR_DBG, "tx fifos\n");
7634 }
7635
7636 #ifndef CONFIG_NETDEVICES_MULTIQUEUE
7637 if (multiq) {
7638 DBG_PRINT(ERR_DBG, "s2io: Multiqueue support not enabled\n");
7639 multiq = 0;
7640 }
7641 #endif
7642 if (multiq)
7643 *dev_multiq = multiq;
7644
7645 if (tx_steering_type && (1 == tx_fifo_num)) {
7646 if (tx_steering_type != TX_DEFAULT_STEERING)
7647 DBG_PRINT(ERR_DBG,
7648 "s2io: Tx steering is not supported with "
7649 "one fifo. Disabling Tx steering.\n");
7650 tx_steering_type = NO_STEERING;
7651 }
7652
7653 if ((tx_steering_type < NO_STEERING) ||
7654 (tx_steering_type > TX_DEFAULT_STEERING)) {
7655 DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
7656 "supported\n");
7657 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7658 tx_steering_type = NO_STEERING;
7659 }
7660
7661 if (rx_ring_num > MAX_RX_RINGS) {
7662 DBG_PRINT(ERR_DBG, "s2io: Requested number of rx rings not "
7663 "supported\n");
7664 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
7665 MAX_RX_RINGS);
7666 rx_ring_num = MAX_RX_RINGS;
7667 }
7668
7669 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7670 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7671 "Defaulting to INTA\n");
7672 *dev_intr_type = INTA;
7673 }
7674
7675 if ((*dev_intr_type == MSI_X) &&
7676 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7677 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7678 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
7679 "Defaulting to INTA\n");
7680 *dev_intr_type = INTA;
7681 }
7682
7683 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7684 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7685 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7686 rx_ring_mode = 1;
7687 }
7688 return SUCCESS;
7689 }
7690
7691 /**
7692 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7693 * or Traffic class respectively.
7694 * @nic: device private variable
7695 * Description: The function configures the receive steering to
7696 * desired receive ring.
7697 * Return Value: SUCCESS on success and
7698 * '-1' on failure (endian settings incorrect).
7699 */
7700 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7701 {
7702 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7703 register u64 val64 = 0;
7704
7705 if (ds_codepoint > 63)
7706 return FAILURE;
7707
7708 val64 = RTS_DS_MEM_DATA(ring);
7709 writeq(val64, &bar0->rts_ds_mem_data);
7710
7711 val64 = RTS_DS_MEM_CTRL_WE |
7712 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7713 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7714
7715 writeq(val64, &bar0->rts_ds_mem_ctrl);
7716
7717 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7718 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7719 S2IO_BIT_RESET);
7720 }
7721
7722 /**
7723 * s2io_init_nic - Initialization of the adapter .
7724 * @pdev : structure containing the PCI related information of the device.
7725 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7726 * Description:
7727 * The function initializes an adapter identified by the pci_dec structure.
7728 * All OS related initialization including memory and device structure and
7729 * initlaization of the device private variable is done. Also the swapper
7730 * control register is initialized to enable read and write into the I/O
7731 * registers of the device.
7732 * Return value:
7733 * returns 0 on success and negative on failure.
7734 */
7735
7736 static int __devinit
7737 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7738 {
7739 struct s2io_nic *sp;
7740 struct net_device *dev;
7741 int i, j, ret;
7742 int dma_flag = FALSE;
7743 u32 mac_up, mac_down;
7744 u64 val64 = 0, tmp64 = 0;
7745 struct XENA_dev_config __iomem *bar0 = NULL;
7746 u16 subid;
7747 struct mac_info *mac_control;
7748 struct config_param *config;
7749 int mode;
7750 u8 dev_intr_type = intr_type;
7751 u8 dev_multiq = 0;
7752 DECLARE_MAC_BUF(mac);
7753
7754 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7755 if (ret)
7756 return ret;
7757
7758 if ((ret = pci_enable_device(pdev))) {
7759 DBG_PRINT(ERR_DBG,
7760 "s2io_init_nic: pci_enable_device failed\n");
7761 return ret;
7762 }
7763
7764 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
7765 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7766 dma_flag = TRUE;
7767 if (pci_set_consistent_dma_mask
7768 (pdev, DMA_64BIT_MASK)) {
7769 DBG_PRINT(ERR_DBG,
7770 "Unable to obtain 64bit DMA for \
7771 consistent allocations\n");
7772 pci_disable_device(pdev);
7773 return -ENOMEM;
7774 }
7775 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
7776 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7777 } else {
7778 pci_disable_device(pdev);
7779 return -ENOMEM;
7780 }
7781 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7782 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7783 pci_disable_device(pdev);
7784 return -ENODEV;
7785 }
7786 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
7787 if (dev_multiq)
7788 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7789 else
7790 #endif
7791 dev = alloc_etherdev(sizeof(struct s2io_nic));
7792 if (dev == NULL) {
7793 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7794 pci_disable_device(pdev);
7795 pci_release_regions(pdev);
7796 return -ENODEV;
7797 }
7798
7799 pci_set_master(pdev);
7800 pci_set_drvdata(pdev, dev);
7801 SET_NETDEV_DEV(dev, &pdev->dev);
7802
7803 /* Private member variable initialized to s2io NIC structure */
7804 sp = dev->priv;
7805 memset(sp, 0, sizeof(struct s2io_nic));
7806 sp->dev = dev;
7807 sp->pdev = pdev;
7808 sp->high_dma_flag = dma_flag;
7809 sp->device_enabled_once = FALSE;
7810 if (rx_ring_mode == 1)
7811 sp->rxd_mode = RXD_MODE_1;
7812 if (rx_ring_mode == 2)
7813 sp->rxd_mode = RXD_MODE_3B;
7814
7815 sp->config.intr_type = dev_intr_type;
7816
7817 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7818 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7819 sp->device_type = XFRAME_II_DEVICE;
7820 else
7821 sp->device_type = XFRAME_I_DEVICE;
7822
7823 sp->lro = lro_enable;
7824
7825 /* Initialize some PCI/PCI-X fields of the NIC. */
7826 s2io_init_pci(sp);
7827
7828 /*
7829 * Setting the device configuration parameters.
7830 * Most of these parameters can be specified by the user during
7831 * module insertion as they are module loadable parameters. If
7832 * these parameters are not not specified during load time, they
7833 * are initialized with default values.
7834 */
7835 mac_control = &sp->mac_control;
7836 config = &sp->config;
7837
7838 config->napi = napi;
7839 config->tx_steering_type = tx_steering_type;
7840
7841 /* Tx side parameters. */
7842 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7843 config->tx_fifo_num = MAX_TX_FIFOS;
7844 else
7845 config->tx_fifo_num = tx_fifo_num;
7846
7847 /* Initialize the fifos used for tx steering */
7848 if (config->tx_fifo_num < 5) {
7849 if (config->tx_fifo_num == 1)
7850 sp->total_tcp_fifos = 1;
7851 else
7852 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7853 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7854 sp->total_udp_fifos = 1;
7855 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7856 } else {
7857 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7858 FIFO_OTHER_MAX_NUM);
7859 sp->udp_fifo_idx = sp->total_tcp_fifos;
7860 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7861 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7862 }
7863
7864 config->multiq = dev_multiq;
7865 for (i = 0; i < config->tx_fifo_num; i++) {
7866 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7867 config->tx_cfg[i].fifo_priority = i;
7868 }
7869
7870 /* mapping the QoS priority to the configured fifos */
7871 for (i = 0; i < MAX_TX_FIFOS; i++)
7872 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7873
7874 /* map the hashing selector table to the configured fifos */
7875 for (i = 0; i < config->tx_fifo_num; i++)
7876 sp->fifo_selector[i] = fifo_selector[i];
7877
7878
7879 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7880 for (i = 0; i < config->tx_fifo_num; i++) {
7881 config->tx_cfg[i].f_no_snoop =
7882 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7883 if (config->tx_cfg[i].fifo_len < 65) {
7884 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7885 break;
7886 }
7887 }
7888 /* + 2 because one Txd for skb->data and one Txd for UFO */
7889 config->max_txds = MAX_SKB_FRAGS + 2;
7890
7891 /* Rx side parameters. */
7892 config->rx_ring_num = rx_ring_num;
7893 for (i = 0; i < config->rx_ring_num; i++) {
7894 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
7895 (rxd_count[sp->rxd_mode] + 1);
7896 config->rx_cfg[i].ring_priority = i;
7897 mac_control->rings[i].rx_bufs_left = 0;
7898 mac_control->rings[i].rxd_mode = sp->rxd_mode;
7899 mac_control->rings[i].rxd_count = rxd_count[sp->rxd_mode];
7900 mac_control->rings[i].pdev = sp->pdev;
7901 mac_control->rings[i].dev = sp->dev;
7902 }
7903
7904 for (i = 0; i < rx_ring_num; i++) {
7905 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7906 config->rx_cfg[i].f_no_snoop =
7907 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7908 }
7909
7910 /* Setting Mac Control parameters */
7911 mac_control->rmac_pause_time = rmac_pause_time;
7912 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7913 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7914
7915
7916 /* initialize the shared memory used by the NIC and the host */
7917 if (init_shared_mem(sp)) {
7918 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
7919 dev->name);
7920 ret = -ENOMEM;
7921 goto mem_alloc_failed;
7922 }
7923
7924 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7925 pci_resource_len(pdev, 0));
7926 if (!sp->bar0) {
7927 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7928 dev->name);
7929 ret = -ENOMEM;
7930 goto bar0_remap_failed;
7931 }
7932
7933 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7934 pci_resource_len(pdev, 2));
7935 if (!sp->bar1) {
7936 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7937 dev->name);
7938 ret = -ENOMEM;
7939 goto bar1_remap_failed;
7940 }
7941
7942 dev->irq = pdev->irq;
7943 dev->base_addr = (unsigned long) sp->bar0;
7944
7945 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7946 for (j = 0; j < MAX_TX_FIFOS; j++) {
7947 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
7948 (sp->bar1 + (j * 0x00020000));
7949 }
7950
7951 /* Driver entry points */
7952 dev->open = &s2io_open;
7953 dev->stop = &s2io_close;
7954 dev->hard_start_xmit = &s2io_xmit;
7955 dev->get_stats = &s2io_get_stats;
7956 dev->set_multicast_list = &s2io_set_multicast;
7957 dev->do_ioctl = &s2io_ioctl;
7958 dev->set_mac_address = &s2io_set_mac_addr;
7959 dev->change_mtu = &s2io_change_mtu;
7960 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7961 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7962 dev->vlan_rx_register = s2io_vlan_rx_register;
7963 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
7964
7965 /*
7966 * will use eth_mac_addr() for dev->set_mac_address
7967 * mac address will be set every time dev->open() is called
7968 */
7969 #ifdef CONFIG_NET_POLL_CONTROLLER
7970 dev->poll_controller = s2io_netpoll;
7971 #endif
7972
7973 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7974 if (sp->high_dma_flag == TRUE)
7975 dev->features |= NETIF_F_HIGHDMA;
7976 dev->features |= NETIF_F_TSO;
7977 dev->features |= NETIF_F_TSO6;
7978 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
7979 dev->features |= NETIF_F_UFO;
7980 dev->features |= NETIF_F_HW_CSUM;
7981 }
7982 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
7983 if (config->multiq)
7984 dev->features |= NETIF_F_MULTI_QUEUE;
7985 #endif
7986 dev->tx_timeout = &s2io_tx_watchdog;
7987 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7988 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7989 INIT_WORK(&sp->set_link_task, s2io_set_link);
7990
7991 pci_save_state(sp->pdev);
7992
7993 /* Setting swapper control on the NIC, for proper reset operation */
7994 if (s2io_set_swapper(sp)) {
7995 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7996 dev->name);
7997 ret = -EAGAIN;
7998 goto set_swap_failed;
7999 }
8000
8001 /* Verify if the Herc works on the slot its placed into */
8002 if (sp->device_type & XFRAME_II_DEVICE) {
8003 mode = s2io_verify_pci_mode(sp);
8004 if (mode < 0) {
8005 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
8006 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8007 ret = -EBADSLT;
8008 goto set_swap_failed;
8009 }
8010 }
8011
8012 if (sp->config.intr_type == MSI_X) {
8013 sp->num_entries = config->rx_ring_num + 1;
8014 ret = s2io_enable_msi_x(sp);
8015
8016 if (!ret) {
8017 ret = s2io_test_msi(sp);
8018 /* rollback MSI-X, will re-enable during add_isr() */
8019 remove_msix_isr(sp);
8020 }
8021 if (ret) {
8022
8023 DBG_PRINT(ERR_DBG,
8024 "%s: MSI-X requested but failed to enable\n",
8025 dev->name);
8026 sp->config.intr_type = INTA;
8027 }
8028 }
8029
8030 if (config->intr_type == MSI_X) {
8031 for (i = 0; i < config->rx_ring_num ; i++)
8032 netif_napi_add(dev, &mac_control->rings[i].napi,
8033 s2io_poll_msix, 64);
8034 } else {
8035 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8036 }
8037
8038 /* Not needed for Herc */
8039 if (sp->device_type & XFRAME_I_DEVICE) {
8040 /*
8041 * Fix for all "FFs" MAC address problems observed on
8042 * Alpha platforms
8043 */
8044 fix_mac_address(sp);
8045 s2io_reset(sp);
8046 }
8047
8048 /*
8049 * MAC address initialization.
8050 * For now only one mac address will be read and used.
8051 */
8052 bar0 = sp->bar0;
8053 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8054 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8055 writeq(val64, &bar0->rmac_addr_cmd_mem);
8056 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8057 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
8058 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8059 mac_down = (u32) tmp64;
8060 mac_up = (u32) (tmp64 >> 32);
8061
8062 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8063 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8064 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8065 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8066 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8067 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8068
8069 /* Set the factory defined MAC address initially */
8070 dev->addr_len = ETH_ALEN;
8071 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8072 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8073
8074 /* initialize number of multicast & unicast MAC entries variables */
8075 if (sp->device_type == XFRAME_I_DEVICE) {
8076 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8077 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8078 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8079 } else if (sp->device_type == XFRAME_II_DEVICE) {
8080 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8081 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8082 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8083 }
8084
8085 /* store mac addresses from CAM to s2io_nic structure */
8086 do_s2io_store_unicast_mc(sp);
8087
8088 /* Configure MSIX vector for number of rings configured plus one */
8089 if ((sp->device_type == XFRAME_II_DEVICE) &&
8090 (config->intr_type == MSI_X))
8091 sp->num_entries = config->rx_ring_num + 1;
8092
8093 /* Store the values of the MSIX table in the s2io_nic structure */
8094 store_xmsi_data(sp);
8095 /* reset Nic and bring it to known state */
8096 s2io_reset(sp);
8097
8098 /*
8099 * Initialize link state flags
8100 * and the card state parameter
8101 */
8102 sp->state = 0;
8103
8104 /* Initialize spinlocks */
8105 for (i = 0; i < sp->config.tx_fifo_num; i++)
8106 spin_lock_init(&mac_control->fifos[i].tx_lock);
8107
8108 /*
8109 * SXE-002: Configure link and activity LED to init state
8110 * on driver load.
8111 */
8112 subid = sp->pdev->subsystem_device;
8113 if ((subid & 0xFF) >= 0x07) {
8114 val64 = readq(&bar0->gpio_control);
8115 val64 |= 0x0000800000000000ULL;
8116 writeq(val64, &bar0->gpio_control);
8117 val64 = 0x0411040400000000ULL;
8118 writeq(val64, (void __iomem *) bar0 + 0x2700);
8119 val64 = readq(&bar0->gpio_control);
8120 }
8121
8122 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8123
8124 if (register_netdev(dev)) {
8125 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8126 ret = -ENODEV;
8127 goto register_failed;
8128 }
8129 s2io_vpd_read(sp);
8130 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
8131 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
8132 sp->product_name, pdev->revision);
8133 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8134 s2io_driver_version);
8135 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
8136 dev->name, print_mac(mac, dev->dev_addr));
8137 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
8138 if (sp->device_type & XFRAME_II_DEVICE) {
8139 mode = s2io_print_pci_mode(sp);
8140 if (mode < 0) {
8141 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8142 ret = -EBADSLT;
8143 unregister_netdev(dev);
8144 goto set_swap_failed;
8145 }
8146 }
8147 switch(sp->rxd_mode) {
8148 case RXD_MODE_1:
8149 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8150 dev->name);
8151 break;
8152 case RXD_MODE_3B:
8153 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8154 dev->name);
8155 break;
8156 }
8157
8158 switch (sp->config.napi) {
8159 case 0:
8160 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8161 break;
8162 case 1:
8163 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8164 break;
8165 }
8166
8167 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8168 sp->config.tx_fifo_num);
8169
8170 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8171 sp->config.rx_ring_num);
8172
8173 switch(sp->config.intr_type) {
8174 case INTA:
8175 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8176 break;
8177 case MSI_X:
8178 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8179 break;
8180 }
8181 if (sp->config.multiq) {
8182 for (i = 0; i < sp->config.tx_fifo_num; i++)
8183 mac_control->fifos[i].multiq = config->multiq;
8184 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8185 dev->name);
8186 } else
8187 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8188 dev->name);
8189
8190 switch (sp->config.tx_steering_type) {
8191 case NO_STEERING:
8192 DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
8193 " transmit\n", dev->name);
8194 break;
8195 case TX_PRIORITY_STEERING:
8196 DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
8197 " transmit\n", dev->name);
8198 break;
8199 case TX_DEFAULT_STEERING:
8200 DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
8201 " transmit\n", dev->name);
8202 }
8203
8204 if (sp->lro)
8205 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8206 dev->name);
8207 if (ufo)
8208 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
8209 " enabled\n", dev->name);
8210 /* Initialize device name */
8211 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8212
8213 /*
8214 * Make Link state as off at this point, when the Link change
8215 * interrupt comes the state will be automatically changed to
8216 * the right state.
8217 */
8218 netif_carrier_off(dev);
8219
8220 return 0;
8221
8222 register_failed:
8223 set_swap_failed:
8224 iounmap(sp->bar1);
8225 bar1_remap_failed:
8226 iounmap(sp->bar0);
8227 bar0_remap_failed:
8228 mem_alloc_failed:
8229 free_shared_mem(sp);
8230 pci_disable_device(pdev);
8231 pci_release_regions(pdev);
8232 pci_set_drvdata(pdev, NULL);
8233 free_netdev(dev);
8234
8235 return ret;
8236 }
8237
8238 /**
8239 * s2io_rem_nic - Free the PCI device
8240 * @pdev: structure containing the PCI related information of the device.
8241 * Description: This function is called by the Pci subsystem to release a
8242 * PCI device and free up all resource held up by the device. This could
8243 * be in response to a Hot plug event or when the driver is to be removed
8244 * from memory.
8245 */
8246
8247 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8248 {
8249 struct net_device *dev =
8250 (struct net_device *) pci_get_drvdata(pdev);
8251 struct s2io_nic *sp;
8252
8253 if (dev == NULL) {
8254 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8255 return;
8256 }
8257
8258 flush_scheduled_work();
8259
8260 sp = dev->priv;
8261 unregister_netdev(dev);
8262
8263 free_shared_mem(sp);
8264 iounmap(sp->bar0);
8265 iounmap(sp->bar1);
8266 pci_release_regions(pdev);
8267 pci_set_drvdata(pdev, NULL);
8268 free_netdev(dev);
8269 pci_disable_device(pdev);
8270 }
8271
8272 /**
8273 * s2io_starter - Entry point for the driver
8274 * Description: This function is the entry point for the driver. It verifies
8275 * the module loadable parameters and initializes PCI configuration space.
8276 */
8277
8278 static int __init s2io_starter(void)
8279 {
8280 return pci_register_driver(&s2io_driver);
8281 }
8282
8283 /**
8284 * s2io_closer - Cleanup routine for the driver
8285 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8286 */
8287
8288 static __exit void s2io_closer(void)
8289 {
8290 pci_unregister_driver(&s2io_driver);
8291 DBG_PRINT(INIT_DBG, "cleanup done\n");
8292 }
8293
8294 module_init(s2io_starter);
8295 module_exit(s2io_closer);
8296
8297 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8298 struct tcphdr **tcp, struct RxD_t *rxdp,
8299 struct s2io_nic *sp)
8300 {
8301 int ip_off;
8302 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8303
8304 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8305 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
8306 __FUNCTION__);
8307 return -1;
8308 }
8309
8310 /* Checking for DIX type or DIX type with VLAN */
8311 if ((l2_type == 0)
8312 || (l2_type == 4)) {
8313 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8314 /*
8315 * If vlan stripping is disabled and the frame is VLAN tagged,
8316 * shift the offset by the VLAN header size bytes.
8317 */
8318 if ((!vlan_strip_flag) &&
8319 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8320 ip_off += HEADER_VLAN_SIZE;
8321 } else {
8322 /* LLC, SNAP etc are considered non-mergeable */
8323 return -1;
8324 }
8325
8326 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8327 ip_len = (u8)((*ip)->ihl);
8328 ip_len <<= 2;
8329 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8330
8331 return 0;
8332 }
8333
8334 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8335 struct tcphdr *tcp)
8336 {
8337 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8338 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8339 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8340 return -1;
8341 return 0;
8342 }
8343
8344 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8345 {
8346 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8347 }
8348
8349 static void initiate_new_session(struct lro *lro, u8 *l2h,
8350 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
8351 {
8352 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8353 lro->l2h = l2h;
8354 lro->iph = ip;
8355 lro->tcph = tcp;
8356 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8357 lro->tcp_ack = tcp->ack_seq;
8358 lro->sg_num = 1;
8359 lro->total_len = ntohs(ip->tot_len);
8360 lro->frags_len = 0;
8361 lro->vlan_tag = vlan_tag;
8362 /*
8363 * check if we saw TCP timestamp. Other consistency checks have
8364 * already been done.
8365 */
8366 if (tcp->doff == 8) {
8367 __be32 *ptr;
8368 ptr = (__be32 *)(tcp+1);
8369 lro->saw_ts = 1;
8370 lro->cur_tsval = ntohl(*(ptr+1));
8371 lro->cur_tsecr = *(ptr+2);
8372 }
8373 lro->in_use = 1;
8374 }
8375
8376 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8377 {
8378 struct iphdr *ip = lro->iph;
8379 struct tcphdr *tcp = lro->tcph;
8380 __sum16 nchk;
8381 struct stat_block *statinfo = sp->mac_control.stats_info;
8382 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8383
8384 /* Update L3 header */
8385 ip->tot_len = htons(lro->total_len);
8386 ip->check = 0;
8387 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8388 ip->check = nchk;
8389
8390 /* Update L4 header */
8391 tcp->ack_seq = lro->tcp_ack;
8392 tcp->window = lro->window;
8393
8394 /* Update tsecr field if this session has timestamps enabled */
8395 if (lro->saw_ts) {
8396 __be32 *ptr = (__be32 *)(tcp + 1);
8397 *(ptr+2) = lro->cur_tsecr;
8398 }
8399
8400 /* Update counters required for calculation of
8401 * average no. of packets aggregated.
8402 */
8403 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8404 statinfo->sw_stat.num_aggregations++;
8405 }
8406
8407 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8408 struct tcphdr *tcp, u32 l4_pyld)
8409 {
8410 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8411 lro->total_len += l4_pyld;
8412 lro->frags_len += l4_pyld;
8413 lro->tcp_next_seq += l4_pyld;
8414 lro->sg_num++;
8415
8416 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8417 lro->tcp_ack = tcp->ack_seq;
8418 lro->window = tcp->window;
8419
8420 if (lro->saw_ts) {
8421 __be32 *ptr;
8422 /* Update tsecr and tsval from this packet */
8423 ptr = (__be32 *)(tcp+1);
8424 lro->cur_tsval = ntohl(*(ptr+1));
8425 lro->cur_tsecr = *(ptr + 2);
8426 }
8427 }
8428
8429 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8430 struct tcphdr *tcp, u32 tcp_pyld_len)
8431 {
8432 u8 *ptr;
8433
8434 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8435
8436 if (!tcp_pyld_len) {
8437 /* Runt frame or a pure ack */
8438 return -1;
8439 }
8440
8441 if (ip->ihl != 5) /* IP has options */
8442 return -1;
8443
8444 /* If we see CE codepoint in IP header, packet is not mergeable */
8445 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8446 return -1;
8447
8448 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8449 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
8450 tcp->ece || tcp->cwr || !tcp->ack) {
8451 /*
8452 * Currently recognize only the ack control word and
8453 * any other control field being set would result in
8454 * flushing the LRO session
8455 */
8456 return -1;
8457 }
8458
8459 /*
8460 * Allow only one TCP timestamp option. Don't aggregate if
8461 * any other options are detected.
8462 */
8463 if (tcp->doff != 5 && tcp->doff != 8)
8464 return -1;
8465
8466 if (tcp->doff == 8) {
8467 ptr = (u8 *)(tcp + 1);
8468 while (*ptr == TCPOPT_NOP)
8469 ptr++;
8470 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8471 return -1;
8472
8473 /* Ensure timestamp value increases monotonically */
8474 if (l_lro)
8475 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8476 return -1;
8477
8478 /* timestamp echo reply should be non-zero */
8479 if (*((__be32 *)(ptr+6)) == 0)
8480 return -1;
8481 }
8482
8483 return 0;
8484 }
8485
8486 static int
8487 s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp,
8488 u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
8489 struct s2io_nic *sp)
8490 {
8491 struct iphdr *ip;
8492 struct tcphdr *tcph;
8493 int ret = 0, i;
8494 u16 vlan_tag = 0;
8495
8496 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8497 rxdp, sp))) {
8498 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8499 ip->saddr, ip->daddr);
8500 } else
8501 return ret;
8502
8503 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8504 tcph = (struct tcphdr *)*tcp;
8505 *tcp_len = get_l4_pyld_length(ip, tcph);
8506 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8507 struct lro *l_lro = &ring_data->lro0_n[i];
8508 if (l_lro->in_use) {
8509 if (check_for_socket_match(l_lro, ip, tcph))
8510 continue;
8511 /* Sock pair matched */
8512 *lro = l_lro;
8513
8514 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8515 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8516 "0x%x, actual 0x%x\n", __FUNCTION__,
8517 (*lro)->tcp_next_seq,
8518 ntohl(tcph->seq));
8519
8520 sp->mac_control.stats_info->
8521 sw_stat.outof_sequence_pkts++;
8522 ret = 2;
8523 break;
8524 }
8525
8526 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8527 ret = 1; /* Aggregate */
8528 else
8529 ret = 2; /* Flush both */
8530 break;
8531 }
8532 }
8533
8534 if (ret == 0) {
8535 /* Before searching for available LRO objects,
8536 * check if the pkt is L3/L4 aggregatable. If not
8537 * don't create new LRO session. Just send this
8538 * packet up.
8539 */
8540 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8541 return 5;
8542 }
8543
8544 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8545 struct lro *l_lro = &ring_data->lro0_n[i];
8546 if (!(l_lro->in_use)) {
8547 *lro = l_lro;
8548 ret = 3; /* Begin anew */
8549 break;
8550 }
8551 }
8552 }
8553
8554 if (ret == 0) { /* sessions exceeded */
8555 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8556 __FUNCTION__);
8557 *lro = NULL;
8558 return ret;
8559 }
8560
8561 switch (ret) {
8562 case 3:
8563 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8564 vlan_tag);
8565 break;
8566 case 2:
8567 update_L3L4_header(sp, *lro);
8568 break;
8569 case 1:
8570 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8571 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8572 update_L3L4_header(sp, *lro);
8573 ret = 4; /* Flush the LRO */
8574 }
8575 break;
8576 default:
8577 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8578 __FUNCTION__);
8579 break;
8580 }
8581
8582 return ret;
8583 }
8584
8585 static void clear_lro_session(struct lro *lro)
8586 {
8587 static u16 lro_struct_size = sizeof(struct lro);
8588
8589 memset(lro, 0, lro_struct_size);
8590 }
8591
8592 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8593 {
8594 struct net_device *dev = skb->dev;
8595 struct s2io_nic *sp = dev->priv;
8596
8597 skb->protocol = eth_type_trans(skb, dev);
8598 if (sp->vlgrp && vlan_tag
8599 && (vlan_strip_flag)) {
8600 /* Queueing the vlan frame to the upper layer */
8601 if (sp->config.napi)
8602 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8603 else
8604 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8605 } else {
8606 if (sp->config.napi)
8607 netif_receive_skb(skb);
8608 else
8609 netif_rx(skb);
8610 }
8611 }
8612
8613 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8614 struct sk_buff *skb,
8615 u32 tcp_len)
8616 {
8617 struct sk_buff *first = lro->parent;
8618
8619 first->len += tcp_len;
8620 first->data_len = lro->frags_len;
8621 skb_pull(skb, (skb->len - tcp_len));
8622 if (skb_shinfo(first)->frag_list)
8623 lro->last_frag->next = skb;
8624 else
8625 skb_shinfo(first)->frag_list = skb;
8626 first->truesize += skb->truesize;
8627 lro->last_frag = skb;
8628 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8629 return;
8630 }
8631
8632 /**
8633 * s2io_io_error_detected - called when PCI error is detected
8634 * @pdev: Pointer to PCI device
8635 * @state: The current pci connection state
8636 *
8637 * This function is called after a PCI bus error affecting
8638 * this device has been detected.
8639 */
8640 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8641 pci_channel_state_t state)
8642 {
8643 struct net_device *netdev = pci_get_drvdata(pdev);
8644 struct s2io_nic *sp = netdev->priv;
8645
8646 netif_device_detach(netdev);
8647
8648 if (netif_running(netdev)) {
8649 /* Bring down the card, while avoiding PCI I/O */
8650 do_s2io_card_down(sp, 0);
8651 }
8652 pci_disable_device(pdev);
8653
8654 return PCI_ERS_RESULT_NEED_RESET;
8655 }
8656
8657 /**
8658 * s2io_io_slot_reset - called after the pci bus has been reset.
8659 * @pdev: Pointer to PCI device
8660 *
8661 * Restart the card from scratch, as if from a cold-boot.
8662 * At this point, the card has exprienced a hard reset,
8663 * followed by fixups by BIOS, and has its config space
8664 * set up identically to what it was at cold boot.
8665 */
8666 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8667 {
8668 struct net_device *netdev = pci_get_drvdata(pdev);
8669 struct s2io_nic *sp = netdev->priv;
8670
8671 if (pci_enable_device(pdev)) {
8672 printk(KERN_ERR "s2io: "
8673 "Cannot re-enable PCI device after reset.\n");
8674 return PCI_ERS_RESULT_DISCONNECT;
8675 }
8676
8677 pci_set_master(pdev);
8678 s2io_reset(sp);
8679
8680 return PCI_ERS_RESULT_RECOVERED;
8681 }
8682
8683 /**
8684 * s2io_io_resume - called when traffic can start flowing again.
8685 * @pdev: Pointer to PCI device
8686 *
8687 * This callback is called when the error recovery driver tells
8688 * us that its OK to resume normal operation.
8689 */
8690 static void s2io_io_resume(struct pci_dev *pdev)
8691 {
8692 struct net_device *netdev = pci_get_drvdata(pdev);
8693 struct s2io_nic *sp = netdev->priv;
8694
8695 if (netif_running(netdev)) {
8696 if (s2io_card_up(sp)) {
8697 printk(KERN_ERR "s2io: "
8698 "Can't bring device back up after reset.\n");
8699 return;
8700 }
8701
8702 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8703 s2io_card_down(sp);
8704 printk(KERN_ERR "s2io: "
8705 "Can't resetore mac addr after reset.\n");
8706 return;
8707 }
8708 }
8709
8710 netif_device_attach(netdev);
8711 netif_wake_queue(netdev);
8712 }
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