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kmemtrace: SLOB hooks.
[linux-2.6/kmemtrace.git] / arch / mips / kernel / traps.c
blobf9165d1a17bfbccec9d64a9a07148696fcf1784c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
17 #include <linux/mm.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26
27 #include <asm/bootinfo.h>
28 #include <asm/branch.h>
29 #include <asm/break.h>
30 #include <asm/cpu.h>
31 #include <asm/dsp.h>
32 #include <asm/fpu.h>
33 #include <asm/mipsregs.h>
34 #include <asm/mipsmtregs.h>
35 #include <asm/module.h>
36 #include <asm/pgtable.h>
37 #include <asm/ptrace.h>
38 #include <asm/sections.h>
39 #include <asm/system.h>
40 #include <asm/tlbdebug.h>
41 #include <asm/traps.h>
42 #include <asm/uaccess.h>
43 #include <asm/mmu_context.h>
44 #include <asm/types.h>
45 #include <asm/stacktrace.h>
46
47 extern asmlinkage void handle_int(void);
48 extern asmlinkage void handle_tlbm(void);
49 extern asmlinkage void handle_tlbl(void);
50 extern asmlinkage void handle_tlbs(void);
51 extern asmlinkage void handle_adel(void);
52 extern asmlinkage void handle_ades(void);
53 extern asmlinkage void handle_ibe(void);
54 extern asmlinkage void handle_dbe(void);
55 extern asmlinkage void handle_sys(void);
56 extern asmlinkage void handle_bp(void);
57 extern asmlinkage void handle_ri(void);
58 extern asmlinkage void handle_ri_rdhwr_vivt(void);
59 extern asmlinkage void handle_ri_rdhwr(void);
60 extern asmlinkage void handle_cpu(void);
61 extern asmlinkage void handle_ov(void);
62 extern asmlinkage void handle_tr(void);
63 extern asmlinkage void handle_fpe(void);
64 extern asmlinkage void handle_mdmx(void);
65 extern asmlinkage void handle_watch(void);
66 extern asmlinkage void handle_mt(void);
67 extern asmlinkage void handle_dsp(void);
68 extern asmlinkage void handle_mcheck(void);
69 extern asmlinkage void handle_reserved(void);
70
71 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
72 struct mips_fpu_struct *ctx, int has_fpu);
73
74 void (*board_watchpoint_handler)(struct pt_regs *regs);
75 void (*board_be_init)(void);
76 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
77 void (*board_nmi_handler_setup)(void);
78 void (*board_ejtag_handler_setup)(void);
79 void (*board_bind_eic_interrupt)(int irq, int regset);
80
81
82 static void show_raw_backtrace(unsigned long reg29)
83 {
84 unsigned long *sp = (unsigned long *)(reg29 & ~3);
85 unsigned long addr;
86
87 printk("Call Trace:");
88 #ifdef CONFIG_KALLSYMS
89 printk("\n");
90 #endif
91 while (!kstack_end(sp)) {
92 unsigned long __user *p =
93 (unsigned long __user *)(unsigned long)sp++;
94 if (__get_user(addr, p)) {
95 printk(" (Bad stack address)");
96 break;
97 }
98 if (__kernel_text_address(addr))
99 print_ip_sym(addr);
100 }
101 printk("\n");
102 }
103
104 #ifdef CONFIG_KALLSYMS
105 int raw_show_trace;
106 static int __init set_raw_show_trace(char *str)
107 {
108 raw_show_trace = 1;
109 return 1;
110 }
111 __setup("raw_show_trace", set_raw_show_trace);
112 #endif
113
114 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
115 {
116 unsigned long sp = regs->regs[29];
117 unsigned long ra = regs->regs[31];
118 unsigned long pc = regs->cp0_epc;
119
120 if (raw_show_trace || !__kernel_text_address(pc)) {
121 show_raw_backtrace(sp);
122 return;
123 }
124 printk("Call Trace:\n");
125 do {
126 print_ip_sym(pc);
127 pc = unwind_stack(task, &sp, pc, &ra);
128 } while (pc);
129 printk("\n");
130 }
131
132 /*
133 * This routine abuses get_user()/put_user() to reference pointers
134 * with at least a bit of error checking ...
135 */
136 static void show_stacktrace(struct task_struct *task,
137 const struct pt_regs *regs)
138 {
139 const int field = 2 * sizeof(unsigned long);
140 long stackdata;
141 int i;
142 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
143
144 printk("Stack :");
145 i = 0;
146 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
147 if (i && ((i % (64 / field)) == 0))
148 printk("\n ");
149 if (i > 39) {
150 printk(" ...");
151 break;
152 }
153
154 if (__get_user(stackdata, sp++)) {
155 printk(" (Bad stack address)");
156 break;
157 }
158
159 printk(" %0*lx", field, stackdata);
160 i++;
161 }
162 printk("\n");
163 show_backtrace(task, regs);
164 }
165
166 void show_stack(struct task_struct *task, unsigned long *sp)
167 {
168 struct pt_regs regs;
169 if (sp) {
170 regs.regs[29] = (unsigned long)sp;
171 regs.regs[31] = 0;
172 regs.cp0_epc = 0;
173 } else {
174 if (task && task != current) {
175 regs.regs[29] = task->thread.reg29;
176 regs.regs[31] = 0;
177 regs.cp0_epc = task->thread.reg31;
178 } else {
179 prepare_frametrace(&regs);
180 }
181 }
182 show_stacktrace(task, &regs);
183 }
184
185 /*
186 * The architecture-independent dump_stack generator
187 */
188 void dump_stack(void)
189 {
190 struct pt_regs regs;
191
192 prepare_frametrace(&regs);
193 show_backtrace(current, &regs);
194 }
195
196 EXPORT_SYMBOL(dump_stack);
197
198 static void show_code(unsigned int __user *pc)
199 {
200 long i;
201 unsigned short __user *pc16 = NULL;
202
203 printk("\nCode:");
204
205 if ((unsigned long)pc & 1)
206 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
207 for(i = -3 ; i < 6 ; i++) {
208 unsigned int insn;
209 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
210 printk(" (Bad address in epc)\n");
211 break;
212 }
213 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
214 }
215 }
216
217 static void __show_regs(const struct pt_regs *regs)
218 {
219 const int field = 2 * sizeof(unsigned long);
220 unsigned int cause = regs->cp0_cause;
221 int i;
222
223 printk("Cpu %d\n", smp_processor_id());
224
225 /*
226 * Saved main processor registers
227 */
228 for (i = 0; i < 32; ) {
229 if ((i % 4) == 0)
230 printk("$%2d :", i);
231 if (i == 0)
232 printk(" %0*lx", field, 0UL);
233 else if (i == 26 || i == 27)
234 printk(" %*s", field, "");
235 else
236 printk(" %0*lx", field, regs->regs[i]);
237
238 i++;
239 if ((i % 4) == 0)
240 printk("\n");
241 }
242
243 #ifdef CONFIG_CPU_HAS_SMARTMIPS
244 printk("Acx : %0*lx\n", field, regs->acx);
245 #endif
246 printk("Hi : %0*lx\n", field, regs->hi);
247 printk("Lo : %0*lx\n", field, regs->lo);
248
249 /*
250 * Saved cp0 registers
251 */
252 printk("epc : %0*lx ", field, regs->cp0_epc);
253 print_symbol("%s ", regs->cp0_epc);
254 printk(" %s\n", print_tainted());
255 printk("ra : %0*lx ", field, regs->regs[31]);
256 print_symbol("%s\n", regs->regs[31]);
257
258 printk("Status: %08x ", (uint32_t) regs->cp0_status);
259
260 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
261 if (regs->cp0_status & ST0_KUO)
262 printk("KUo ");
263 if (regs->cp0_status & ST0_IEO)
264 printk("IEo ");
265 if (regs->cp0_status & ST0_KUP)
266 printk("KUp ");
267 if (regs->cp0_status & ST0_IEP)
268 printk("IEp ");
269 if (regs->cp0_status & ST0_KUC)
270 printk("KUc ");
271 if (regs->cp0_status & ST0_IEC)
272 printk("IEc ");
273 } else {
274 if (regs->cp0_status & ST0_KX)
275 printk("KX ");
276 if (regs->cp0_status & ST0_SX)
277 printk("SX ");
278 if (regs->cp0_status & ST0_UX)
279 printk("UX ");
280 switch (regs->cp0_status & ST0_KSU) {
281 case KSU_USER:
282 printk("USER ");
283 break;
284 case KSU_SUPERVISOR:
285 printk("SUPERVISOR ");
286 break;
287 case KSU_KERNEL:
288 printk("KERNEL ");
289 break;
290 default:
291 printk("BAD_MODE ");
292 break;
293 }
294 if (regs->cp0_status & ST0_ERL)
295 printk("ERL ");
296 if (regs->cp0_status & ST0_EXL)
297 printk("EXL ");
298 if (regs->cp0_status & ST0_IE)
299 printk("IE ");
300 }
301 printk("\n");
302
303 printk("Cause : %08x\n", cause);
304
305 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
306 if (1 <= cause && cause <= 5)
307 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
308
309 printk("PrId : %08x (%s)\n", read_c0_prid(),
310 cpu_name_string());
311 }
312
313 /*
314 * FIXME: really the generic show_regs should take a const pointer argument.
315 */
316 void show_regs(struct pt_regs *regs)
317 {
318 __show_regs((struct pt_regs *)regs);
319 }
320
321 void show_registers(const struct pt_regs *regs)
322 {
323 const int field = 2 * sizeof(unsigned long);
324
325 __show_regs(regs);
326 print_modules();
327 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
328 current->comm, current->pid, current_thread_info(), current,
329 field, current_thread_info()->tp_value);
330 if (cpu_has_userlocal) {
331 unsigned long tls;
332
333 tls = read_c0_userlocal();
334 if (tls != current_thread_info()->tp_value)
335 printk("*HwTLS: %0*lx\n", field, tls);
336 }
337
338 show_stacktrace(current, regs);
339 show_code((unsigned int __user *) regs->cp0_epc);
340 printk("\n");
341 }
342
343 static DEFINE_SPINLOCK(die_lock);
344
345 void __noreturn die(const char * str, const struct pt_regs * regs)
346 {
347 static int die_counter;
348 #ifdef CONFIG_MIPS_MT_SMTC
349 unsigned long dvpret = dvpe();
350 #endif /* CONFIG_MIPS_MT_SMTC */
351
352 console_verbose();
353 spin_lock_irq(&die_lock);
354 bust_spinlocks(1);
355 #ifdef CONFIG_MIPS_MT_SMTC
356 mips_mt_regdump(dvpret);
357 #endif /* CONFIG_MIPS_MT_SMTC */
358 printk("%s[#%d]:\n", str, ++die_counter);
359 show_registers(regs);
360 add_taint(TAINT_DIE);
361 spin_unlock_irq(&die_lock);
362
363 if (in_interrupt())
364 panic("Fatal exception in interrupt");
365
366 if (panic_on_oops) {
367 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
368 ssleep(5);
369 panic("Fatal exception");
370 }
371
372 do_exit(SIGSEGV);
373 }
374
375 extern const struct exception_table_entry __start___dbe_table[];
376 extern const struct exception_table_entry __stop___dbe_table[];
377
378 __asm__(
379 " .section __dbe_table, \"a\"\n"
380 " .previous \n");
381
382 /* Given an address, look for it in the exception tables. */
383 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
384 {
385 const struct exception_table_entry *e;
386
387 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
388 if (!e)
389 e = search_module_dbetables(addr);
390 return e;
391 }
392
393 asmlinkage void do_be(struct pt_regs *regs)
394 {
395 const int field = 2 * sizeof(unsigned long);
396 const struct exception_table_entry *fixup = NULL;
397 int data = regs->cp0_cause & 4;
398 int action = MIPS_BE_FATAL;
399
400 /* XXX For now. Fixme, this searches the wrong table ... */
401 if (data && !user_mode(regs))
402 fixup = search_dbe_tables(exception_epc(regs));
403
404 if (fixup)
405 action = MIPS_BE_FIXUP;
406
407 if (board_be_handler)
408 action = board_be_handler(regs, fixup != NULL);
409
410 switch (action) {
411 case MIPS_BE_DISCARD:
412 return;
413 case MIPS_BE_FIXUP:
414 if (fixup) {
415 regs->cp0_epc = fixup->nextinsn;
416 return;
417 }
418 break;
419 default:
420 break;
421 }
422
423 /*
424 * Assume it would be too dangerous to continue ...
425 */
426 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
427 data ? "Data" : "Instruction",
428 field, regs->cp0_epc, field, regs->regs[31]);
429 die_if_kernel("Oops", regs);
430 force_sig(SIGBUS, current);
431 }
432
433 /*
434 * ll/sc, rdhwr, sync emulation
435 */
436
437 #define OPCODE 0xfc000000
438 #define BASE 0x03e00000
439 #define RT 0x001f0000
440 #define OFFSET 0x0000ffff
441 #define LL 0xc0000000
442 #define SC 0xe0000000
443 #define SPEC0 0x00000000
444 #define SPEC3 0x7c000000
445 #define RD 0x0000f800
446 #define FUNC 0x0000003f
447 #define SYNC 0x0000000f
448 #define RDHWR 0x0000003b
449
450 /*
451 * The ll_bit is cleared by r*_switch.S
452 */
453
454 unsigned long ll_bit;
455
456 static struct task_struct *ll_task = NULL;
457
458 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
459 {
460 unsigned long value, __user *vaddr;
461 long offset;
462
463 /*
464 * analyse the ll instruction that just caused a ri exception
465 * and put the referenced address to addr.
466 */
467
468 /* sign extend offset */
469 offset = opcode & OFFSET;
470 offset <<= 16;
471 offset >>= 16;
472
473 vaddr = (unsigned long __user *)
474 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
475
476 if ((unsigned long)vaddr & 3)
477 return SIGBUS;
478 if (get_user(value, vaddr))
479 return SIGSEGV;
480
481 preempt_disable();
482
483 if (ll_task == NULL || ll_task == current) {
484 ll_bit = 1;
485 } else {
486 ll_bit = 0;
487 }
488 ll_task = current;
489
490 preempt_enable();
491
492 regs->regs[(opcode & RT) >> 16] = value;
493
494 return 0;
495 }
496
497 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
498 {
499 unsigned long __user *vaddr;
500 unsigned long reg;
501 long offset;
502
503 /*
504 * analyse the sc instruction that just caused a ri exception
505 * and put the referenced address to addr.
506 */
507
508 /* sign extend offset */
509 offset = opcode & OFFSET;
510 offset <<= 16;
511 offset >>= 16;
512
513 vaddr = (unsigned long __user *)
514 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
515 reg = (opcode & RT) >> 16;
516
517 if ((unsigned long)vaddr & 3)
518 return SIGBUS;
519
520 preempt_disable();
521
522 if (ll_bit == 0 || ll_task != current) {
523 regs->regs[reg] = 0;
524 preempt_enable();
525 return 0;
526 }
527
528 preempt_enable();
529
530 if (put_user(regs->regs[reg], vaddr))
531 return SIGSEGV;
532
533 regs->regs[reg] = 1;
534
535 return 0;
536 }
537
538 /*
539 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
540 * opcodes are supposed to result in coprocessor unusable exceptions if
541 * executed on ll/sc-less processors. That's the theory. In practice a
542 * few processors such as NEC's VR4100 throw reserved instruction exceptions
543 * instead, so we're doing the emulation thing in both exception handlers.
544 */
545 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
546 {
547 if ((opcode & OPCODE) == LL)
548 return simulate_ll(regs, opcode);
549 if ((opcode & OPCODE) == SC)
550 return simulate_sc(regs, opcode);
551
552 return -1; /* Must be something else ... */
553 }
554
555 /*
556 * Simulate trapping 'rdhwr' instructions to provide user accessible
557 * registers not implemented in hardware.
558 */
559 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
560 {
561 struct thread_info *ti = task_thread_info(current);
562
563 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
564 int rd = (opcode & RD) >> 11;
565 int rt = (opcode & RT) >> 16;
566 switch (rd) {
567 case 0: /* CPU number */
568 regs->regs[rt] = smp_processor_id();
569 return 0;
570 case 1: /* SYNCI length */
571 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
572 current_cpu_data.icache.linesz);
573 return 0;
574 case 2: /* Read count register */
575 regs->regs[rt] = read_c0_count();
576 return 0;
577 case 3: /* Count register resolution */
578 switch (current_cpu_data.cputype) {
579 case CPU_20KC:
580 case CPU_25KF:
581 regs->regs[rt] = 1;
582 break;
583 default:
584 regs->regs[rt] = 2;
585 }
586 return 0;
587 case 29:
588 regs->regs[rt] = ti->tp_value;
589 return 0;
590 default:
591 return -1;
592 }
593 }
594
595 /* Not ours. */
596 return -1;
597 }
598
599 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
600 {
601 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
602 return 0;
603
604 return -1; /* Must be something else ... */
605 }
606
607 asmlinkage void do_ov(struct pt_regs *regs)
608 {
609 siginfo_t info;
610
611 die_if_kernel("Integer overflow", regs);
612
613 info.si_code = FPE_INTOVF;
614 info.si_signo = SIGFPE;
615 info.si_errno = 0;
616 info.si_addr = (void __user *) regs->cp0_epc;
617 force_sig_info(SIGFPE, &info, current);
618 }
619
620 /*
621 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
622 */
623 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
624 {
625 siginfo_t info;
626
627 die_if_kernel("FP exception in kernel code", regs);
628
629 if (fcr31 & FPU_CSR_UNI_X) {
630 int sig;
631
632 /*
633 * Unimplemented operation exception. If we've got the full
634 * software emulator on-board, let's use it...
635 *
636 * Force FPU to dump state into task/thread context. We're
637 * moving a lot of data here for what is probably a single
638 * instruction, but the alternative is to pre-decode the FP
639 * register operands before invoking the emulator, which seems
640 * a bit extreme for what should be an infrequent event.
641 */
642 /* Ensure 'resume' not overwrite saved fp context again. */
643 lose_fpu(1);
644
645 /* Run the emulator */
646 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1);
647
648 /*
649 * We can't allow the emulated instruction to leave any of
650 * the cause bit set in $fcr31.
651 */
652 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
653
654 /* Restore the hardware register state */
655 own_fpu(1); /* Using the FPU again. */
656
657 /* If something went wrong, signal */
658 if (sig)
659 force_sig(sig, current);
660
661 return;
662 } else if (fcr31 & FPU_CSR_INV_X)
663 info.si_code = FPE_FLTINV;
664 else if (fcr31 & FPU_CSR_DIV_X)
665 info.si_code = FPE_FLTDIV;
666 else if (fcr31 & FPU_CSR_OVF_X)
667 info.si_code = FPE_FLTOVF;
668 else if (fcr31 & FPU_CSR_UDF_X)
669 info.si_code = FPE_FLTUND;
670 else if (fcr31 & FPU_CSR_INE_X)
671 info.si_code = FPE_FLTRES;
672 else
673 info.si_code = __SI_FAULT;
674 info.si_signo = SIGFPE;
675 info.si_errno = 0;
676 info.si_addr = (void __user *) regs->cp0_epc;
677 force_sig_info(SIGFPE, &info, current);
678 }
679
680 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
681 const char *str)
682 {
683 siginfo_t info;
684 char b[40];
685
686 /*
687 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
688 * insns, even for trap and break codes that indicate arithmetic
689 * failures. Weird ...
690 * But should we continue the brokenness??? --macro
691 */
692 switch (code) {
693 case BRK_OVERFLOW:
694 case BRK_DIVZERO:
695 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
696 die_if_kernel(b, regs);
697 if (code == BRK_DIVZERO)
698 info.si_code = FPE_INTDIV;
699 else
700 info.si_code = FPE_INTOVF;
701 info.si_signo = SIGFPE;
702 info.si_errno = 0;
703 info.si_addr = (void __user *) regs->cp0_epc;
704 force_sig_info(SIGFPE, &info, current);
705 break;
706 case BRK_BUG:
707 die_if_kernel("Kernel bug detected", regs);
708 force_sig(SIGTRAP, current);
709 break;
710 default:
711 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
712 die_if_kernel(b, regs);
713 force_sig(SIGTRAP, current);
714 }
715 }
716
717 asmlinkage void do_bp(struct pt_regs *regs)
718 {
719 unsigned int opcode, bcode;
720
721 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
722 goto out_sigsegv;
723
724 /*
725 * There is the ancient bug in the MIPS assemblers that the break
726 * code starts left to bit 16 instead to bit 6 in the opcode.
727 * Gas is bug-compatible, but not always, grrr...
728 * We handle both cases with a simple heuristics. --macro
729 */
730 bcode = ((opcode >> 6) & ((1 << 20) - 1));
731 if (bcode >= (1 << 10))
732 bcode >>= 10;
733
734 do_trap_or_bp(regs, bcode, "Break");
735 return;
736
737 out_sigsegv:
738 force_sig(SIGSEGV, current);
739 }
740
741 asmlinkage void do_tr(struct pt_regs *regs)
742 {
743 unsigned int opcode, tcode = 0;
744
745 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
746 goto out_sigsegv;
747
748 /* Immediate versions don't provide a code. */
749 if (!(opcode & OPCODE))
750 tcode = ((opcode >> 6) & ((1 << 10) - 1));
751
752 do_trap_or_bp(regs, tcode, "Trap");
753 return;
754
755 out_sigsegv:
756 force_sig(SIGSEGV, current);
757 }
758
759 asmlinkage void do_ri(struct pt_regs *regs)
760 {
761 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
762 unsigned long old_epc = regs->cp0_epc;
763 unsigned int opcode = 0;
764 int status = -1;
765
766 die_if_kernel("Reserved instruction in kernel code", regs);
767
768 if (unlikely(compute_return_epc(regs) < 0))
769 return;
770
771 if (unlikely(get_user(opcode, epc) < 0))
772 status = SIGSEGV;
773
774 if (!cpu_has_llsc && status < 0)
775 status = simulate_llsc(regs, opcode);
776
777 if (status < 0)
778 status = simulate_rdhwr(regs, opcode);
779
780 if (status < 0)
781 status = simulate_sync(regs, opcode);
782
783 if (status < 0)
784 status = SIGILL;
785
786 if (unlikely(status > 0)) {
787 regs->cp0_epc = old_epc; /* Undo skip-over. */
788 force_sig(status, current);
789 }
790 }
791
792 /*
793 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
794 * emulated more than some threshold number of instructions, force migration to
795 * a "CPU" that has FP support.
796 */
797 static void mt_ase_fp_affinity(void)
798 {
799 #ifdef CONFIG_MIPS_MT_FPAFF
800 if (mt_fpemul_threshold > 0 &&
801 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
802 /*
803 * If there's no FPU present, or if the application has already
804 * restricted the allowed set to exclude any CPUs with FPUs,
805 * we'll skip the procedure.
806 */
807 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
808 cpumask_t tmask;
809
810 cpus_and(tmask, current->thread.user_cpus_allowed,
811 mt_fpu_cpumask);
812 set_cpus_allowed(current, tmask);
813 set_thread_flag(TIF_FPUBOUND);
814 }
815 }
816 #endif /* CONFIG_MIPS_MT_FPAFF */
817 }
818
819 asmlinkage void do_cpu(struct pt_regs *regs)
820 {
821 unsigned int __user *epc;
822 unsigned long old_epc;
823 unsigned int opcode;
824 unsigned int cpid;
825 int status;
826
827 die_if_kernel("do_cpu invoked from kernel context!", regs);
828
829 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
830
831 switch (cpid) {
832 case 0:
833 epc = (unsigned int __user *)exception_epc(regs);
834 old_epc = regs->cp0_epc;
835 opcode = 0;
836 status = -1;
837
838 if (unlikely(compute_return_epc(regs) < 0))
839 return;
840
841 if (unlikely(get_user(opcode, epc) < 0))
842 status = SIGSEGV;
843
844 if (!cpu_has_llsc && status < 0)
845 status = simulate_llsc(regs, opcode);
846
847 if (status < 0)
848 status = simulate_rdhwr(regs, opcode);
849
850 if (status < 0)
851 status = SIGILL;
852
853 if (unlikely(status > 0)) {
854 regs->cp0_epc = old_epc; /* Undo skip-over. */
855 force_sig(status, current);
856 }
857
858 return;
859
860 case 1:
861 if (used_math()) /* Using the FPU again. */
862 own_fpu(1);
863 else { /* First time FPU user. */
864 init_fpu();
865 set_used_math();
866 }
867
868 if (!raw_cpu_has_fpu) {
869 int sig;
870 sig = fpu_emulator_cop1Handler(regs,
871 &current->thread.fpu, 0);
872 if (sig)
873 force_sig(sig, current);
874 else
875 mt_ase_fp_affinity();
876 }
877
878 return;
879
880 case 2:
881 case 3:
882 break;
883 }
884
885 force_sig(SIGILL, current);
886 }
887
888 asmlinkage void do_mdmx(struct pt_regs *regs)
889 {
890 force_sig(SIGILL, current);
891 }
892
893 asmlinkage void do_watch(struct pt_regs *regs)
894 {
895 if (board_watchpoint_handler) {
896 (*board_watchpoint_handler)(regs);
897 return;
898 }
899
900 /*
901 * We use the watch exception where available to detect stack
902 * overflows.
903 */
904 dump_tlb_all();
905 show_regs(regs);
906 panic("Caught WATCH exception - probably caused by stack overflow.");
907 }
908
909 asmlinkage void do_mcheck(struct pt_regs *regs)
910 {
911 const int field = 2 * sizeof(unsigned long);
912 int multi_match = regs->cp0_status & ST0_TS;
913
914 show_regs(regs);
915
916 if (multi_match) {
917 printk("Index : %0x\n", read_c0_index());
918 printk("Pagemask: %0x\n", read_c0_pagemask());
919 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
920 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
921 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
922 printk("\n");
923 dump_tlb_all();
924 }
925
926 show_code((unsigned int __user *) regs->cp0_epc);
927
928 /*
929 * Some chips may have other causes of machine check (e.g. SB1
930 * graduation timer)
931 */
932 panic("Caught Machine Check exception - %scaused by multiple "
933 "matching entries in the TLB.",
934 (multi_match) ? "" : "not ");
935 }
936
937 asmlinkage void do_mt(struct pt_regs *regs)
938 {
939 int subcode;
940
941 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
942 >> VPECONTROL_EXCPT_SHIFT;
943 switch (subcode) {
944 case 0:
945 printk(KERN_DEBUG "Thread Underflow\n");
946 break;
947 case 1:
948 printk(KERN_DEBUG "Thread Overflow\n");
949 break;
950 case 2:
951 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
952 break;
953 case 3:
954 printk(KERN_DEBUG "Gating Storage Exception\n");
955 break;
956 case 4:
957 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
958 break;
959 case 5:
960 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
961 break;
962 default:
963 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
964 subcode);
965 break;
966 }
967 die_if_kernel("MIPS MT Thread exception in kernel", regs);
968
969 force_sig(SIGILL, current);
970 }
971
972
973 asmlinkage void do_dsp(struct pt_regs *regs)
974 {
975 if (cpu_has_dsp)
976 panic("Unexpected DSP exception\n");
977
978 force_sig(SIGILL, current);
979 }
980
981 asmlinkage void do_reserved(struct pt_regs *regs)
982 {
983 /*
984 * Game over - no way to handle this if it ever occurs. Most probably
985 * caused by a new unknown cpu type or after another deadly
986 * hard/software error.
987 */
988 show_regs(regs);
989 panic("Caught reserved exception %ld - should not happen.",
990 (regs->cp0_cause & 0x7f) >> 2);
991 }
992
993 static int __initdata l1parity = 1;
994 static int __init nol1parity(char *s)
995 {
996 l1parity = 0;
997 return 1;
998 }
999 __setup("nol1par", nol1parity);
1000 static int __initdata l2parity = 1;
1001 static int __init nol2parity(char *s)
1002 {
1003 l2parity = 0;
1004 return 1;
1005 }
1006 __setup("nol2par", nol2parity);
1007
1008 /*
1009 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1010 * it different ways.
1011 */
1012 static inline void parity_protection_init(void)
1013 {
1014 switch (current_cpu_type()) {
1015 case CPU_24K:
1016 case CPU_34K:
1017 case CPU_74K:
1018 case CPU_1004K:
1019 {
1020 #define ERRCTL_PE 0x80000000
1021 #define ERRCTL_L2P 0x00800000
1022 unsigned long errctl;
1023 unsigned int l1parity_present, l2parity_present;
1024
1025 errctl = read_c0_ecc();
1026 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1027
1028 /* probe L1 parity support */
1029 write_c0_ecc(errctl | ERRCTL_PE);
1030 back_to_back_c0_hazard();
1031 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1032
1033 /* probe L2 parity support */
1034 write_c0_ecc(errctl|ERRCTL_L2P);
1035 back_to_back_c0_hazard();
1036 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1037
1038 if (l1parity_present && l2parity_present) {
1039 if (l1parity)
1040 errctl |= ERRCTL_PE;
1041 if (l1parity ^ l2parity)
1042 errctl |= ERRCTL_L2P;
1043 } else if (l1parity_present) {
1044 if (l1parity)
1045 errctl |= ERRCTL_PE;
1046 } else if (l2parity_present) {
1047 if (l2parity)
1048 errctl |= ERRCTL_L2P;
1049 } else {
1050 /* No parity available */
1051 }
1052
1053 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1054
1055 write_c0_ecc(errctl);
1056 back_to_back_c0_hazard();
1057 errctl = read_c0_ecc();
1058 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1059
1060 if (l1parity_present)
1061 printk(KERN_INFO "Cache parity protection %sabled\n",
1062 (errctl & ERRCTL_PE) ? "en" : "dis");
1063
1064 if (l2parity_present) {
1065 if (l1parity_present && l1parity)
1066 errctl ^= ERRCTL_L2P;
1067 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1068 (errctl & ERRCTL_L2P) ? "en" : "dis");
1069 }
1070 }
1071 break;
1072
1073 case CPU_5KC:
1074 write_c0_ecc(0x80000000);
1075 back_to_back_c0_hazard();
1076 /* Set the PE bit (bit 31) in the c0_errctl register. */
1077 printk(KERN_INFO "Cache parity protection %sabled\n",
1078 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1079 break;
1080 case CPU_20KC:
1081 case CPU_25KF:
1082 /* Clear the DE bit (bit 16) in the c0_status register. */
1083 printk(KERN_INFO "Enable cache parity protection for "
1084 "MIPS 20KC/25KF CPUs.\n");
1085 clear_c0_status(ST0_DE);
1086 break;
1087 default:
1088 break;
1089 }
1090 }
1091
1092 asmlinkage void cache_parity_error(void)
1093 {
1094 const int field = 2 * sizeof(unsigned long);
1095 unsigned int reg_val;
1096
1097 /* For the moment, report the problem and hang. */
1098 printk("Cache error exception:\n");
1099 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1100 reg_val = read_c0_cacheerr();
1101 printk("c0_cacheerr == %08x\n", reg_val);
1102
1103 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1104 reg_val & (1<<30) ? "secondary" : "primary",
1105 reg_val & (1<<31) ? "data" : "insn");
1106 printk("Error bits: %s%s%s%s%s%s%s\n",
1107 reg_val & (1<<29) ? "ED " : "",
1108 reg_val & (1<<28) ? "ET " : "",
1109 reg_val & (1<<26) ? "EE " : "",
1110 reg_val & (1<<25) ? "EB " : "",
1111 reg_val & (1<<24) ? "EI " : "",
1112 reg_val & (1<<23) ? "E1 " : "",
1113 reg_val & (1<<22) ? "E0 " : "");
1114 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1115
1116 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1117 if (reg_val & (1<<22))
1118 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1119
1120 if (reg_val & (1<<23))
1121 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1122 #endif
1123
1124 panic("Can't handle the cache error!");
1125 }
1126
1127 /*
1128 * SDBBP EJTAG debug exception handler.
1129 * We skip the instruction and return to the next instruction.
1130 */
1131 void ejtag_exception_handler(struct pt_regs *regs)
1132 {
1133 const int field = 2 * sizeof(unsigned long);
1134 unsigned long depc, old_epc;
1135 unsigned int debug;
1136
1137 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1138 depc = read_c0_depc();
1139 debug = read_c0_debug();
1140 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1141 if (debug & 0x80000000) {
1142 /*
1143 * In branch delay slot.
1144 * We cheat a little bit here and use EPC to calculate the
1145 * debug return address (DEPC). EPC is restored after the
1146 * calculation.
1147 */
1148 old_epc = regs->cp0_epc;
1149 regs->cp0_epc = depc;
1150 __compute_return_epc(regs);
1151 depc = regs->cp0_epc;
1152 regs->cp0_epc = old_epc;
1153 } else
1154 depc += 4;
1155 write_c0_depc(depc);
1156
1157 #if 0
1158 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1159 write_c0_debug(debug | 0x100);
1160 #endif
1161 }
1162
1163 /*
1164 * NMI exception handler.
1165 */
1166 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1167 {
1168 bust_spinlocks(1);
1169 printk("NMI taken!!!!\n");
1170 die("NMI", regs);
1171 }
1172
1173 #define VECTORSPACING 0x100 /* for EI/VI mode */
1174
1175 unsigned long ebase;
1176 unsigned long exception_handlers[32];
1177 unsigned long vi_handlers[64];
1178
1179 /*
1180 * As a side effect of the way this is implemented we're limited
1181 * to interrupt handlers in the address range from
1182 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1183 */
1184 void *set_except_vector(int n, void *addr)
1185 {
1186 unsigned long handler = (unsigned long) addr;
1187 unsigned long old_handler = exception_handlers[n];
1188
1189 exception_handlers[n] = handler;
1190 if (n == 0 && cpu_has_divec) {
1191 *(u32 *)(ebase + 0x200) = 0x08000000 |
1192 (0x03ffffff & (handler >> 2));
1193 flush_icache_range(ebase + 0x200, ebase + 0x204);
1194 }
1195 return (void *)old_handler;
1196 }
1197
1198 static asmlinkage void do_default_vi(void)
1199 {
1200 show_regs(get_irq_regs());
1201 panic("Caught unexpected vectored interrupt.");
1202 }
1203
1204 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1205 {
1206 unsigned long handler;
1207 unsigned long old_handler = vi_handlers[n];
1208 int srssets = current_cpu_data.srsets;
1209 u32 *w;
1210 unsigned char *b;
1211
1212 if (!cpu_has_veic && !cpu_has_vint)
1213 BUG();
1214
1215 if (addr == NULL) {
1216 handler = (unsigned long) do_default_vi;
1217 srs = 0;
1218 } else
1219 handler = (unsigned long) addr;
1220 vi_handlers[n] = (unsigned long) addr;
1221
1222 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1223
1224 if (srs >= srssets)
1225 panic("Shadow register set %d not supported", srs);
1226
1227 if (cpu_has_veic) {
1228 if (board_bind_eic_interrupt)
1229 board_bind_eic_interrupt(n, srs);
1230 } else if (cpu_has_vint) {
1231 /* SRSMap is only defined if shadow sets are implemented */
1232 if (srssets > 1)
1233 change_c0_srsmap(0xf << n*4, srs << n*4);
1234 }
1235
1236 if (srs == 0) {
1237 /*
1238 * If no shadow set is selected then use the default handler
1239 * that does normal register saving and a standard interrupt exit
1240 */
1241
1242 extern char except_vec_vi, except_vec_vi_lui;
1243 extern char except_vec_vi_ori, except_vec_vi_end;
1244 #ifdef CONFIG_MIPS_MT_SMTC
1245 /*
1246 * We need to provide the SMTC vectored interrupt handler
1247 * not only with the address of the handler, but with the
1248 * Status.IM bit to be masked before going there.
1249 */
1250 extern char except_vec_vi_mori;
1251 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1252 #endif /* CONFIG_MIPS_MT_SMTC */
1253 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1254 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1255 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1256
1257 if (handler_len > VECTORSPACING) {
1258 /*
1259 * Sigh... panicing won't help as the console
1260 * is probably not configured :(
1261 */
1262 panic("VECTORSPACING too small");
1263 }
1264
1265 memcpy(b, &except_vec_vi, handler_len);
1266 #ifdef CONFIG_MIPS_MT_SMTC
1267 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1268
1269 w = (u32 *)(b + mori_offset);
1270 *w = (*w & 0xffff0000) | (0x100 << n);
1271 #endif /* CONFIG_MIPS_MT_SMTC */
1272 w = (u32 *)(b + lui_offset);
1273 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1274 w = (u32 *)(b + ori_offset);
1275 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1276 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1277 }
1278 else {
1279 /*
1280 * In other cases jump directly to the interrupt handler
1281 *
1282 * It is the handlers responsibility to save registers if required
1283 * (eg hi/lo) and return from the exception using "eret"
1284 */
1285 w = (u32 *)b;
1286 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1287 *w = 0;
1288 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1289 }
1290
1291 return (void *)old_handler;
1292 }
1293
1294 void *set_vi_handler(int n, vi_handler_t addr)
1295 {
1296 return set_vi_srs_handler(n, addr, 0);
1297 }
1298
1299 /*
1300 * This is used by native signal handling
1301 */
1302 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
1303 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
1304
1305 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
1306 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
1307
1308 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
1309 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
1310
1311 #ifdef CONFIG_SMP
1312 static int smp_save_fp_context(struct sigcontext __user *sc)
1313 {
1314 return raw_cpu_has_fpu
1315 ? _save_fp_context(sc)
1316 : fpu_emulator_save_context(sc);
1317 }
1318
1319 static int smp_restore_fp_context(struct sigcontext __user *sc)
1320 {
1321 return raw_cpu_has_fpu
1322 ? _restore_fp_context(sc)
1323 : fpu_emulator_restore_context(sc);
1324 }
1325 #endif
1326
1327 static inline void signal_init(void)
1328 {
1329 #ifdef CONFIG_SMP
1330 /* For now just do the cpu_has_fpu check when the functions are invoked */
1331 save_fp_context = smp_save_fp_context;
1332 restore_fp_context = smp_restore_fp_context;
1333 #else
1334 if (cpu_has_fpu) {
1335 save_fp_context = _save_fp_context;
1336 restore_fp_context = _restore_fp_context;
1337 } else {
1338 save_fp_context = fpu_emulator_save_context;
1339 restore_fp_context = fpu_emulator_restore_context;
1340 }
1341 #endif
1342 }
1343
1344 #ifdef CONFIG_MIPS32_COMPAT
1345
1346 /*
1347 * This is used by 32-bit signal stuff on the 64-bit kernel
1348 */
1349 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
1350 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
1351
1352 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
1353 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
1354
1355 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
1356 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
1357
1358 static inline void signal32_init(void)
1359 {
1360 if (cpu_has_fpu) {
1361 save_fp_context32 = _save_fp_context32;
1362 restore_fp_context32 = _restore_fp_context32;
1363 } else {
1364 save_fp_context32 = fpu_emulator_save_context32;
1365 restore_fp_context32 = fpu_emulator_restore_context32;
1366 }
1367 }
1368 #endif
1369
1370 extern void cpu_cache_init(void);
1371 extern void tlb_init(void);
1372 extern void flush_tlb_handlers(void);
1373
1374 /*
1375 * Timer interrupt
1376 */
1377 int cp0_compare_irq;
1378
1379 /*
1380 * Performance counter IRQ or -1 if shared with timer
1381 */
1382 int cp0_perfcount_irq;
1383 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1384
1385 static int __cpuinitdata noulri;
1386
1387 static int __init ulri_disable(char *s)
1388 {
1389 pr_info("Disabling ulri\n");
1390 noulri = 1;
1391
1392 return 1;
1393 }
1394 __setup("noulri", ulri_disable);
1395
1396 void __cpuinit per_cpu_trap_init(void)
1397 {
1398 unsigned int cpu = smp_processor_id();
1399 unsigned int status_set = ST0_CU0;
1400 #ifdef CONFIG_MIPS_MT_SMTC
1401 int secondaryTC = 0;
1402 int bootTC = (cpu == 0);
1403
1404 /*
1405 * Only do per_cpu_trap_init() for first TC of Each VPE.
1406 * Note that this hack assumes that the SMTC init code
1407 * assigns TCs consecutively and in ascending order.
1408 */
1409
1410 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1411 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1412 secondaryTC = 1;
1413 #endif /* CONFIG_MIPS_MT_SMTC */
1414
1415 /*
1416 * Disable coprocessors and select 32-bit or 64-bit addressing
1417 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1418 * flag that some firmware may have left set and the TS bit (for
1419 * IP27). Set XX for ISA IV code to work.
1420 */
1421 #ifdef CONFIG_64BIT
1422 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1423 #endif
1424 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1425 status_set |= ST0_XX;
1426 if (cpu_has_dsp)
1427 status_set |= ST0_MX;
1428
1429 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1430 status_set);
1431
1432 if (cpu_has_mips_r2) {
1433 unsigned int enable = 0x0000000f;
1434
1435 if (!noulri && cpu_has_userlocal)
1436 enable |= (1 << 29);
1437
1438 write_c0_hwrena(enable);
1439 }
1440
1441 #ifdef CONFIG_MIPS_MT_SMTC
1442 if (!secondaryTC) {
1443 #endif /* CONFIG_MIPS_MT_SMTC */
1444
1445 if (cpu_has_veic || cpu_has_vint) {
1446 write_c0_ebase(ebase);
1447 /* Setting vector spacing enables EI/VI mode */
1448 change_c0_intctl(0x3e0, VECTORSPACING);
1449 }
1450 if (cpu_has_divec) {
1451 if (cpu_has_mipsmt) {
1452 unsigned int vpflags = dvpe();
1453 set_c0_cause(CAUSEF_IV);
1454 evpe(vpflags);
1455 } else
1456 set_c0_cause(CAUSEF_IV);
1457 }
1458
1459 /*
1460 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1461 *
1462 * o read IntCtl.IPTI to determine the timer interrupt
1463 * o read IntCtl.IPPCI to determine the performance counter interrupt
1464 */
1465 if (cpu_has_mips_r2) {
1466 cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
1467 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
1468 if (cp0_perfcount_irq == cp0_compare_irq)
1469 cp0_perfcount_irq = -1;
1470 } else {
1471 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1472 cp0_perfcount_irq = -1;
1473 }
1474
1475 #ifdef CONFIG_MIPS_MT_SMTC
1476 }
1477 #endif /* CONFIG_MIPS_MT_SMTC */
1478
1479 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1480 TLBMISS_HANDLER_SETUP();
1481
1482 atomic_inc(&init_mm.mm_count);
1483 current->active_mm = &init_mm;
1484 BUG_ON(current->mm);
1485 enter_lazy_tlb(&init_mm, current);
1486
1487 #ifdef CONFIG_MIPS_MT_SMTC
1488 if (bootTC) {
1489 #endif /* CONFIG_MIPS_MT_SMTC */
1490 cpu_cache_init();
1491 tlb_init();
1492 #ifdef CONFIG_MIPS_MT_SMTC
1493 } else if (!secondaryTC) {
1494 /*
1495 * First TC in non-boot VPE must do subset of tlb_init()
1496 * for MMU countrol registers.
1497 */
1498 write_c0_pagemask(PM_DEFAULT_MASK);
1499 write_c0_wired(0);
1500 }
1501 #endif /* CONFIG_MIPS_MT_SMTC */
1502 }
1503
1504 /* Install CPU exception handler */
1505 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1506 {
1507 memcpy((void *)(ebase + offset), addr, size);
1508 flush_icache_range(ebase + offset, ebase + offset + size);
1509 }
1510
1511 static char panic_null_cerr[] __cpuinitdata =
1512 "Trying to set NULL cache error exception handler";
1513
1514 /* Install uncached CPU exception handler */
1515 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1516 unsigned long size)
1517 {
1518 #ifdef CONFIG_32BIT
1519 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1520 #endif
1521 #ifdef CONFIG_64BIT
1522 unsigned long uncached_ebase = TO_UNCAC(ebase);
1523 #endif
1524
1525 if (!addr)
1526 panic(panic_null_cerr);
1527
1528 memcpy((void *)(uncached_ebase + offset), addr, size);
1529 }
1530
1531 static int __initdata rdhwr_noopt;
1532 static int __init set_rdhwr_noopt(char *str)
1533 {
1534 rdhwr_noopt = 1;
1535 return 1;
1536 }
1537
1538 __setup("rdhwr_noopt", set_rdhwr_noopt);
1539
1540 void __init trap_init(void)
1541 {
1542 extern char except_vec3_generic, except_vec3_r4000;
1543 extern char except_vec4;
1544 unsigned long i;
1545
1546 if (cpu_has_veic || cpu_has_vint)
1547 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
1548 else
1549 ebase = CAC_BASE;
1550
1551 per_cpu_trap_init();
1552
1553 /*
1554 * Copy the generic exception handlers to their final destination.
1555 * This will be overriden later as suitable for a particular
1556 * configuration.
1557 */
1558 set_handler(0x180, &except_vec3_generic, 0x80);
1559
1560 /*
1561 * Setup default vectors
1562 */
1563 for (i = 0; i <= 31; i++)
1564 set_except_vector(i, handle_reserved);
1565
1566 /*
1567 * Copy the EJTAG debug exception vector handler code to it's final
1568 * destination.
1569 */
1570 if (cpu_has_ejtag && board_ejtag_handler_setup)
1571 board_ejtag_handler_setup();
1572
1573 /*
1574 * Only some CPUs have the watch exceptions.
1575 */
1576 if (cpu_has_watch)
1577 set_except_vector(23, handle_watch);
1578
1579 /*
1580 * Initialise interrupt handlers
1581 */
1582 if (cpu_has_veic || cpu_has_vint) {
1583 int nvec = cpu_has_veic ? 64 : 8;
1584 for (i = 0; i < nvec; i++)
1585 set_vi_handler(i, NULL);
1586 }
1587 else if (cpu_has_divec)
1588 set_handler(0x200, &except_vec4, 0x8);
1589
1590 /*
1591 * Some CPUs can enable/disable for cache parity detection, but does
1592 * it different ways.
1593 */
1594 parity_protection_init();
1595
1596 /*
1597 * The Data Bus Errors / Instruction Bus Errors are signaled
1598 * by external hardware. Therefore these two exceptions
1599 * may have board specific handlers.
1600 */
1601 if (board_be_init)
1602 board_be_init();
1603
1604 set_except_vector(0, handle_int);
1605 set_except_vector(1, handle_tlbm);
1606 set_except_vector(2, handle_tlbl);
1607 set_except_vector(3, handle_tlbs);
1608
1609 set_except_vector(4, handle_adel);
1610 set_except_vector(5, handle_ades);
1611
1612 set_except_vector(6, handle_ibe);
1613 set_except_vector(7, handle_dbe);
1614
1615 set_except_vector(8, handle_sys);
1616 set_except_vector(9, handle_bp);
1617 set_except_vector(10, rdhwr_noopt ? handle_ri :
1618 (cpu_has_vtag_icache ?
1619 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1620 set_except_vector(11, handle_cpu);
1621 set_except_vector(12, handle_ov);
1622 set_except_vector(13, handle_tr);
1623
1624 if (current_cpu_type() == CPU_R6000 ||
1625 current_cpu_type() == CPU_R6000A) {
1626 /*
1627 * The R6000 is the only R-series CPU that features a machine
1628 * check exception (similar to the R4000 cache error) and
1629 * unaligned ldc1/sdc1 exception. The handlers have not been
1630 * written yet. Well, anyway there is no R6000 machine on the
1631 * current list of targets for Linux/MIPS.
1632 * (Duh, crap, there is someone with a triple R6k machine)
1633 */
1634 //set_except_vector(14, handle_mc);
1635 //set_except_vector(15, handle_ndc);
1636 }
1637
1638
1639 if (board_nmi_handler_setup)
1640 board_nmi_handler_setup();
1641
1642 if (cpu_has_fpu && !cpu_has_nofpuex)
1643 set_except_vector(15, handle_fpe);
1644
1645 set_except_vector(22, handle_mdmx);
1646
1647 if (cpu_has_mcheck)
1648 set_except_vector(24, handle_mcheck);
1649
1650 if (cpu_has_mipsmt)
1651 set_except_vector(25, handle_mt);
1652
1653 set_except_vector(26, handle_dsp);
1654
1655 if (cpu_has_vce)
1656 /* Special exception: R4[04]00 uses also the divec space. */
1657 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1658 else if (cpu_has_4kex)
1659 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1660 else
1661 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1662
1663 signal_init();
1664 #ifdef CONFIG_MIPS32_COMPAT
1665 signal32_init();
1666 #endif
1667
1668 flush_icache_range(ebase, ebase + 0x400);
1669 flush_tlb_handlers();
1670 }
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