1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
3 * Copyright 1996-1999 Thomas Bogendoerfer
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
13 * This driver is for PCnet32 and PCnetPCI based ethercards
15 /**************************************************************************
17 * Fixed a few bugs, related to running the controller in 32bit mode.
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
22 *************************************************************************/
24 #define DRV_NAME "pcnet32"
25 #ifdef CONFIG_PCNET32_NAPI
26 #define DRV_VERSION "1.34-NAPI"
28 #define DRV_VERSION "1.34"
30 #define DRV_RELDATE "14.Aug.2007"
31 #define PFX DRV_NAME ": "
33 static const char *const version
=
34 DRV_NAME
".c:v" DRV_VERSION
" " DRV_RELDATE
" tsbogend@alpha.franken.de\n";
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/string.h>
39 #include <linux/errno.h>
40 #include <linux/ioport.h>
41 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/delay.h>
45 #include <linux/init.h>
46 #include <linux/ethtool.h>
47 #include <linux/mii.h>
48 #include <linux/crc32.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/skbuff.h>
52 #include <linux/spinlock.h>
53 #include <linux/moduleparam.h>
54 #include <linux/bitops.h>
58 #include <asm/uaccess.h>
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
64 static struct pci_device_id pcnet32_pci_tbl
[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE_HOME
), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE
), },
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT
, PCI_DEVICE_ID_AMD_LANCE
),
73 .class = (PCI_CLASS_NETWORK_ETHERNET
<< 8), .class_mask
= 0xffff00, },
75 { } /* terminate list */
78 MODULE_DEVICE_TABLE(pci
, pcnet32_pci_tbl
);
80 static int cards_found
;
85 static unsigned int pcnet32_portlist
[] __initdata
=
86 { 0x300, 0x320, 0x340, 0x360, 0 };
88 static int pcnet32_debug
= 0;
89 static int tx_start
= 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90 static int pcnet32vlb
; /* check for VLB cards ? */
92 static struct net_device
*pcnet32_dev
;
94 static int max_interrupt_work
= 2;
95 static int rx_copybreak
= 200;
97 #define PCNET32_PORT_AUI 0x00
98 #define PCNET32_PORT_10BT 0x01
99 #define PCNET32_PORT_GPSI 0x02
100 #define PCNET32_PORT_MII 0x03
102 #define PCNET32_PORT_PORTSEL 0x03
103 #define PCNET32_PORT_ASEL 0x04
104 #define PCNET32_PORT_100 0x40
105 #define PCNET32_PORT_FD 0x80
107 #define PCNET32_DMA_MASK 0xffffffff
109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
113 * table to translate option values from tulip
114 * to internal options
116 static const unsigned char options_mapping
[] = {
117 PCNET32_PORT_ASEL
, /* 0 Auto-select */
118 PCNET32_PORT_AUI
, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI
, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL
, /* 3 not supported */
121 PCNET32_PORT_10BT
| PCNET32_PORT_FD
, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL
, /* 5 not supported */
123 PCNET32_PORT_ASEL
, /* 6 not supported */
124 PCNET32_PORT_ASEL
, /* 7 not supported */
125 PCNET32_PORT_ASEL
, /* 8 not supported */
126 PCNET32_PORT_MII
, /* 9 MII 10baseT */
127 PCNET32_PORT_MII
| PCNET32_PORT_FD
, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII
, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT
, /* 12 10BaseT */
130 PCNET32_PORT_MII
| PCNET32_PORT_100
, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII
| PCNET32_PORT_100
| PCNET32_PORT_FD
,
133 PCNET32_PORT_ASEL
/* 15 not supported */
136 static const char pcnet32_gstrings_test
[][ETH_GSTRING_LEN
] = {
137 "Loopback test (offline)"
140 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
142 #define PCNET32_NUM_REGS 136
144 #define MAX_UNITS 8 /* More are supported, limit only on options */
145 static int options
[MAX_UNITS
];
146 static int full_duplex
[MAX_UNITS
];
147 static int homepna
[MAX_UNITS
];
150 * Theory of Operation
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
164 #ifndef PCNET32_LOG_TX_BUFFERS
165 #define PCNET32_LOG_TX_BUFFERS 4
166 #define PCNET32_LOG_RX_BUFFERS 5
167 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168 #define PCNET32_LOG_MAX_RX_BUFFERS 9
171 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
172 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
174 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
175 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
177 #define PKT_BUF_SZ 1544
179 /* Offsets from base I/O address. */
180 #define PCNET32_WIO_RDP 0x10
181 #define PCNET32_WIO_RAP 0x12
182 #define PCNET32_WIO_RESET 0x14
183 #define PCNET32_WIO_BDP 0x16
185 #define PCNET32_DWIO_RDP 0x10
186 #define PCNET32_DWIO_RAP 0x14
187 #define PCNET32_DWIO_RESET 0x18
188 #define PCNET32_DWIO_BDP 0x1C
190 #define PCNET32_TOTAL_SIZE 0x20
193 #define CSR0_INIT 0x1
194 #define CSR0_START 0x2
195 #define CSR0_STOP 0x4
196 #define CSR0_TXPOLL 0x8
197 #define CSR0_INTEN 0x40
198 #define CSR0_IDON 0x0100
199 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200 #define PCNET32_INIT_LOW 1
201 #define PCNET32_INIT_HIGH 2
205 #define CSR5_SUSPEND 0x0001
207 #define PCNET32_MC_FILTER 8
209 #define PCNET32_79C970A 0x2621
211 /* The PCNET32 Rx and Tx ring descriptors. */
212 struct pcnet32_rx_head
{
214 s16 buf_length
; /* two`s complement of length */
220 struct pcnet32_tx_head
{
222 s16 length
; /* two`s complement of length */
228 /* The PCNET32 32-Bit initialization block, described in databook. */
229 struct pcnet32_init_block
{
235 /* Receive and transmit ring base, along with extra bits. */
240 /* PCnet32 access functions */
241 struct pcnet32_access
{
242 u16 (*read_csr
) (unsigned long, int);
243 void (*write_csr
) (unsigned long, int, u16
);
244 u16 (*read_bcr
) (unsigned long, int);
245 void (*write_bcr
) (unsigned long, int, u16
);
246 u16 (*read_rap
) (unsigned long);
247 void (*write_rap
) (unsigned long, u16
);
248 void (*reset
) (unsigned long);
252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using pci_alloc_consistent().
255 struct pcnet32_private
{
256 struct pcnet32_init_block
*init_block
;
257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
258 struct pcnet32_rx_head
*rx_ring
;
259 struct pcnet32_tx_head
*tx_ring
;
260 dma_addr_t init_dma_addr
;/* DMA address of beginning of the init block,
261 returned by pci_alloc_consistent */
262 struct pci_dev
*pci_dev
;
264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
265 struct sk_buff
**tx_skbuff
;
266 struct sk_buff
**rx_skbuff
;
267 dma_addr_t
*tx_dma_addr
;
268 dma_addr_t
*rx_dma_addr
;
269 struct pcnet32_access a
;
270 spinlock_t lock
; /* Guard lock */
271 unsigned int cur_rx
, cur_tx
; /* The next free ring entry */
272 unsigned int rx_ring_size
; /* current rx ring size */
273 unsigned int tx_ring_size
; /* current tx ring size */
274 unsigned int rx_mod_mask
; /* rx ring modular mask */
275 unsigned int tx_mod_mask
; /* tx ring modular mask */
276 unsigned short rx_len_bits
;
277 unsigned short tx_len_bits
;
278 dma_addr_t rx_ring_dma_addr
;
279 dma_addr_t tx_ring_dma_addr
;
280 unsigned int dirty_rx
, /* ring entries to be freed. */
283 struct net_device
*dev
;
284 struct napi_struct napi
;
285 struct net_device_stats stats
;
287 char phycount
; /* number of phys found */
289 unsigned int shared_irq
:1, /* shared irq possible */
290 dxsuflo
:1, /* disable transmit stop on uflo */
291 mii
:1; /* mii port available */
292 struct net_device
*next
;
293 struct mii_if_info mii_if
;
294 struct timer_list watchdog_timer
;
295 struct timer_list blink_timer
;
296 u32 msg_enable
; /* debug message level */
298 /* each bit indicates an available PHY */
300 unsigned short chip_version
; /* which variant this is */
303 static int pcnet32_probe_pci(struct pci_dev
*, const struct pci_device_id
*);
304 static int pcnet32_probe1(unsigned long, int, struct pci_dev
*);
305 static int pcnet32_open(struct net_device
*);
306 static int pcnet32_init_ring(struct net_device
*);
307 static int pcnet32_start_xmit(struct sk_buff
*, struct net_device
*);
308 static void pcnet32_tx_timeout(struct net_device
*dev
);
309 static irqreturn_t
pcnet32_interrupt(int, void *);
310 static int pcnet32_close(struct net_device
*);
311 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*);
312 static void pcnet32_load_multicast(struct net_device
*dev
);
313 static void pcnet32_set_multicast_list(struct net_device
*);
314 static int pcnet32_ioctl(struct net_device
*, struct ifreq
*, int);
315 static void pcnet32_watchdog(struct net_device
*);
316 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
);
317 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
,
319 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
);
320 static void pcnet32_ethtool_test(struct net_device
*dev
,
321 struct ethtool_test
*eth_test
, u64
* data
);
322 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
);
323 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
);
324 static void pcnet32_led_blink_callback(struct net_device
*dev
);
325 static int pcnet32_get_regs_len(struct net_device
*dev
);
326 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
328 static void pcnet32_purge_tx_ring(struct net_device
*dev
);
329 static int pcnet32_alloc_ring(struct net_device
*dev
, char *name
);
330 static void pcnet32_free_ring(struct net_device
*dev
);
331 static void pcnet32_check_media(struct net_device
*dev
, int verbose
);
333 static u16
pcnet32_wio_read_csr(unsigned long addr
, int index
)
335 outw(index
, addr
+ PCNET32_WIO_RAP
);
336 return inw(addr
+ PCNET32_WIO_RDP
);
339 static void pcnet32_wio_write_csr(unsigned long addr
, int index
, u16 val
)
341 outw(index
, addr
+ PCNET32_WIO_RAP
);
342 outw(val
, addr
+ PCNET32_WIO_RDP
);
345 static u16
pcnet32_wio_read_bcr(unsigned long addr
, int index
)
347 outw(index
, addr
+ PCNET32_WIO_RAP
);
348 return inw(addr
+ PCNET32_WIO_BDP
);
351 static void pcnet32_wio_write_bcr(unsigned long addr
, int index
, u16 val
)
353 outw(index
, addr
+ PCNET32_WIO_RAP
);
354 outw(val
, addr
+ PCNET32_WIO_BDP
);
357 static u16
pcnet32_wio_read_rap(unsigned long addr
)
359 return inw(addr
+ PCNET32_WIO_RAP
);
362 static void pcnet32_wio_write_rap(unsigned long addr
, u16 val
)
364 outw(val
, addr
+ PCNET32_WIO_RAP
);
367 static void pcnet32_wio_reset(unsigned long addr
)
369 inw(addr
+ PCNET32_WIO_RESET
);
372 static int pcnet32_wio_check(unsigned long addr
)
374 outw(88, addr
+ PCNET32_WIO_RAP
);
375 return (inw(addr
+ PCNET32_WIO_RAP
) == 88);
378 static struct pcnet32_access pcnet32_wio
= {
379 .read_csr
= pcnet32_wio_read_csr
,
380 .write_csr
= pcnet32_wio_write_csr
,
381 .read_bcr
= pcnet32_wio_read_bcr
,
382 .write_bcr
= pcnet32_wio_write_bcr
,
383 .read_rap
= pcnet32_wio_read_rap
,
384 .write_rap
= pcnet32_wio_write_rap
,
385 .reset
= pcnet32_wio_reset
388 static u16
pcnet32_dwio_read_csr(unsigned long addr
, int index
)
390 outl(index
, addr
+ PCNET32_DWIO_RAP
);
391 return (inl(addr
+ PCNET32_DWIO_RDP
) & 0xffff);
394 static void pcnet32_dwio_write_csr(unsigned long addr
, int index
, u16 val
)
396 outl(index
, addr
+ PCNET32_DWIO_RAP
);
397 outl(val
, addr
+ PCNET32_DWIO_RDP
);
400 static u16
pcnet32_dwio_read_bcr(unsigned long addr
, int index
)
402 outl(index
, addr
+ PCNET32_DWIO_RAP
);
403 return (inl(addr
+ PCNET32_DWIO_BDP
) & 0xffff);
406 static void pcnet32_dwio_write_bcr(unsigned long addr
, int index
, u16 val
)
408 outl(index
, addr
+ PCNET32_DWIO_RAP
);
409 outl(val
, addr
+ PCNET32_DWIO_BDP
);
412 static u16
pcnet32_dwio_read_rap(unsigned long addr
)
414 return (inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff);
417 static void pcnet32_dwio_write_rap(unsigned long addr
, u16 val
)
419 outl(val
, addr
+ PCNET32_DWIO_RAP
);
422 static void pcnet32_dwio_reset(unsigned long addr
)
424 inl(addr
+ PCNET32_DWIO_RESET
);
427 static int pcnet32_dwio_check(unsigned long addr
)
429 outl(88, addr
+ PCNET32_DWIO_RAP
);
430 return ((inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff) == 88);
433 static struct pcnet32_access pcnet32_dwio
= {
434 .read_csr
= pcnet32_dwio_read_csr
,
435 .write_csr
= pcnet32_dwio_write_csr
,
436 .read_bcr
= pcnet32_dwio_read_bcr
,
437 .write_bcr
= pcnet32_dwio_write_bcr
,
438 .read_rap
= pcnet32_dwio_read_rap
,
439 .write_rap
= pcnet32_dwio_write_rap
,
440 .reset
= pcnet32_dwio_reset
443 static void pcnet32_netif_stop(struct net_device
*dev
)
445 struct pcnet32_private
*lp
= netdev_priv(dev
);
446 dev
->trans_start
= jiffies
;
447 #ifdef CONFIG_PCNET32_NAPI
448 napi_disable(&lp
->napi
);
450 netif_tx_disable(dev
);
453 static void pcnet32_netif_start(struct net_device
*dev
)
455 struct pcnet32_private
*lp
= netdev_priv(dev
);
456 netif_wake_queue(dev
);
457 #ifdef CONFIG_PCNET32_NAPI
458 napi_enable(&lp
->napi
);
463 * Allocate space for the new sized tx ring.
465 * Save new resources.
466 * Any failure keeps old resources.
467 * Must be called with lp->lock held.
469 static void pcnet32_realloc_tx_ring(struct net_device
*dev
,
470 struct pcnet32_private
*lp
,
473 dma_addr_t new_ring_dma_addr
;
474 dma_addr_t
*new_dma_addr_list
;
475 struct pcnet32_tx_head
*new_tx_ring
;
476 struct sk_buff
**new_skb_list
;
478 pcnet32_purge_tx_ring(dev
);
480 new_tx_ring
= pci_alloc_consistent(lp
->pci_dev
,
481 sizeof(struct pcnet32_tx_head
) *
484 if (new_tx_ring
== NULL
) {
485 if (netif_msg_drv(lp
))
487 "%s: Consistent memory allocation failed.\n",
491 memset(new_tx_ring
, 0, sizeof(struct pcnet32_tx_head
) * (1 << size
));
493 new_dma_addr_list
= kcalloc((1 << size
), sizeof(dma_addr_t
),
495 if (!new_dma_addr_list
) {
496 if (netif_msg_drv(lp
))
498 "%s: Memory allocation failed.\n", dev
->name
);
499 goto free_new_tx_ring
;
502 new_skb_list
= kcalloc((1 << size
), sizeof(struct sk_buff
*),
505 if (netif_msg_drv(lp
))
507 "%s: Memory allocation failed.\n", dev
->name
);
511 kfree(lp
->tx_skbuff
);
512 kfree(lp
->tx_dma_addr
);
513 pci_free_consistent(lp
->pci_dev
,
514 sizeof(struct pcnet32_tx_head
) *
515 lp
->tx_ring_size
, lp
->tx_ring
,
516 lp
->tx_ring_dma_addr
);
518 lp
->tx_ring_size
= (1 << size
);
519 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
520 lp
->tx_len_bits
= (size
<< 12);
521 lp
->tx_ring
= new_tx_ring
;
522 lp
->tx_ring_dma_addr
= new_ring_dma_addr
;
523 lp
->tx_dma_addr
= new_dma_addr_list
;
524 lp
->tx_skbuff
= new_skb_list
;
528 kfree(new_dma_addr_list
);
530 pci_free_consistent(lp
->pci_dev
,
531 sizeof(struct pcnet32_tx_head
) *
539 * Allocate space for the new sized rx ring.
540 * Re-use old receive buffers.
541 * alloc extra buffers
542 * free unneeded buffers
543 * free unneeded buffers
544 * Save new resources.
545 * Any failure keeps old resources.
546 * Must be called with lp->lock held.
548 static void pcnet32_realloc_rx_ring(struct net_device
*dev
,
549 struct pcnet32_private
*lp
,
552 dma_addr_t new_ring_dma_addr
;
553 dma_addr_t
*new_dma_addr_list
;
554 struct pcnet32_rx_head
*new_rx_ring
;
555 struct sk_buff
**new_skb_list
;
558 new_rx_ring
= pci_alloc_consistent(lp
->pci_dev
,
559 sizeof(struct pcnet32_rx_head
) *
562 if (new_rx_ring
== NULL
) {
563 if (netif_msg_drv(lp
))
565 "%s: Consistent memory allocation failed.\n",
569 memset(new_rx_ring
, 0, sizeof(struct pcnet32_rx_head
) * (1 << size
));
571 new_dma_addr_list
= kcalloc((1 << size
), sizeof(dma_addr_t
),
573 if (!new_dma_addr_list
) {
574 if (netif_msg_drv(lp
))
576 "%s: Memory allocation failed.\n", dev
->name
);
577 goto free_new_rx_ring
;
580 new_skb_list
= kcalloc((1 << size
), sizeof(struct sk_buff
*),
583 if (netif_msg_drv(lp
))
585 "%s: Memory allocation failed.\n", dev
->name
);
589 /* first copy the current receive buffers */
590 overlap
= min(size
, lp
->rx_ring_size
);
591 for (new = 0; new < overlap
; new++) {
592 new_rx_ring
[new] = lp
->rx_ring
[new];
593 new_dma_addr_list
[new] = lp
->rx_dma_addr
[new];
594 new_skb_list
[new] = lp
->rx_skbuff
[new];
596 /* now allocate any new buffers needed */
597 for (; new < size
; new++ ) {
598 struct sk_buff
*rx_skbuff
;
599 new_skb_list
[new] = dev_alloc_skb(PKT_BUF_SZ
);
600 if (!(rx_skbuff
= new_skb_list
[new])) {
601 /* keep the original lists and buffers */
602 if (netif_msg_drv(lp
))
604 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
608 skb_reserve(rx_skbuff
, 2);
610 new_dma_addr_list
[new] =
611 pci_map_single(lp
->pci_dev
, rx_skbuff
->data
,
612 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
613 new_rx_ring
[new].base
= (u32
) le32_to_cpu(new_dma_addr_list
[new]);
614 new_rx_ring
[new].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
615 new_rx_ring
[new].status
= le16_to_cpu(0x8000);
617 /* and free any unneeded buffers */
618 for (; new < lp
->rx_ring_size
; new++) {
619 if (lp
->rx_skbuff
[new]) {
620 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[new],
621 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
622 dev_kfree_skb(lp
->rx_skbuff
[new]);
626 kfree(lp
->rx_skbuff
);
627 kfree(lp
->rx_dma_addr
);
628 pci_free_consistent(lp
->pci_dev
,
629 sizeof(struct pcnet32_rx_head
) *
630 lp
->rx_ring_size
, lp
->rx_ring
,
631 lp
->rx_ring_dma_addr
);
633 lp
->rx_ring_size
= (1 << size
);
634 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
635 lp
->rx_len_bits
= (size
<< 4);
636 lp
->rx_ring
= new_rx_ring
;
637 lp
->rx_ring_dma_addr
= new_ring_dma_addr
;
638 lp
->rx_dma_addr
= new_dma_addr_list
;
639 lp
->rx_skbuff
= new_skb_list
;
643 for (; --new >= lp
->rx_ring_size
; ) {
644 if (new_skb_list
[new]) {
645 pci_unmap_single(lp
->pci_dev
, new_dma_addr_list
[new],
646 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
647 dev_kfree_skb(new_skb_list
[new]);
652 kfree(new_dma_addr_list
);
654 pci_free_consistent(lp
->pci_dev
,
655 sizeof(struct pcnet32_rx_head
) *
662 static void pcnet32_purge_rx_ring(struct net_device
*dev
)
664 struct pcnet32_private
*lp
= netdev_priv(dev
);
667 /* free all allocated skbuffs */
668 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
669 lp
->rx_ring
[i
].status
= 0; /* CPU owns buffer */
670 wmb(); /* Make sure adapter sees owner change */
671 if (lp
->rx_skbuff
[i
]) {
672 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[i
],
673 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
674 dev_kfree_skb_any(lp
->rx_skbuff
[i
]);
676 lp
->rx_skbuff
[i
] = NULL
;
677 lp
->rx_dma_addr
[i
] = 0;
681 #ifdef CONFIG_NET_POLL_CONTROLLER
682 static void pcnet32_poll_controller(struct net_device
*dev
)
684 disable_irq(dev
->irq
);
685 pcnet32_interrupt(0, dev
);
686 enable_irq(dev
->irq
);
690 static int pcnet32_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
692 struct pcnet32_private
*lp
= netdev_priv(dev
);
697 spin_lock_irqsave(&lp
->lock
, flags
);
698 mii_ethtool_gset(&lp
->mii_if
, cmd
);
699 spin_unlock_irqrestore(&lp
->lock
, flags
);
705 static int pcnet32_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
707 struct pcnet32_private
*lp
= netdev_priv(dev
);
712 spin_lock_irqsave(&lp
->lock
, flags
);
713 r
= mii_ethtool_sset(&lp
->mii_if
, cmd
);
714 spin_unlock_irqrestore(&lp
->lock
, flags
);
719 static void pcnet32_get_drvinfo(struct net_device
*dev
,
720 struct ethtool_drvinfo
*info
)
722 struct pcnet32_private
*lp
= netdev_priv(dev
);
724 strcpy(info
->driver
, DRV_NAME
);
725 strcpy(info
->version
, DRV_VERSION
);
727 strcpy(info
->bus_info
, pci_name(lp
->pci_dev
));
729 sprintf(info
->bus_info
, "VLB 0x%lx", dev
->base_addr
);
732 static u32
pcnet32_get_link(struct net_device
*dev
)
734 struct pcnet32_private
*lp
= netdev_priv(dev
);
738 spin_lock_irqsave(&lp
->lock
, flags
);
740 r
= mii_link_ok(&lp
->mii_if
);
741 } else if (lp
->chip_version
>= PCNET32_79C970A
) {
742 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
743 r
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
744 } else { /* can not detect link on really old chips */
747 spin_unlock_irqrestore(&lp
->lock
, flags
);
752 static u32
pcnet32_get_msglevel(struct net_device
*dev
)
754 struct pcnet32_private
*lp
= netdev_priv(dev
);
755 return lp
->msg_enable
;
758 static void pcnet32_set_msglevel(struct net_device
*dev
, u32 value
)
760 struct pcnet32_private
*lp
= netdev_priv(dev
);
761 lp
->msg_enable
= value
;
764 static int pcnet32_nway_reset(struct net_device
*dev
)
766 struct pcnet32_private
*lp
= netdev_priv(dev
);
771 spin_lock_irqsave(&lp
->lock
, flags
);
772 r
= mii_nway_restart(&lp
->mii_if
);
773 spin_unlock_irqrestore(&lp
->lock
, flags
);
778 static void pcnet32_get_ringparam(struct net_device
*dev
,
779 struct ethtool_ringparam
*ering
)
781 struct pcnet32_private
*lp
= netdev_priv(dev
);
783 ering
->tx_max_pending
= TX_MAX_RING_SIZE
;
784 ering
->tx_pending
= lp
->tx_ring_size
;
785 ering
->rx_max_pending
= RX_MAX_RING_SIZE
;
786 ering
->rx_pending
= lp
->rx_ring_size
;
789 static int pcnet32_set_ringparam(struct net_device
*dev
,
790 struct ethtool_ringparam
*ering
)
792 struct pcnet32_private
*lp
= netdev_priv(dev
);
795 ulong ioaddr
= dev
->base_addr
;
798 if (ering
->rx_mini_pending
|| ering
->rx_jumbo_pending
)
801 if (netif_running(dev
))
802 pcnet32_netif_stop(dev
);
804 spin_lock_irqsave(&lp
->lock
, flags
);
805 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* stop the chip */
807 size
= min(ering
->tx_pending
, (unsigned int)TX_MAX_RING_SIZE
);
809 /* set the minimum ring size to 4, to allow the loopback test to work
812 for (i
= 2; i
<= PCNET32_LOG_MAX_TX_BUFFERS
; i
++) {
813 if (size
<= (1 << i
))
816 if ((1 << i
) != lp
->tx_ring_size
)
817 pcnet32_realloc_tx_ring(dev
, lp
, i
);
819 size
= min(ering
->rx_pending
, (unsigned int)RX_MAX_RING_SIZE
);
820 for (i
= 2; i
<= PCNET32_LOG_MAX_RX_BUFFERS
; i
++) {
821 if (size
<= (1 << i
))
824 if ((1 << i
) != lp
->rx_ring_size
)
825 pcnet32_realloc_rx_ring(dev
, lp
, i
);
827 lp
->napi
.weight
= lp
->rx_ring_size
/ 2;
829 if (netif_running(dev
)) {
830 pcnet32_netif_start(dev
);
831 pcnet32_restart(dev
, CSR0_NORMAL
);
834 spin_unlock_irqrestore(&lp
->lock
, flags
);
836 if (netif_msg_drv(lp
))
838 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev
->name
,
839 lp
->rx_ring_size
, lp
->tx_ring_size
);
844 static void pcnet32_get_strings(struct net_device
*dev
, u32 stringset
,
847 memcpy(data
, pcnet32_gstrings_test
, sizeof(pcnet32_gstrings_test
));
850 static int pcnet32_self_test_count(struct net_device
*dev
)
852 return PCNET32_TEST_LEN
;
855 static void pcnet32_ethtool_test(struct net_device
*dev
,
856 struct ethtool_test
*test
, u64
* data
)
858 struct pcnet32_private
*lp
= netdev_priv(dev
);
861 if (test
->flags
== ETH_TEST_FL_OFFLINE
) {
862 rc
= pcnet32_loopback_test(dev
, data
);
864 if (netif_msg_hw(lp
))
865 printk(KERN_DEBUG
"%s: Loopback test failed.\n",
867 test
->flags
|= ETH_TEST_FL_FAILED
;
868 } else if (netif_msg_hw(lp
))
869 printk(KERN_DEBUG
"%s: Loopback test passed.\n",
871 } else if (netif_msg_hw(lp
))
873 "%s: No tests to run (specify 'Offline' on ethtool).",
875 } /* end pcnet32_ethtool_test */
877 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
)
879 struct pcnet32_private
*lp
= netdev_priv(dev
);
880 struct pcnet32_access
*a
= &lp
->a
; /* access to registers */
881 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
882 struct sk_buff
*skb
; /* sk buff */
883 int x
, i
; /* counters */
884 int numbuffs
= 4; /* number of TX/RX buffers and descs */
885 u16 status
= 0x8300; /* TX ring status */
886 u16 teststatus
; /* test of ring status */
887 int rc
; /* return code */
888 int size
; /* size of packets */
889 unsigned char *packet
; /* source packet data */
890 static const int data_len
= 60; /* length of source packets */
894 rc
= 1; /* default to fail */
896 if (netif_running(dev
))
897 #ifdef CONFIG_PCNET32_NAPI
898 pcnet32_netif_stop(dev
);
903 spin_lock_irqsave(&lp
->lock
, flags
);
904 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* stop the chip */
906 numbuffs
= min(numbuffs
, (int)min(lp
->rx_ring_size
, lp
->tx_ring_size
));
908 /* Reset the PCNET32 */
910 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
912 /* switch pcnet32 to 32bit mode */
913 lp
->a
.write_bcr(ioaddr
, 20, 2);
915 /* purge & init rings but don't actually restart */
916 pcnet32_restart(dev
, 0x0000);
918 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* Set STOP bit */
920 /* Initialize Transmit buffers. */
921 size
= data_len
+ 15;
922 for (x
= 0; x
< numbuffs
; x
++) {
923 if (!(skb
= dev_alloc_skb(size
))) {
924 if (netif_msg_hw(lp
))
926 "%s: Cannot allocate skb at line: %d!\n",
927 dev
->name
, __LINE__
);
931 skb_put(skb
, size
); /* create space for data */
932 lp
->tx_skbuff
[x
] = skb
;
933 lp
->tx_ring
[x
].length
= le16_to_cpu(-skb
->len
);
934 lp
->tx_ring
[x
].misc
= 0;
936 /* put DA and SA into the skb */
937 for (i
= 0; i
< 6; i
++)
938 *packet
++ = dev
->dev_addr
[i
];
939 for (i
= 0; i
< 6; i
++)
940 *packet
++ = dev
->dev_addr
[i
];
946 /* fill packet with data */
947 for (i
= 0; i
< data_len
; i
++)
951 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
,
953 lp
->tx_ring
[x
].base
=
954 (u32
) le32_to_cpu(lp
->tx_dma_addr
[x
]);
955 wmb(); /* Make sure owner changes after all others are visible */
956 lp
->tx_ring
[x
].status
= le16_to_cpu(status
);
960 x
= a
->read_bcr(ioaddr
, 32); /* set internal loopback in BCR32 */
961 a
->write_bcr(ioaddr
, 32, x
| 0x0002);
963 /* set int loopback in CSR15 */
964 x
= a
->read_csr(ioaddr
, CSR15
) & 0xfffc;
965 lp
->a
.write_csr(ioaddr
, CSR15
, x
| 0x0044);
967 teststatus
= le16_to_cpu(0x8000);
968 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_START
); /* Set STRT bit */
970 /* Check status of descriptors */
971 for (x
= 0; x
< numbuffs
; x
++) {
974 while ((lp
->rx_ring
[x
].status
& teststatus
) && (ticks
< 200)) {
975 spin_unlock_irqrestore(&lp
->lock
, flags
);
977 spin_lock_irqsave(&lp
->lock
, flags
);
982 if (netif_msg_hw(lp
))
983 printk("%s: Desc %d failed to reset!\n",
989 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
); /* Set STOP bit */
991 if (netif_msg_hw(lp
) && netif_msg_pktdata(lp
)) {
992 printk(KERN_DEBUG
"%s: RX loopback packets:\n", dev
->name
);
994 for (x
= 0; x
< numbuffs
; x
++) {
995 printk(KERN_DEBUG
"%s: Packet %d:\n", dev
->name
, x
);
996 skb
= lp
->rx_skbuff
[x
];
997 for (i
= 0; i
< size
; i
++) {
998 printk("%02x ", *(skb
->data
+ i
));
1006 while (x
< numbuffs
&& !rc
) {
1007 skb
= lp
->rx_skbuff
[x
];
1008 packet
= lp
->tx_skbuff
[x
]->data
;
1009 for (i
= 0; i
< size
; i
++) {
1010 if (*(skb
->data
+ i
) != packet
[i
]) {
1011 if (netif_msg_hw(lp
))
1013 "%s: Error in compare! %2x - %02x %02x\n",
1014 dev
->name
, i
, *(skb
->data
+ i
),
1025 pcnet32_purge_tx_ring(dev
);
1027 x
= a
->read_csr(ioaddr
, CSR15
);
1028 a
->write_csr(ioaddr
, CSR15
, (x
& ~0x0044)); /* reset bits 6 and 2 */
1030 x
= a
->read_bcr(ioaddr
, 32); /* reset internal loopback */
1031 a
->write_bcr(ioaddr
, 32, (x
& ~0x0002));
1033 #ifdef CONFIG_PCNET32_NAPI
1034 if (netif_running(dev
)) {
1035 pcnet32_netif_start(dev
);
1036 pcnet32_restart(dev
, CSR0_NORMAL
);
1038 pcnet32_purge_rx_ring(dev
);
1039 lp
->a
.write_bcr(ioaddr
, 20, 4); /* return to 16bit mode */
1041 spin_unlock_irqrestore(&lp
->lock
, flags
);
1043 if (netif_running(dev
)) {
1044 spin_unlock_irqrestore(&lp
->lock
, flags
);
1047 pcnet32_purge_rx_ring(dev
);
1048 lp
->a
.write_bcr(ioaddr
, 20, 4); /* return to 16bit mode */
1049 spin_unlock_irqrestore(&lp
->lock
, flags
);
1054 } /* end pcnet32_loopback_test */
1056 static void pcnet32_led_blink_callback(struct net_device
*dev
)
1058 struct pcnet32_private
*lp
= netdev_priv(dev
);
1059 struct pcnet32_access
*a
= &lp
->a
;
1060 ulong ioaddr
= dev
->base_addr
;
1061 unsigned long flags
;
1064 spin_lock_irqsave(&lp
->lock
, flags
);
1065 for (i
= 4; i
< 8; i
++) {
1066 a
->write_bcr(ioaddr
, i
, a
->read_bcr(ioaddr
, i
) ^ 0x4000);
1068 spin_unlock_irqrestore(&lp
->lock
, flags
);
1070 mod_timer(&lp
->blink_timer
, PCNET32_BLINK_TIMEOUT
);
1073 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
)
1075 struct pcnet32_private
*lp
= netdev_priv(dev
);
1076 struct pcnet32_access
*a
= &lp
->a
;
1077 ulong ioaddr
= dev
->base_addr
;
1078 unsigned long flags
;
1081 if (!lp
->blink_timer
.function
) {
1082 init_timer(&lp
->blink_timer
);
1083 lp
->blink_timer
.function
= (void *)pcnet32_led_blink_callback
;
1084 lp
->blink_timer
.data
= (unsigned long)dev
;
1087 /* Save the current value of the bcrs */
1088 spin_lock_irqsave(&lp
->lock
, flags
);
1089 for (i
= 4; i
< 8; i
++) {
1090 regs
[i
- 4] = a
->read_bcr(ioaddr
, i
);
1092 spin_unlock_irqrestore(&lp
->lock
, flags
);
1094 mod_timer(&lp
->blink_timer
, jiffies
);
1095 set_current_state(TASK_INTERRUPTIBLE
);
1097 if ((!data
) || (data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
)))
1098 data
= (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
);
1100 msleep_interruptible(data
* 1000);
1101 del_timer_sync(&lp
->blink_timer
);
1103 /* Restore the original value of the bcrs */
1104 spin_lock_irqsave(&lp
->lock
, flags
);
1105 for (i
= 4; i
< 8; i
++) {
1106 a
->write_bcr(ioaddr
, i
, regs
[i
- 4]);
1108 spin_unlock_irqrestore(&lp
->lock
, flags
);
1114 * lp->lock must be held.
1116 static int pcnet32_suspend(struct net_device
*dev
, unsigned long *flags
,
1120 struct pcnet32_private
*lp
= netdev_priv(dev
);
1121 struct pcnet32_access
*a
= &lp
->a
;
1122 ulong ioaddr
= dev
->base_addr
;
1125 /* really old chips have to be stopped. */
1126 if (lp
->chip_version
< PCNET32_79C970A
)
1129 /* set SUSPEND (SPND) - CSR5 bit 0 */
1130 csr5
= a
->read_csr(ioaddr
, CSR5
);
1131 a
->write_csr(ioaddr
, CSR5
, csr5
| CSR5_SUSPEND
);
1133 /* poll waiting for bit to be set */
1135 while (!(a
->read_csr(ioaddr
, CSR5
) & CSR5_SUSPEND
)) {
1136 spin_unlock_irqrestore(&lp
->lock
, *flags
);
1141 spin_lock_irqsave(&lp
->lock
, *flags
);
1144 if (netif_msg_hw(lp
))
1146 "%s: Error getting into suspend!\n",
1155 * process one receive descriptor entry
1158 static void pcnet32_rx_entry(struct net_device
*dev
,
1159 struct pcnet32_private
*lp
,
1160 struct pcnet32_rx_head
*rxp
,
1163 int status
= (short)le16_to_cpu(rxp
->status
) >> 8;
1164 int rx_in_place
= 0;
1165 struct sk_buff
*skb
;
1168 if (status
!= 0x03) { /* There was an error. */
1170 * There is a tricky error noted by John Murphy,
1171 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1172 * buffers it's possible for a jabber packet to use two
1173 * buffers, with only the last correctly noting the error.
1175 if (status
& 0x01) /* Only count a general error at the */
1176 lp
->stats
.rx_errors
++; /* end of a packet. */
1178 lp
->stats
.rx_frame_errors
++;
1180 lp
->stats
.rx_over_errors
++;
1182 lp
->stats
.rx_crc_errors
++;
1184 lp
->stats
.rx_fifo_errors
++;
1188 pkt_len
= (le32_to_cpu(rxp
->msg_length
) & 0xfff) - 4;
1190 /* Discard oversize frames. */
1191 if (unlikely(pkt_len
> PKT_BUF_SZ
- 2)) {
1192 if (netif_msg_drv(lp
))
1193 printk(KERN_ERR
"%s: Impossible packet size %d!\n",
1194 dev
->name
, pkt_len
);
1195 lp
->stats
.rx_errors
++;
1199 if (netif_msg_rx_err(lp
))
1200 printk(KERN_ERR
"%s: Runt packet!\n", dev
->name
);
1201 lp
->stats
.rx_errors
++;
1205 if (pkt_len
> rx_copybreak
) {
1206 struct sk_buff
*newskb
;
1208 if ((newskb
= dev_alloc_skb(PKT_BUF_SZ
))) {
1209 skb_reserve(newskb
, 2);
1210 skb
= lp
->rx_skbuff
[entry
];
1211 pci_unmap_single(lp
->pci_dev
,
1212 lp
->rx_dma_addr
[entry
],
1214 PCI_DMA_FROMDEVICE
);
1215 skb_put(skb
, pkt_len
);
1216 lp
->rx_skbuff
[entry
] = newskb
;
1217 lp
->rx_dma_addr
[entry
] =
1218 pci_map_single(lp
->pci_dev
,
1221 PCI_DMA_FROMDEVICE
);
1222 rxp
->base
= le32_to_cpu(lp
->rx_dma_addr
[entry
]);
1227 skb
= dev_alloc_skb(pkt_len
+ 2);
1231 if (netif_msg_drv(lp
))
1233 "%s: Memory squeeze, dropping packet.\n",
1235 lp
->stats
.rx_dropped
++;
1240 skb_reserve(skb
, 2); /* 16 byte align */
1241 skb_put(skb
, pkt_len
); /* Make room */
1242 pci_dma_sync_single_for_cpu(lp
->pci_dev
,
1243 lp
->rx_dma_addr
[entry
],
1245 PCI_DMA_FROMDEVICE
);
1246 skb_copy_to_linear_data(skb
,
1247 (unsigned char *)(lp
->rx_skbuff
[entry
]->data
),
1249 pci_dma_sync_single_for_device(lp
->pci_dev
,
1250 lp
->rx_dma_addr
[entry
],
1252 PCI_DMA_FROMDEVICE
);
1254 lp
->stats
.rx_bytes
+= skb
->len
;
1255 skb
->protocol
= eth_type_trans(skb
, dev
);
1256 #ifdef CONFIG_PCNET32_NAPI
1257 netif_receive_skb(skb
);
1261 dev
->last_rx
= jiffies
;
1262 lp
->stats
.rx_packets
++;
1266 static int pcnet32_rx(struct net_device
*dev
, int budget
)
1268 struct pcnet32_private
*lp
= netdev_priv(dev
);
1269 int entry
= lp
->cur_rx
& lp
->rx_mod_mask
;
1270 struct pcnet32_rx_head
*rxp
= &lp
->rx_ring
[entry
];
1273 /* If we own the next entry, it's a new packet. Send it up. */
1274 while (npackets
< budget
&& (short)le16_to_cpu(rxp
->status
) >= 0) {
1275 pcnet32_rx_entry(dev
, lp
, rxp
, entry
);
1278 * The docs say that the buffer length isn't touched, but Andrew
1279 * Boyd of QNX reports that some revs of the 79C965 clear it.
1281 rxp
->buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
1282 wmb(); /* Make sure owner changes after others are visible */
1283 rxp
->status
= le16_to_cpu(0x8000);
1284 entry
= (++lp
->cur_rx
) & lp
->rx_mod_mask
;
1285 rxp
= &lp
->rx_ring
[entry
];
1291 static int pcnet32_tx(struct net_device
*dev
)
1293 struct pcnet32_private
*lp
= netdev_priv(dev
);
1294 unsigned int dirty_tx
= lp
->dirty_tx
;
1296 int must_restart
= 0;
1298 while (dirty_tx
!= lp
->cur_tx
) {
1299 int entry
= dirty_tx
& lp
->tx_mod_mask
;
1300 int status
= (short)le16_to_cpu(lp
->tx_ring
[entry
].status
);
1303 break; /* It still hasn't been Txed */
1305 lp
->tx_ring
[entry
].base
= 0;
1307 if (status
& 0x4000) {
1308 /* There was a major error, log it. */
1309 int err_status
= le32_to_cpu(lp
->tx_ring
[entry
].misc
);
1310 lp
->stats
.tx_errors
++;
1311 if (netif_msg_tx_err(lp
))
1313 "%s: Tx error status=%04x err_status=%08x\n",
1316 if (err_status
& 0x04000000)
1317 lp
->stats
.tx_aborted_errors
++;
1318 if (err_status
& 0x08000000)
1319 lp
->stats
.tx_carrier_errors
++;
1320 if (err_status
& 0x10000000)
1321 lp
->stats
.tx_window_errors
++;
1323 if (err_status
& 0x40000000) {
1324 lp
->stats
.tx_fifo_errors
++;
1325 /* Ackk! On FIFO errors the Tx unit is turned off! */
1326 /* Remove this verbosity later! */
1327 if (netif_msg_tx_err(lp
))
1329 "%s: Tx FIFO error!\n",
1334 if (err_status
& 0x40000000) {
1335 lp
->stats
.tx_fifo_errors
++;
1336 if (!lp
->dxsuflo
) { /* If controller doesn't recover ... */
1337 /* Ackk! On FIFO errors the Tx unit is turned off! */
1338 /* Remove this verbosity later! */
1339 if (netif_msg_tx_err(lp
))
1341 "%s: Tx FIFO error!\n",
1348 if (status
& 0x1800)
1349 lp
->stats
.collisions
++;
1350 lp
->stats
.tx_packets
++;
1353 /* We must free the original skb */
1354 if (lp
->tx_skbuff
[entry
]) {
1355 pci_unmap_single(lp
->pci_dev
,
1356 lp
->tx_dma_addr
[entry
],
1357 lp
->tx_skbuff
[entry
]->
1358 len
, PCI_DMA_TODEVICE
);
1359 dev_kfree_skb_any(lp
->tx_skbuff
[entry
]);
1360 lp
->tx_skbuff
[entry
] = NULL
;
1361 lp
->tx_dma_addr
[entry
] = 0;
1366 delta
= (lp
->cur_tx
- dirty_tx
) & (lp
->tx_mod_mask
+ lp
->tx_ring_size
);
1367 if (delta
> lp
->tx_ring_size
) {
1368 if (netif_msg_drv(lp
))
1370 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1371 dev
->name
, dirty_tx
, lp
->cur_tx
,
1373 dirty_tx
+= lp
->tx_ring_size
;
1374 delta
-= lp
->tx_ring_size
;
1378 netif_queue_stopped(dev
) &&
1379 delta
< lp
->tx_ring_size
- 2) {
1380 /* The ring is no longer full, clear tbusy. */
1382 netif_wake_queue(dev
);
1384 lp
->dirty_tx
= dirty_tx
;
1386 return must_restart
;
1389 #ifdef CONFIG_PCNET32_NAPI
1390 static int pcnet32_poll(struct napi_struct
*napi
, int budget
)
1392 struct pcnet32_private
*lp
= container_of(napi
, struct pcnet32_private
, napi
);
1393 struct net_device
*dev
= lp
->dev
;
1394 unsigned long ioaddr
= dev
->base_addr
;
1395 unsigned long flags
;
1399 work_done
= pcnet32_rx(dev
, budget
);
1401 spin_lock_irqsave(&lp
->lock
, flags
);
1402 if (pcnet32_tx(dev
)) {
1403 /* reset the chip to clear the error condition, then restart */
1404 lp
->a
.reset(ioaddr
);
1405 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
1406 pcnet32_restart(dev
, CSR0_START
);
1407 netif_wake_queue(dev
);
1409 spin_unlock_irqrestore(&lp
->lock
, flags
);
1411 if (work_done
< budget
) {
1412 spin_lock_irqsave(&lp
->lock
, flags
);
1414 __netif_rx_complete(dev
, napi
);
1416 /* clear interrupt masks */
1417 val
= lp
->a
.read_csr(ioaddr
, CSR3
);
1419 lp
->a
.write_csr(ioaddr
, CSR3
, val
);
1421 /* Set interrupt enable. */
1422 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INTEN
);
1424 spin_unlock_irqrestore(&lp
->lock
, flags
);
1430 #define PCNET32_REGS_PER_PHY 32
1431 #define PCNET32_MAX_PHYS 32
1432 static int pcnet32_get_regs_len(struct net_device
*dev
)
1434 struct pcnet32_private
*lp
= netdev_priv(dev
);
1435 int j
= lp
->phycount
* PCNET32_REGS_PER_PHY
;
1437 return ((PCNET32_NUM_REGS
+ j
) * sizeof(u16
));
1440 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1445 struct pcnet32_private
*lp
= netdev_priv(dev
);
1446 struct pcnet32_access
*a
= &lp
->a
;
1447 ulong ioaddr
= dev
->base_addr
;
1448 unsigned long flags
;
1450 spin_lock_irqsave(&lp
->lock
, flags
);
1452 csr0
= a
->read_csr(ioaddr
, CSR0
);
1453 if (!(csr0
& CSR0_STOP
)) /* If not stopped */
1454 pcnet32_suspend(dev
, &flags
, 1);
1456 /* read address PROM */
1457 for (i
= 0; i
< 16; i
+= 2)
1458 *buff
++ = inw(ioaddr
+ i
);
1460 /* read control and status registers */
1461 for (i
= 0; i
< 90; i
++) {
1462 *buff
++ = a
->read_csr(ioaddr
, i
);
1465 *buff
++ = a
->read_csr(ioaddr
, 112);
1466 *buff
++ = a
->read_csr(ioaddr
, 114);
1468 /* read bus configuration registers */
1469 for (i
= 0; i
< 30; i
++) {
1470 *buff
++ = a
->read_bcr(ioaddr
, i
);
1472 *buff
++ = 0; /* skip bcr30 so as not to hang 79C976 */
1473 for (i
= 31; i
< 36; i
++) {
1474 *buff
++ = a
->read_bcr(ioaddr
, i
);
1477 /* read mii phy registers */
1480 for (j
= 0; j
< PCNET32_MAX_PHYS
; j
++) {
1481 if (lp
->phymask
& (1 << j
)) {
1482 for (i
= 0; i
< PCNET32_REGS_PER_PHY
; i
++) {
1483 lp
->a
.write_bcr(ioaddr
, 33,
1485 *buff
++ = lp
->a
.read_bcr(ioaddr
, 34);
1491 if (!(csr0
& CSR0_STOP
)) { /* If not stopped */
1494 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1495 csr5
= a
->read_csr(ioaddr
, CSR5
);
1496 a
->write_csr(ioaddr
, CSR5
, csr5
& (~CSR5_SUSPEND
));
1499 spin_unlock_irqrestore(&lp
->lock
, flags
);
1502 static const struct ethtool_ops pcnet32_ethtool_ops
= {
1503 .get_settings
= pcnet32_get_settings
,
1504 .set_settings
= pcnet32_set_settings
,
1505 .get_drvinfo
= pcnet32_get_drvinfo
,
1506 .get_msglevel
= pcnet32_get_msglevel
,
1507 .set_msglevel
= pcnet32_set_msglevel
,
1508 .nway_reset
= pcnet32_nway_reset
,
1509 .get_link
= pcnet32_get_link
,
1510 .get_ringparam
= pcnet32_get_ringparam
,
1511 .set_ringparam
= pcnet32_set_ringparam
,
1512 .get_strings
= pcnet32_get_strings
,
1513 .self_test_count
= pcnet32_self_test_count
,
1514 .self_test
= pcnet32_ethtool_test
,
1515 .phys_id
= pcnet32_phys_id
,
1516 .get_regs_len
= pcnet32_get_regs_len
,
1517 .get_regs
= pcnet32_get_regs
,
1520 /* only probes for non-PCI devices, the rest are handled by
1521 * pci_register_driver via pcnet32_probe_pci */
1523 static void __devinit
pcnet32_probe_vlbus(unsigned int *pcnet32_portlist
)
1525 unsigned int *port
, ioaddr
;
1527 /* search for PCnet32 VLB cards at known addresses */
1528 for (port
= pcnet32_portlist
; (ioaddr
= *port
); port
++) {
1530 (ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_vlbus")) {
1531 /* check if there is really a pcnet chip on that ioaddr */
1532 if ((inb(ioaddr
+ 14) == 0x57)
1533 && (inb(ioaddr
+ 15) == 0x57)) {
1534 pcnet32_probe1(ioaddr
, 0, NULL
);
1536 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
1542 static int __devinit
1543 pcnet32_probe_pci(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1545 unsigned long ioaddr
;
1548 err
= pci_enable_device(pdev
);
1550 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1552 "failed to enable device -- err=%d\n", err
);
1555 pci_set_master(pdev
);
1557 ioaddr
= pci_resource_start(pdev
, 0);
1559 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1561 "card has no PCI IO resources, aborting\n");
1565 if (!pci_dma_supported(pdev
, PCNET32_DMA_MASK
)) {
1566 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1568 "architecture does not support 32bit PCI busmaster DMA\n");
1571 if (request_region(ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_pci") ==
1573 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1575 "io address range already allocated\n");
1579 err
= pcnet32_probe1(ioaddr
, 1, pdev
);
1581 pci_disable_device(pdev
);
1587 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1588 * pdev will be NULL when called from pcnet32_probe_vlbus.
1590 static int __devinit
1591 pcnet32_probe1(unsigned long ioaddr
, int shared
, struct pci_dev
*pdev
)
1593 struct pcnet32_private
*lp
;
1595 int fdx
, mii
, fset
, dxsuflo
;
1598 struct net_device
*dev
;
1599 struct pcnet32_access
*a
= NULL
;
1603 /* reset the chip */
1604 pcnet32_wio_reset(ioaddr
);
1606 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1607 if (pcnet32_wio_read_csr(ioaddr
, 0) == 4 && pcnet32_wio_check(ioaddr
)) {
1610 pcnet32_dwio_reset(ioaddr
);
1611 if (pcnet32_dwio_read_csr(ioaddr
, 0) == 4
1612 && pcnet32_dwio_check(ioaddr
)) {
1615 goto err_release_region
;
1619 a
->read_csr(ioaddr
, 88) | (a
->read_csr(ioaddr
, 89) << 16);
1620 if ((pcnet32_debug
& NETIF_MSG_PROBE
) && (pcnet32_debug
& NETIF_MSG_HW
))
1621 printk(KERN_INFO
" PCnet chip version is %#x.\n",
1623 if ((chip_version
& 0xfff) != 0x003) {
1624 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1625 printk(KERN_INFO PFX
"Unsupported chip version.\n");
1626 goto err_release_region
;
1629 /* initialize variables */
1630 fdx
= mii
= fset
= dxsuflo
= 0;
1631 chip_version
= (chip_version
>> 12) & 0xffff;
1633 switch (chip_version
) {
1635 chipname
= "PCnet/PCI 79C970"; /* PCI */
1639 chipname
= "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1641 chipname
= "PCnet/32 79C965"; /* 486/VL bus */
1644 chipname
= "PCnet/PCI II 79C970A"; /* PCI */
1648 chipname
= "PCnet/FAST 79C971"; /* PCI */
1654 chipname
= "PCnet/FAST+ 79C972"; /* PCI */
1660 chipname
= "PCnet/FAST III 79C973"; /* PCI */
1665 chipname
= "PCnet/Home 79C978"; /* PCI */
1668 * This is based on specs published at www.amd.com. This section
1669 * assumes that a card with a 79C978 wants to go into standard
1670 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1671 * and the module option homepna=1 can select this instead.
1673 media
= a
->read_bcr(ioaddr
, 49);
1674 media
&= ~3; /* default to 10Mb ethernet */
1675 if (cards_found
< MAX_UNITS
&& homepna
[cards_found
])
1676 media
|= 1; /* switch to home wiring mode */
1677 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1678 printk(KERN_DEBUG PFX
"media set to %sMbit mode.\n",
1679 (media
& 1) ? "1" : "10");
1680 a
->write_bcr(ioaddr
, 49, media
);
1683 chipname
= "PCnet/FAST III 79C975"; /* PCI */
1688 chipname
= "PCnet/PRO 79C976";
1693 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1694 printk(KERN_INFO PFX
1695 "PCnet version %#x, no PCnet32 chip.\n",
1697 goto err_release_region
;
1701 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1702 * starting until the packet is loaded. Strike one for reliability, lose
1703 * one for latency - although on PCI this isnt a big loss. Older chips
1704 * have FIFO's smaller than a packet, so you can't do this.
1705 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1709 a
->write_bcr(ioaddr
, 18, (a
->read_bcr(ioaddr
, 18) | 0x0860));
1710 a
->write_csr(ioaddr
, 80,
1711 (a
->read_csr(ioaddr
, 80) & 0x0C00) | 0x0c00);
1715 dev
= alloc_etherdev(sizeof(*lp
));
1717 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1718 printk(KERN_ERR PFX
"Memory allocation failed.\n");
1720 goto err_release_region
;
1722 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1724 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1725 printk(KERN_INFO PFX
"%s at %#3lx,", chipname
, ioaddr
);
1727 /* In most chips, after a chip reset, the ethernet address is read from the
1728 * station address PROM at the base address and programmed into the
1729 * "Physical Address Registers" CSR12-14.
1730 * As a precautionary measure, we read the PROM values and complain if
1731 * they disagree with the CSRs. If they miscompare, and the PROM addr
1732 * is valid, then the PROM addr is used.
1734 for (i
= 0; i
< 3; i
++) {
1736 val
= a
->read_csr(ioaddr
, i
+ 12) & 0x0ffff;
1737 /* There may be endianness issues here. */
1738 dev
->dev_addr
[2 * i
] = val
& 0x0ff;
1739 dev
->dev_addr
[2 * i
+ 1] = (val
>> 8) & 0x0ff;
1742 /* read PROM address and compare with CSR address */
1743 for (i
= 0; i
< 6; i
++)
1744 promaddr
[i
] = inb(ioaddr
+ i
);
1746 if (memcmp(promaddr
, dev
->dev_addr
, 6)
1747 || !is_valid_ether_addr(dev
->dev_addr
)) {
1748 if (is_valid_ether_addr(promaddr
)) {
1749 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1750 printk(" warning: CSR address invalid,\n");
1752 " using instead PROM address of");
1754 memcpy(dev
->dev_addr
, promaddr
, 6);
1757 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1759 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1760 if (!is_valid_ether_addr(dev
->perm_addr
))
1761 memset(dev
->dev_addr
, 0, sizeof(dev
->dev_addr
));
1763 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1764 for (i
= 0; i
< 6; i
++)
1765 printk(" %2.2x", dev
->dev_addr
[i
]);
1767 /* Version 0x2623 and 0x2624 */
1768 if (((chip_version
+ 1) & 0xfffe) == 0x2624) {
1769 i
= a
->read_csr(ioaddr
, 80) & 0x0C00; /* Check tx_start_pt */
1770 printk("\n" KERN_INFO
" tx_start_pt(0x%04x):", i
);
1773 printk(" 20 bytes,");
1776 printk(" 64 bytes,");
1779 printk(" 128 bytes,");
1782 printk("~220 bytes,");
1785 i
= a
->read_bcr(ioaddr
, 18); /* Check Burst/Bus control */
1786 printk(" BCR18(%x):", i
& 0xffff);
1788 printk("BurstWrEn ");
1790 printk("BurstRdEn ");
1795 i
= a
->read_bcr(ioaddr
, 25);
1796 printk("\n" KERN_INFO
" SRAMSIZE=0x%04x,", i
<< 8);
1797 i
= a
->read_bcr(ioaddr
, 26);
1798 printk(" SRAM_BND=0x%04x,", i
<< 8);
1799 i
= a
->read_bcr(ioaddr
, 27);
1805 dev
->base_addr
= ioaddr
;
1806 lp
= netdev_priv(dev
);
1807 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1808 if ((lp
->init_block
=
1809 pci_alloc_consistent(pdev
, sizeof(*lp
->init_block
), &lp
->init_dma_addr
)) == NULL
) {
1810 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1812 "Consistent memory allocation failed.\n");
1814 goto err_free_netdev
;
1820 spin_lock_init(&lp
->lock
);
1822 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1823 lp
->name
= chipname
;
1824 lp
->shared_irq
= shared
;
1825 lp
->tx_ring_size
= TX_RING_SIZE
; /* default tx ring size */
1826 lp
->rx_ring_size
= RX_RING_SIZE
; /* default rx ring size */
1827 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
1828 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
1829 lp
->tx_len_bits
= (PCNET32_LOG_TX_BUFFERS
<< 12);
1830 lp
->rx_len_bits
= (PCNET32_LOG_RX_BUFFERS
<< 4);
1831 lp
->mii_if
.full_duplex
= fdx
;
1832 lp
->mii_if
.phy_id_mask
= 0x1f;
1833 lp
->mii_if
.reg_num_mask
= 0x1f;
1834 lp
->dxsuflo
= dxsuflo
;
1836 lp
->chip_version
= chip_version
;
1837 lp
->msg_enable
= pcnet32_debug
;
1838 if ((cards_found
>= MAX_UNITS
)
1839 || (options
[cards_found
] > sizeof(options_mapping
)))
1840 lp
->options
= PCNET32_PORT_ASEL
;
1842 lp
->options
= options_mapping
[options
[cards_found
]];
1843 lp
->mii_if
.dev
= dev
;
1844 lp
->mii_if
.mdio_read
= mdio_read
;
1845 lp
->mii_if
.mdio_write
= mdio_write
;
1847 #ifdef CONFIG_PCNET32_NAPI
1848 netif_napi_add(dev
, &lp
->napi
, pcnet32_poll
, lp
->rx_ring_size
/ 2);
1851 if (fdx
&& !(lp
->options
& PCNET32_PORT_ASEL
) &&
1852 ((cards_found
>= MAX_UNITS
) || full_duplex
[cards_found
]))
1853 lp
->options
|= PCNET32_PORT_FD
;
1856 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1857 printk(KERN_ERR PFX
"No access methods\n");
1859 goto err_free_consistent
;
1863 /* prior to register_netdev, dev->name is not yet correct */
1864 if (pcnet32_alloc_ring(dev
, pci_name(lp
->pci_dev
))) {
1868 /* detect special T1/E1 WAN card by checking for MAC address */
1869 if (dev
->dev_addr
[0] == 0x00 && dev
->dev_addr
[1] == 0xe0
1870 && dev
->dev_addr
[2] == 0x75)
1871 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_GPSI
;
1873 lp
->init_block
->mode
= le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1874 lp
->init_block
->tlen_rlen
=
1875 le16_to_cpu(lp
->tx_len_bits
| lp
->rx_len_bits
);
1876 for (i
= 0; i
< 6; i
++)
1877 lp
->init_block
->phys_addr
[i
] = dev
->dev_addr
[i
];
1878 lp
->init_block
->filter
[0] = 0x00000000;
1879 lp
->init_block
->filter
[1] = 0x00000000;
1880 lp
->init_block
->rx_ring
= (u32
) le32_to_cpu(lp
->rx_ring_dma_addr
);
1881 lp
->init_block
->tx_ring
= (u32
) le32_to_cpu(lp
->tx_ring_dma_addr
);
1883 /* switch pcnet32 to 32bit mode */
1884 a
->write_bcr(ioaddr
, 20, 2);
1886 a
->write_csr(ioaddr
, 1, (lp
->init_dma_addr
& 0xffff));
1887 a
->write_csr(ioaddr
, 2, (lp
->init_dma_addr
>> 16));
1889 if (pdev
) { /* use the IRQ provided by PCI */
1890 dev
->irq
= pdev
->irq
;
1891 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1892 printk(" assigned IRQ %d.\n", dev
->irq
);
1894 unsigned long irq_mask
= probe_irq_on();
1897 * To auto-IRQ we enable the initialization-done and DMA error
1898 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1901 /* Trigger an initialization just for the interrupt. */
1902 a
->write_csr(ioaddr
, CSR0
, CSR0_INTEN
| CSR0_INIT
);
1905 dev
->irq
= probe_irq_off(irq_mask
);
1907 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1908 printk(", failed to detect IRQ line.\n");
1912 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1913 printk(", probed IRQ %d.\n", dev
->irq
);
1916 /* Set the mii phy_id so that we can query the link state */
1918 /* lp->phycount and lp->phymask are set to 0 by memset above */
1920 lp
->mii_if
.phy_id
= ((lp
->a
.read_bcr(ioaddr
, 33)) >> 5) & 0x1f;
1922 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
1923 unsigned short id1
, id2
;
1925 id1
= mdio_read(dev
, i
, MII_PHYSID1
);
1928 id2
= mdio_read(dev
, i
, MII_PHYSID2
);
1931 if (i
== 31 && ((chip_version
+ 1) & 0xfffe) == 0x2624)
1932 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1934 lp
->phymask
|= (1 << i
);
1935 lp
->mii_if
.phy_id
= i
;
1936 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1937 printk(KERN_INFO PFX
1938 "Found PHY %04x:%04x at address %d.\n",
1941 lp
->a
.write_bcr(ioaddr
, 33, (lp
->mii_if
.phy_id
) << 5);
1942 if (lp
->phycount
> 1) {
1943 lp
->options
|= PCNET32_PORT_MII
;
1947 init_timer(&lp
->watchdog_timer
);
1948 lp
->watchdog_timer
.data
= (unsigned long)dev
;
1949 lp
->watchdog_timer
.function
= (void *)&pcnet32_watchdog
;
1951 /* The PCNET32-specific entries in the device structure. */
1952 dev
->open
= &pcnet32_open
;
1953 dev
->hard_start_xmit
= &pcnet32_start_xmit
;
1954 dev
->stop
= &pcnet32_close
;
1955 dev
->get_stats
= &pcnet32_get_stats
;
1956 dev
->set_multicast_list
= &pcnet32_set_multicast_list
;
1957 dev
->do_ioctl
= &pcnet32_ioctl
;
1958 dev
->ethtool_ops
= &pcnet32_ethtool_ops
;
1959 dev
->tx_timeout
= pcnet32_tx_timeout
;
1960 dev
->watchdog_timeo
= (5 * HZ
);
1962 #ifdef CONFIG_NET_POLL_CONTROLLER
1963 dev
->poll_controller
= pcnet32_poll_controller
;
1966 /* Fill in the generic fields of the device structure. */
1967 if (register_netdev(dev
))
1971 pci_set_drvdata(pdev
, dev
);
1973 lp
->next
= pcnet32_dev
;
1977 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1978 printk(KERN_INFO
"%s: registered as %s\n", dev
->name
, lp
->name
);
1981 /* enable LED writes */
1982 a
->write_bcr(ioaddr
, 2, a
->read_bcr(ioaddr
, 2) | 0x1000);
1987 pcnet32_free_ring(dev
);
1988 err_free_consistent
:
1989 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
->init_block
),
1990 lp
->init_block
, lp
->init_dma_addr
);
1994 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
1998 /* if any allocation fails, caller must also call pcnet32_free_ring */
1999 static int pcnet32_alloc_ring(struct net_device
*dev
, char *name
)
2001 struct pcnet32_private
*lp
= netdev_priv(dev
);
2003 lp
->tx_ring
= pci_alloc_consistent(lp
->pci_dev
,
2004 sizeof(struct pcnet32_tx_head
) *
2006 &lp
->tx_ring_dma_addr
);
2007 if (lp
->tx_ring
== NULL
) {
2008 if (netif_msg_drv(lp
))
2009 printk("\n" KERN_ERR PFX
2010 "%s: Consistent memory allocation failed.\n",
2015 lp
->rx_ring
= pci_alloc_consistent(lp
->pci_dev
,
2016 sizeof(struct pcnet32_rx_head
) *
2018 &lp
->rx_ring_dma_addr
);
2019 if (lp
->rx_ring
== NULL
) {
2020 if (netif_msg_drv(lp
))
2021 printk("\n" KERN_ERR PFX
2022 "%s: Consistent memory allocation failed.\n",
2027 lp
->tx_dma_addr
= kcalloc(lp
->tx_ring_size
, sizeof(dma_addr_t
),
2029 if (!lp
->tx_dma_addr
) {
2030 if (netif_msg_drv(lp
))
2031 printk("\n" KERN_ERR PFX
2032 "%s: Memory allocation failed.\n", name
);
2036 lp
->rx_dma_addr
= kcalloc(lp
->rx_ring_size
, sizeof(dma_addr_t
),
2038 if (!lp
->rx_dma_addr
) {
2039 if (netif_msg_drv(lp
))
2040 printk("\n" KERN_ERR PFX
2041 "%s: Memory allocation failed.\n", name
);
2045 lp
->tx_skbuff
= kcalloc(lp
->tx_ring_size
, sizeof(struct sk_buff
*),
2047 if (!lp
->tx_skbuff
) {
2048 if (netif_msg_drv(lp
))
2049 printk("\n" KERN_ERR PFX
2050 "%s: Memory allocation failed.\n", name
);
2054 lp
->rx_skbuff
= kcalloc(lp
->rx_ring_size
, sizeof(struct sk_buff
*),
2056 if (!lp
->rx_skbuff
) {
2057 if (netif_msg_drv(lp
))
2058 printk("\n" KERN_ERR PFX
2059 "%s: Memory allocation failed.\n", name
);
2066 static void pcnet32_free_ring(struct net_device
*dev
)
2068 struct pcnet32_private
*lp
= netdev_priv(dev
);
2070 kfree(lp
->tx_skbuff
);
2071 lp
->tx_skbuff
= NULL
;
2073 kfree(lp
->rx_skbuff
);
2074 lp
->rx_skbuff
= NULL
;
2076 kfree(lp
->tx_dma_addr
);
2077 lp
->tx_dma_addr
= NULL
;
2079 kfree(lp
->rx_dma_addr
);
2080 lp
->rx_dma_addr
= NULL
;
2083 pci_free_consistent(lp
->pci_dev
,
2084 sizeof(struct pcnet32_tx_head
) *
2085 lp
->tx_ring_size
, lp
->tx_ring
,
2086 lp
->tx_ring_dma_addr
);
2091 pci_free_consistent(lp
->pci_dev
,
2092 sizeof(struct pcnet32_rx_head
) *
2093 lp
->rx_ring_size
, lp
->rx_ring
,
2094 lp
->rx_ring_dma_addr
);
2099 static int pcnet32_open(struct net_device
*dev
)
2101 struct pcnet32_private
*lp
= netdev_priv(dev
);
2102 unsigned long ioaddr
= dev
->base_addr
;
2106 unsigned long flags
;
2108 if (request_irq(dev
->irq
, &pcnet32_interrupt
,
2109 lp
->shared_irq
? IRQF_SHARED
: 0, dev
->name
,
2114 spin_lock_irqsave(&lp
->lock
, flags
);
2115 /* Check for a valid station address */
2116 if (!is_valid_ether_addr(dev
->dev_addr
)) {
2121 /* Reset the PCNET32 */
2122 lp
->a
.reset(ioaddr
);
2124 /* switch pcnet32 to 32bit mode */
2125 lp
->a
.write_bcr(ioaddr
, 20, 2);
2127 if (netif_msg_ifup(lp
))
2129 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2130 dev
->name
, dev
->irq
, (u32
) (lp
->tx_ring_dma_addr
),
2131 (u32
) (lp
->rx_ring_dma_addr
),
2132 (u32
) (lp
->init_dma_addr
));
2134 /* set/reset autoselect bit */
2135 val
= lp
->a
.read_bcr(ioaddr
, 2) & ~2;
2136 if (lp
->options
& PCNET32_PORT_ASEL
)
2138 lp
->a
.write_bcr(ioaddr
, 2, val
);
2140 /* handle full duplex setting */
2141 if (lp
->mii_if
.full_duplex
) {
2142 val
= lp
->a
.read_bcr(ioaddr
, 9) & ~3;
2143 if (lp
->options
& PCNET32_PORT_FD
) {
2145 if (lp
->options
== (PCNET32_PORT_FD
| PCNET32_PORT_AUI
))
2147 } else if (lp
->options
& PCNET32_PORT_ASEL
) {
2148 /* workaround of xSeries250, turn on for 79C975 only */
2149 if (lp
->chip_version
== 0x2627)
2152 lp
->a
.write_bcr(ioaddr
, 9, val
);
2155 /* set/reset GPSI bit in test register */
2156 val
= lp
->a
.read_csr(ioaddr
, 124) & ~0x10;
2157 if ((lp
->options
& PCNET32_PORT_PORTSEL
) == PCNET32_PORT_GPSI
)
2159 lp
->a
.write_csr(ioaddr
, 124, val
);
2161 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2162 if (lp
->pci_dev
->subsystem_vendor
== PCI_VENDOR_ID_AT
&&
2163 (lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2700FX
||
2164 lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2701FX
)) {
2165 if (lp
->options
& PCNET32_PORT_ASEL
) {
2166 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_100
;
2167 if (netif_msg_link(lp
))
2169 "%s: Setting 100Mb-Full Duplex.\n",
2173 if (lp
->phycount
< 2) {
2175 * 24 Jun 2004 according AMD, in order to change the PHY,
2176 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2177 * duplex, and/or enable auto negotiation, and clear DANAS
2179 if (lp
->mii
&& !(lp
->options
& PCNET32_PORT_ASEL
)) {
2180 lp
->a
.write_bcr(ioaddr
, 32,
2181 lp
->a
.read_bcr(ioaddr
, 32) | 0x0080);
2182 /* disable Auto Negotiation, set 10Mpbs, HD */
2183 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0xb8;
2184 if (lp
->options
& PCNET32_PORT_FD
)
2186 if (lp
->options
& PCNET32_PORT_100
)
2188 lp
->a
.write_bcr(ioaddr
, 32, val
);
2190 if (lp
->options
& PCNET32_PORT_ASEL
) {
2191 lp
->a
.write_bcr(ioaddr
, 32,
2192 lp
->a
.read_bcr(ioaddr
,
2194 /* enable auto negotiate, setup, disable fd */
2195 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0x98;
2197 lp
->a
.write_bcr(ioaddr
, 32, val
);
2204 struct ethtool_cmd ecmd
;
2207 * There is really no good other way to handle multiple PHYs
2208 * other than turning off all automatics
2210 val
= lp
->a
.read_bcr(ioaddr
, 2);
2211 lp
->a
.write_bcr(ioaddr
, 2, val
& ~2);
2212 val
= lp
->a
.read_bcr(ioaddr
, 32);
2213 lp
->a
.write_bcr(ioaddr
, 32, val
& ~(1 << 7)); /* stop MII manager */
2215 if (!(lp
->options
& PCNET32_PORT_ASEL
)) {
2217 ecmd
.port
= PORT_MII
;
2218 ecmd
.transceiver
= XCVR_INTERNAL
;
2219 ecmd
.autoneg
= AUTONEG_DISABLE
;
2222 options
& PCNET32_PORT_100
? SPEED_100
: SPEED_10
;
2223 bcr9
= lp
->a
.read_bcr(ioaddr
, 9);
2225 if (lp
->options
& PCNET32_PORT_FD
) {
2226 ecmd
.duplex
= DUPLEX_FULL
;
2229 ecmd
.duplex
= DUPLEX_HALF
;
2232 lp
->a
.write_bcr(ioaddr
, 9, bcr9
);
2235 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
2236 if (lp
->phymask
& (1 << i
)) {
2237 /* isolate all but the first PHY */
2238 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
2239 if (first_phy
== -1) {
2241 mdio_write(dev
, i
, MII_BMCR
,
2242 bmcr
& ~BMCR_ISOLATE
);
2244 mdio_write(dev
, i
, MII_BMCR
,
2245 bmcr
| BMCR_ISOLATE
);
2247 /* use mii_ethtool_sset to setup PHY */
2248 lp
->mii_if
.phy_id
= i
;
2249 ecmd
.phy_address
= i
;
2250 if (lp
->options
& PCNET32_PORT_ASEL
) {
2251 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
2252 ecmd
.autoneg
= AUTONEG_ENABLE
;
2254 mii_ethtool_sset(&lp
->mii_if
, &ecmd
);
2257 lp
->mii_if
.phy_id
= first_phy
;
2258 if (netif_msg_link(lp
))
2259 printk(KERN_INFO
"%s: Using PHY number %d.\n",
2260 dev
->name
, first_phy
);
2264 if (lp
->dxsuflo
) { /* Disable transmit stop on underflow */
2265 val
= lp
->a
.read_csr(ioaddr
, CSR3
);
2267 lp
->a
.write_csr(ioaddr
, CSR3
, val
);
2271 lp
->init_block
->mode
=
2272 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
2273 pcnet32_load_multicast(dev
);
2275 if (pcnet32_init_ring(dev
)) {
2280 #ifdef CONFIG_PCNET32_NAPI
2281 napi_enable(&lp
->napi
);
2284 /* Re-initialize the PCNET32, and start it when done. */
2285 lp
->a
.write_csr(ioaddr
, 1, (lp
->init_dma_addr
& 0xffff));
2286 lp
->a
.write_csr(ioaddr
, 2, (lp
->init_dma_addr
>> 16));
2288 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
2289 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INIT
);
2291 netif_start_queue(dev
);
2293 if (lp
->chip_version
>= PCNET32_79C970A
) {
2294 /* Print the link status and start the watchdog */
2295 pcnet32_check_media(dev
, 1);
2296 mod_timer(&(lp
->watchdog_timer
), PCNET32_WATCHDOG_TIMEOUT
);
2301 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_IDON
)
2304 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2305 * reports that doing so triggers a bug in the '974.
2307 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_NORMAL
);
2309 if (netif_msg_ifup(lp
))
2311 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2313 (u32
) (lp
->init_dma_addr
),
2314 lp
->a
.read_csr(ioaddr
, CSR0
));
2316 spin_unlock_irqrestore(&lp
->lock
, flags
);
2318 return 0; /* Always succeed */
2321 /* free any allocated skbuffs */
2322 pcnet32_purge_rx_ring(dev
);
2325 * Switch back to 16bit mode to avoid problems with dumb
2326 * DOS packet driver after a warm reboot
2328 lp
->a
.write_bcr(ioaddr
, 20, 4);
2331 spin_unlock_irqrestore(&lp
->lock
, flags
);
2332 free_irq(dev
->irq
, dev
);
2337 * The LANCE has been halted for one reason or another (busmaster memory
2338 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2339 * etc.). Modern LANCE variants always reload their ring-buffer
2340 * configuration when restarted, so we must reinitialize our ring
2341 * context before restarting. As part of this reinitialization,
2342 * find all packets still on the Tx ring and pretend that they had been
2343 * sent (in effect, drop the packets on the floor) - the higher-level
2344 * protocols will time out and retransmit. It'd be better to shuffle
2345 * these skbs to a temp list and then actually re-Tx them after
2346 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2349 static void pcnet32_purge_tx_ring(struct net_device
*dev
)
2351 struct pcnet32_private
*lp
= netdev_priv(dev
);
2354 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2355 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2356 wmb(); /* Make sure adapter sees owner change */
2357 if (lp
->tx_skbuff
[i
]) {
2358 pci_unmap_single(lp
->pci_dev
, lp
->tx_dma_addr
[i
],
2359 lp
->tx_skbuff
[i
]->len
,
2361 dev_kfree_skb_any(lp
->tx_skbuff
[i
]);
2363 lp
->tx_skbuff
[i
] = NULL
;
2364 lp
->tx_dma_addr
[i
] = 0;
2368 /* Initialize the PCNET32 Rx and Tx rings. */
2369 static int pcnet32_init_ring(struct net_device
*dev
)
2371 struct pcnet32_private
*lp
= netdev_priv(dev
);
2375 lp
->cur_rx
= lp
->cur_tx
= 0;
2376 lp
->dirty_rx
= lp
->dirty_tx
= 0;
2378 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
2379 struct sk_buff
*rx_skbuff
= lp
->rx_skbuff
[i
];
2380 if (rx_skbuff
== NULL
) {
2382 (rx_skbuff
= lp
->rx_skbuff
[i
] =
2383 dev_alloc_skb(PKT_BUF_SZ
))) {
2384 /* there is not much, we can do at this point */
2385 if (netif_msg_drv(lp
))
2387 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2391 skb_reserve(rx_skbuff
, 2);
2395 if (lp
->rx_dma_addr
[i
] == 0)
2396 lp
->rx_dma_addr
[i
] =
2397 pci_map_single(lp
->pci_dev
, rx_skbuff
->data
,
2398 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
2399 lp
->rx_ring
[i
].base
= (u32
) le32_to_cpu(lp
->rx_dma_addr
[i
]);
2400 lp
->rx_ring
[i
].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
2401 wmb(); /* Make sure owner changes after all others are visible */
2402 lp
->rx_ring
[i
].status
= le16_to_cpu(0x8000);
2404 /* The Tx buffer address is filled in as needed, but we do need to clear
2405 * the upper ownership bit. */
2406 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2407 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2408 wmb(); /* Make sure adapter sees owner change */
2409 lp
->tx_ring
[i
].base
= 0;
2410 lp
->tx_dma_addr
[i
] = 0;
2413 lp
->init_block
->tlen_rlen
=
2414 le16_to_cpu(lp
->tx_len_bits
| lp
->rx_len_bits
);
2415 for (i
= 0; i
< 6; i
++)
2416 lp
->init_block
->phys_addr
[i
] = dev
->dev_addr
[i
];
2417 lp
->init_block
->rx_ring
= (u32
) le32_to_cpu(lp
->rx_ring_dma_addr
);
2418 lp
->init_block
->tx_ring
= (u32
) le32_to_cpu(lp
->tx_ring_dma_addr
);
2419 wmb(); /* Make sure all changes are visible */
2423 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2424 * then flush the pending transmit operations, re-initialize the ring,
2425 * and tell the chip to initialize.
2427 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
)
2429 struct pcnet32_private
*lp
= netdev_priv(dev
);
2430 unsigned long ioaddr
= dev
->base_addr
;
2434 for (i
= 0; i
< 100; i
++)
2435 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_STOP
)
2438 if (i
>= 100 && netif_msg_drv(lp
))
2440 "%s: pcnet32_restart timed out waiting for stop.\n",
2443 pcnet32_purge_tx_ring(dev
);
2444 if (pcnet32_init_ring(dev
))
2448 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INIT
);
2451 if (lp
->a
.read_csr(ioaddr
, CSR0
) & CSR0_IDON
)
2454 lp
->a
.write_csr(ioaddr
, CSR0
, csr0_bits
);
2457 static void pcnet32_tx_timeout(struct net_device
*dev
)
2459 struct pcnet32_private
*lp
= netdev_priv(dev
);
2460 unsigned long ioaddr
= dev
->base_addr
, flags
;
2462 spin_lock_irqsave(&lp
->lock
, flags
);
2463 /* Transmitter timeout, serious problems. */
2464 if (pcnet32_debug
& NETIF_MSG_DRV
)
2466 "%s: transmit timed out, status %4.4x, resetting.\n",
2467 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2468 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2469 lp
->stats
.tx_errors
++;
2470 if (netif_msg_tx_err(lp
)) {
2473 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2474 lp
->dirty_tx
, lp
->cur_tx
, lp
->tx_full
? " (full)" : "",
2476 for (i
= 0; i
< lp
->rx_ring_size
; i
++)
2477 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
2478 le32_to_cpu(lp
->rx_ring
[i
].base
),
2479 (-le16_to_cpu(lp
->rx_ring
[i
].buf_length
)) &
2480 0xffff, le32_to_cpu(lp
->rx_ring
[i
].msg_length
),
2481 le16_to_cpu(lp
->rx_ring
[i
].status
));
2482 for (i
= 0; i
< lp
->tx_ring_size
; i
++)
2483 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
2484 le32_to_cpu(lp
->tx_ring
[i
].base
),
2485 (-le16_to_cpu(lp
->tx_ring
[i
].length
)) & 0xffff,
2486 le32_to_cpu(lp
->tx_ring
[i
].misc
),
2487 le16_to_cpu(lp
->tx_ring
[i
].status
));
2490 pcnet32_restart(dev
, CSR0_NORMAL
);
2492 dev
->trans_start
= jiffies
;
2493 netif_wake_queue(dev
);
2495 spin_unlock_irqrestore(&lp
->lock
, flags
);
2498 static int pcnet32_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2500 struct pcnet32_private
*lp
= netdev_priv(dev
);
2501 unsigned long ioaddr
= dev
->base_addr
;
2504 unsigned long flags
;
2506 spin_lock_irqsave(&lp
->lock
, flags
);
2508 if (netif_msg_tx_queued(lp
)) {
2510 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2511 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2514 /* Default status -- will not enable Successful-TxDone
2515 * interrupt when that option is available to us.
2519 /* Fill in a Tx ring entry */
2521 /* Mask to ring buffer boundary. */
2522 entry
= lp
->cur_tx
& lp
->tx_mod_mask
;
2524 /* Caution: the write order is important here, set the status
2525 * with the "ownership" bits last. */
2527 lp
->tx_ring
[entry
].length
= le16_to_cpu(-skb
->len
);
2529 lp
->tx_ring
[entry
].misc
= 0x00000000;
2531 lp
->tx_skbuff
[entry
] = skb
;
2532 lp
->tx_dma_addr
[entry
] =
2533 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
, PCI_DMA_TODEVICE
);
2534 lp
->tx_ring
[entry
].base
= (u32
) le32_to_cpu(lp
->tx_dma_addr
[entry
]);
2535 wmb(); /* Make sure owner changes after all others are visible */
2536 lp
->tx_ring
[entry
].status
= le16_to_cpu(status
);
2539 lp
->stats
.tx_bytes
+= skb
->len
;
2541 /* Trigger an immediate send poll. */
2542 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INTEN
| CSR0_TXPOLL
);
2544 dev
->trans_start
= jiffies
;
2546 if (lp
->tx_ring
[(entry
+ 1) & lp
->tx_mod_mask
].base
!= 0) {
2548 netif_stop_queue(dev
);
2550 spin_unlock_irqrestore(&lp
->lock
, flags
);
2554 /* The PCNET32 interrupt handler. */
2556 pcnet32_interrupt(int irq
, void *dev_id
)
2558 struct net_device
*dev
= dev_id
;
2559 struct pcnet32_private
*lp
;
2560 unsigned long ioaddr
;
2562 int boguscnt
= max_interrupt_work
;
2564 ioaddr
= dev
->base_addr
;
2565 lp
= netdev_priv(dev
);
2567 spin_lock(&lp
->lock
);
2569 csr0
= lp
->a
.read_csr(ioaddr
, CSR0
);
2570 while ((csr0
& 0x8f00) && --boguscnt
>= 0) {
2571 if (csr0
== 0xffff) {
2572 break; /* PCMCIA remove happened */
2574 /* Acknowledge all of the current interrupt sources ASAP. */
2575 lp
->a
.write_csr(ioaddr
, CSR0
, csr0
& ~0x004f);
2577 if (netif_msg_intr(lp
))
2579 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2580 dev
->name
, csr0
, lp
->a
.read_csr(ioaddr
, CSR0
));
2582 /* Log misc errors. */
2584 lp
->stats
.tx_errors
++; /* Tx babble. */
2585 if (csr0
& 0x1000) {
2587 * This happens when our receive ring is full. This
2588 * shouldn't be a problem as we will see normal rx
2589 * interrupts for the frames in the receive ring. But
2590 * there are some PCI chipsets (I can reproduce this
2591 * on SP3G with Intel saturn chipset) which have
2592 * sometimes problems and will fill up the receive
2593 * ring with error descriptors. In this situation we
2594 * don't get a rx interrupt, but a missed frame
2595 * interrupt sooner or later.
2597 lp
->stats
.rx_errors
++; /* Missed a Rx frame. */
2599 if (csr0
& 0x0800) {
2600 if (netif_msg_drv(lp
))
2602 "%s: Bus master arbitration failure, status %4.4x.\n",
2604 /* unlike for the lance, there is no restart needed */
2606 #ifdef CONFIG_PCNET32_NAPI
2607 if (netif_rx_schedule_prep(dev
, &lp
->napi
)) {
2609 /* set interrupt masks */
2610 val
= lp
->a
.read_csr(ioaddr
, CSR3
);
2612 lp
->a
.write_csr(ioaddr
, CSR3
, val
);
2614 __netif_rx_schedule(dev
, &lp
->napi
);
2618 pcnet32_rx(dev
, lp
->napi
.weight
);
2619 if (pcnet32_tx(dev
)) {
2620 /* reset the chip to clear the error condition, then restart */
2621 lp
->a
.reset(ioaddr
);
2622 lp
->a
.write_csr(ioaddr
, CSR4
, 0x0915); /* auto tx pad */
2623 pcnet32_restart(dev
, CSR0_START
);
2624 netif_wake_queue(dev
);
2627 csr0
= lp
->a
.read_csr(ioaddr
, CSR0
);
2630 #ifndef CONFIG_PCNET32_NAPI
2631 /* Set interrupt enable. */
2632 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_INTEN
);
2635 if (netif_msg_intr(lp
))
2636 printk(KERN_DEBUG
"%s: exiting interrupt, csr0=%#4.4x.\n",
2637 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2639 spin_unlock(&lp
->lock
);
2644 static int pcnet32_close(struct net_device
*dev
)
2646 unsigned long ioaddr
= dev
->base_addr
;
2647 struct pcnet32_private
*lp
= netdev_priv(dev
);
2648 unsigned long flags
;
2650 del_timer_sync(&lp
->watchdog_timer
);
2652 netif_stop_queue(dev
);
2653 #ifdef CONFIG_PCNET32_NAPI
2654 napi_disable(&lp
->napi
);
2657 spin_lock_irqsave(&lp
->lock
, flags
);
2659 lp
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2661 if (netif_msg_ifdown(lp
))
2663 "%s: Shutting down ethercard, status was %2.2x.\n",
2664 dev
->name
, lp
->a
.read_csr(ioaddr
, CSR0
));
2666 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2667 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2670 * Switch back to 16bit mode to avoid problems with dumb
2671 * DOS packet driver after a warm reboot
2673 lp
->a
.write_bcr(ioaddr
, 20, 4);
2675 spin_unlock_irqrestore(&lp
->lock
, flags
);
2677 free_irq(dev
->irq
, dev
);
2679 spin_lock_irqsave(&lp
->lock
, flags
);
2681 pcnet32_purge_rx_ring(dev
);
2682 pcnet32_purge_tx_ring(dev
);
2684 spin_unlock_irqrestore(&lp
->lock
, flags
);
2689 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*dev
)
2691 struct pcnet32_private
*lp
= netdev_priv(dev
);
2692 unsigned long ioaddr
= dev
->base_addr
;
2693 unsigned long flags
;
2695 spin_lock_irqsave(&lp
->lock
, flags
);
2696 lp
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2697 spin_unlock_irqrestore(&lp
->lock
, flags
);
2702 /* taken from the sunlance driver, which it took from the depca driver */
2703 static void pcnet32_load_multicast(struct net_device
*dev
)
2705 struct pcnet32_private
*lp
= netdev_priv(dev
);
2706 volatile struct pcnet32_init_block
*ib
= lp
->init_block
;
2707 volatile u16
*mcast_table
= (u16
*) & ib
->filter
;
2708 struct dev_mc_list
*dmi
= dev
->mc_list
;
2709 unsigned long ioaddr
= dev
->base_addr
;
2714 /* set all multicast bits */
2715 if (dev
->flags
& IFF_ALLMULTI
) {
2716 ib
->filter
[0] = 0xffffffff;
2717 ib
->filter
[1] = 0xffffffff;
2718 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
, 0xffff);
2719 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+1, 0xffff);
2720 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+2, 0xffff);
2721 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+3, 0xffff);
2724 /* clear the multicast filter */
2729 for (i
= 0; i
< dev
->mc_count
; i
++) {
2730 addrs
= dmi
->dmi_addr
;
2733 /* multicast address? */
2737 crc
= ether_crc_le(6, addrs
);
2739 mcast_table
[crc
>> 4] =
2740 le16_to_cpu(le16_to_cpu(mcast_table
[crc
>> 4]) |
2741 (1 << (crc
& 0xf)));
2743 for (i
= 0; i
< 4; i
++)
2744 lp
->a
.write_csr(ioaddr
, PCNET32_MC_FILTER
+ i
,
2745 le16_to_cpu(mcast_table
[i
]));
2750 * Set or clear the multicast filter for this adaptor.
2752 static void pcnet32_set_multicast_list(struct net_device
*dev
)
2754 unsigned long ioaddr
= dev
->base_addr
, flags
;
2755 struct pcnet32_private
*lp
= netdev_priv(dev
);
2756 int csr15
, suspended
;
2758 spin_lock_irqsave(&lp
->lock
, flags
);
2759 suspended
= pcnet32_suspend(dev
, &flags
, 0);
2760 csr15
= lp
->a
.read_csr(ioaddr
, CSR15
);
2761 if (dev
->flags
& IFF_PROMISC
) {
2762 /* Log any net taps. */
2763 if (netif_msg_hw(lp
))
2764 printk(KERN_INFO
"%s: Promiscuous mode enabled.\n",
2766 lp
->init_block
->mode
=
2767 le16_to_cpu(0x8000 | (lp
->options
& PCNET32_PORT_PORTSEL
) <<
2769 lp
->a
.write_csr(ioaddr
, CSR15
, csr15
| 0x8000);
2771 lp
->init_block
->mode
=
2772 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
2773 lp
->a
.write_csr(ioaddr
, CSR15
, csr15
& 0x7fff);
2774 pcnet32_load_multicast(dev
);
2779 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2780 csr5
= lp
->a
.read_csr(ioaddr
, CSR5
);
2781 lp
->a
.write_csr(ioaddr
, CSR5
, csr5
& (~CSR5_SUSPEND
));
2783 lp
->a
.write_csr(ioaddr
, CSR0
, CSR0_STOP
);
2784 pcnet32_restart(dev
, CSR0_NORMAL
);
2785 netif_wake_queue(dev
);
2788 spin_unlock_irqrestore(&lp
->lock
, flags
);
2791 /* This routine assumes that the lp->lock is held */
2792 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
)
2794 struct pcnet32_private
*lp
= netdev_priv(dev
);
2795 unsigned long ioaddr
= dev
->base_addr
;
2801 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2802 val_out
= lp
->a
.read_bcr(ioaddr
, 34);
2807 /* This routine assumes that the lp->lock is held */
2808 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
, int val
)
2810 struct pcnet32_private
*lp
= netdev_priv(dev
);
2811 unsigned long ioaddr
= dev
->base_addr
;
2816 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2817 lp
->a
.write_bcr(ioaddr
, 34, val
);
2820 static int pcnet32_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2822 struct pcnet32_private
*lp
= netdev_priv(dev
);
2824 unsigned long flags
;
2826 /* SIOC[GS]MIIxxx ioctls */
2828 spin_lock_irqsave(&lp
->lock
, flags
);
2829 rc
= generic_mii_ioctl(&lp
->mii_if
, if_mii(rq
), cmd
, NULL
);
2830 spin_unlock_irqrestore(&lp
->lock
, flags
);
2838 static int pcnet32_check_otherphy(struct net_device
*dev
)
2840 struct pcnet32_private
*lp
= netdev_priv(dev
);
2841 struct mii_if_info mii
= lp
->mii_if
;
2845 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
2846 if (i
== lp
->mii_if
.phy_id
)
2847 continue; /* skip active phy */
2848 if (lp
->phymask
& (1 << i
)) {
2850 if (mii_link_ok(&mii
)) {
2851 /* found PHY with active link */
2852 if (netif_msg_link(lp
))
2854 "%s: Using PHY number %d.\n",
2857 /* isolate inactive phy */
2859 mdio_read(dev
, lp
->mii_if
.phy_id
, MII_BMCR
);
2860 mdio_write(dev
, lp
->mii_if
.phy_id
, MII_BMCR
,
2861 bmcr
| BMCR_ISOLATE
);
2863 /* de-isolate new phy */
2864 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
2865 mdio_write(dev
, i
, MII_BMCR
,
2866 bmcr
& ~BMCR_ISOLATE
);
2868 /* set new phy address */
2869 lp
->mii_if
.phy_id
= i
;
2878 * Show the status of the media. Similar to mii_check_media however it
2879 * correctly shows the link speed for all (tested) pcnet32 variants.
2880 * Devices with no mii just report link state without speed.
2882 * Caller is assumed to hold and release the lp->lock.
2885 static void pcnet32_check_media(struct net_device
*dev
, int verbose
)
2887 struct pcnet32_private
*lp
= netdev_priv(dev
);
2889 int prev_link
= netif_carrier_ok(dev
) ? 1 : 0;
2893 curr_link
= mii_link_ok(&lp
->mii_if
);
2895 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
2896 curr_link
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
2899 if (prev_link
|| verbose
) {
2900 netif_carrier_off(dev
);
2901 if (netif_msg_link(lp
))
2902 printk(KERN_INFO
"%s: link down\n", dev
->name
);
2904 if (lp
->phycount
> 1) {
2905 curr_link
= pcnet32_check_otherphy(dev
);
2908 } else if (verbose
|| !prev_link
) {
2909 netif_carrier_on(dev
);
2911 if (netif_msg_link(lp
)) {
2912 struct ethtool_cmd ecmd
;
2913 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
2915 "%s: link up, %sMbps, %s-duplex\n",
2917 (ecmd
.speed
== SPEED_100
) ? "100" : "10",
2919 DUPLEX_FULL
) ? "full" : "half");
2921 bcr9
= lp
->a
.read_bcr(dev
->base_addr
, 9);
2922 if ((bcr9
& (1 << 0)) != lp
->mii_if
.full_duplex
) {
2923 if (lp
->mii_if
.full_duplex
)
2927 lp
->a
.write_bcr(dev
->base_addr
, 9, bcr9
);
2930 if (netif_msg_link(lp
))
2931 printk(KERN_INFO
"%s: link up\n", dev
->name
);
2937 * Check for loss of link and link establishment.
2938 * Can not use mii_check_media because it does nothing if mode is forced.
2941 static void pcnet32_watchdog(struct net_device
*dev
)
2943 struct pcnet32_private
*lp
= netdev_priv(dev
);
2944 unsigned long flags
;
2946 /* Print the link status if it has changed */
2947 spin_lock_irqsave(&lp
->lock
, flags
);
2948 pcnet32_check_media(dev
, 0);
2949 spin_unlock_irqrestore(&lp
->lock
, flags
);
2951 mod_timer(&(lp
->watchdog_timer
), PCNET32_WATCHDOG_TIMEOUT
);
2954 static int pcnet32_pm_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2956 struct net_device
*dev
= pci_get_drvdata(pdev
);
2958 if (netif_running(dev
)) {
2959 netif_device_detach(dev
);
2962 pci_save_state(pdev
);
2963 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
2967 static int pcnet32_pm_resume(struct pci_dev
*pdev
)
2969 struct net_device
*dev
= pci_get_drvdata(pdev
);
2971 pci_set_power_state(pdev
, PCI_D0
);
2972 pci_restore_state(pdev
);
2974 if (netif_running(dev
)) {
2976 netif_device_attach(dev
);
2981 static void __devexit
pcnet32_remove_one(struct pci_dev
*pdev
)
2983 struct net_device
*dev
= pci_get_drvdata(pdev
);
2986 struct pcnet32_private
*lp
= netdev_priv(dev
);
2988 unregister_netdev(dev
);
2989 pcnet32_free_ring(dev
);
2990 release_region(dev
->base_addr
, PCNET32_TOTAL_SIZE
);
2991 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
->init_block
),
2992 lp
->init_block
, lp
->init_dma_addr
);
2994 pci_disable_device(pdev
);
2995 pci_set_drvdata(pdev
, NULL
);
2999 static struct pci_driver pcnet32_driver
= {
3001 .probe
= pcnet32_probe_pci
,
3002 .remove
= __devexit_p(pcnet32_remove_one
),
3003 .id_table
= pcnet32_pci_tbl
,
3004 .suspend
= pcnet32_pm_suspend
,
3005 .resume
= pcnet32_pm_resume
,
3008 /* An additional parameter that may be passed in... */
3009 static int debug
= -1;
3010 static int tx_start_pt
= -1;
3011 static int pcnet32_have_pci
;
3013 module_param(debug
, int, 0);
3014 MODULE_PARM_DESC(debug
, DRV_NAME
" debug level");
3015 module_param(max_interrupt_work
, int, 0);
3016 MODULE_PARM_DESC(max_interrupt_work
,
3017 DRV_NAME
" maximum events handled per interrupt");
3018 module_param(rx_copybreak
, int, 0);
3019 MODULE_PARM_DESC(rx_copybreak
,
3020 DRV_NAME
" copy breakpoint for copy-only-tiny-frames");
3021 module_param(tx_start_pt
, int, 0);
3022 MODULE_PARM_DESC(tx_start_pt
, DRV_NAME
" transmit start point (0-3)");
3023 module_param(pcnet32vlb
, int, 0);
3024 MODULE_PARM_DESC(pcnet32vlb
, DRV_NAME
" Vesa local bus (VLB) support (0/1)");
3025 module_param_array(options
, int, NULL
, 0);
3026 MODULE_PARM_DESC(options
, DRV_NAME
" initial option setting(s) (0-15)");
3027 module_param_array(full_duplex
, int, NULL
, 0);
3028 MODULE_PARM_DESC(full_duplex
, DRV_NAME
" full duplex setting(s) (1)");
3029 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
3030 module_param_array(homepna
, int, NULL
, 0);
3031 MODULE_PARM_DESC(homepna
,
3033 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
3035 MODULE_AUTHOR("Thomas Bogendoerfer");
3036 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3037 MODULE_LICENSE("GPL");
3039 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3041 static int __init
pcnet32_init_module(void)
3043 printk(KERN_INFO
"%s", version
);
3045 pcnet32_debug
= netif_msg_init(debug
, PCNET32_MSG_DEFAULT
);
3047 if ((tx_start_pt
>= 0) && (tx_start_pt
<= 3))
3048 tx_start
= tx_start_pt
;
3050 /* find the PCI devices */
3051 if (!pci_register_driver(&pcnet32_driver
))
3052 pcnet32_have_pci
= 1;
3054 /* should we find any remaining VLbus devices ? */
3056 pcnet32_probe_vlbus(pcnet32_portlist
);
3058 if (cards_found
&& (pcnet32_debug
& NETIF_MSG_PROBE
))
3059 printk(KERN_INFO PFX
"%d cards_found.\n", cards_found
);
3061 return (pcnet32_have_pci
+ cards_found
) ? 0 : -ENODEV
;
3064 static void __exit
pcnet32_cleanup_module(void)
3066 struct net_device
*next_dev
;
3068 while (pcnet32_dev
) {
3069 struct pcnet32_private
*lp
= netdev_priv(pcnet32_dev
);
3070 next_dev
= lp
->next
;
3071 unregister_netdev(pcnet32_dev
);
3072 pcnet32_free_ring(pcnet32_dev
);
3073 release_region(pcnet32_dev
->base_addr
, PCNET32_TOTAL_SIZE
);
3074 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
->init_block
),
3075 lp
->init_block
, lp
->init_dma_addr
);
3076 free_netdev(pcnet32_dev
);
3077 pcnet32_dev
= next_dev
;
3080 if (pcnet32_have_pci
)
3081 pci_unregister_driver(&pcnet32_driver
);
3084 module_init(pcnet32_init_module
);
3085 module_exit(pcnet32_cleanup_module
);