[PATCH] bcm43xx: Fix array overrun in bcm43xx_geo_init
[linux-2.6/kmemtrace.git] / include / asm-sparc64 / irq.h
blobde33d6e1afb52d008d63cb3067390871bb9eb752
1 /* $Id: irq.h,v 1.21 2002/01/23 11:27:36 davem Exp $
2 * irq.h: IRQ registers on the 64-bit Sparc.
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
6 */
8 #ifndef _SPARC64_IRQ_H
9 #define _SPARC64_IRQ_H
11 #include <linux/config.h>
12 #include <linux/linkage.h>
13 #include <linux/kernel.h>
14 #include <linux/errno.h>
15 #include <linux/interrupt.h>
16 #include <asm/pil.h>
17 #include <asm/ptrace.h>
19 struct ino_bucket;
21 #define MAX_IRQ_DESC_ACTION 4
23 struct irq_desc {
24 void (*pre_handler)(struct ino_bucket *, void *, void *);
25 void *pre_handler_arg1;
26 void *pre_handler_arg2;
27 u32 action_active_mask;
28 struct irqaction action[MAX_IRQ_DESC_ACTION];
31 /* You should not mess with this directly. That's the job of irq.c.
33 * If you make changes here, please update hand coded assembler of
34 * the vectored interrupt trap handler in entry.S -DaveM
36 * This is currently one DCACHE line, two buckets per L2 cache
37 * line. Keep this in mind please.
39 struct ino_bucket {
40 /* Next handler in per-CPU PIL worklist. We know that
41 * bucket pointers have the high 32-bits clear, so to
42 * save space we only store the bits we need.
44 /*0x00*/unsigned int irq_chain;
46 /* PIL to schedule this IVEC at. */
47 /*0x04*/unsigned char pil;
49 /* If an IVEC arrives while irq_info is NULL, we
50 * set this to notify request_irq() about the event.
52 /*0x05*/unsigned char pending;
54 /* Miscellaneous flags. */
55 /*0x06*/unsigned char flags;
57 /* Currently unused. */
58 /*0x07*/unsigned char __pad;
60 /* Reference to IRQ descriptor for this bucket. */
61 /*0x08*/struct irq_desc *irq_info;
63 /* Sun5 Interrupt Clear Register. */
64 /*0x10*/unsigned long iclr;
66 /* Sun5 Interrupt Mapping Register. */
67 /*0x18*/unsigned long imap;
71 /* IMAP/ICLR register defines */
72 #define IMAP_VALID 0x80000000 /* IRQ Enabled */
73 #define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
74 #define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */
75 #define IMAP_TID_SHIFT 26
76 #define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */
77 #define IMAP_AID_SHIFT 26
78 #define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */
79 #define IMAP_NID_SHIFT 21
80 #define IMAP_IGN 0x000007c0 /* IRQ Group Number */
81 #define IMAP_INO 0x0000003f /* IRQ Number */
82 #define IMAP_INR 0x000007ff /* Full interrupt number*/
84 #define ICLR_IDLE 0x00000000 /* Idle state */
85 #define ICLR_TRANSMIT 0x00000001 /* Transmit state */
86 #define ICLR_PENDING 0x00000003 /* Pending state */
88 /* Only 8-bits are available, be careful. -DaveM */
89 #define IBF_PCI 0x02 /* PSYCHO/SABRE/SCHIZO PCI interrupt. */
90 #define IBF_ACTIVE 0x04 /* Interrupt is active and has a handler.*/
91 #define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */
93 #define NUM_IVECS (IMAP_INR + 1)
94 extern struct ino_bucket ivector_table[NUM_IVECS];
96 #define __irq_ino(irq) \
97 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
98 #define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
99 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
100 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
102 static __inline__ char *__irq_itoa(unsigned int irq)
104 static char buff[16];
106 sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
107 return buff;
110 #define NR_IRQS 16
112 #define irq_canonicalize(irq) (irq)
113 extern void disable_irq(unsigned int);
114 #define disable_irq_nosync disable_irq
115 extern void enable_irq(unsigned int);
116 extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
117 extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags);
118 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
120 static __inline__ void set_softint(unsigned long bits)
122 __asm__ __volatile__("wr %0, 0x0, %%set_softint"
123 : /* No outputs */
124 : "r" (bits));
127 static __inline__ void clear_softint(unsigned long bits)
129 __asm__ __volatile__("wr %0, 0x0, %%clear_softint"
130 : /* No outputs */
131 : "r" (bits));
134 static __inline__ unsigned long get_softint(void)
136 unsigned long retval;
138 __asm__ __volatile__("rd %%softint, %0"
139 : "=r" (retval));
140 return retval;
143 struct irqaction;
144 struct pt_regs;
145 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
147 #endif