2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
13 #include <asm/processor.h>
14 #include <asm/tlbflush.h>
15 #include <asm/sections.h>
16 #include <asm/uaccess.h>
17 #include <asm/pgalloc.h>
20 * The current flushing context - we pass it instead of 5 arguments:
31 within(unsigned long addr
, unsigned long start
, unsigned long end
)
33 return addr
>= start
&& addr
< end
;
41 * clflush_cache_range - flush a cache range with clflush
42 * @addr: virtual start address
43 * @size: number of bytes to flush
45 * clflush is an unordered instruction which needs fencing with mfence
46 * to avoid ordering issues.
48 void clflush_cache_range(void *vaddr
, unsigned int size
)
50 void *vend
= vaddr
+ size
- 1;
54 for (; vaddr
< vend
; vaddr
+= boot_cpu_data
.x86_clflush_size
)
57 * Flush any possible final partial cacheline:
64 static void __cpa_flush_all(void *arg
)
66 unsigned long cache
= (unsigned long)arg
;
69 * Flush all to work around Errata in early athlons regarding
70 * large page flushing.
74 if (cache
&& boot_cpu_data
.x86_model
>= 4)
78 static void cpa_flush_all(unsigned long cache
)
80 BUG_ON(irqs_disabled());
82 on_each_cpu(__cpa_flush_all
, (void *) cache
, 1, 1);
85 static void __cpa_flush_range(void *arg
)
88 * We could optimize that further and do individual per page
89 * tlb invalidates for a low number of pages. Caveat: we must
90 * flush the high aliases on 64bit as well.
95 static void cpa_flush_range(unsigned long start
, int numpages
, int cache
)
97 unsigned int i
, level
;
100 BUG_ON(irqs_disabled());
101 WARN_ON(PAGE_ALIGN(start
) != start
);
103 on_each_cpu(__cpa_flush_range
, NULL
, 1, 1);
109 * We only need to flush on one CPU,
110 * clflush is a MESI-coherent instruction that
111 * will cause all other CPUs to flush the same
114 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
+= PAGE_SIZE
) {
115 pte_t
*pte
= lookup_address(addr
, &level
);
118 * Only flush present addresses:
120 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
121 clflush_cache_range((void *) addr
, PAGE_SIZE
);
125 #define HIGH_MAP_START __START_KERNEL_map
126 #define HIGH_MAP_END (__START_KERNEL_map + KERNEL_TEXT_SIZE)
130 * Converts a virtual address to a X86-64 highmap address
132 static unsigned long virt_to_highmap(void *address
)
135 return __pa((unsigned long)address
) + HIGH_MAP_START
- phys_base
;
137 return (unsigned long)address
;
142 * Certain areas of memory on x86 require very specific protection flags,
143 * for example the BIOS area or kernel text. Callers don't always get this
144 * right (again, ioremap() on BIOS memory is not uncommon) so this function
145 * checks and fixes these known static required protection bits.
147 static inline pgprot_t
static_protections(pgprot_t prot
, unsigned long address
)
149 pgprot_t forbidden
= __pgprot(0);
152 * The BIOS area between 640k and 1Mb needs to be executable for
153 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
155 if (within(__pa(address
), BIOS_BEGIN
, BIOS_END
))
156 pgprot_val(forbidden
) |= _PAGE_NX
;
159 * The kernel text needs to be executable for obvious reasons
160 * Does not cover __inittext since that is gone later on
162 if (within(address
, (unsigned long)_text
, (unsigned long)_etext
))
163 pgprot_val(forbidden
) |= _PAGE_NX
;
165 * Do the same for the x86-64 high kernel mapping
167 if (within(address
, virt_to_highmap(_text
), virt_to_highmap(_etext
)))
168 pgprot_val(forbidden
) |= _PAGE_NX
;
171 #ifdef CONFIG_DEBUG_RODATA
172 /* The .rodata section needs to be read-only */
173 if (within(address
, (unsigned long)__start_rodata
,
174 (unsigned long)__end_rodata
))
175 pgprot_val(forbidden
) |= _PAGE_RW
;
177 * Do the same for the x86-64 high kernel mapping
179 if (within(address
, virt_to_highmap(__start_rodata
),
180 virt_to_highmap(__end_rodata
)))
181 pgprot_val(forbidden
) |= _PAGE_RW
;
184 prot
= __pgprot(pgprot_val(prot
) & ~pgprot_val(forbidden
));
190 * Lookup the page table entry for a virtual address. Return a pointer
191 * to the entry and the level of the mapping.
193 * Note: We return pud and pmd either when the entry is marked large
194 * or when the present bit is not set. Otherwise we would return a
195 * pointer to a nonexisting mapping.
197 pte_t
*lookup_address(unsigned long address
, int *level
)
199 pgd_t
*pgd
= pgd_offset_k(address
);
203 *level
= PG_LEVEL_NONE
;
208 pud
= pud_offset(pgd
, address
);
212 *level
= PG_LEVEL_1G
;
213 if (pud_large(*pud
) || !pud_present(*pud
))
216 pmd
= pmd_offset(pud
, address
);
220 *level
= PG_LEVEL_2M
;
221 if (pmd_large(*pmd
) || !pmd_present(*pmd
))
224 *level
= PG_LEVEL_4K
;
226 return pte_offset_kernel(pmd
, address
);
230 * Set the new pmd in all the pgds we know about:
232 static void __set_pmd_pte(pte_t
*kpte
, unsigned long address
, pte_t pte
)
235 set_pte_atomic(kpte
, pte
);
237 if (!SHARED_KERNEL_PMD
) {
240 address
= __pa(address
);
241 list_for_each_entry(page
, &pgd_list
, lru
) {
246 pgd
= (pgd_t
*)page_address(page
) + pgd_index(address
);
247 pud
= pud_offset(pgd
, address
);
248 pmd
= pmd_offset(pud
, address
);
249 set_pte_atomic((pte_t
*)pmd
, pte
);
256 try_preserve_large_page(pte_t
*kpte
, unsigned long address
,
257 struct cpa_data
*cpa
)
259 unsigned long nextpage_addr
, numpages
, pmask
, psize
, flags
;
260 pte_t new_pte
, old_pte
, *tmp
;
261 pgprot_t old_prot
, new_prot
;
262 int level
, do_split
= 1;
265 * An Athlon 64 X2 showed hard hangs if we tried to preserve
266 * largepages and changed the PSE entry from RW to RO.
268 * As AMD CPUs have a long series of erratas in this area,
269 * (and none of the known ones seem to explain this hang),
270 * disable this code until the hang can be debugged:
272 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
275 spin_lock_irqsave(&pgd_lock
, flags
);
277 * Check for races, another CPU might have split this page
280 tmp
= lookup_address(address
, &level
);
286 psize
= PMD_PAGE_SIZE
;
287 pmask
= PMD_PAGE_MASK
;
291 psize
= PMD_PAGE_SIZE
;
292 pmask
= PMD_PAGE_MASK
;
301 * Calculate the number of pages, which fit into this large
302 * page starting at address:
304 nextpage_addr
= (address
+ psize
) & pmask
;
305 numpages
= (nextpage_addr
- address
) >> PAGE_SHIFT
;
306 if (numpages
< cpa
->numpages
)
307 cpa
->numpages
= numpages
;
310 * We are safe now. Check whether the new pgprot is the same:
313 old_prot
= new_prot
= pte_pgprot(old_pte
);
315 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
316 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
317 new_prot
= static_protections(new_prot
, address
);
320 * If there are no changes, return. maxpages has been updated
323 if (pgprot_val(new_prot
) == pgprot_val(old_prot
)) {
329 * We need to change the attributes. Check, whether we can
330 * change the large page in one go. We request a split, when
331 * the address is not aligned and the number of pages is
332 * smaller than the number of pages in the large page. Note
333 * that we limited the number of possible pages already to
334 * the number of pages in the large page.
336 if (address
== (nextpage_addr
- psize
) && cpa
->numpages
== numpages
) {
338 * The address is aligned and the number of pages
339 * covers the full page.
341 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
342 __set_pmd_pte(kpte
, address
, new_pte
);
348 spin_unlock_irqrestore(&pgd_lock
, flags
);
353 static int split_large_page(pte_t
*kpte
, unsigned long address
)
355 unsigned long flags
, pfn
, pfninc
= 1;
356 gfp_t gfp_flags
= GFP_KERNEL
;
357 unsigned int i
, level
;
362 #ifdef CONFIG_DEBUG_PAGEALLOC
363 gfp_flags
= GFP_ATOMIC
| __GFP_NOWARN
;
365 base
= alloc_pages(gfp_flags
, 0);
369 spin_lock_irqsave(&pgd_lock
, flags
);
371 * Check for races, another CPU might have split this page
374 tmp
= lookup_address(address
, &level
);
378 pbase
= (pte_t
*)page_address(base
);
380 paravirt_alloc_pt(&init_mm
, page_to_pfn(base
));
382 ref_prot
= pte_pgprot(pte_clrhuge(*kpte
));
385 if (level
== PG_LEVEL_1G
) {
386 pfninc
= PMD_PAGE_SIZE
>> PAGE_SHIFT
;
387 pgprot_val(ref_prot
) |= _PAGE_PSE
;
392 * Get the target pfn from the original entry:
394 pfn
= pte_pfn(*kpte
);
395 for (i
= 0; i
< PTRS_PER_PTE
; i
++, pfn
+= pfninc
)
396 set_pte(&pbase
[i
], pfn_pte(pfn
, ref_prot
));
399 * Install the new, split up pagetable. Important details here:
401 * On Intel the NX bit of all levels must be cleared to make a
402 * page executable. See section 4.13.2 of Intel 64 and IA-32
403 * Architectures Software Developer's Manual).
405 * Mark the entry present. The current mapping might be
406 * set to not present, which we preserved above.
408 ref_prot
= pte_pgprot(pte_mkexec(pte_clrhuge(*kpte
)));
409 pgprot_val(ref_prot
) |= _PAGE_PRESENT
;
410 __set_pmd_pte(kpte
, address
, mk_pte(base
, ref_prot
));
414 spin_unlock_irqrestore(&pgd_lock
, flags
);
417 __free_pages(base
, 0);
422 static int __change_page_attr(unsigned long address
, struct cpa_data
*cpa
)
424 int level
, do_split
, err
;
425 struct page
*kpte_page
;
429 kpte
= lookup_address(address
, &level
);
433 kpte_page
= virt_to_page(kpte
);
434 BUG_ON(PageLRU(kpte_page
));
435 BUG_ON(PageCompound(kpte_page
));
437 if (level
== PG_LEVEL_4K
) {
438 pte_t new_pte
, old_pte
= *kpte
;
439 pgprot_t new_prot
= pte_pgprot(old_pte
);
441 if(!pte_val(old_pte
)) {
442 printk(KERN_WARNING
"CPA: called for zero pte. "
443 "vaddr = %lx cpa->vaddr = %lx\n", address
,
449 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
450 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
452 new_prot
= static_protections(new_prot
, address
);
455 * We need to keep the pfn from the existing PTE,
456 * after all we're only going to change it's attributes
457 * not the memory it points to
459 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
462 * Do we really change anything ?
464 if (pte_val(old_pte
) != pte_val(new_pte
)) {
465 set_pte_atomic(kpte
, new_pte
);
473 * Check, whether we can keep the large page intact
474 * and just change the pte:
476 do_split
= try_preserve_large_page(kpte
, address
, cpa
);
478 * When the range fits into the existing large page,
479 * return. cp->numpages and cpa->tlbflush have been updated in
486 * We have to split the large page:
488 err
= split_large_page(kpte
, address
);
498 * change_page_attr_addr - Change page table attributes in linear mapping
499 * @address: Virtual address in linear mapping.
500 * @prot: New page table attribute (PAGE_*)
502 * Change page attributes of a page in the direct mapping. This is a variant
503 * of change_page_attr() that also works on memory holes that do not have
504 * mem_map entry (pfn_valid() is false).
506 * See change_page_attr() documentation for more details.
508 * Modules and drivers should use the set_memory_* APIs instead.
510 static int change_page_attr_addr(struct cpa_data
*cpa
)
513 unsigned long address
= cpa
->vaddr
;
516 unsigned long phys_addr
= __pa(address
);
519 * If we are inside the high mapped kernel range, then we
520 * fixup the low mapping first. __va() returns the virtual
521 * address in the linear mapping:
523 if (within(address
, HIGH_MAP_START
, HIGH_MAP_END
))
524 address
= (unsigned long) __va(phys_addr
);
527 err
= __change_page_attr(address
, cpa
);
533 * If the physical address is inside the kernel map, we need
534 * to touch the high mapped kernel as well:
536 if (within(phys_addr
, 0, KERNEL_TEXT_SIZE
)) {
538 * Calc the high mapping address. See __phys_addr()
539 * for the non obvious details.
541 * Note that NX and other required permissions are
542 * checked in static_protections().
544 address
= phys_addr
+ HIGH_MAP_START
- phys_base
;
547 * Our high aliases are imprecise, because we check
548 * everything between 0 and KERNEL_TEXT_SIZE, so do
549 * not propagate lookup failures back to users:
551 __change_page_attr(address
, cpa
);
557 static int __change_page_attr_set_clr(struct cpa_data
*cpa
)
559 int ret
, numpages
= cpa
->numpages
;
563 * Store the remaining nr of pages for the large page
564 * preservation check.
566 cpa
->numpages
= numpages
;
567 ret
= change_page_attr_addr(cpa
);
572 * Adjust the number of pages with the result of the
573 * CPA operation. Either a large page has been
574 * preserved or a single page update happened.
576 BUG_ON(cpa
->numpages
> numpages
);
577 numpages
-= cpa
->numpages
;
578 cpa
->vaddr
+= cpa
->numpages
* PAGE_SIZE
;
583 static inline int cache_attr(pgprot_t attr
)
585 return pgprot_val(attr
) &
586 (_PAGE_PAT
| _PAGE_PAT_LARGE
| _PAGE_PWT
| _PAGE_PCD
);
589 static int change_page_attr_set_clr(unsigned long addr
, int numpages
,
590 pgprot_t mask_set
, pgprot_t mask_clr
)
596 * Check, if we are requested to change a not supported
599 mask_set
= canon_pgprot(mask_set
);
600 mask_clr
= canon_pgprot(mask_clr
);
601 if (!pgprot_val(mask_set
) && !pgprot_val(mask_clr
))
605 cpa
.numpages
= numpages
;
606 cpa
.mask_set
= mask_set
;
607 cpa
.mask_clr
= mask_clr
;
610 ret
= __change_page_attr_set_clr(&cpa
);
613 * Check whether we really changed something:
619 * No need to flush, when we did not set any of the caching
622 cache
= cache_attr(mask_set
);
625 * On success we use clflush, when the CPU supports it to
626 * avoid the wbindv. If the CPU does not support it and in the
627 * error case we fall back to cpa_flush_all (which uses
630 if (!ret
&& cpu_has_clflush
)
631 cpa_flush_range(addr
, numpages
, cache
);
633 cpa_flush_all(cache
);
638 static inline int change_page_attr_set(unsigned long addr
, int numpages
,
641 return change_page_attr_set_clr(addr
, numpages
, mask
, __pgprot(0));
644 static inline int change_page_attr_clear(unsigned long addr
, int numpages
,
647 return change_page_attr_set_clr(addr
, numpages
, __pgprot(0), mask
);
650 int set_memory_uc(unsigned long addr
, int numpages
)
652 return change_page_attr_set(addr
, numpages
,
653 __pgprot(_PAGE_PCD
| _PAGE_PWT
));
655 EXPORT_SYMBOL(set_memory_uc
);
657 int set_memory_wb(unsigned long addr
, int numpages
)
659 return change_page_attr_clear(addr
, numpages
,
660 __pgprot(_PAGE_PCD
| _PAGE_PWT
));
662 EXPORT_SYMBOL(set_memory_wb
);
664 int set_memory_x(unsigned long addr
, int numpages
)
666 return change_page_attr_clear(addr
, numpages
, __pgprot(_PAGE_NX
));
668 EXPORT_SYMBOL(set_memory_x
);
670 int set_memory_nx(unsigned long addr
, int numpages
)
672 return change_page_attr_set(addr
, numpages
, __pgprot(_PAGE_NX
));
674 EXPORT_SYMBOL(set_memory_nx
);
676 int set_memory_ro(unsigned long addr
, int numpages
)
678 return change_page_attr_clear(addr
, numpages
, __pgprot(_PAGE_RW
));
681 int set_memory_rw(unsigned long addr
, int numpages
)
683 return change_page_attr_set(addr
, numpages
, __pgprot(_PAGE_RW
));
686 int set_memory_np(unsigned long addr
, int numpages
)
688 return change_page_attr_clear(addr
, numpages
, __pgprot(_PAGE_PRESENT
));
691 int set_pages_uc(struct page
*page
, int numpages
)
693 unsigned long addr
= (unsigned long)page_address(page
);
695 return set_memory_uc(addr
, numpages
);
697 EXPORT_SYMBOL(set_pages_uc
);
699 int set_pages_wb(struct page
*page
, int numpages
)
701 unsigned long addr
= (unsigned long)page_address(page
);
703 return set_memory_wb(addr
, numpages
);
705 EXPORT_SYMBOL(set_pages_wb
);
707 int set_pages_x(struct page
*page
, int numpages
)
709 unsigned long addr
= (unsigned long)page_address(page
);
711 return set_memory_x(addr
, numpages
);
713 EXPORT_SYMBOL(set_pages_x
);
715 int set_pages_nx(struct page
*page
, int numpages
)
717 unsigned long addr
= (unsigned long)page_address(page
);
719 return set_memory_nx(addr
, numpages
);
721 EXPORT_SYMBOL(set_pages_nx
);
723 int set_pages_ro(struct page
*page
, int numpages
)
725 unsigned long addr
= (unsigned long)page_address(page
);
727 return set_memory_ro(addr
, numpages
);
730 int set_pages_rw(struct page
*page
, int numpages
)
732 unsigned long addr
= (unsigned long)page_address(page
);
734 return set_memory_rw(addr
, numpages
);
737 #ifdef CONFIG_DEBUG_PAGEALLOC
739 static int __set_pages_p(struct page
*page
, int numpages
)
741 struct cpa_data cpa
= { .vaddr
= (unsigned long) page_address(page
),
742 .numpages
= numpages
,
743 .mask_set
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
744 .mask_clr
= __pgprot(0)};
746 return __change_page_attr_set_clr(&cpa
);
749 static int __set_pages_np(struct page
*page
, int numpages
)
751 struct cpa_data cpa
= { .vaddr
= (unsigned long) page_address(page
),
752 .numpages
= numpages
,
753 .mask_set
= __pgprot(0),
754 .mask_clr
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
)};
756 return __change_page_attr_set_clr(&cpa
);
759 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
761 if (PageHighMem(page
))
764 debug_check_no_locks_freed(page_address(page
),
765 numpages
* PAGE_SIZE
);
769 * If page allocator is not up yet then do not call c_p_a():
771 if (!debug_pagealloc_enabled
)
775 * The return value is ignored - the calls cannot fail,
776 * large pages are disabled at boot time:
779 __set_pages_p(page
, numpages
);
781 __set_pages_np(page
, numpages
);
784 * We should perform an IPI and flush all tlbs,
785 * but that can deadlock->flush only current cpu:
792 * The testcases use internal knowledge of the implementation that shouldn't
793 * be exposed to the rest of the kernel. Include these directly here.
795 #ifdef CONFIG_CPA_DEBUG
796 #include "pageattr-test.c"