1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
4 #include <asm/asm-compat.h>
6 #define PPC_FEATURE_32 0x80000000
7 #define PPC_FEATURE_64 0x40000000
8 #define PPC_FEATURE_601_INSTR 0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10 #define PPC_FEATURE_HAS_FPU 0x08000000
11 #define PPC_FEATURE_HAS_MMU 0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14 #define PPC_FEATURE_HAS_SPE 0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16 #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
17 #define PPC_FEATURE_NO_TB 0x00100000
18 #define PPC_FEATURE_POWER4 0x00080000
19 #define PPC_FEATURE_POWER5 0x00040000
20 #define PPC_FEATURE_POWER5_PLUS 0x00020000
21 #define PPC_FEATURE_CELL 0x00010000
22 #define PPC_FEATURE_BOOKE 0x00008000
27 /* This structure can grow, it's real size is used by head.S code
28 * via the mkdefs mechanism.
32 typedef void (*cpu_setup_t
)(unsigned long offset
, struct cpu_spec
* spec
);
34 enum powerpc_oprofile_type
{
35 PPC_OPROFILE_INVALID
= 0,
36 PPC_OPROFILE_RS64
= 1,
37 PPC_OPROFILE_POWER4
= 2,
39 PPC_OPROFILE_BOOKE
= 4,
43 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
44 unsigned int pvr_mask
;
45 unsigned int pvr_value
;
48 unsigned long cpu_features
; /* Kernel features */
49 unsigned int cpu_user_features
; /* Userland features */
51 /* cache line sizes */
52 unsigned int icache_bsize
;
53 unsigned int dcache_bsize
;
55 /* number of performance monitor counters */
56 unsigned int num_pmcs
;
58 /* this is called to initialize various CPU bits like L1 cache,
59 * BHT, SPD, etc... from head.S before branching to identify_machine
61 cpu_setup_t cpu_setup
;
63 /* Used by oprofile userspace to select the right counters */
64 char *oprofile_cpu_type
;
66 /* Processor specific oprofile operations */
67 enum powerpc_oprofile_type oprofile_type
;
69 /* Name of processor class, for the ELF AT_PLATFORM entry */
73 extern struct cpu_spec
*cur_cpu_spec
;
75 extern void identify_cpu(unsigned long offset
, unsigned long cpu
);
76 extern void do_cpu_ftr_fixups(unsigned long offset
);
78 #endif /* __ASSEMBLY__ */
80 /* CPU kernel features */
82 /* Retain the 32b definitions all use bottom half of word */
83 #define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
84 #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
85 #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
86 #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
87 #define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
88 #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
89 #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
90 #define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
91 #define CPU_FTR_601 ASM_CONST(0x0000000000000100)
92 #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
93 #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
94 #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
95 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
96 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
97 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
98 #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
99 #define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
100 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
101 #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
102 #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
103 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
106 /* Add the 64b processor unique features in the top half of the word */
107 #define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
108 #define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
109 #define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
110 #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
111 #define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
112 #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
113 #define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
114 #define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
115 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
116 #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
117 #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
118 #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
119 #define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
121 /* ensure on 32b processors the flags are available for compiling but
122 * don't do anything */
123 #define CPU_FTR_SLB ASM_CONST(0x0)
124 #define CPU_FTR_16M_PAGE ASM_CONST(0x0)
125 #define CPU_FTR_TLBIEL ASM_CONST(0x0)
126 #define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
127 #define CPU_FTR_IABR ASM_CONST(0x0)
128 #define CPU_FTR_MMCRA ASM_CONST(0x0)
129 #define CPU_FTR_CTRL ASM_CONST(0x0)
130 #define CPU_FTR_SMT ASM_CONST(0x0)
131 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
132 #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
133 #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
134 #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
139 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
140 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
141 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
143 /* iSeries doesn't support large pages */
144 #ifdef CONFIG_PPC_ISERIES
145 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
147 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
148 #endif /* CONFIG_PPC_ISERIES */
150 /* We only set the altivec features if the kernel was compiled with altivec
153 #ifdef CONFIG_ALTIVEC
154 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
155 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
157 #define CPU_FTR_ALTIVEC_COMP 0
158 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
161 /* We need to mark all pages as being coherent if we're SMP or we
162 * have a 74[45]x and an MPC107 host bridge.
164 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
165 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
167 #define CPU_FTR_COMMON 0
170 /* The powersave features NAP & DOZE seems to confuse BDI when
171 debugging. So if a BDI is used, disable theses
173 #ifndef CONFIG_BDI_SWITCH
174 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
175 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
177 #define CPU_FTR_MAYBE_CAN_DOZE 0
178 #define CPU_FTR_MAYBE_CAN_NAP 0
181 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
182 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
183 !defined(CONFIG_BOOKE))
186 CPU_FTRS_PPC601
= CPU_FTR_COMMON
| CPU_FTR_601
| CPU_FTR_HPTE_TABLE
,
187 CPU_FTRS_603
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
188 CPU_FTR_MAYBE_CAN_DOZE
| CPU_FTR_USE_TB
|
189 CPU_FTR_MAYBE_CAN_NAP
,
190 CPU_FTRS_604
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
191 CPU_FTR_USE_TB
| CPU_FTR_604_PERF_MON
| CPU_FTR_HPTE_TABLE
,
192 CPU_FTRS_740_NOTAU
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
193 CPU_FTR_MAYBE_CAN_DOZE
| CPU_FTR_USE_TB
| CPU_FTR_L2CR
|
194 CPU_FTR_HPTE_TABLE
| CPU_FTR_MAYBE_CAN_NAP
,
195 CPU_FTRS_740
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
196 CPU_FTR_MAYBE_CAN_DOZE
| CPU_FTR_USE_TB
| CPU_FTR_L2CR
|
197 CPU_FTR_TAU
| CPU_FTR_HPTE_TABLE
| CPU_FTR_MAYBE_CAN_NAP
,
198 CPU_FTRS_750
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
199 CPU_FTR_MAYBE_CAN_DOZE
| CPU_FTR_USE_TB
| CPU_FTR_L2CR
|
200 CPU_FTR_TAU
| CPU_FTR_HPTE_TABLE
| CPU_FTR_MAYBE_CAN_NAP
,
201 CPU_FTRS_750FX1
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
202 CPU_FTR_MAYBE_CAN_DOZE
| CPU_FTR_USE_TB
| CPU_FTR_L2CR
|
203 CPU_FTR_TAU
| CPU_FTR_HPTE_TABLE
| CPU_FTR_MAYBE_CAN_NAP
|
204 CPU_FTR_DUAL_PLL_750FX
| CPU_FTR_NO_DPM
,
205 CPU_FTRS_750FX2
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
206 CPU_FTR_MAYBE_CAN_DOZE
| CPU_FTR_USE_TB
| CPU_FTR_L2CR
|
207 CPU_FTR_TAU
| CPU_FTR_HPTE_TABLE
| CPU_FTR_MAYBE_CAN_NAP
|
209 CPU_FTRS_750FX
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
210 CPU_FTR_MAYBE_CAN_DOZE
| CPU_FTR_USE_TB
| CPU_FTR_L2CR
|
211 CPU_FTR_TAU
| CPU_FTR_HPTE_TABLE
| CPU_FTR_MAYBE_CAN_NAP
|
212 CPU_FTR_DUAL_PLL_750FX
| CPU_FTR_HAS_HIGH_BATS
,
213 CPU_FTRS_750GX
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_MAYBE_CAN_DOZE
|
214 CPU_FTR_USE_TB
| CPU_FTR_L2CR
| CPU_FTR_TAU
|
215 CPU_FTR_HPTE_TABLE
| CPU_FTR_MAYBE_CAN_NAP
|
216 CPU_FTR_DUAL_PLL_750FX
| CPU_FTR_HAS_HIGH_BATS
,
217 CPU_FTRS_7400_NOTAU
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
218 CPU_FTR_MAYBE_CAN_DOZE
| CPU_FTR_USE_TB
| CPU_FTR_L2CR
|
219 CPU_FTR_ALTIVEC_COMP
| CPU_FTR_HPTE_TABLE
|
220 CPU_FTR_MAYBE_CAN_NAP
,
221 CPU_FTRS_7400
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
222 CPU_FTR_MAYBE_CAN_DOZE
| CPU_FTR_USE_TB
| CPU_FTR_L2CR
|
223 CPU_FTR_TAU
| CPU_FTR_ALTIVEC_COMP
| CPU_FTR_HPTE_TABLE
|
224 CPU_FTR_MAYBE_CAN_NAP
,
225 CPU_FTRS_7450_20
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
226 CPU_FTR_USE_TB
| CPU_FTR_L2CR
| CPU_FTR_ALTIVEC_COMP
|
227 CPU_FTR_L3CR
| CPU_FTR_HPTE_TABLE
| CPU_FTR_SPEC7450
|
228 CPU_FTR_NEED_COHERENT
,
229 CPU_FTRS_7450_21
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
231 CPU_FTR_MAYBE_CAN_NAP
| CPU_FTR_L2CR
| CPU_FTR_ALTIVEC_COMP
|
232 CPU_FTR_L3CR
| CPU_FTR_HPTE_TABLE
| CPU_FTR_SPEC7450
|
233 CPU_FTR_NAP_DISABLE_L2_PR
| CPU_FTR_L3_DISABLE_NAP
|
234 CPU_FTR_NEED_COHERENT
,
235 CPU_FTRS_7450_23
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
237 CPU_FTR_MAYBE_CAN_NAP
| CPU_FTR_L2CR
| CPU_FTR_ALTIVEC_COMP
|
238 CPU_FTR_L3CR
| CPU_FTR_HPTE_TABLE
| CPU_FTR_SPEC7450
|
239 CPU_FTR_NAP_DISABLE_L2_PR
| CPU_FTR_NEED_COHERENT
,
240 CPU_FTRS_7455_1
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
242 CPU_FTR_L2CR
| CPU_FTR_ALTIVEC_COMP
| CPU_FTR_L3CR
|
243 CPU_FTR_HPTE_TABLE
| CPU_FTR_SPEC7450
| CPU_FTR_HAS_HIGH_BATS
|
244 CPU_FTR_NEED_COHERENT
,
245 CPU_FTRS_7455_20
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
247 CPU_FTR_MAYBE_CAN_NAP
| CPU_FTR_L2CR
| CPU_FTR_ALTIVEC_COMP
|
248 CPU_FTR_L3CR
| CPU_FTR_HPTE_TABLE
| CPU_FTR_SPEC7450
|
249 CPU_FTR_NAP_DISABLE_L2_PR
| CPU_FTR_L3_DISABLE_NAP
|
250 CPU_FTR_NEED_COHERENT
| CPU_FTR_HAS_HIGH_BATS
,
251 CPU_FTRS_7455
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
253 CPU_FTR_MAYBE_CAN_NAP
| CPU_FTR_L2CR
| CPU_FTR_ALTIVEC_COMP
|
254 CPU_FTR_L3CR
| CPU_FTR_HPTE_TABLE
| CPU_FTR_SPEC7450
|
255 CPU_FTR_NAP_DISABLE_L2_PR
| CPU_FTR_HAS_HIGH_BATS
|
256 CPU_FTR_NEED_COHERENT
,
257 CPU_FTRS_7447_10
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
259 CPU_FTR_MAYBE_CAN_NAP
| CPU_FTR_L2CR
| CPU_FTR_ALTIVEC_COMP
|
260 CPU_FTR_L3CR
| CPU_FTR_HPTE_TABLE
| CPU_FTR_SPEC7450
|
261 CPU_FTR_NAP_DISABLE_L2_PR
| CPU_FTR_HAS_HIGH_BATS
|
262 CPU_FTR_NEED_COHERENT
| CPU_FTR_NO_BTIC
,
263 CPU_FTRS_7447
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
265 CPU_FTR_MAYBE_CAN_NAP
| CPU_FTR_L2CR
| CPU_FTR_ALTIVEC_COMP
|
266 CPU_FTR_L3CR
| CPU_FTR_HPTE_TABLE
| CPU_FTR_SPEC7450
|
267 CPU_FTR_NAP_DISABLE_L2_PR
| CPU_FTR_HAS_HIGH_BATS
|
268 CPU_FTR_NEED_COHERENT
,
269 CPU_FTRS_7447A
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
271 CPU_FTR_MAYBE_CAN_NAP
| CPU_FTR_L2CR
| CPU_FTR_ALTIVEC_COMP
|
272 CPU_FTR_HPTE_TABLE
| CPU_FTR_SPEC7450
|
273 CPU_FTR_NAP_DISABLE_L2_PR
| CPU_FTR_HAS_HIGH_BATS
|
274 CPU_FTR_NEED_COHERENT
,
275 CPU_FTRS_82XX
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
276 CPU_FTR_MAYBE_CAN_DOZE
| CPU_FTR_USE_TB
,
277 CPU_FTRS_G2_LE
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_MAYBE_CAN_DOZE
|
278 CPU_FTR_USE_TB
| CPU_FTR_MAYBE_CAN_NAP
| CPU_FTR_HAS_HIGH_BATS
,
279 CPU_FTRS_E300
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_MAYBE_CAN_DOZE
|
280 CPU_FTR_USE_TB
| CPU_FTR_MAYBE_CAN_NAP
| CPU_FTR_HAS_HIGH_BATS
,
281 CPU_FTRS_CLASSIC32
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
282 CPU_FTR_USE_TB
| CPU_FTR_HPTE_TABLE
,
283 CPU_FTRS_POWER3_32
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
284 CPU_FTR_USE_TB
| CPU_FTR_HPTE_TABLE
,
285 CPU_FTRS_POWER4_32
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
286 CPU_FTR_USE_TB
| CPU_FTR_HPTE_TABLE
| CPU_FTR_NODSISRALIGN
,
287 CPU_FTRS_970_32
= CPU_FTR_COMMON
| CPU_FTR_SPLIT_ID_CACHE
|
288 CPU_FTR_USE_TB
| CPU_FTR_HPTE_TABLE
| CPU_FTR_ALTIVEC_COMP
|
289 CPU_FTR_MAYBE_CAN_NAP
| CPU_FTR_NODSISRALIGN
,
290 CPU_FTRS_8XX
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
,
291 CPU_FTRS_40X
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
|
292 CPU_FTR_NODSISRALIGN
,
293 CPU_FTRS_44X
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
|
294 CPU_FTR_NODSISRALIGN
,
295 CPU_FTRS_E200
= CPU_FTR_USE_TB
| CPU_FTR_NODSISRALIGN
,
296 CPU_FTRS_E500
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
|
297 CPU_FTR_NODSISRALIGN
,
298 CPU_FTRS_E500_2
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
|
299 CPU_FTR_BIG_PHYS
| CPU_FTR_NODSISRALIGN
,
300 CPU_FTRS_GENERIC_32
= CPU_FTR_COMMON
| CPU_FTR_NODSISRALIGN
,
302 CPU_FTRS_POWER3
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
|
303 CPU_FTR_HPTE_TABLE
| CPU_FTR_IABR
,
304 CPU_FTRS_RS64
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
|
305 CPU_FTR_HPTE_TABLE
| CPU_FTR_IABR
|
306 CPU_FTR_MMCRA
| CPU_FTR_CTRL
,
307 CPU_FTRS_POWER4
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
|
308 CPU_FTR_HPTE_TABLE
| CPU_FTR_PPCAS_ARCH_V2
| CPU_FTR_MMCRA
,
309 CPU_FTRS_PPC970
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
|
310 CPU_FTR_HPTE_TABLE
| CPU_FTR_PPCAS_ARCH_V2
|
311 CPU_FTR_ALTIVEC_COMP
| CPU_FTR_CAN_NAP
| CPU_FTR_MMCRA
,
312 CPU_FTRS_POWER5
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
|
313 CPU_FTR_HPTE_TABLE
| CPU_FTR_PPCAS_ARCH_V2
|
314 CPU_FTR_MMCRA
| CPU_FTR_SMT
|
315 CPU_FTR_COHERENT_ICACHE
| CPU_FTR_LOCKLESS_TLBIE
|
317 CPU_FTRS_CELL
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
|
318 CPU_FTR_HPTE_TABLE
| CPU_FTR_PPCAS_ARCH_V2
|
319 CPU_FTR_ALTIVEC_COMP
| CPU_FTR_MMCRA
| CPU_FTR_SMT
|
320 CPU_FTR_CTRL
| CPU_FTR_PAUSE_ZERO
,
321 CPU_FTRS_COMPATIBLE
= CPU_FTR_SPLIT_ID_CACHE
| CPU_FTR_USE_TB
|
322 CPU_FTR_HPTE_TABLE
| CPU_FTR_PPCAS_ARCH_V2
,
327 CPU_FTRS_POWER3
| CPU_FTRS_RS64
| CPU_FTRS_POWER4
|
328 CPU_FTRS_PPC970
| CPU_FTRS_POWER5
| CPU_FTRS_CELL
|
329 CPU_FTR_CI_LARGE_PAGE
|
332 CPU_FTRS_PPC601
| CPU_FTRS_603
| CPU_FTRS_604
| CPU_FTRS_740_NOTAU
|
333 CPU_FTRS_740
| CPU_FTRS_750
| CPU_FTRS_750FX1
|
334 CPU_FTRS_750FX2
| CPU_FTRS_750FX
| CPU_FTRS_750GX
|
335 CPU_FTRS_7400_NOTAU
| CPU_FTRS_7400
| CPU_FTRS_7450_20
|
336 CPU_FTRS_7450_21
| CPU_FTRS_7450_23
| CPU_FTRS_7455_1
|
337 CPU_FTRS_7455_20
| CPU_FTRS_7455
| CPU_FTRS_7447_10
|
338 CPU_FTRS_7447
| CPU_FTRS_7447A
| CPU_FTRS_82XX
|
339 CPU_FTRS_G2_LE
| CPU_FTRS_E300
| CPU_FTRS_CLASSIC32
|
341 CPU_FTRS_GENERIC_32
|
343 #ifdef CONFIG_PPC64BRIDGE
347 CPU_FTRS_POWER4_32
| CPU_FTRS_970_32
|
362 CPU_FTRS_E500
| CPU_FTRS_E500_2
|
364 #endif /* __powerpc64__ */
369 CPU_FTRS_POWER3
& CPU_FTRS_RS64
& CPU_FTRS_POWER4
&
370 CPU_FTRS_PPC970
& CPU_FTRS_POWER5
& CPU_FTRS_CELL
&
373 CPU_FTRS_PPC601
& CPU_FTRS_603
& CPU_FTRS_604
& CPU_FTRS_740_NOTAU
&
374 CPU_FTRS_740
& CPU_FTRS_750
& CPU_FTRS_750FX1
&
375 CPU_FTRS_750FX2
& CPU_FTRS_750FX
& CPU_FTRS_750GX
&
376 CPU_FTRS_7400_NOTAU
& CPU_FTRS_7400
& CPU_FTRS_7450_20
&
377 CPU_FTRS_7450_21
& CPU_FTRS_7450_23
& CPU_FTRS_7455_1
&
378 CPU_FTRS_7455_20
& CPU_FTRS_7455
& CPU_FTRS_7447_10
&
379 CPU_FTRS_7447
& CPU_FTRS_7447A
& CPU_FTRS_82XX
&
380 CPU_FTRS_G2_LE
& CPU_FTRS_E300
& CPU_FTRS_CLASSIC32
&
382 CPU_FTRS_GENERIC_32
&
384 #ifdef CONFIG_PPC64BRIDGE
388 CPU_FTRS_POWER4_32
& CPU_FTRS_970_32
&
403 CPU_FTRS_E500
& CPU_FTRS_E500_2
&
405 #endif /* __powerpc64__ */
409 static inline int cpu_has_feature(unsigned long feature
)
411 return (CPU_FTRS_ALWAYS
& feature
) ||
413 & cur_cpu_spec
->cpu_features
417 #endif /* !__ASSEMBLY__ */
421 #define BEGIN_FTR_SECTION 98:
423 #ifndef __powerpc64__
424 #define END_FTR_SECTION(msk, val) \
426 .section __ftr_fixup,"a"; \
433 #else /* __powerpc64__ */
434 #define END_FTR_SECTION(msk, val) \
436 .section __ftr_fixup,"a"; \
443 #endif /* __powerpc64__ */
445 #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
446 #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
447 #endif /* __ASSEMBLY__ */
449 #endif /* __KERNEL__ */
450 #endif /* __ASM_POWERPC_CPUTABLE_H */