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sata_promise: separate SATA and PATA ops
[linux-2.6/kmemtrace.git] / drivers / ata / sata_promise.c
blobacc9913dd6dca61244d8d111b90aa493bb443927
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
46
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "2.03"
49
50
51 enum {
52 PDC_MMIO_BAR = 3,
53
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
65 PDC_FLASH_CTL = 0x44, /* Flash control register */
66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
72
73 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
74 (1<<8) | (1<<9) | (1<<10),
75
76 board_2037x = 0, /* FastTrak S150 TX2plus */
77 board_20319 = 1, /* FastTrak S150 TX4 */
78 board_20619 = 2, /* FastTrak TX4000 */
79 board_2057x = 3, /* SATAII150 Tx2plus */
80 board_40518 = 4, /* SATAII150 Tx4 */
81
82 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
83
84 /* Sequence counter control registers bit definitions */
85 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
86
87 /* Feature register values */
88 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
89 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
90
91 /* Device/Head register values */
92 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
93
94 /* PDC_CTLSTAT bit definitions */
95 PDC_DMA_ENABLE = (1 << 7),
96 PDC_IRQ_DISABLE = (1 << 10),
97 PDC_RESET = (1 << 11), /* HDMA reset */
98
99 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
100 ATA_FLAG_MMIO |
101 ATA_FLAG_PIO_POLLING,
102
103 /* hp->flags bits */
104 PDC_FLAG_GEN_II = (1 << 0),
105 };
106
107
108 struct pdc_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 };
112
113 struct pdc_host_priv {
114 unsigned long flags;
115 unsigned long port_flags[ATA_MAX_PORTS];
116 };
117
118 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
119 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
121 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
122 static int pdc_port_start(struct ata_port *ap);
123 static void pdc_qc_prep(struct ata_queued_cmd *qc);
124 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
125 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
126 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
127 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
128 static void pdc_irq_clear(struct ata_port *ap);
129 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
130 static void pdc_freeze(struct ata_port *ap);
131 static void pdc_thaw(struct ata_port *ap);
132 static void pdc_pata_error_handler(struct ata_port *ap);
133 static void pdc_sata_error_handler(struct ata_port *ap);
134 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
135 static int pdc_pata_cable_detect(struct ata_port *ap);
136 static int pdc_sata_cable_detect(struct ata_port *ap);
137
138 static struct scsi_host_template pdc_ata_sht = {
139 .module = THIS_MODULE,
140 .name = DRV_NAME,
141 .ioctl = ata_scsi_ioctl,
142 .queuecommand = ata_scsi_queuecmd,
143 .can_queue = ATA_DEF_QUEUE,
144 .this_id = ATA_SHT_THIS_ID,
145 .sg_tablesize = LIBATA_MAX_PRD,
146 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
147 .emulated = ATA_SHT_EMULATED,
148 .use_clustering = ATA_SHT_USE_CLUSTERING,
149 .proc_name = DRV_NAME,
150 .dma_boundary = ATA_DMA_BOUNDARY,
151 .slave_configure = ata_scsi_slave_config,
152 .slave_destroy = ata_scsi_slave_destroy,
153 .bios_param = ata_std_bios_param,
154 };
155
156 static const struct ata_port_operations pdc_sata_ops = {
157 .port_disable = ata_port_disable,
158 .tf_load = pdc_tf_load_mmio,
159 .tf_read = ata_tf_read,
160 .check_status = ata_check_status,
161 .exec_command = pdc_exec_command_mmio,
162 .dev_select = ata_std_dev_select,
163 .check_atapi_dma = pdc_check_atapi_dma,
164
165 .qc_prep = pdc_qc_prep,
166 .qc_issue = pdc_qc_issue_prot,
167 .freeze = pdc_freeze,
168 .thaw = pdc_thaw,
169 .error_handler = pdc_sata_error_handler,
170 .post_internal_cmd = pdc_post_internal_cmd,
171 .cable_detect = pdc_sata_cable_detect,
172 .data_xfer = ata_data_xfer,
173 .irq_handler = pdc_interrupt,
174 .irq_clear = pdc_irq_clear,
175 .irq_on = ata_irq_on,
176 .irq_ack = ata_irq_ack,
177
178 .scr_read = pdc_sata_scr_read,
179 .scr_write = pdc_sata_scr_write,
180 .port_start = pdc_port_start,
181 };
182
183 /* First-generation chips need a more restrictive ->check_atapi_dma op */
184 static const struct ata_port_operations pdc_old_sata_ops = {
185 .port_disable = ata_port_disable,
186 .tf_load = pdc_tf_load_mmio,
187 .tf_read = ata_tf_read,
188 .check_status = ata_check_status,
189 .exec_command = pdc_exec_command_mmio,
190 .dev_select = ata_std_dev_select,
191 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
192
193 .qc_prep = pdc_qc_prep,
194 .qc_issue = pdc_qc_issue_prot,
195 .freeze = pdc_freeze,
196 .thaw = pdc_thaw,
197 .error_handler = pdc_sata_error_handler,
198 .post_internal_cmd = pdc_post_internal_cmd,
199 .cable_detect = pdc_sata_cable_detect,
200 .data_xfer = ata_data_xfer,
201 .irq_handler = pdc_interrupt,
202 .irq_clear = pdc_irq_clear,
203 .irq_on = ata_irq_on,
204 .irq_ack = ata_irq_ack,
205
206 .scr_read = pdc_sata_scr_read,
207 .scr_write = pdc_sata_scr_write,
208 .port_start = pdc_port_start,
209 };
210
211 static const struct ata_port_operations pdc_pata_ops = {
212 .port_disable = ata_port_disable,
213 .tf_load = pdc_tf_load_mmio,
214 .tf_read = ata_tf_read,
215 .check_status = ata_check_status,
216 .exec_command = pdc_exec_command_mmio,
217 .dev_select = ata_std_dev_select,
218 .check_atapi_dma = pdc_check_atapi_dma,
219
220 .qc_prep = pdc_qc_prep,
221 .qc_issue = pdc_qc_issue_prot,
222 .freeze = pdc_freeze,
223 .thaw = pdc_thaw,
224 .error_handler = pdc_pata_error_handler,
225 .post_internal_cmd = pdc_post_internal_cmd,
226 .cable_detect = pdc_pata_cable_detect,
227 .data_xfer = ata_data_xfer,
228 .irq_handler = pdc_interrupt,
229 .irq_clear = pdc_irq_clear,
230 .irq_on = ata_irq_on,
231 .irq_ack = ata_irq_ack,
232
233 .port_start = pdc_port_start,
234 };
235
236 static const struct ata_port_info pdc_port_info[] = {
237 /* board_2037x */
238 {
239 .sht = &pdc_ata_sht,
240 .flags = PDC_COMMON_FLAGS,
241 .pio_mask = 0x1f, /* pio0-4 */
242 .mwdma_mask = 0x07, /* mwdma0-2 */
243 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
244 .port_ops = &pdc_old_sata_ops,
245 },
246
247 /* board_20319 */
248 {
249 .sht = &pdc_ata_sht,
250 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
251 .pio_mask = 0x1f, /* pio0-4 */
252 .mwdma_mask = 0x07, /* mwdma0-2 */
253 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
254 .port_ops = &pdc_old_sata_ops,
255 },
256
257 /* board_20619 */
258 {
259 .sht = &pdc_ata_sht,
260 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
261 .pio_mask = 0x1f, /* pio0-4 */
262 .mwdma_mask = 0x07, /* mwdma0-2 */
263 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
264 .port_ops = &pdc_pata_ops,
265 },
266
267 /* board_2057x */
268 {
269 .sht = &pdc_ata_sht,
270 .flags = PDC_COMMON_FLAGS,
271 .pio_mask = 0x1f, /* pio0-4 */
272 .mwdma_mask = 0x07, /* mwdma0-2 */
273 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
274 .port_ops = &pdc_sata_ops,
275 },
276
277 /* board_40518 */
278 {
279 .sht = &pdc_ata_sht,
280 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
281 .pio_mask = 0x1f, /* pio0-4 */
282 .mwdma_mask = 0x07, /* mwdma0-2 */
283 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
284 .port_ops = &pdc_sata_ops,
285 },
286 };
287
288 static const struct pci_device_id pdc_ata_pci_tbl[] = {
289 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
290 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
291 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
292 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
293 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
294 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
295 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
296 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
297 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
298 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
299
300 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
301 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
302 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
303 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
304 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
305 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
306
307 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
308
309 { } /* terminate list */
310 };
311
312
313 static struct pci_driver pdc_ata_pci_driver = {
314 .name = DRV_NAME,
315 .id_table = pdc_ata_pci_tbl,
316 .probe = pdc_ata_init_one,
317 .remove = ata_pci_remove_one,
318 };
319
320
321 static int pdc_common_port_start(struct ata_port *ap)
322 {
323 struct device *dev = ap->host->dev;
324 struct pdc_port_priv *pp;
325 int rc;
326
327 rc = ata_port_start(ap);
328 if (rc)
329 return rc;
330
331 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
332 if (!pp)
333 return -ENOMEM;
334
335 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
336 if (!pp->pkt)
337 return -ENOMEM;
338
339 ap->private_data = pp;
340
341 return 0;
342 }
343
344 static int pdc_sata_port_start(struct ata_port *ap)
345 {
346 struct pdc_host_priv *hp = ap->host->private_data;
347 int rc;
348
349 rc = pdc_common_port_start(ap);
350 if (rc)
351 return rc;
352
353 /* fix up PHYMODE4 align timing */
354 if (hp->flags & PDC_FLAG_GEN_II) {
355 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
356 unsigned int tmp;
357
358 tmp = readl(mmio + 0x014);
359 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
360 writel(tmp, mmio + 0x014);
361 }
362
363 return 0;
364 }
365
366 static int pdc_port_start(struct ata_port *ap)
367 {
368 struct pdc_host_priv *hp = ap->host->private_data;
369
370 /* fix up port flags and cable type for SATA+PATA chips */
371 ap->flags |= hp->port_flags[ap->port_no];
372 if (ap->flags & ATA_FLAG_SATA) {
373 ap->cbl = ATA_CBL_SATA;
374 return pdc_sata_port_start(ap);
375 } else {
376 ap->ops = &pdc_pata_ops;
377 return pdc_common_port_start(ap);
378 }
379 }
380
381 static void pdc_reset_port(struct ata_port *ap)
382 {
383 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
384 unsigned int i;
385 u32 tmp;
386
387 for (i = 11; i > 0; i--) {
388 tmp = readl(mmio);
389 if (tmp & PDC_RESET)
390 break;
391
392 udelay(100);
393
394 tmp |= PDC_RESET;
395 writel(tmp, mmio);
396 }
397
398 tmp &= ~PDC_RESET;
399 writel(tmp, mmio);
400 readl(mmio); /* flush */
401 }
402
403 static int pdc_pata_cable_detect(struct ata_port *ap)
404 {
405 u8 tmp;
406 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
407
408 tmp = readb(mmio);
409 if (tmp & 0x01)
410 return ATA_CBL_PATA40;
411 return ATA_CBL_PATA80;
412 }
413
414 static int pdc_sata_cable_detect(struct ata_port *ap)
415 {
416 return ATA_CBL_SATA;
417 }
418
419 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
420 {
421 if (sc_reg > SCR_CONTROL)
422 return 0xffffffffU;
423 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
424 }
425
426
427 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
428 u32 val)
429 {
430 if (sc_reg > SCR_CONTROL)
431 return;
432 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
433 }
434
435 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
436 {
437 struct ata_port *ap = qc->ap;
438 dma_addr_t sg_table = ap->prd_dma;
439 unsigned int cdb_len = qc->dev->cdb_len;
440 u8 *cdb = qc->cdb;
441 struct pdc_port_priv *pp = ap->private_data;
442 u8 *buf = pp->pkt;
443 u32 *buf32 = (u32 *) buf;
444 unsigned int dev_sel, feature, nbytes;
445
446 /* set control bits (byte 0), zero delay seq id (byte 3),
447 * and seq id (byte 2)
448 */
449 switch (qc->tf.protocol) {
450 case ATA_PROT_ATAPI_DMA:
451 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
452 buf32[0] = cpu_to_le32(PDC_PKT_READ);
453 else
454 buf32[0] = 0;
455 break;
456 case ATA_PROT_ATAPI_NODATA:
457 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
458 break;
459 default:
460 BUG();
461 break;
462 }
463 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
464 buf32[2] = 0; /* no next-packet */
465
466 /* select drive */
467 if (sata_scr_valid(ap)) {
468 dev_sel = PDC_DEVICE_SATA;
469 } else {
470 dev_sel = ATA_DEVICE_OBS;
471 if (qc->dev->devno != 0)
472 dev_sel |= ATA_DEV1;
473 }
474 buf[12] = (1 << 5) | ATA_REG_DEVICE;
475 buf[13] = dev_sel;
476 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
477 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
478
479 buf[16] = (1 << 5) | ATA_REG_NSECT;
480 buf[17] = 0x00;
481 buf[18] = (1 << 5) | ATA_REG_LBAL;
482 buf[19] = 0x00;
483
484 /* set feature and byte counter registers */
485 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
486 feature = PDC_FEATURE_ATAPI_PIO;
487 /* set byte counter register to real transfer byte count */
488 nbytes = qc->nbytes;
489 if (nbytes > 0xffff)
490 nbytes = 0xffff;
491 } else {
492 feature = PDC_FEATURE_ATAPI_DMA;
493 /* set byte counter register to 0 */
494 nbytes = 0;
495 }
496 buf[20] = (1 << 5) | ATA_REG_FEATURE;
497 buf[21] = feature;
498 buf[22] = (1 << 5) | ATA_REG_BYTEL;
499 buf[23] = nbytes & 0xFF;
500 buf[24] = (1 << 5) | ATA_REG_BYTEH;
501 buf[25] = (nbytes >> 8) & 0xFF;
502
503 /* send ATAPI packet command 0xA0 */
504 buf[26] = (1 << 5) | ATA_REG_CMD;
505 buf[27] = ATA_CMD_PACKET;
506
507 /* select drive and check DRQ */
508 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
509 buf[29] = dev_sel;
510
511 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
512 BUG_ON(cdb_len & ~0x1E);
513
514 /* append the CDB as the final part */
515 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
516 memcpy(buf+31, cdb, cdb_len);
517 }
518
519 static void pdc_qc_prep(struct ata_queued_cmd *qc)
520 {
521 struct pdc_port_priv *pp = qc->ap->private_data;
522 unsigned int i;
523
524 VPRINTK("ENTER\n");
525
526 switch (qc->tf.protocol) {
527 case ATA_PROT_DMA:
528 ata_qc_prep(qc);
529 /* fall through */
530
531 case ATA_PROT_NODATA:
532 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
533 qc->dev->devno, pp->pkt);
534
535 if (qc->tf.flags & ATA_TFLAG_LBA48)
536 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
537 else
538 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
539
540 pdc_pkt_footer(&qc->tf, pp->pkt, i);
541 break;
542
543 case ATA_PROT_ATAPI:
544 ata_qc_prep(qc);
545 break;
546
547 case ATA_PROT_ATAPI_DMA:
548 ata_qc_prep(qc);
549 /*FALLTHROUGH*/
550 case ATA_PROT_ATAPI_NODATA:
551 pdc_atapi_pkt(qc);
552 break;
553
554 default:
555 break;
556 }
557 }
558
559 static void pdc_freeze(struct ata_port *ap)
560 {
561 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
562 u32 tmp;
563
564 tmp = readl(mmio + PDC_CTLSTAT);
565 tmp |= PDC_IRQ_DISABLE;
566 tmp &= ~PDC_DMA_ENABLE;
567 writel(tmp, mmio + PDC_CTLSTAT);
568 readl(mmio + PDC_CTLSTAT); /* flush */
569 }
570
571 static void pdc_thaw(struct ata_port *ap)
572 {
573 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
574 u32 tmp;
575
576 /* clear IRQ */
577 readl(mmio + PDC_INT_SEQMASK);
578
579 /* turn IRQ back on */
580 tmp = readl(mmio + PDC_CTLSTAT);
581 tmp &= ~PDC_IRQ_DISABLE;
582 writel(tmp, mmio + PDC_CTLSTAT);
583 readl(mmio + PDC_CTLSTAT); /* flush */
584 }
585
586 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
587 {
588 if (!(ap->pflags & ATA_PFLAG_FROZEN))
589 pdc_reset_port(ap);
590
591 /* perform recovery */
592 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
593 ata_std_postreset);
594 }
595
596 static void pdc_pata_error_handler(struct ata_port *ap)
597 {
598 pdc_common_error_handler(ap, NULL);
599 }
600
601 static void pdc_sata_error_handler(struct ata_port *ap)
602 {
603 pdc_common_error_handler(ap, sata_std_hardreset);
604 }
605
606 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
607 {
608 struct ata_port *ap = qc->ap;
609
610 if (qc->flags & ATA_QCFLAG_FAILED)
611 qc->err_mask |= AC_ERR_OTHER;
612
613 /* make DMA engine forget about the failed command */
614 if (qc->err_mask)
615 pdc_reset_port(ap);
616 }
617
618 static inline unsigned int pdc_host_intr( struct ata_port *ap,
619 struct ata_queued_cmd *qc)
620 {
621 unsigned int handled = 0;
622 u32 tmp;
623 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
624
625 tmp = readl(mmio);
626 if (tmp & PDC_ERR_MASK) {
627 qc->err_mask |= AC_ERR_DEV;
628 pdc_reset_port(ap);
629 }
630
631 switch (qc->tf.protocol) {
632 case ATA_PROT_DMA:
633 case ATA_PROT_NODATA:
634 case ATA_PROT_ATAPI_DMA:
635 case ATA_PROT_ATAPI_NODATA:
636 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
637 ata_qc_complete(qc);
638 handled = 1;
639 break;
640
641 default:
642 ap->stats.idle_irq++;
643 break;
644 }
645
646 return handled;
647 }
648
649 static void pdc_irq_clear(struct ata_port *ap)
650 {
651 struct ata_host *host = ap->host;
652 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
653
654 readl(mmio + PDC_INT_SEQMASK);
655 }
656
657 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
658 {
659 struct ata_host *host = dev_instance;
660 struct ata_port *ap;
661 u32 mask = 0;
662 unsigned int i, tmp;
663 unsigned int handled = 0;
664 void __iomem *mmio_base;
665
666 VPRINTK("ENTER\n");
667
668 if (!host || !host->iomap[PDC_MMIO_BAR]) {
669 VPRINTK("QUICK EXIT\n");
670 return IRQ_NONE;
671 }
672
673 mmio_base = host->iomap[PDC_MMIO_BAR];
674
675 /* reading should also clear interrupts */
676 mask = readl(mmio_base + PDC_INT_SEQMASK);
677
678 if (mask == 0xffffffff) {
679 VPRINTK("QUICK EXIT 2\n");
680 return IRQ_NONE;
681 }
682
683 spin_lock(&host->lock);
684
685 mask &= 0xffff; /* only 16 tags possible */
686 if (!mask) {
687 VPRINTK("QUICK EXIT 3\n");
688 goto done_irq;
689 }
690
691 writel(mask, mmio_base + PDC_INT_SEQMASK);
692
693 for (i = 0; i < host->n_ports; i++) {
694 VPRINTK("port %u\n", i);
695 ap = host->ports[i];
696 tmp = mask & (1 << (i + 1));
697 if (tmp && ap &&
698 !(ap->flags & ATA_FLAG_DISABLED)) {
699 struct ata_queued_cmd *qc;
700
701 qc = ata_qc_from_tag(ap, ap->active_tag);
702 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
703 handled += pdc_host_intr(ap, qc);
704 }
705 }
706
707 VPRINTK("EXIT\n");
708
709 done_irq:
710 spin_unlock(&host->lock);
711 return IRQ_RETVAL(handled);
712 }
713
714 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
715 {
716 struct ata_port *ap = qc->ap;
717 struct pdc_port_priv *pp = ap->private_data;
718 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
719 unsigned int port_no = ap->port_no;
720 u8 seq = (u8) (port_no + 1);
721
722 VPRINTK("ENTER, ap %p\n", ap);
723
724 writel(0x00000001, mmio + (seq * 4));
725 readl(mmio + (seq * 4)); /* flush */
726
727 pp->pkt[2] = seq;
728 wmb(); /* flush PRD, pkt writes */
729 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
730 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
731 }
732
733 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
734 {
735 switch (qc->tf.protocol) {
736 case ATA_PROT_ATAPI_NODATA:
737 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
738 break;
739 /*FALLTHROUGH*/
740 case ATA_PROT_ATAPI_DMA:
741 case ATA_PROT_DMA:
742 case ATA_PROT_NODATA:
743 pdc_packet_start(qc);
744 return 0;
745
746 default:
747 break;
748 }
749
750 return ata_qc_issue_prot(qc);
751 }
752
753 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
754 {
755 WARN_ON (tf->protocol == ATA_PROT_DMA ||
756 tf->protocol == ATA_PROT_NODATA);
757 ata_tf_load(ap, tf);
758 }
759
760
761 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
762 {
763 WARN_ON (tf->protocol == ATA_PROT_DMA ||
764 tf->protocol == ATA_PROT_NODATA);
765 ata_exec_command(ap, tf);
766 }
767
768 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
769 {
770 u8 *scsicmd = qc->scsicmd->cmnd;
771 int pio = 1; /* atapi dma off by default */
772
773 /* Whitelist commands that may use DMA. */
774 switch (scsicmd[0]) {
775 case WRITE_12:
776 case WRITE_10:
777 case WRITE_6:
778 case READ_12:
779 case READ_10:
780 case READ_6:
781 case 0xad: /* READ_DVD_STRUCTURE */
782 case 0xbe: /* READ_CD */
783 pio = 0;
784 }
785 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
786 if (scsicmd[0] == WRITE_10) {
787 unsigned int lba;
788 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
789 if (lba >= 0xFFFF4FA2)
790 pio = 1;
791 }
792 return pio;
793 }
794
795 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
796 {
797 /* First generation chips cannot use ATAPI DMA on SATA ports */
798 return 1;
799 }
800
801 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base,
802 void __iomem *scr_addr)
803 {
804 port->cmd_addr = base;
805 port->data_addr = base;
806 port->feature_addr =
807 port->error_addr = base + 0x4;
808 port->nsect_addr = base + 0x8;
809 port->lbal_addr = base + 0xc;
810 port->lbam_addr = base + 0x10;
811 port->lbah_addr = base + 0x14;
812 port->device_addr = base + 0x18;
813 port->command_addr =
814 port->status_addr = base + 0x1c;
815 port->altstatus_addr =
816 port->ctl_addr = base + 0x38;
817 port->scr_addr = scr_addr;
818 }
819
820
821 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
822 {
823 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
824 struct pdc_host_priv *hp = pe->private_data;
825 int hotplug_offset;
826 u32 tmp;
827
828 if (hp->flags & PDC_FLAG_GEN_II)
829 hotplug_offset = PDC2_SATA_PLUG_CSR;
830 else
831 hotplug_offset = PDC_SATA_PLUG_CSR;
832
833 /*
834 * Except for the hotplug stuff, this is voodoo from the
835 * Promise driver. Label this entire section
836 * "TODO: figure out why we do this"
837 */
838
839 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
840 tmp = readl(mmio + PDC_FLASH_CTL);
841 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
842 if (!(hp->flags & PDC_FLAG_GEN_II))
843 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
844 writel(tmp, mmio + PDC_FLASH_CTL);
845
846 /* clear plug/unplug flags for all ports */
847 tmp = readl(mmio + hotplug_offset);
848 writel(tmp | 0xff, mmio + hotplug_offset);
849
850 /* mask plug/unplug ints */
851 tmp = readl(mmio + hotplug_offset);
852 writel(tmp | 0xff0000, mmio + hotplug_offset);
853
854 /* don't initialise TBG or SLEW on 2nd generation chips */
855 if (hp->flags & PDC_FLAG_GEN_II)
856 return;
857
858 /* reduce TBG clock to 133 Mhz. */
859 tmp = readl(mmio + PDC_TBG_MODE);
860 tmp &= ~0x30000; /* clear bit 17, 16*/
861 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
862 writel(tmp, mmio + PDC_TBG_MODE);
863
864 readl(mmio + PDC_TBG_MODE); /* flush */
865 msleep(10);
866
867 /* adjust slew rate control register. */
868 tmp = readl(mmio + PDC_SLEW_CTL);
869 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
870 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
871 writel(tmp, mmio + PDC_SLEW_CTL);
872 }
873
874 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
875 {
876 static int printed_version;
877 struct ata_probe_ent *probe_ent;
878 struct pdc_host_priv *hp;
879 void __iomem *base;
880 unsigned int board_idx = (unsigned int) ent->driver_data;
881 int rc;
882 u8 tmp;
883
884 if (!printed_version++)
885 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
886
887 rc = pcim_enable_device(pdev);
888 if (rc)
889 return rc;
890
891 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
892 if (rc == -EBUSY)
893 pcim_pin_device(pdev);
894 if (rc)
895 return rc;
896
897 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
898 if (rc)
899 return rc;
900 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
901 if (rc)
902 return rc;
903
904 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
905 if (probe_ent == NULL)
906 return -ENOMEM;
907
908 probe_ent->dev = pci_dev_to_dev(pdev);
909 INIT_LIST_HEAD(&probe_ent->node);
910
911 hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL);
912 if (hp == NULL)
913 return -ENOMEM;
914
915 probe_ent->private_data = hp;
916
917 probe_ent->sht = pdc_port_info[board_idx].sht;
918 probe_ent->port_flags = pdc_port_info[board_idx].flags;
919 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
920 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
921 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
922 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
923
924 probe_ent->irq = pdev->irq;
925 probe_ent->irq_flags = IRQF_SHARED;
926 probe_ent->iomap = pcim_iomap_table(pdev);
927
928 base = probe_ent->iomap[PDC_MMIO_BAR];
929
930 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200, base + 0x400);
931 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280, base + 0x500);
932
933 /* notice 4-port boards */
934 switch (board_idx) {
935 case board_40518:
936 hp->flags |= PDC_FLAG_GEN_II;
937 /* Fall through */
938 case board_20319:
939 probe_ent->n_ports = 4;
940 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, base + 0x600);
941 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, base + 0x700);
942 break;
943 case board_2057x:
944 hp->flags |= PDC_FLAG_GEN_II;
945 /* Fall through */
946 case board_2037x:
947 /* TX2plus boards also have a PATA port */
948 tmp = readb(base + PDC_FLASH_CTL+1);
949 if (!(tmp & 0x80)) {
950 probe_ent->n_ports = 3;
951 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
952 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
953 printk(KERN_INFO DRV_NAME " PATA port found\n");
954 } else
955 probe_ent->n_ports = 2;
956 hp->port_flags[0] = ATA_FLAG_SATA;
957 hp->port_flags[1] = ATA_FLAG_SATA;
958 break;
959 case board_20619:
960 probe_ent->n_ports = 4;
961 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
962 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, NULL);
963 break;
964 default:
965 BUG();
966 break;
967 }
968
969 pci_set_master(pdev);
970
971 /* initialize adapter */
972 pdc_host_init(board_idx, probe_ent);
973
974 if (!ata_device_add(probe_ent))
975 return -ENODEV;
976
977 devm_kfree(&pdev->dev, probe_ent);
978 return 0;
979 }
980
981
982 static int __init pdc_ata_init(void)
983 {
984 return pci_register_driver(&pdc_ata_pci_driver);
985 }
986
987
988 static void __exit pdc_ata_exit(void)
989 {
990 pci_unregister_driver(&pdc_ata_pci_driver);
991 }
992
993
994 MODULE_AUTHOR("Jeff Garzik");
995 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
996 MODULE_LICENSE("GPL");
997 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
998 MODULE_VERSION(DRV_VERSION);
999
1000 module_init(pdc_ata_init);
1001 module_exit(pdc_ata_exit);
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