2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.18"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg
=
86 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
87 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
90 static int debug
= -1; /* defaults above */
91 module_param(debug
, int, 0);
92 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly
= 128;
95 module_param(copybreak
, int, 0);
96 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
98 static int disable_msi
= 0;
99 module_param(disable_msi
, int, 0);
100 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
102 static const struct pci_device_id sky2_id_table
[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4354) }, /* 88E8040 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
139 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
141 /* Avoid conditionals by using array */
142 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
143 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
144 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
146 /* This driver supports yukon2 chipset only */
147 static const char *yukon2_name
[] = {
149 "EC Ultra", /* 0xb4 */
150 "Extreme", /* 0xb5 */
156 static void sky2_set_multicast(struct net_device
*dev
);
158 /* Access to external PHY */
159 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
163 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
164 gma_write16(hw
, port
, GM_SMI_CTRL
,
165 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
167 for (i
= 0; i
< PHY_RETRIES
; i
++) {
168 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
173 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
177 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
181 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
182 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
184 for (i
= 0; i
< PHY_RETRIES
; i
++) {
185 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
186 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
196 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
200 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
201 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
206 static void sky2_power_on(struct sky2_hw
*hw
)
208 /* switch power to VCC (WA for VAUX problem) */
209 sky2_write8(hw
, B0_POWER_CTRL
,
210 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
212 /* disable Core Clock Division, */
213 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
215 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
216 /* enable bits are inverted */
217 sky2_write8(hw
, B2_Y2_CLK_GATE
,
218 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
219 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
220 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
222 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
224 if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
) {
227 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
229 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
230 /* set all bits to 0 except bits 15..12 and 8 */
231 reg
&= P_ASPM_CONTROL_MSK
;
232 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
234 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
235 /* set all bits to 0 except bits 28 & 27 */
236 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
237 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
239 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
241 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
242 reg
= sky2_read32(hw
, B2_GP_IO
);
243 reg
|= GLB_GPIO_STAT_RACE_DIS
;
244 sky2_write32(hw
, B2_GP_IO
, reg
);
246 sky2_read32(hw
, B2_GP_IO
);
250 static void sky2_power_aux(struct sky2_hw
*hw
)
252 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
253 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
255 /* enable bits are inverted */
256 sky2_write8(hw
, B2_Y2_CLK_GATE
,
257 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
258 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
259 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
261 /* switch power to VAUX */
262 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
263 sky2_write8(hw
, B0_POWER_CTRL
,
264 (PC_VAUX_ENA
| PC_VCC_ENA
|
265 PC_VAUX_ON
| PC_VCC_OFF
));
268 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
277 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
278 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
279 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
280 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
282 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
283 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
284 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
287 /* flow control to advertise bits */
288 static const u16 copper_fc_adv
[] = {
290 [FC_TX
] = PHY_M_AN_ASP
,
291 [FC_RX
] = PHY_M_AN_PC
,
292 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
295 /* flow control to advertise bits when using 1000BaseX */
296 static const u16 fiber_fc_adv
[] = {
297 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
298 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
299 [FC_RX
] = PHY_M_P_SYM_MD_X
,
300 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
303 /* flow control to GMA disable bits */
304 static const u16 gm_fc_disable
[] = {
305 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
306 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
307 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
312 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
314 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
315 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
317 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
318 !(hw
->flags
& SKY2_HW_NEWER_PHY
)) {
319 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
321 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
323 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
325 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
326 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
327 /* set downshift counter to 3x and enable downshift */
328 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
330 /* set master & slave downshift counter to 1x */
331 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
333 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
336 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
337 if (sky2_is_copper(hw
)) {
338 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
339 /* enable automatic crossover */
340 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
342 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
343 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
346 /* Enable Class A driver for FE+ A0 */
347 spec
= gm_phy_read(hw
, port
, PHY_MARV_FE_SPEC_2
);
348 spec
|= PHY_M_FESC_SEL_CL_A
;
349 gm_phy_write(hw
, port
, PHY_MARV_FE_SPEC_2
, spec
);
352 /* disable energy detect */
353 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
355 /* enable automatic crossover */
356 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
358 /* downshift on PHY 88E1112 and 88E1149 is changed */
359 if (sky2
->autoneg
== AUTONEG_ENABLE
360 && (hw
->flags
& SKY2_HW_NEWER_PHY
)) {
361 /* set downshift counter to 3x and enable downshift */
362 ctrl
&= ~PHY_M_PC_DSC_MSK
;
363 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
367 /* workaround for deviation #4.88 (CRC errors) */
368 /* disable Automatic Crossover */
370 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
373 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
375 /* special setup for PHY 88E1112 Fiber */
376 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& (hw
->flags
& SKY2_HW_FIBRE_PHY
)) {
377 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
379 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
380 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
381 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
382 ctrl
&= ~PHY_M_MAC_MD_MSK
;
383 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
384 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
386 if (hw
->pmd_type
== 'P') {
387 /* select page 1 to access Fiber registers */
388 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
390 /* for SFP-module set SIGDET polarity to low */
391 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
392 ctrl
|= PHY_M_FIB_SIGD_POL
;
393 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
396 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
404 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
405 if (sky2_is_copper(hw
)) {
406 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
407 ct1000
|= PHY_M_1000C_AFD
;
408 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
409 ct1000
|= PHY_M_1000C_AHD
;
410 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
411 adv
|= PHY_M_AN_100_FD
;
412 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
413 adv
|= PHY_M_AN_100_HD
;
414 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
415 adv
|= PHY_M_AN_10_FD
;
416 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
417 adv
|= PHY_M_AN_10_HD
;
419 adv
|= copper_fc_adv
[sky2
->flow_mode
];
420 } else { /* special defines for FIBER (88E1040S only) */
421 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
422 adv
|= PHY_M_AN_1000X_AFD
;
423 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
424 adv
|= PHY_M_AN_1000X_AHD
;
426 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
429 /* Restart Auto-negotiation */
430 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
432 /* forced speed/duplex settings */
433 ct1000
= PHY_M_1000C_MSE
;
435 /* Disable auto update for duplex flow control and speed */
436 reg
|= GM_GPCR_AU_ALL_DIS
;
438 switch (sky2
->speed
) {
440 ctrl
|= PHY_CT_SP1000
;
441 reg
|= GM_GPCR_SPEED_1000
;
444 ctrl
|= PHY_CT_SP100
;
445 reg
|= GM_GPCR_SPEED_100
;
449 if (sky2
->duplex
== DUPLEX_FULL
) {
450 reg
|= GM_GPCR_DUP_FULL
;
451 ctrl
|= PHY_CT_DUP_MD
;
452 } else if (sky2
->speed
< SPEED_1000
)
453 sky2
->flow_mode
= FC_NONE
;
456 reg
|= gm_fc_disable
[sky2
->flow_mode
];
458 /* Forward pause packets to GMAC? */
459 if (sky2
->flow_mode
& FC_RX
)
460 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
462 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
465 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
467 if (hw
->flags
& SKY2_HW_GIGABIT
)
468 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
470 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
471 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
473 /* Setup Phy LED's */
474 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
477 switch (hw
->chip_id
) {
478 case CHIP_ID_YUKON_FE
:
479 /* on 88E3082 these bits are at 11..9 (shifted left) */
480 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
482 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
484 /* delete ACT LED control bits */
485 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
486 /* change ACT LED control to blink mode */
487 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
488 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
491 case CHIP_ID_YUKON_FE_P
:
492 /* Enable Link Partner Next Page */
493 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
494 ctrl
|= PHY_M_PC_ENA_LIP_NP
;
496 /* disable Energy Detect and enable scrambler */
497 ctrl
&= ~(PHY_M_PC_ENA_ENE_DT
| PHY_M_PC_DIS_SCRAMB
);
498 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
500 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
501 ctrl
= PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL
) |
502 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK
) |
503 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED
);
505 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
508 case CHIP_ID_YUKON_XL
:
509 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
511 /* select page 3 to access LED control register */
512 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
514 /* set LED Function Control register */
515 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
516 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
517 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
518 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
519 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
521 /* set Polarity Control register */
522 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
523 (PHY_M_POLC_LS1_P_MIX(4) |
524 PHY_M_POLC_IS0_P_MIX(4) |
525 PHY_M_POLC_LOS_CTRL(2) |
526 PHY_M_POLC_INIT_CTRL(2) |
527 PHY_M_POLC_STA1_CTRL(2) |
528 PHY_M_POLC_STA0_CTRL(2)));
530 /* restore page register */
531 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
534 case CHIP_ID_YUKON_EC_U
:
535 case CHIP_ID_YUKON_EX
:
536 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
538 /* select page 3 to access LED control register */
539 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
541 /* set LED Function Control register */
542 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
543 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
544 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
545 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
546 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
548 /* set Blink Rate in LED Timer Control Register */
549 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
550 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
551 /* restore page register */
552 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
556 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
557 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
558 /* turn off the Rx LED (LED_RX) */
559 ledover
&= ~PHY_M_LED_MO_RX
;
562 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
563 hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
) {
564 /* apply fixes in PHY AFE */
565 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
567 /* increase differential signal amplitude in 10BASE-T */
568 gm_phy_write(hw
, port
, 0x18, 0xaa99);
569 gm_phy_write(hw
, port
, 0x17, 0x2011);
571 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
572 gm_phy_write(hw
, port
, 0x18, 0xa204);
573 gm_phy_write(hw
, port
, 0x17, 0x2002);
575 /* set page register to 0 */
576 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
577 } else if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
578 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
579 /* apply workaround for integrated resistors calibration */
580 gm_phy_write(hw
, port
, PHY_MARV_PAGE_ADDR
, 17);
581 gm_phy_write(hw
, port
, PHY_MARV_PAGE_DATA
, 0x3f60);
582 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
583 /* no effect on Yukon-XL */
584 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
586 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
587 /* turn on 100 Mbps LED (LED_LINK100) */
588 ledover
|= PHY_M_LED_MO_100
;
592 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
596 /* Enable phy interrupt on auto-negotiation complete (or link up) */
597 if (sky2
->autoneg
== AUTONEG_ENABLE
)
598 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
600 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
603 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
606 static const u32 phy_power
[]
607 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
609 /* looks like this XL is back asswards .. */
610 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
613 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
614 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
616 /* Turn off phy power saving */
617 reg1
&= ~phy_power
[port
];
619 reg1
|= phy_power
[port
];
621 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
622 sky2_pci_read32(hw
, PCI_DEV_REG1
);
623 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
627 /* Force a renegotiation */
628 static void sky2_phy_reinit(struct sky2_port
*sky2
)
630 spin_lock_bh(&sky2
->phy_lock
);
631 sky2_phy_init(sky2
->hw
, sky2
->port
);
632 spin_unlock_bh(&sky2
->phy_lock
);
635 /* Put device in state to listen for Wake On Lan */
636 static void sky2_wol_init(struct sky2_port
*sky2
)
638 struct sky2_hw
*hw
= sky2
->hw
;
639 unsigned port
= sky2
->port
;
640 enum flow_control save_mode
;
644 /* Bring hardware out of reset */
645 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
646 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
648 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
649 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
652 * sky2_reset will re-enable on resume
654 save_mode
= sky2
->flow_mode
;
655 ctrl
= sky2
->advertising
;
657 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
658 sky2
->flow_mode
= FC_NONE
;
659 sky2_phy_power(hw
, port
, 1);
660 sky2_phy_reinit(sky2
);
662 sky2
->flow_mode
= save_mode
;
663 sky2
->advertising
= ctrl
;
665 /* Set GMAC to no flow control and auto update for speed/duplex */
666 gma_write16(hw
, port
, GM_GP_CTRL
,
667 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
668 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
670 /* Set WOL address */
671 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
672 sky2
->netdev
->dev_addr
, ETH_ALEN
);
674 /* Turn on appropriate WOL control bits */
675 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
677 if (sky2
->wol
& WAKE_PHY
)
678 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
680 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
682 if (sky2
->wol
& WAKE_MAGIC
)
683 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
685 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
687 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
688 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
690 /* Turn on legacy PCI-Express PME mode */
691 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
692 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
693 reg1
|= PCI_Y2_PME_LEGACY
;
694 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
695 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
698 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
702 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
704 struct net_device
*dev
= hw
->dev
[port
];
706 if (dev
->mtu
<= ETH_DATA_LEN
)
707 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
708 TX_JUMBO_DIS
| TX_STFW_ENA
);
710 else if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
711 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
712 TX_STFW_ENA
| TX_JUMBO_ENA
);
714 /* set Tx GMAC FIFO Almost Empty Threshold */
715 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
716 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
718 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
719 TX_JUMBO_ENA
| TX_STFW_DIS
);
721 /* Can't do offload because of lack of store/forward */
722 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_SG
| NETIF_F_ALL_CSUM
);
726 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
728 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
732 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
734 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
735 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
737 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
739 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
740 /* WA DEV_472 -- looks like crossed wires on port 2 */
741 /* clear GMAC 1 Control reset */
742 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
744 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
745 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
746 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
747 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
748 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
751 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
753 /* Enable Transmit FIFO Underrun */
754 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
756 spin_lock_bh(&sky2
->phy_lock
);
757 sky2_phy_init(hw
, port
);
758 spin_unlock_bh(&sky2
->phy_lock
);
761 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
762 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
764 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
765 gma_read16(hw
, port
, i
);
766 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
768 /* transmit control */
769 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
771 /* receive control reg: unicast + multicast + no FCS */
772 gma_write16(hw
, port
, GM_RX_CTRL
,
773 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
775 /* transmit flow control */
776 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
778 /* transmit parameter */
779 gma_write16(hw
, port
, GM_TX_PARAM
,
780 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
781 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
782 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
783 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
785 /* serial mode register */
786 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
787 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
789 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
790 reg
|= GM_SMOD_JUMBO_ENA
;
792 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
794 /* virtual address for data */
795 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
797 /* physical address: used for pause frames */
798 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
800 /* ignore counter overflows */
801 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
802 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
803 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
805 /* Configure Rx MAC FIFO */
806 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
807 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
808 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
809 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
810 rx_reg
|= GMF_RX_OVER_ON
;
812 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
814 /* Flush Rx MAC FIFO on any flow control or error */
815 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
817 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
818 reg
= RX_GMF_FL_THR_DEF
+ 1;
819 /* Another magic mystery workaround from sk98lin */
820 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
821 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
823 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), reg
);
825 /* Configure Tx MAC FIFO */
826 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
827 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
829 /* On chips without ram buffer, pause is controled by MAC level */
830 if (sky2_read8(hw
, B2_E_0
) == 0) {
831 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
832 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
834 sky2_set_tx_stfwd(hw
, port
);
839 /* Assign Ram Buffer allocation to queue */
840 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
844 /* convert from K bytes to qwords used for hw register */
847 end
= start
+ space
- 1;
849 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
850 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
851 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
852 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
853 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
855 if (q
== Q_R1
|| q
== Q_R2
) {
856 u32 tp
= space
- space
/4;
858 /* On receive queue's set the thresholds
859 * give receiver priority when > 3/4 full
860 * send pause when down to 2K
862 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
863 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
866 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
867 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
869 /* Enable store & forward on Tx queue's because
870 * Tx FIFO is only 1K on Yukon
872 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
875 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
876 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
879 /* Setup Bus Memory Interface */
880 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
882 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
883 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
884 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
885 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
888 /* Setup prefetch unit registers. This is the interface between
889 * hardware and driver list elements
891 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
894 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
895 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
896 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
897 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
898 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
899 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
901 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
904 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
906 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
908 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
913 static void tx_init(struct sky2_port
*sky2
)
915 struct sky2_tx_le
*le
;
917 sky2
->tx_prod
= sky2
->tx_cons
= 0;
919 sky2
->tx_last_mss
= 0;
921 le
= get_tx_le(sky2
);
923 le
->opcode
= OP_ADDR64
| HW_OWNER
;
927 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
928 struct sky2_tx_le
*le
)
930 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
933 /* Update chip's next pointer */
934 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
936 /* Make sure write' to descriptors are complete before we tell hardware */
938 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
940 /* Synchronize I/O on since next processor may write to tail */
945 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
947 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
948 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
953 /* Build description to hardware for one receive segment */
954 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
955 dma_addr_t map
, unsigned len
)
957 struct sky2_rx_le
*le
;
958 u32 hi
= upper_32_bits(map
);
960 if (sky2
->rx_addr64
!= hi
) {
961 le
= sky2_next_rx(sky2
);
962 le
->addr
= cpu_to_le32(hi
);
963 le
->opcode
= OP_ADDR64
| HW_OWNER
;
964 sky2
->rx_addr64
= upper_32_bits(map
+ len
);
967 le
= sky2_next_rx(sky2
);
968 le
->addr
= cpu_to_le32((u32
) map
);
969 le
->length
= cpu_to_le16(len
);
970 le
->opcode
= op
| HW_OWNER
;
973 /* Build description to hardware for one possibly fragmented skb */
974 static void sky2_rx_submit(struct sky2_port
*sky2
,
975 const struct rx_ring_info
*re
)
979 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
981 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
982 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
986 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
989 struct sk_buff
*skb
= re
->skb
;
992 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
993 pci_unmap_len_set(re
, data_size
, size
);
995 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
996 re
->frag_addr
[i
] = pci_map_page(pdev
,
997 skb_shinfo(skb
)->frags
[i
].page
,
998 skb_shinfo(skb
)->frags
[i
].page_offset
,
999 skb_shinfo(skb
)->frags
[i
].size
,
1000 PCI_DMA_FROMDEVICE
);
1003 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
1005 struct sk_buff
*skb
= re
->skb
;
1008 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
1009 PCI_DMA_FROMDEVICE
);
1011 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1012 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1013 skb_shinfo(skb
)->frags
[i
].size
,
1014 PCI_DMA_FROMDEVICE
);
1017 /* Tell chip where to start receive checksum.
1018 * Actually has two checksums, but set both same to avoid possible byte
1021 static void rx_set_checksum(struct sky2_port
*sky2
)
1023 struct sky2_rx_le
*le
= sky2_next_rx(sky2
);
1025 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
1027 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
1029 sky2_write32(sky2
->hw
,
1030 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1031 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
1035 * The RX Stop command will not work for Yukon-2 if the BMU does not
1036 * reach the end of packet and since we can't make sure that we have
1037 * incoming data, we must reset the BMU while it is not doing a DMA
1038 * transfer. Since it is possible that the RX path is still active,
1039 * the RX RAM buffer will be stopped first, so any possible incoming
1040 * data will not trigger a DMA. After the RAM buffer is stopped, the
1041 * BMU is polled until any DMA in progress is ended and only then it
1044 static void sky2_rx_stop(struct sky2_port
*sky2
)
1046 struct sky2_hw
*hw
= sky2
->hw
;
1047 unsigned rxq
= rxqaddr
[sky2
->port
];
1050 /* disable the RAM Buffer receive queue */
1051 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1053 for (i
= 0; i
< 0xffff; i
++)
1054 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1055 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1058 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
1059 sky2
->netdev
->name
);
1061 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1063 /* reset the Rx prefetch unit */
1064 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1068 /* Clean out receive buffer area, assumes receiver hardware stopped */
1069 static void sky2_rx_clean(struct sky2_port
*sky2
)
1073 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1074 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1075 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1078 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1085 /* Basic MII support */
1086 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1088 struct mii_ioctl_data
*data
= if_mii(ifr
);
1089 struct sky2_port
*sky2
= netdev_priv(dev
);
1090 struct sky2_hw
*hw
= sky2
->hw
;
1091 int err
= -EOPNOTSUPP
;
1093 if (!netif_running(dev
))
1094 return -ENODEV
; /* Phy still in reset */
1098 data
->phy_id
= PHY_ADDR_MARV
;
1104 spin_lock_bh(&sky2
->phy_lock
);
1105 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1106 spin_unlock_bh(&sky2
->phy_lock
);
1108 data
->val_out
= val
;
1113 if (!capable(CAP_NET_ADMIN
))
1116 spin_lock_bh(&sky2
->phy_lock
);
1117 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1119 spin_unlock_bh(&sky2
->phy_lock
);
1125 #ifdef SKY2_VLAN_TAG_USED
1126 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1128 struct sky2_port
*sky2
= netdev_priv(dev
);
1129 struct sky2_hw
*hw
= sky2
->hw
;
1130 u16 port
= sky2
->port
;
1132 netif_tx_lock_bh(dev
);
1133 netif_poll_disable(sky2
->hw
->dev
[0]);
1137 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1139 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1142 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1144 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1148 netif_poll_enable(sky2
->hw
->dev
[0]);
1149 netif_tx_unlock_bh(dev
);
1154 * Allocate an skb for receiving. If the MTU is large enough
1155 * make the skb non-linear with a fragment list of pages.
1157 * It appears the hardware has a bug in the FIFO logic that
1158 * cause it to hang if the FIFO gets overrun and the receive buffer
1159 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1160 * aligned except if slab debugging is enabled.
1162 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1164 struct sk_buff
*skb
;
1168 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ RX_SKB_ALIGN
);
1172 p
= (unsigned long) skb
->data
;
1173 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
1175 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1176 struct page
*page
= alloc_page(GFP_ATOMIC
);
1180 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1190 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1192 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1196 * Allocate and setup receiver buffer pool.
1197 * Normal case this ends up creating one list element for skb
1198 * in the receive ring. Worst case if using large MTU and each
1199 * allocation falls on a different 64 bit region, that results
1200 * in 6 list elements per ring entry.
1201 * One element is used for checksum enable/disable, and one
1202 * extra to avoid wrap.
1204 static int sky2_rx_start(struct sky2_port
*sky2
)
1206 struct sky2_hw
*hw
= sky2
->hw
;
1207 struct rx_ring_info
*re
;
1208 unsigned rxq
= rxqaddr
[sky2
->port
];
1209 unsigned i
, size
, space
, thresh
;
1211 sky2
->rx_put
= sky2
->rx_next
= 0;
1214 /* On PCI express lowering the watermark gives better performance */
1215 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1216 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1218 /* These chips have no ram buffer?
1219 * MAC Rx RAM Read is controlled by hardware */
1220 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1221 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1222 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1223 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1225 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1227 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1228 rx_set_checksum(sky2
);
1230 /* Space needed for frame data + headers rounded up */
1231 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1233 /* Stopping point for hardware truncation */
1234 thresh
= (size
- 8) / sizeof(u32
);
1236 /* Account for overhead of skb - to avoid order > 0 allocation */
1237 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1238 + sizeof(struct skb_shared_info
);
1240 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1241 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1243 if (sky2
->rx_nfrags
!= 0) {
1244 /* Compute residue after pages */
1245 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1252 /* Optimize to handle small packets and headers */
1253 if (size
< copybreak
)
1255 if (size
< ETH_HLEN
)
1258 sky2
->rx_data_size
= size
;
1261 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1262 re
= sky2
->rx_ring
+ i
;
1264 re
->skb
= sky2_rx_alloc(sky2
);
1268 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1269 sky2_rx_submit(sky2
, re
);
1273 * The receiver hangs if it receives frames larger than the
1274 * packet buffer. As a workaround, truncate oversize frames, but
1275 * the register is limited to 9 bits, so if you do frames > 2052
1276 * you better get the MTU right!
1279 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1281 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1282 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1285 /* Tell chip about available buffers */
1286 sky2_rx_update(sky2
, rxq
);
1289 sky2_rx_clean(sky2
);
1293 /* Bring up network interface. */
1294 static int sky2_up(struct net_device
*dev
)
1296 struct sky2_port
*sky2
= netdev_priv(dev
);
1297 struct sky2_hw
*hw
= sky2
->hw
;
1298 unsigned port
= sky2
->port
;
1300 int cap
, err
= -ENOMEM
;
1301 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1304 * On dual port PCI-X card, there is an problem where status
1305 * can be received out of order due to split transactions
1307 if (otherdev
&& netif_running(otherdev
) &&
1308 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1309 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1312 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1313 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1314 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1320 if (netif_msg_ifup(sky2
))
1321 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1323 netif_carrier_off(dev
);
1325 /* must be power of 2 */
1326 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1328 sizeof(struct sky2_tx_le
),
1333 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1340 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1344 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1346 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1351 sky2_phy_power(hw
, port
, 1);
1353 sky2_mac_init(hw
, port
);
1355 /* Register is number of 4K blocks on internal RAM buffer. */
1356 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1360 pr_debug(PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1362 rxspace
= ramsize
/ 2;
1364 rxspace
= 8 + (2*(ramsize
- 16))/3;
1366 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1367 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1369 /* Make sure SyncQ is disabled */
1370 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1374 sky2_qset(hw
, txqaddr
[port
]);
1376 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1377 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1378 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1380 /* Set almost empty threshold */
1381 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1382 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1383 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1385 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1388 err
= sky2_rx_start(sky2
);
1392 /* Enable interrupts from phy/mac for port */
1393 imask
= sky2_read32(hw
, B0_IMSK
);
1394 imask
|= portirq_msk
[port
];
1395 sky2_write32(hw
, B0_IMSK
, imask
);
1401 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1402 sky2
->rx_le
, sky2
->rx_le_map
);
1406 pci_free_consistent(hw
->pdev
,
1407 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1408 sky2
->tx_le
, sky2
->tx_le_map
);
1411 kfree(sky2
->tx_ring
);
1412 kfree(sky2
->rx_ring
);
1414 sky2
->tx_ring
= NULL
;
1415 sky2
->rx_ring
= NULL
;
1419 /* Modular subtraction in ring */
1420 static inline int tx_dist(unsigned tail
, unsigned head
)
1422 return (head
- tail
) & (TX_RING_SIZE
- 1);
1425 /* Number of list elements available for next tx */
1426 static inline int tx_avail(const struct sky2_port
*sky2
)
1428 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1431 /* Estimate of number of transmit list elements required */
1432 static unsigned tx_le_req(const struct sk_buff
*skb
)
1436 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1437 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1439 if (skb_is_gso(skb
))
1442 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1449 * Put one packet in ring for transmit.
1450 * A single packet can generate multiple list elements, and
1451 * the number of ring elements will probably be less than the number
1452 * of list elements used.
1454 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1456 struct sky2_port
*sky2
= netdev_priv(dev
);
1457 struct sky2_hw
*hw
= sky2
->hw
;
1458 struct sky2_tx_le
*le
= NULL
;
1459 struct tx_ring_info
*re
;
1466 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1467 return NETDEV_TX_BUSY
;
1469 if (unlikely(netif_msg_tx_queued(sky2
)))
1470 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1471 dev
->name
, sky2
->tx_prod
, skb
->len
);
1473 len
= skb_headlen(skb
);
1474 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1475 addr64
= upper_32_bits(mapping
);
1477 /* Send high bits if changed or crosses boundary */
1478 if (addr64
!= sky2
->tx_addr64
||
1479 upper_32_bits(mapping
+ len
) != sky2
->tx_addr64
) {
1480 le
= get_tx_le(sky2
);
1481 le
->addr
= cpu_to_le32(addr64
);
1482 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1483 sky2
->tx_addr64
= upper_32_bits(mapping
+ len
);
1486 /* Check for TCP Segmentation Offload */
1487 mss
= skb_shinfo(skb
)->gso_size
;
1490 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1491 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1493 if (mss
!= sky2
->tx_last_mss
) {
1494 le
= get_tx_le(sky2
);
1495 le
->addr
= cpu_to_le32(mss
);
1497 if (hw
->flags
& SKY2_HW_NEW_LE
)
1498 le
->opcode
= OP_MSS
| HW_OWNER
;
1500 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1501 sky2
->tx_last_mss
= mss
;
1506 #ifdef SKY2_VLAN_TAG_USED
1507 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1508 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1510 le
= get_tx_le(sky2
);
1512 le
->opcode
= OP_VLAN
|HW_OWNER
;
1514 le
->opcode
|= OP_VLAN
;
1515 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1520 /* Handle TCP checksum offload */
1521 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1522 /* On Yukon EX (some versions) encoding change. */
1523 if (hw
->flags
& SKY2_HW_AUTO_TX_SUM
)
1524 ctrl
|= CALSUM
; /* auto checksum */
1526 const unsigned offset
= skb_transport_offset(skb
);
1529 tcpsum
= offset
<< 16; /* sum start */
1530 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1532 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1533 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1536 if (tcpsum
!= sky2
->tx_tcpsum
) {
1537 sky2
->tx_tcpsum
= tcpsum
;
1539 le
= get_tx_le(sky2
);
1540 le
->addr
= cpu_to_le32(tcpsum
);
1541 le
->length
= 0; /* initial checksum value */
1542 le
->ctrl
= 1; /* one packet */
1543 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1548 le
= get_tx_le(sky2
);
1549 le
->addr
= cpu_to_le32((u32
) mapping
);
1550 le
->length
= cpu_to_le16(len
);
1552 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1554 re
= tx_le_re(sky2
, le
);
1556 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1557 pci_unmap_len_set(re
, maplen
, len
);
1559 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1560 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1562 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1563 frag
->size
, PCI_DMA_TODEVICE
);
1564 addr64
= upper_32_bits(mapping
);
1565 if (addr64
!= sky2
->tx_addr64
) {
1566 le
= get_tx_le(sky2
);
1567 le
->addr
= cpu_to_le32(addr64
);
1569 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1570 sky2
->tx_addr64
= addr64
;
1573 le
= get_tx_le(sky2
);
1574 le
->addr
= cpu_to_le32((u32
) mapping
);
1575 le
->length
= cpu_to_le16(frag
->size
);
1577 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1579 re
= tx_le_re(sky2
, le
);
1581 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1582 pci_unmap_len_set(re
, maplen
, frag
->size
);
1587 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1588 netif_stop_queue(dev
);
1590 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1592 dev
->trans_start
= jiffies
;
1593 return NETDEV_TX_OK
;
1597 * Free ring elements from starting at tx_cons until "done"
1599 * NB: the hardware will tell us about partial completion of multi-part
1600 * buffers so make sure not to free skb to early.
1602 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1604 struct net_device
*dev
= sky2
->netdev
;
1605 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1608 BUG_ON(done
>= TX_RING_SIZE
);
1610 for (idx
= sky2
->tx_cons
; idx
!= done
;
1611 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1612 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1613 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1615 switch(le
->opcode
& ~HW_OWNER
) {
1618 pci_unmap_single(pdev
,
1619 pci_unmap_addr(re
, mapaddr
),
1620 pci_unmap_len(re
, maplen
),
1624 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1625 pci_unmap_len(re
, maplen
),
1630 if (le
->ctrl
& EOP
) {
1631 if (unlikely(netif_msg_tx_done(sky2
)))
1632 printk(KERN_DEBUG
"%s: tx done %u\n",
1635 sky2
->net_stats
.tx_packets
++;
1636 sky2
->net_stats
.tx_bytes
+= re
->skb
->len
;
1638 dev_kfree_skb_any(re
->skb
);
1639 sky2
->tx_next
= RING_NEXT(idx
, TX_RING_SIZE
);
1643 sky2
->tx_cons
= idx
;
1646 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1647 netif_wake_queue(dev
);
1650 /* Cleanup all untransmitted buffers, assume transmitter not running */
1651 static void sky2_tx_clean(struct net_device
*dev
)
1653 struct sky2_port
*sky2
= netdev_priv(dev
);
1655 netif_tx_lock_bh(dev
);
1656 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1657 netif_tx_unlock_bh(dev
);
1660 /* Network shutdown */
1661 static int sky2_down(struct net_device
*dev
)
1663 struct sky2_port
*sky2
= netdev_priv(dev
);
1664 struct sky2_hw
*hw
= sky2
->hw
;
1665 unsigned port
= sky2
->port
;
1669 /* Never really got started! */
1673 if (netif_msg_ifdown(sky2
))
1674 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1676 /* Stop more packets from being queued */
1677 netif_stop_queue(dev
);
1679 /* Disable port IRQ */
1680 imask
= sky2_read32(hw
, B0_IMSK
);
1681 imask
&= ~portirq_msk
[port
];
1682 sky2_write32(hw
, B0_IMSK
, imask
);
1684 sky2_gmac_reset(hw
, port
);
1686 /* Stop transmitter */
1687 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1688 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1690 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1691 RB_RST_SET
| RB_DIS_OP_MD
);
1693 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1694 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1695 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1697 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1699 /* Workaround shared GMAC reset */
1700 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1701 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1702 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1704 /* Disable Force Sync bit and Enable Alloc bit */
1705 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1706 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1708 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1709 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1710 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1712 /* Reset the PCI FIFO of the async Tx queue */
1713 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1714 BMU_RST_SET
| BMU_FIFO_RST
);
1716 /* Reset the Tx prefetch units */
1717 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1720 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1724 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1725 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1727 sky2_phy_power(hw
, port
, 0);
1729 netif_carrier_off(dev
);
1731 /* turn off LED's */
1732 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1734 synchronize_irq(hw
->pdev
->irq
);
1737 sky2_rx_clean(sky2
);
1739 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1740 sky2
->rx_le
, sky2
->rx_le_map
);
1741 kfree(sky2
->rx_ring
);
1743 pci_free_consistent(hw
->pdev
,
1744 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1745 sky2
->tx_le
, sky2
->tx_le_map
);
1746 kfree(sky2
->tx_ring
);
1751 sky2
->rx_ring
= NULL
;
1752 sky2
->tx_ring
= NULL
;
1757 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1759 if (hw
->flags
& SKY2_HW_FIBRE_PHY
)
1762 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
1763 if (aux
& PHY_M_PS_SPEED_100
)
1769 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1770 case PHY_M_PS_SPEED_1000
:
1772 case PHY_M_PS_SPEED_100
:
1779 static void sky2_link_up(struct sky2_port
*sky2
)
1781 struct sky2_hw
*hw
= sky2
->hw
;
1782 unsigned port
= sky2
->port
;
1784 static const char *fc_name
[] = {
1792 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1793 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1794 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1796 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1798 netif_carrier_on(sky2
->netdev
);
1800 mod_timer(&hw
->watchdog_timer
, jiffies
+ 1);
1802 /* Turn on link LED */
1803 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1804 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1806 if (hw
->flags
& SKY2_HW_NEWER_PHY
) {
1807 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1808 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1810 switch(sky2
->speed
) {
1812 led
|= PHY_M_LEDC_INIT_CTRL(7);
1816 led
|= PHY_M_LEDC_STA1_CTRL(7);
1820 led
|= PHY_M_LEDC_STA0_CTRL(7);
1824 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1825 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1826 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1829 if (netif_msg_link(sky2
))
1830 printk(KERN_INFO PFX
1831 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1832 sky2
->netdev
->name
, sky2
->speed
,
1833 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1834 fc_name
[sky2
->flow_status
]);
1837 static void sky2_link_down(struct sky2_port
*sky2
)
1839 struct sky2_hw
*hw
= sky2
->hw
;
1840 unsigned port
= sky2
->port
;
1843 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1845 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1846 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1847 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1849 netif_carrier_off(sky2
->netdev
);
1851 /* Turn on link LED */
1852 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1854 if (netif_msg_link(sky2
))
1855 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1857 sky2_phy_init(hw
, port
);
1860 static enum flow_control
sky2_flow(int rx
, int tx
)
1863 return tx
? FC_BOTH
: FC_RX
;
1865 return tx
? FC_TX
: FC_NONE
;
1868 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1870 struct sky2_hw
*hw
= sky2
->hw
;
1871 unsigned port
= sky2
->port
;
1874 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1875 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1876 if (lpa
& PHY_M_AN_RF
) {
1877 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1881 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1882 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1883 sky2
->netdev
->name
);
1887 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1888 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1890 /* Since the pause result bits seem to in different positions on
1891 * different chips. look at registers.
1893 if (hw
->flags
& SKY2_HW_FIBRE_PHY
) {
1894 /* Shift for bits in fiber PHY */
1895 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
1896 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
1898 if (advert
& ADVERTISE_1000XPAUSE
)
1899 advert
|= ADVERTISE_PAUSE_CAP
;
1900 if (advert
& ADVERTISE_1000XPSE_ASYM
)
1901 advert
|= ADVERTISE_PAUSE_ASYM
;
1902 if (lpa
& LPA_1000XPAUSE
)
1903 lpa
|= LPA_PAUSE_CAP
;
1904 if (lpa
& LPA_1000XPAUSE_ASYM
)
1905 lpa
|= LPA_PAUSE_ASYM
;
1908 sky2
->flow_status
= FC_NONE
;
1909 if (advert
& ADVERTISE_PAUSE_CAP
) {
1910 if (lpa
& LPA_PAUSE_CAP
)
1911 sky2
->flow_status
= FC_BOTH
;
1912 else if (advert
& ADVERTISE_PAUSE_ASYM
)
1913 sky2
->flow_status
= FC_RX
;
1914 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
1915 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
1916 sky2
->flow_status
= FC_TX
;
1919 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1920 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
1921 sky2
->flow_status
= FC_NONE
;
1923 if (sky2
->flow_status
& FC_TX
)
1924 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1926 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1931 /* Interrupt from PHY */
1932 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1934 struct net_device
*dev
= hw
->dev
[port
];
1935 struct sky2_port
*sky2
= netdev_priv(dev
);
1936 u16 istatus
, phystat
;
1938 if (!netif_running(dev
))
1941 spin_lock(&sky2
->phy_lock
);
1942 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1943 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1945 if (netif_msg_intr(sky2
))
1946 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1947 sky2
->netdev
->name
, istatus
, phystat
);
1949 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1950 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1955 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1956 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1958 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1960 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1962 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1963 if (phystat
& PHY_M_PS_LINK_UP
)
1966 sky2_link_down(sky2
);
1969 spin_unlock(&sky2
->phy_lock
);
1972 /* Transmit timeout is only called if we are running, carrier is up
1973 * and tx queue is full (stopped).
1975 static void sky2_tx_timeout(struct net_device
*dev
)
1977 struct sky2_port
*sky2
= netdev_priv(dev
);
1978 struct sky2_hw
*hw
= sky2
->hw
;
1980 if (netif_msg_timer(sky2
))
1981 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1983 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1984 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
1985 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
1986 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
1988 /* can't restart safely under softirq */
1989 schedule_work(&hw
->restart_work
);
1992 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1994 struct sky2_port
*sky2
= netdev_priv(dev
);
1995 struct sky2_hw
*hw
= sky2
->hw
;
1996 unsigned port
= sky2
->port
;
2001 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2004 if (new_mtu
> ETH_DATA_LEN
&&
2005 (hw
->chip_id
== CHIP_ID_YUKON_FE
||
2006 hw
->chip_id
== CHIP_ID_YUKON_FE_P
))
2009 if (!netif_running(dev
)) {
2014 imask
= sky2_read32(hw
, B0_IMSK
);
2015 sky2_write32(hw
, B0_IMSK
, 0);
2017 dev
->trans_start
= jiffies
; /* prevent tx timeout */
2018 netif_stop_queue(dev
);
2019 netif_poll_disable(hw
->dev
[0]);
2021 synchronize_irq(hw
->pdev
->irq
);
2023 if (sky2_read8(hw
, B2_E_0
) == 0)
2024 sky2_set_tx_stfwd(hw
, port
);
2026 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2027 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
2029 sky2_rx_clean(sky2
);
2033 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
2034 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2036 if (dev
->mtu
> ETH_DATA_LEN
)
2037 mode
|= GM_SMOD_JUMBO_ENA
;
2039 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
2041 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
2043 err
= sky2_rx_start(sky2
);
2044 sky2_write32(hw
, B0_IMSK
, imask
);
2049 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2051 netif_poll_enable(hw
->dev
[0]);
2052 netif_wake_queue(dev
);
2058 /* For small just reuse existing skb for next receive */
2059 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2060 const struct rx_ring_info
*re
,
2063 struct sk_buff
*skb
;
2065 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
2067 skb_reserve(skb
, 2);
2068 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2069 length
, PCI_DMA_FROMDEVICE
);
2070 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2071 skb
->ip_summed
= re
->skb
->ip_summed
;
2072 skb
->csum
= re
->skb
->csum
;
2073 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2074 length
, PCI_DMA_FROMDEVICE
);
2075 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2076 skb_put(skb
, length
);
2081 /* Adjust length of skb with fragments to match received data */
2082 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2083 unsigned int length
)
2088 /* put header into skb */
2089 size
= min(length
, hdr_space
);
2094 num_frags
= skb_shinfo(skb
)->nr_frags
;
2095 for (i
= 0; i
< num_frags
; i
++) {
2096 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2099 /* don't need this page */
2100 __free_page(frag
->page
);
2101 --skb_shinfo(skb
)->nr_frags
;
2103 size
= min(length
, (unsigned) PAGE_SIZE
);
2106 skb
->data_len
+= size
;
2107 skb
->truesize
+= size
;
2114 /* Normal packet - take skb from ring element and put in a new one */
2115 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2116 struct rx_ring_info
*re
,
2117 unsigned int length
)
2119 struct sk_buff
*skb
, *nskb
;
2120 unsigned hdr_space
= sky2
->rx_data_size
;
2122 /* Don't be tricky about reusing pages (yet) */
2123 nskb
= sky2_rx_alloc(sky2
);
2124 if (unlikely(!nskb
))
2128 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2130 prefetch(skb
->data
);
2132 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
2134 if (skb_shinfo(skb
)->nr_frags
)
2135 skb_put_frags(skb
, hdr_space
, length
);
2137 skb_put(skb
, length
);
2142 * Receive one packet.
2143 * For larger packets, get new buffer.
2145 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2146 u16 length
, u32 status
)
2148 struct sky2_port
*sky2
= netdev_priv(dev
);
2149 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2150 struct sk_buff
*skb
= NULL
;
2151 u16 count
= (status
& GMR_FS_LEN
) >> 16;
2153 #ifdef SKY2_VLAN_TAG_USED
2154 /* Account for vlan tag */
2155 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
))
2159 if (unlikely(netif_msg_rx_status(sky2
)))
2160 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2161 dev
->name
, sky2
->rx_next
, status
, length
);
2163 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2164 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2166 /* This chip has hardware problems that generates bogus status.
2167 * So do only marginal checking and expect higher level protocols
2168 * to handle crap frames.
2170 if (sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
2171 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
&&
2175 if (status
& GMR_FS_ANY_ERR
)
2178 if (!(status
& GMR_FS_RX_OK
))
2181 /* if length reported by DMA does not match PHY, packet was truncated */
2182 if (length
!= count
)
2186 if (length
< copybreak
)
2187 skb
= receive_copy(sky2
, re
, length
);
2189 skb
= receive_new(sky2
, re
, length
);
2191 sky2_rx_submit(sky2
, re
);
2196 /* Truncation of overlength packets
2197 causes PHY length to not match MAC length */
2198 ++sky2
->net_stats
.rx_length_errors
;
2199 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2200 pr_info(PFX
"%s: rx length error: status %#x length %d\n",
2201 dev
->name
, status
, length
);
2205 ++sky2
->net_stats
.rx_errors
;
2206 if (status
& GMR_FS_RX_FF_OV
) {
2207 sky2
->net_stats
.rx_over_errors
++;
2211 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2212 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2213 dev
->name
, status
, length
);
2215 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2216 sky2
->net_stats
.rx_length_errors
++;
2217 if (status
& GMR_FS_FRAGMENT
)
2218 sky2
->net_stats
.rx_frame_errors
++;
2219 if (status
& GMR_FS_CRC_ERR
)
2220 sky2
->net_stats
.rx_crc_errors
++;
2225 /* Transmit complete */
2226 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2228 struct sky2_port
*sky2
= netdev_priv(dev
);
2230 if (netif_running(dev
)) {
2232 sky2_tx_complete(sky2
, last
);
2233 netif_tx_unlock(dev
);
2237 /* Process status response ring */
2238 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
2241 unsigned rx
[2] = { 0, 0 };
2242 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
2246 while (hw
->st_idx
!= hwidx
) {
2247 struct sky2_port
*sky2
;
2248 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2249 unsigned port
= le
->css
& CSS_LINK_BIT
;
2250 struct net_device
*dev
;
2251 struct sk_buff
*skb
;
2255 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2257 dev
= hw
->dev
[port
];
2258 sky2
= netdev_priv(dev
);
2259 length
= le16_to_cpu(le
->length
);
2260 status
= le32_to_cpu(le
->status
);
2262 switch (le
->opcode
& ~HW_OWNER
) {
2265 skb
= sky2_receive(dev
, length
, status
);
2266 if (unlikely(!skb
)) {
2267 sky2
->net_stats
.rx_dropped
++;
2271 /* This chip reports checksum status differently */
2272 if (hw
->flags
& SKY2_HW_NEW_LE
) {
2273 if (sky2
->rx_csum
&&
2274 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2275 (le
->css
& CSS_TCPUDPCSOK
))
2276 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2278 skb
->ip_summed
= CHECKSUM_NONE
;
2281 skb
->protocol
= eth_type_trans(skb
, dev
);
2282 sky2
->net_stats
.rx_packets
++;
2283 sky2
->net_stats
.rx_bytes
+= skb
->len
;
2284 dev
->last_rx
= jiffies
;
2286 #ifdef SKY2_VLAN_TAG_USED
2287 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2288 vlan_hwaccel_receive_skb(skb
,
2290 be16_to_cpu(sky2
->rx_tag
));
2293 netif_receive_skb(skb
);
2295 /* Stop after net poll weight */
2296 if (++work_done
>= to_do
)
2300 #ifdef SKY2_VLAN_TAG_USED
2302 sky2
->rx_tag
= length
;
2306 sky2
->rx_tag
= length
;
2313 /* If this happens then driver assuming wrong format */
2314 if (unlikely(hw
->flags
& SKY2_HW_NEW_LE
)) {
2315 if (net_ratelimit())
2316 printk(KERN_NOTICE
"%s: unexpected"
2317 " checksum status\n",
2322 /* Both checksum counters are programmed to start at
2323 * the same offset, so unless there is a problem they
2324 * should match. This failure is an early indication that
2325 * hardware receive checksumming won't work.
2327 if (likely(status
>> 16 == (status
& 0xffff))) {
2328 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2329 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2330 skb
->csum
= status
& 0xffff;
2332 printk(KERN_NOTICE PFX
"%s: hardware receive "
2333 "checksum problem (status = %#x)\n",
2336 sky2_write32(sky2
->hw
,
2337 Q_ADDR(rxqaddr
[port
], Q_CSR
),
2343 /* TX index reports status for both ports */
2344 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2345 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2347 sky2_tx_done(hw
->dev
[1],
2348 ((status
>> 24) & 0xff)
2349 | (u16
)(length
& 0xf) << 8);
2353 if (net_ratelimit())
2354 printk(KERN_WARNING PFX
2355 "unknown status opcode 0x%x\n", le
->opcode
);
2359 /* Fully processed status ring so clear irq */
2360 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2364 sky2_rx_update(netdev_priv(hw
->dev
[0]), Q_R1
);
2367 sky2_rx_update(netdev_priv(hw
->dev
[1]), Q_R2
);
2372 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2374 struct net_device
*dev
= hw
->dev
[port
];
2376 if (net_ratelimit())
2377 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2380 if (status
& Y2_IS_PAR_RD1
) {
2381 if (net_ratelimit())
2382 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2385 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2388 if (status
& Y2_IS_PAR_WR1
) {
2389 if (net_ratelimit())
2390 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2393 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2396 if (status
& Y2_IS_PAR_MAC1
) {
2397 if (net_ratelimit())
2398 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2399 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2402 if (status
& Y2_IS_PAR_RX1
) {
2403 if (net_ratelimit())
2404 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2405 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2408 if (status
& Y2_IS_TCP_TXA1
) {
2409 if (net_ratelimit())
2410 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2412 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2416 static void sky2_hw_intr(struct sky2_hw
*hw
)
2418 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2420 if (status
& Y2_IS_TIST_OV
)
2421 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2423 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2426 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2427 if (net_ratelimit())
2428 dev_err(&hw
->pdev
->dev
, "PCI hardware error (0x%x)\n",
2431 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2432 sky2_pci_write16(hw
, PCI_STATUS
,
2433 pci_err
| PCI_STATUS_ERROR_BITS
);
2434 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2437 if (status
& Y2_IS_PCI_EXP
) {
2438 /* PCI-Express uncorrectable Error occurred */
2441 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2443 if (net_ratelimit())
2444 dev_err(&hw
->pdev
->dev
, "PCI Express error (0x%x)\n",
2447 /* clear the interrupt */
2448 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2449 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2451 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2453 if (pex_err
& PEX_FATAL_ERRORS
) {
2454 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2455 hwmsk
&= ~Y2_IS_PCI_EXP
;
2456 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2460 if (status
& Y2_HWE_L1_MASK
)
2461 sky2_hw_error(hw
, 0, status
);
2463 if (status
& Y2_HWE_L1_MASK
)
2464 sky2_hw_error(hw
, 1, status
);
2467 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2469 struct net_device
*dev
= hw
->dev
[port
];
2470 struct sky2_port
*sky2
= netdev_priv(dev
);
2471 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2473 if (netif_msg_intr(sky2
))
2474 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2477 if (status
& GM_IS_RX_CO_OV
)
2478 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2480 if (status
& GM_IS_TX_CO_OV
)
2481 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2483 if (status
& GM_IS_RX_FF_OR
) {
2484 ++sky2
->net_stats
.rx_fifo_errors
;
2485 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2488 if (status
& GM_IS_TX_FF_UR
) {
2489 ++sky2
->net_stats
.tx_fifo_errors
;
2490 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2494 /* This should never happen it is a bug. */
2495 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
,
2496 u16 q
, unsigned ring_size
)
2498 struct net_device
*dev
= hw
->dev
[port
];
2499 struct sky2_port
*sky2
= netdev_priv(dev
);
2501 const u64
*le
= (q
== Q_R1
|| q
== Q_R2
)
2502 ? (u64
*) sky2
->rx_le
: (u64
*) sky2
->tx_le
;
2504 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2505 printk(KERN_ERR PFX
"%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2506 dev
->name
, (unsigned) q
, idx
, (unsigned long long) le
[idx
],
2507 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2509 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2512 static int sky2_rx_hung(struct net_device
*dev
)
2514 struct sky2_port
*sky2
= netdev_priv(dev
);
2515 struct sky2_hw
*hw
= sky2
->hw
;
2516 unsigned port
= sky2
->port
;
2517 unsigned rxq
= rxqaddr
[port
];
2518 u32 mac_rp
= sky2_read32(hw
, SK_REG(port
, RX_GMF_RP
));
2519 u8 mac_lev
= sky2_read8(hw
, SK_REG(port
, RX_GMF_RLEV
));
2520 u8 fifo_rp
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RP
));
2521 u8 fifo_lev
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RL
));
2523 /* If idle and MAC or PCI is stuck */
2524 if (sky2
->check
.last
== dev
->last_rx
&&
2525 ((mac_rp
== sky2
->check
.mac_rp
&&
2526 mac_lev
!= 0 && mac_lev
>= sky2
->check
.mac_lev
) ||
2527 /* Check if the PCI RX hang */
2528 (fifo_rp
== sky2
->check
.fifo_rp
&&
2529 fifo_lev
!= 0 && fifo_lev
>= sky2
->check
.fifo_lev
))) {
2530 printk(KERN_DEBUG PFX
"%s: hung mac %d:%d fifo %d (%d:%d)\n",
2531 dev
->name
, mac_lev
, mac_rp
, fifo_lev
, fifo_rp
,
2532 sky2_read8(hw
, Q_ADDR(rxq
, Q_WP
)));
2535 sky2
->check
.last
= dev
->last_rx
;
2536 sky2
->check
.mac_rp
= mac_rp
;
2537 sky2
->check
.mac_lev
= mac_lev
;
2538 sky2
->check
.fifo_rp
= fifo_rp
;
2539 sky2
->check
.fifo_lev
= fifo_lev
;
2544 static void sky2_watchdog(unsigned long arg
)
2546 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2547 struct net_device
*dev
;
2549 /* Check for lost IRQ once a second */
2550 if (sky2_read32(hw
, B0_ISRC
)) {
2552 if (__netif_rx_schedule_prep(dev
))
2553 __netif_rx_schedule(dev
);
2557 for (i
= 0; i
< hw
->ports
; i
++) {
2559 if (!netif_running(dev
))
2563 /* For chips with Rx FIFO, check if stuck */
2564 if ((hw
->flags
& SKY2_HW_FIFO_HANG_CHECK
) &&
2565 sky2_rx_hung(dev
)) {
2566 pr_info(PFX
"%s: receiver hang detected\n",
2568 schedule_work(&hw
->restart_work
);
2577 mod_timer(&hw
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
2580 /* Hardware/software error handling */
2581 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2583 if (net_ratelimit())
2584 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2586 if (status
& Y2_IS_HW_ERR
)
2589 if (status
& Y2_IS_IRQ_MAC1
)
2590 sky2_mac_intr(hw
, 0);
2592 if (status
& Y2_IS_IRQ_MAC2
)
2593 sky2_mac_intr(hw
, 1);
2595 if (status
& Y2_IS_CHK_RX1
)
2596 sky2_le_error(hw
, 0, Q_R1
, RX_LE_SIZE
);
2598 if (status
& Y2_IS_CHK_RX2
)
2599 sky2_le_error(hw
, 1, Q_R2
, RX_LE_SIZE
);
2601 if (status
& Y2_IS_CHK_TXA1
)
2602 sky2_le_error(hw
, 0, Q_XA1
, TX_RING_SIZE
);
2604 if (status
& Y2_IS_CHK_TXA2
)
2605 sky2_le_error(hw
, 1, Q_XA2
, TX_RING_SIZE
);
2608 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2610 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2612 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2614 if (unlikely(status
& Y2_IS_ERROR
))
2615 sky2_err_intr(hw
, status
);
2617 if (status
& Y2_IS_IRQ_PHY1
)
2618 sky2_phy_intr(hw
, 0);
2620 if (status
& Y2_IS_IRQ_PHY2
)
2621 sky2_phy_intr(hw
, 1);
2623 work_done
= sky2_status_intr(hw
, min(dev0
->quota
, *budget
));
2624 *budget
-= work_done
;
2625 dev0
->quota
-= work_done
;
2628 if (hw
->st_idx
!= sky2_read16(hw
, STAT_PUT_IDX
))
2631 /* Bug/Errata workaround?
2632 * Need to kick the TX irq moderation timer.
2634 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_START
) {
2635 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2636 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2638 netif_rx_complete(dev0
);
2640 sky2_read32(hw
, B0_Y2_SP_LISR
);
2644 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2646 struct sky2_hw
*hw
= dev_id
;
2647 struct net_device
*dev0
= hw
->dev
[0];
2650 /* Reading this mask interrupts as side effect */
2651 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2652 if (status
== 0 || status
== ~0)
2655 prefetch(&hw
->st_le
[hw
->st_idx
]);
2656 if (likely(__netif_rx_schedule_prep(dev0
)))
2657 __netif_rx_schedule(dev0
);
2662 #ifdef CONFIG_NET_POLL_CONTROLLER
2663 static void sky2_netpoll(struct net_device
*dev
)
2665 struct sky2_port
*sky2
= netdev_priv(dev
);
2666 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2668 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2669 __netif_rx_schedule(dev0
);
2673 /* Chip internal frequency for clock calculations */
2674 static u32
sky2_mhz(const struct sky2_hw
*hw
)
2676 switch (hw
->chip_id
) {
2677 case CHIP_ID_YUKON_EC
:
2678 case CHIP_ID_YUKON_EC_U
:
2679 case CHIP_ID_YUKON_EX
:
2682 case CHIP_ID_YUKON_FE
:
2685 case CHIP_ID_YUKON_FE_P
:
2688 case CHIP_ID_YUKON_XL
:
2696 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2698 return sky2_mhz(hw
) * us
;
2701 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2703 return clk
/ sky2_mhz(hw
);
2707 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2711 /* Enable all clocks */
2712 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2714 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2716 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2717 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2719 switch(hw
->chip_id
) {
2720 case CHIP_ID_YUKON_XL
:
2721 hw
->flags
= SKY2_HW_GIGABIT
2722 | SKY2_HW_NEWER_PHY
;
2723 if (hw
->chip_rev
< 3)
2724 hw
->flags
|= SKY2_HW_FIFO_HANG_CHECK
;
2728 case CHIP_ID_YUKON_EC_U
:
2729 hw
->flags
= SKY2_HW_GIGABIT
2731 | SKY2_HW_ADV_POWER_CTL
;
2734 case CHIP_ID_YUKON_EX
:
2735 hw
->flags
= SKY2_HW_GIGABIT
2738 | SKY2_HW_ADV_POWER_CTL
;
2740 /* New transmit checksum */
2741 if (hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
2742 hw
->flags
|= SKY2_HW_AUTO_TX_SUM
;
2745 case CHIP_ID_YUKON_EC
:
2746 /* This rev is really old, and requires untested workarounds */
2747 if (hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2748 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-EC rev A1\n");
2751 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_FIFO_HANG_CHECK
;
2754 case CHIP_ID_YUKON_FE
:
2757 case CHIP_ID_YUKON_FE_P
:
2758 hw
->flags
= SKY2_HW_NEWER_PHY
2760 | SKY2_HW_AUTO_TX_SUM
2761 | SKY2_HW_ADV_POWER_CTL
;
2764 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2769 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2770 if (hw
->pmd_type
== 'L' || hw
->pmd_type
== 'S' || hw
->pmd_type
== 'P')
2771 hw
->flags
|= SKY2_HW_FIBRE_PHY
;
2775 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2776 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2777 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2784 static void sky2_reset(struct sky2_hw
*hw
)
2790 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2791 status
= sky2_read16(hw
, HCU_CCSR
);
2792 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2793 HCU_CCSR_UC_STATE_MSK
);
2794 sky2_write16(hw
, HCU_CCSR
, status
);
2796 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2797 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2800 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2801 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2803 /* clear PCI errors, if any */
2804 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2806 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2807 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2810 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2812 /* clear any PEX errors */
2813 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2814 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2819 for (i
= 0; i
< hw
->ports
; i
++) {
2820 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2821 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2823 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2824 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
2825 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
2829 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2831 /* Clear I2C IRQ noise */
2832 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2834 /* turn off hardware timer (unused) */
2835 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2836 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2838 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2840 /* Turn off descriptor polling */
2841 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2843 /* Turn off receive timestamp */
2844 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2845 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2847 /* enable the Tx Arbiters */
2848 for (i
= 0; i
< hw
->ports
; i
++)
2849 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2851 /* Initialize ram interface */
2852 for (i
= 0; i
< hw
->ports
; i
++) {
2853 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2855 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2856 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2857 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2858 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2859 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2860 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2861 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2862 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2863 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2864 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2865 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2866 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2869 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2871 for (i
= 0; i
< hw
->ports
; i
++)
2872 sky2_gmac_reset(hw
, i
);
2874 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2877 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2878 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2880 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2881 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2883 /* Set the list last index */
2884 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2886 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2887 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2889 /* set Status-FIFO ISR watermark */
2890 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2891 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2893 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2895 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2896 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2897 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2899 /* enable status unit */
2900 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2902 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2903 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2904 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2907 static void sky2_restart(struct work_struct
*work
)
2909 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
2910 struct net_device
*dev
;
2914 sky2_write32(hw
, B0_IMSK
, 0);
2915 sky2_read32(hw
, B0_IMSK
);
2917 netif_poll_disable(hw
->dev
[0]);
2919 for (i
= 0; i
< hw
->ports
; i
++) {
2921 if (netif_running(dev
))
2926 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
2927 netif_poll_enable(hw
->dev
[0]);
2929 for (i
= 0; i
< hw
->ports
; i
++) {
2931 if (netif_running(dev
)) {
2934 printk(KERN_INFO PFX
"%s: could not restart %d\n",
2944 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
2946 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
2949 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2951 const struct sky2_port
*sky2
= netdev_priv(dev
);
2953 wol
->supported
= sky2_wol_supported(sky2
->hw
);
2954 wol
->wolopts
= sky2
->wol
;
2957 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2959 struct sky2_port
*sky2
= netdev_priv(dev
);
2960 struct sky2_hw
*hw
= sky2
->hw
;
2962 if (wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
2965 sky2
->wol
= wol
->wolopts
;
2967 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
2968 hw
->chip_id
== CHIP_ID_YUKON_EX
||
2969 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
2970 sky2_write32(hw
, B0_CTST
, sky2
->wol
2971 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
2973 if (!netif_running(dev
))
2974 sky2_wol_init(sky2
);
2978 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2980 if (sky2_is_copper(hw
)) {
2981 u32 modes
= SUPPORTED_10baseT_Half
2982 | SUPPORTED_10baseT_Full
2983 | SUPPORTED_100baseT_Half
2984 | SUPPORTED_100baseT_Full
2985 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2987 if (hw
->flags
& SKY2_HW_GIGABIT
)
2988 modes
|= SUPPORTED_1000baseT_Half
2989 | SUPPORTED_1000baseT_Full
;
2992 return SUPPORTED_1000baseT_Half
2993 | SUPPORTED_1000baseT_Full
2998 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3000 struct sky2_port
*sky2
= netdev_priv(dev
);
3001 struct sky2_hw
*hw
= sky2
->hw
;
3003 ecmd
->transceiver
= XCVR_INTERNAL
;
3004 ecmd
->supported
= sky2_supported_modes(hw
);
3005 ecmd
->phy_address
= PHY_ADDR_MARV
;
3006 if (sky2_is_copper(hw
)) {
3007 ecmd
->port
= PORT_TP
;
3008 ecmd
->speed
= sky2
->speed
;
3010 ecmd
->speed
= SPEED_1000
;
3011 ecmd
->port
= PORT_FIBRE
;
3014 ecmd
->advertising
= sky2
->advertising
;
3015 ecmd
->autoneg
= sky2
->autoneg
;
3016 ecmd
->duplex
= sky2
->duplex
;
3020 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3022 struct sky2_port
*sky2
= netdev_priv(dev
);
3023 const struct sky2_hw
*hw
= sky2
->hw
;
3024 u32 supported
= sky2_supported_modes(hw
);
3026 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3027 ecmd
->advertising
= supported
;
3033 switch (ecmd
->speed
) {
3035 if (ecmd
->duplex
== DUPLEX_FULL
)
3036 setting
= SUPPORTED_1000baseT_Full
;
3037 else if (ecmd
->duplex
== DUPLEX_HALF
)
3038 setting
= SUPPORTED_1000baseT_Half
;
3043 if (ecmd
->duplex
== DUPLEX_FULL
)
3044 setting
= SUPPORTED_100baseT_Full
;
3045 else if (ecmd
->duplex
== DUPLEX_HALF
)
3046 setting
= SUPPORTED_100baseT_Half
;
3052 if (ecmd
->duplex
== DUPLEX_FULL
)
3053 setting
= SUPPORTED_10baseT_Full
;
3054 else if (ecmd
->duplex
== DUPLEX_HALF
)
3055 setting
= SUPPORTED_10baseT_Half
;
3063 if ((setting
& supported
) == 0)
3066 sky2
->speed
= ecmd
->speed
;
3067 sky2
->duplex
= ecmd
->duplex
;
3070 sky2
->autoneg
= ecmd
->autoneg
;
3071 sky2
->advertising
= ecmd
->advertising
;
3073 if (netif_running(dev
)) {
3074 sky2_phy_reinit(sky2
);
3075 sky2_set_multicast(dev
);
3081 static void sky2_get_drvinfo(struct net_device
*dev
,
3082 struct ethtool_drvinfo
*info
)
3084 struct sky2_port
*sky2
= netdev_priv(dev
);
3086 strcpy(info
->driver
, DRV_NAME
);
3087 strcpy(info
->version
, DRV_VERSION
);
3088 strcpy(info
->fw_version
, "N/A");
3089 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
3092 static const struct sky2_stat
{
3093 char name
[ETH_GSTRING_LEN
];
3096 { "tx_bytes", GM_TXO_OK_HI
},
3097 { "rx_bytes", GM_RXO_OK_HI
},
3098 { "tx_broadcast", GM_TXF_BC_OK
},
3099 { "rx_broadcast", GM_RXF_BC_OK
},
3100 { "tx_multicast", GM_TXF_MC_OK
},
3101 { "rx_multicast", GM_RXF_MC_OK
},
3102 { "tx_unicast", GM_TXF_UC_OK
},
3103 { "rx_unicast", GM_RXF_UC_OK
},
3104 { "tx_mac_pause", GM_TXF_MPAUSE
},
3105 { "rx_mac_pause", GM_RXF_MPAUSE
},
3106 { "collisions", GM_TXF_COL
},
3107 { "late_collision",GM_TXF_LAT_COL
},
3108 { "aborted", GM_TXF_ABO_COL
},
3109 { "single_collisions", GM_TXF_SNG_COL
},
3110 { "multi_collisions", GM_TXF_MUL_COL
},
3112 { "rx_short", GM_RXF_SHT
},
3113 { "rx_runt", GM_RXE_FRAG
},
3114 { "rx_64_byte_packets", GM_RXF_64B
},
3115 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
3116 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
3117 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
3118 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
3119 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
3120 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
3121 { "rx_too_long", GM_RXF_LNG_ERR
},
3122 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
3123 { "rx_jabber", GM_RXF_JAB_PKT
},
3124 { "rx_fcs_error", GM_RXF_FCS_ERR
},
3126 { "tx_64_byte_packets", GM_TXF_64B
},
3127 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
3128 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
3129 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
3130 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
3131 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
3132 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
3133 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
3136 static u32
sky2_get_rx_csum(struct net_device
*dev
)
3138 struct sky2_port
*sky2
= netdev_priv(dev
);
3140 return sky2
->rx_csum
;
3143 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
3145 struct sky2_port
*sky2
= netdev_priv(dev
);
3147 sky2
->rx_csum
= data
;
3149 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
3150 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
3155 static u32
sky2_get_msglevel(struct net_device
*netdev
)
3157 struct sky2_port
*sky2
= netdev_priv(netdev
);
3158 return sky2
->msg_enable
;
3161 static int sky2_nway_reset(struct net_device
*dev
)
3163 struct sky2_port
*sky2
= netdev_priv(dev
);
3165 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
3168 sky2_phy_reinit(sky2
);
3169 sky2_set_multicast(dev
);
3174 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3176 struct sky2_hw
*hw
= sky2
->hw
;
3177 unsigned port
= sky2
->port
;
3180 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
3181 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
3182 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
3183 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
3185 for (i
= 2; i
< count
; i
++)
3186 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
3189 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3191 struct sky2_port
*sky2
= netdev_priv(netdev
);
3192 sky2
->msg_enable
= value
;
3195 static int sky2_get_stats_count(struct net_device
*dev
)
3197 return ARRAY_SIZE(sky2_stats
);
3200 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3201 struct ethtool_stats
*stats
, u64
* data
)
3203 struct sky2_port
*sky2
= netdev_priv(dev
);
3205 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3208 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3212 switch (stringset
) {
3214 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3215 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3216 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3221 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
3223 struct sky2_port
*sky2
= netdev_priv(dev
);
3224 return &sky2
->net_stats
;
3227 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3229 struct sky2_port
*sky2
= netdev_priv(dev
);
3230 struct sky2_hw
*hw
= sky2
->hw
;
3231 unsigned port
= sky2
->port
;
3232 const struct sockaddr
*addr
= p
;
3234 if (!is_valid_ether_addr(addr
->sa_data
))
3235 return -EADDRNOTAVAIL
;
3237 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3238 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3239 dev
->dev_addr
, ETH_ALEN
);
3240 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3241 dev
->dev_addr
, ETH_ALEN
);
3243 /* virtual address for data */
3244 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3246 /* physical address: used for pause frames */
3247 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3252 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3256 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3257 filter
[bit
>> 3] |= 1 << (bit
& 7);
3260 static void sky2_set_multicast(struct net_device
*dev
)
3262 struct sky2_port
*sky2
= netdev_priv(dev
);
3263 struct sky2_hw
*hw
= sky2
->hw
;
3264 unsigned port
= sky2
->port
;
3265 struct dev_mc_list
*list
= dev
->mc_list
;
3269 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3271 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3272 memset(filter
, 0, sizeof(filter
));
3274 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3275 reg
|= GM_RXCR_UCF_ENA
;
3277 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3278 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3279 else if (dev
->flags
& IFF_ALLMULTI
)
3280 memset(filter
, 0xff, sizeof(filter
));
3281 else if (dev
->mc_count
== 0 && !rx_pause
)
3282 reg
&= ~GM_RXCR_MCF_ENA
;
3285 reg
|= GM_RXCR_MCF_ENA
;
3288 sky2_add_filter(filter
, pause_mc_addr
);
3290 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3291 sky2_add_filter(filter
, list
->dmi_addr
);
3294 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3295 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3296 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3297 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3298 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3299 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3300 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3301 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3303 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3306 /* Can have one global because blinking is controlled by
3307 * ethtool and that is always under RTNL mutex
3309 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
3313 switch (hw
->chip_id
) {
3314 case CHIP_ID_YUKON_XL
:
3315 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3316 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3317 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3318 on
? (PHY_M_LEDC_LOS_CTRL(1) |
3319 PHY_M_LEDC_INIT_CTRL(7) |
3320 PHY_M_LEDC_STA1_CTRL(7) |
3321 PHY_M_LEDC_STA0_CTRL(7))
3324 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3328 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
3329 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3330 on
? PHY_M_LED_ALL
: 0);
3334 /* blink LED's for finding board */
3335 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3337 struct sky2_port
*sky2
= netdev_priv(dev
);
3338 struct sky2_hw
*hw
= sky2
->hw
;
3339 unsigned port
= sky2
->port
;
3340 u16 ledctrl
, ledover
= 0;
3345 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
3346 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
3350 /* save initial values */
3351 spin_lock_bh(&sky2
->phy_lock
);
3352 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3353 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3354 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3355 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
3356 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3358 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
3359 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
3363 while (!interrupted
&& ms
> 0) {
3364 sky2_led(hw
, port
, onoff
);
3367 spin_unlock_bh(&sky2
->phy_lock
);
3368 interrupted
= msleep_interruptible(250);
3369 spin_lock_bh(&sky2
->phy_lock
);
3374 /* resume regularly scheduled programming */
3375 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3376 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3377 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3378 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
3379 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3381 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
3382 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
3384 spin_unlock_bh(&sky2
->phy_lock
);
3389 static void sky2_get_pauseparam(struct net_device
*dev
,
3390 struct ethtool_pauseparam
*ecmd
)
3392 struct sky2_port
*sky2
= netdev_priv(dev
);
3394 switch (sky2
->flow_mode
) {
3396 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3399 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3402 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3405 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3408 ecmd
->autoneg
= sky2
->autoneg
;
3411 static int sky2_set_pauseparam(struct net_device
*dev
,
3412 struct ethtool_pauseparam
*ecmd
)
3414 struct sky2_port
*sky2
= netdev_priv(dev
);
3416 sky2
->autoneg
= ecmd
->autoneg
;
3417 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3419 if (netif_running(dev
))
3420 sky2_phy_reinit(sky2
);
3425 static int sky2_get_coalesce(struct net_device
*dev
,
3426 struct ethtool_coalesce
*ecmd
)
3428 struct sky2_port
*sky2
= netdev_priv(dev
);
3429 struct sky2_hw
*hw
= sky2
->hw
;
3431 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3432 ecmd
->tx_coalesce_usecs
= 0;
3434 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3435 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3437 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3439 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3440 ecmd
->rx_coalesce_usecs
= 0;
3442 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3443 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3445 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3447 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3448 ecmd
->rx_coalesce_usecs_irq
= 0;
3450 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3451 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3454 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3459 /* Note: this affect both ports */
3460 static int sky2_set_coalesce(struct net_device
*dev
,
3461 struct ethtool_coalesce
*ecmd
)
3463 struct sky2_port
*sky2
= netdev_priv(dev
);
3464 struct sky2_hw
*hw
= sky2
->hw
;
3465 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3467 if (ecmd
->tx_coalesce_usecs
> tmax
||
3468 ecmd
->rx_coalesce_usecs
> tmax
||
3469 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3472 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3474 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3476 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3479 if (ecmd
->tx_coalesce_usecs
== 0)
3480 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3482 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3483 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3484 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3486 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3488 if (ecmd
->rx_coalesce_usecs
== 0)
3489 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3491 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3492 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3493 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3495 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3497 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3498 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3500 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3501 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3502 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3504 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3508 static void sky2_get_ringparam(struct net_device
*dev
,
3509 struct ethtool_ringparam
*ering
)
3511 struct sky2_port
*sky2
= netdev_priv(dev
);
3513 ering
->rx_max_pending
= RX_MAX_PENDING
;
3514 ering
->rx_mini_max_pending
= 0;
3515 ering
->rx_jumbo_max_pending
= 0;
3516 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3518 ering
->rx_pending
= sky2
->rx_pending
;
3519 ering
->rx_mini_pending
= 0;
3520 ering
->rx_jumbo_pending
= 0;
3521 ering
->tx_pending
= sky2
->tx_pending
;
3524 static int sky2_set_ringparam(struct net_device
*dev
,
3525 struct ethtool_ringparam
*ering
)
3527 struct sky2_port
*sky2
= netdev_priv(dev
);
3530 if (ering
->rx_pending
> RX_MAX_PENDING
||
3531 ering
->rx_pending
< 8 ||
3532 ering
->tx_pending
< MAX_SKB_TX_LE
||
3533 ering
->tx_pending
> TX_RING_SIZE
- 1)
3536 if (netif_running(dev
))
3539 sky2
->rx_pending
= ering
->rx_pending
;
3540 sky2
->tx_pending
= ering
->tx_pending
;
3542 if (netif_running(dev
)) {
3547 sky2_set_multicast(dev
);
3553 static int sky2_get_regs_len(struct net_device
*dev
)
3559 * Returns copy of control register region
3560 * Note: ethtool_get_regs always provides full size (16k) buffer
3562 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3565 const struct sky2_port
*sky2
= netdev_priv(dev
);
3566 const void __iomem
*io
= sky2
->hw
->regs
;
3569 memset(p
, 0, regs
->len
);
3571 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3573 /* skip diagnostic ram region */
3574 memcpy_fromio(p
+ B3_RI_WTO_R1
, io
+ B3_RI_WTO_R1
, 0x2000 - B3_RI_WTO_R1
);
3576 /* copy GMAC registers */
3577 memcpy_fromio(p
+ BASE_GMAC_1
, io
+ BASE_GMAC_1
, 0x1000);
3578 if (sky2
->hw
->ports
> 1)
3579 memcpy_fromio(p
+ BASE_GMAC_2
, io
+ BASE_GMAC_2
, 0x1000);
3583 /* In order to do Jumbo packets on these chips, need to turn off the
3584 * transmit store/forward. Therefore checksum offload won't work.
3586 static int no_tx_offload(struct net_device
*dev
)
3588 const struct sky2_port
*sky2
= netdev_priv(dev
);
3589 const struct sky2_hw
*hw
= sky2
->hw
;
3591 return dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
;
3594 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3596 if (data
&& no_tx_offload(dev
))
3599 return ethtool_op_set_tx_csum(dev
, data
);
3603 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3605 if (data
&& no_tx_offload(dev
))
3608 return ethtool_op_set_tso(dev
, data
);
3611 static int sky2_get_eeprom_len(struct net_device
*dev
)
3613 struct sky2_port
*sky2
= netdev_priv(dev
);
3616 reg2
= sky2_pci_read32(sky2
->hw
, PCI_DEV_REG2
);
3617 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
3620 static u32
sky2_vpd_read(struct sky2_hw
*hw
, int cap
, u16 offset
)
3622 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
3624 while (!(sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
))
3626 return sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
3629 static void sky2_vpd_write(struct sky2_hw
*hw
, int cap
, u16 offset
, u32 val
)
3631 sky2_pci_write32(hw
, cap
+ PCI_VPD_DATA
, val
);
3632 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
3635 } while (sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
);
3638 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3641 struct sky2_port
*sky2
= netdev_priv(dev
);
3642 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3643 int length
= eeprom
->len
;
3644 u16 offset
= eeprom
->offset
;
3649 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
3651 while (length
> 0) {
3652 u32 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3653 int n
= min_t(int, length
, sizeof(val
));
3655 memcpy(data
, &val
, n
);
3663 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3666 struct sky2_port
*sky2
= netdev_priv(dev
);
3667 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3668 int length
= eeprom
->len
;
3669 u16 offset
= eeprom
->offset
;
3674 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
3677 while (length
> 0) {
3679 int n
= min_t(int, length
, sizeof(val
));
3681 if (n
< sizeof(val
))
3682 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3683 memcpy(&val
, data
, n
);
3685 sky2_vpd_write(sky2
->hw
, cap
, offset
, val
);
3695 static const struct ethtool_ops sky2_ethtool_ops
= {
3696 .get_settings
= sky2_get_settings
,
3697 .set_settings
= sky2_set_settings
,
3698 .get_drvinfo
= sky2_get_drvinfo
,
3699 .get_wol
= sky2_get_wol
,
3700 .set_wol
= sky2_set_wol
,
3701 .get_msglevel
= sky2_get_msglevel
,
3702 .set_msglevel
= sky2_set_msglevel
,
3703 .nway_reset
= sky2_nway_reset
,
3704 .get_regs_len
= sky2_get_regs_len
,
3705 .get_regs
= sky2_get_regs
,
3706 .get_link
= ethtool_op_get_link
,
3707 .get_eeprom_len
= sky2_get_eeprom_len
,
3708 .get_eeprom
= sky2_get_eeprom
,
3709 .set_eeprom
= sky2_set_eeprom
,
3710 .get_sg
= ethtool_op_get_sg
,
3711 .set_sg
= ethtool_op_set_sg
,
3712 .get_tx_csum
= ethtool_op_get_tx_csum
,
3713 .set_tx_csum
= sky2_set_tx_csum
,
3714 .get_tso
= ethtool_op_get_tso
,
3715 .set_tso
= sky2_set_tso
,
3716 .get_rx_csum
= sky2_get_rx_csum
,
3717 .set_rx_csum
= sky2_set_rx_csum
,
3718 .get_strings
= sky2_get_strings
,
3719 .get_coalesce
= sky2_get_coalesce
,
3720 .set_coalesce
= sky2_set_coalesce
,
3721 .get_ringparam
= sky2_get_ringparam
,
3722 .set_ringparam
= sky2_set_ringparam
,
3723 .get_pauseparam
= sky2_get_pauseparam
,
3724 .set_pauseparam
= sky2_set_pauseparam
,
3725 .phys_id
= sky2_phys_id
,
3726 .get_stats_count
= sky2_get_stats_count
,
3727 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3730 #ifdef CONFIG_SKY2_DEBUG
3732 static struct dentry
*sky2_debug
;
3734 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
3736 struct net_device
*dev
= seq
->private;
3737 const struct sky2_port
*sky2
= netdev_priv(dev
);
3738 const struct sky2_hw
*hw
= sky2
->hw
;
3739 unsigned port
= sky2
->port
;
3743 if (!netif_running(dev
))
3746 seq_printf(seq
, "IRQ src=%x mask=%x control=%x\n",
3747 sky2_read32(hw
, B0_ISRC
),
3748 sky2_read32(hw
, B0_IMSK
),
3749 sky2_read32(hw
, B0_Y2_SP_ICR
));
3751 netif_poll_disable(hw
->dev
[0]);
3752 last
= sky2_read16(hw
, STAT_PUT_IDX
);
3754 if (hw
->st_idx
== last
)
3755 seq_puts(seq
, "Status ring (empty)\n");
3757 seq_puts(seq
, "Status ring\n");
3758 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< STATUS_RING_SIZE
;
3759 idx
= RING_NEXT(idx
, STATUS_RING_SIZE
)) {
3760 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
3761 seq_printf(seq
, "[%d] %#x %d %#x\n",
3762 idx
, le
->opcode
, le
->length
, le
->status
);
3764 seq_puts(seq
, "\n");
3767 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
3768 sky2
->tx_cons
, sky2
->tx_prod
,
3769 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
3770 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
3772 /* Dump contents of tx ring */
3774 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< TX_RING_SIZE
;
3775 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
3776 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
3777 u32 a
= le32_to_cpu(le
->addr
);
3780 seq_printf(seq
, "%u:", idx
);
3783 switch(le
->opcode
& ~HW_OWNER
) {
3785 seq_printf(seq
, " %#x:", a
);
3788 seq_printf(seq
, " mtu=%d", a
);
3791 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
3794 seq_printf(seq
, " csum=%#x", a
);
3797 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
3800 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
3803 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
3806 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
3807 a
, le16_to_cpu(le
->length
));
3810 if (le
->ctrl
& EOP
) {
3811 seq_putc(seq
, '\n');
3816 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
3817 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
3818 last
= sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
3819 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
3821 netif_poll_enable(hw
->dev
[0]);
3825 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
3827 return single_open(file
, sky2_debug_show
, inode
->i_private
);
3830 static const struct file_operations sky2_debug_fops
= {
3831 .owner
= THIS_MODULE
,
3832 .open
= sky2_debug_open
,
3834 .llseek
= seq_lseek
,
3835 .release
= single_release
,
3839 * Use network device events to create/remove/rename
3840 * debugfs file entries
3842 static int sky2_device_event(struct notifier_block
*unused
,
3843 unsigned long event
, void *ptr
)
3845 struct net_device
*dev
= ptr
;
3847 if (dev
->open
== sky2_up
) {
3848 struct sky2_port
*sky2
= netdev_priv(dev
);
3851 case NETDEV_CHANGENAME
:
3852 if (!netif_running(dev
))
3856 case NETDEV_GOING_DOWN
:
3857 if (sky2
->debugfs
) {
3858 printk(KERN_DEBUG PFX
"%s: remove debugfs\n",
3860 debugfs_remove(sky2
->debugfs
);
3861 sky2
->debugfs
= NULL
;
3864 if (event
!= NETDEV_CHANGENAME
)
3866 /* fallthrough for changename */
3870 d
= debugfs_create_file(dev
->name
, S_IRUGO
,
3873 if (d
== NULL
|| IS_ERR(d
))
3874 printk(KERN_INFO PFX
3875 "%s: debugfs create failed\n",
3887 static struct notifier_block sky2_notifier
= {
3888 .notifier_call
= sky2_device_event
,
3892 static __init
void sky2_debug_init(void)
3896 ent
= debugfs_create_dir("sky2", NULL
);
3897 if (!ent
|| IS_ERR(ent
))
3901 register_netdevice_notifier(&sky2_notifier
);
3904 static __exit
void sky2_debug_cleanup(void)
3907 unregister_netdevice_notifier(&sky2_notifier
);
3908 debugfs_remove(sky2_debug
);
3914 #define sky2_debug_init()
3915 #define sky2_debug_cleanup()
3919 /* Initialize network device */
3920 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3922 int highmem
, int wol
)
3924 struct sky2_port
*sky2
;
3925 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3928 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed");
3932 SET_MODULE_OWNER(dev
);
3933 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3934 dev
->irq
= hw
->pdev
->irq
;
3935 dev
->open
= sky2_up
;
3936 dev
->stop
= sky2_down
;
3937 dev
->do_ioctl
= sky2_ioctl
;
3938 dev
->hard_start_xmit
= sky2_xmit_frame
;
3939 dev
->get_stats
= sky2_get_stats
;
3940 dev
->set_multicast_list
= sky2_set_multicast
;
3941 dev
->set_mac_address
= sky2_set_mac_address
;
3942 dev
->change_mtu
= sky2_change_mtu
;
3943 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3944 dev
->tx_timeout
= sky2_tx_timeout
;
3945 dev
->watchdog_timeo
= TX_WATCHDOG
;
3947 dev
->poll
= sky2_poll
;
3948 dev
->weight
= NAPI_WEIGHT
;
3949 #ifdef CONFIG_NET_POLL_CONTROLLER
3950 /* Network console (only works on port 0)
3951 * because netpoll makes assumptions about NAPI
3954 dev
->poll_controller
= sky2_netpoll
;
3957 sky2
= netdev_priv(dev
);
3960 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3962 /* Auto speed and flow control */
3963 sky2
->autoneg
= AUTONEG_ENABLE
;
3964 sky2
->flow_mode
= FC_BOTH
;
3968 sky2
->advertising
= sky2_supported_modes(hw
);
3972 spin_lock_init(&sky2
->phy_lock
);
3973 sky2
->tx_pending
= TX_DEF_PENDING
;
3974 sky2
->rx_pending
= RX_DEF_PENDING
;
3976 hw
->dev
[port
] = dev
;
3980 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
3982 dev
->features
|= NETIF_F_HIGHDMA
;
3984 #ifdef SKY2_VLAN_TAG_USED
3985 /* The workaround for FE+ status conflicts with VLAN tag detection. */
3986 if (!(sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
3987 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)) {
3988 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3989 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3993 /* read the mac address */
3994 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3995 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4000 static void __devinit
sky2_show_addr(struct net_device
*dev
)
4002 const struct sky2_port
*sky2
= netdev_priv(dev
);
4004 if (netif_msg_probe(sky2
))
4005 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
4007 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
4008 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
4011 /* Handle software interrupt used during MSI test */
4012 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
4014 struct sky2_hw
*hw
= dev_id
;
4015 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
4020 if (status
& Y2_IS_IRQ_SW
) {
4021 hw
->flags
|= SKY2_HW_USE_MSI
;
4022 wake_up(&hw
->msi_wait
);
4023 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4025 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
4030 /* Test interrupt path by forcing a a software IRQ */
4031 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
4033 struct pci_dev
*pdev
= hw
->pdev
;
4036 init_waitqueue_head (&hw
->msi_wait
);
4038 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
4040 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
4042 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4046 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
4047 sky2_read8(hw
, B0_CTST
);
4049 wait_event_timeout(hw
->msi_wait
, (hw
->flags
& SKY2_HW_USE_MSI
), HZ
/10);
4051 if (!(hw
->flags
& SKY2_HW_USE_MSI
)) {
4052 /* MSI test failed, go back to INTx mode */
4053 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
4054 "switching to INTx mode.\n");
4057 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4060 sky2_write32(hw
, B0_IMSK
, 0);
4061 sky2_read32(hw
, B0_IMSK
);
4063 free_irq(pdev
->irq
, hw
);
4068 static int __devinit
pci_wake_enabled(struct pci_dev
*dev
)
4070 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
4075 if (pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
))
4077 return value
& PCI_PM_CTRL_PME_ENABLE
;
4080 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
4081 const struct pci_device_id
*ent
)
4083 struct net_device
*dev
;
4085 int err
, using_dac
= 0, wol_default
;
4087 err
= pci_enable_device(pdev
);
4089 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
4093 err
= pci_request_regions(pdev
, DRV_NAME
);
4095 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
4096 goto err_out_disable
;
4099 pci_set_master(pdev
);
4101 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
4102 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
4104 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
4106 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
4107 "for consistent allocations\n");
4108 goto err_out_free_regions
;
4111 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
4113 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
4114 goto err_out_free_regions
;
4118 wol_default
= pci_wake_enabled(pdev
) ? WAKE_MAGIC
: 0;
4121 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
4123 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
4124 goto err_out_free_regions
;
4129 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
4131 dev_err(&pdev
->dev
, "cannot map device registers\n");
4132 goto err_out_free_hw
;
4136 /* The sk98lin vendor driver uses hardware byte swapping but
4137 * this driver uses software swapping.
4141 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
4142 reg
&= ~PCI_REV_DESC
;
4143 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
4147 /* ring for status responses */
4148 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
4151 goto err_out_iounmap
;
4153 err
= sky2_init(hw
);
4155 goto err_out_iounmap
;
4157 dev_info(&pdev
->dev
, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4158 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
4159 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
4160 hw
->chip_id
, hw
->chip_rev
);
4164 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
4167 goto err_out_free_pci
;
4170 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
4171 err
= sky2_test_msi(hw
);
4172 if (err
== -EOPNOTSUPP
)
4173 pci_disable_msi(pdev
);
4175 goto err_out_free_netdev
;
4178 err
= register_netdev(dev
);
4180 dev_err(&pdev
->dev
, "cannot register net device\n");
4181 goto err_out_free_netdev
;
4184 err
= request_irq(pdev
->irq
, sky2_intr
,
4185 (hw
->flags
& SKY2_HW_USE_MSI
) ? 0 : IRQF_SHARED
,
4188 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4189 goto err_out_unregister
;
4191 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4193 sky2_show_addr(dev
);
4195 if (hw
->ports
> 1) {
4196 struct net_device
*dev1
;
4198 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
4200 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
4201 else if ((err
= register_netdev(dev1
))) {
4202 dev_warn(&pdev
->dev
,
4203 "register of second port failed (%d)\n", err
);
4207 sky2_show_addr(dev1
);
4210 setup_timer(&hw
->watchdog_timer
, sky2_watchdog
, (unsigned long) hw
);
4211 INIT_WORK(&hw
->restart_work
, sky2_restart
);
4213 pci_set_drvdata(pdev
, hw
);
4218 if (hw
->flags
& SKY2_HW_USE_MSI
)
4219 pci_disable_msi(pdev
);
4220 unregister_netdev(dev
);
4221 err_out_free_netdev
:
4224 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4225 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4230 err_out_free_regions
:
4231 pci_release_regions(pdev
);
4233 pci_disable_device(pdev
);
4235 pci_set_drvdata(pdev
, NULL
);
4239 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
4241 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4242 struct net_device
*dev0
, *dev1
;
4247 del_timer_sync(&hw
->watchdog_timer
);
4249 flush_scheduled_work();
4251 sky2_write32(hw
, B0_IMSK
, 0);
4252 synchronize_irq(hw
->pdev
->irq
);
4257 unregister_netdev(dev1
);
4258 unregister_netdev(dev0
);
4262 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
4263 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4264 sky2_read8(hw
, B0_CTST
);
4266 free_irq(pdev
->irq
, hw
);
4267 if (hw
->flags
& SKY2_HW_USE_MSI
)
4268 pci_disable_msi(pdev
);
4269 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4270 pci_release_regions(pdev
);
4271 pci_disable_device(pdev
);
4279 pci_set_drvdata(pdev
, NULL
);
4283 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4285 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4291 netif_poll_disable(hw
->dev
[0]);
4293 for (i
= 0; i
< hw
->ports
; i
++) {
4294 struct net_device
*dev
= hw
->dev
[i
];
4295 struct sky2_port
*sky2
= netdev_priv(dev
);
4297 if (netif_running(dev
))
4301 sky2_wol_init(sky2
);
4306 sky2_write32(hw
, B0_IMSK
, 0);
4309 pci_save_state(pdev
);
4310 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
4311 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4316 static int sky2_resume(struct pci_dev
*pdev
)
4318 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4324 err
= pci_set_power_state(pdev
, PCI_D0
);
4328 err
= pci_restore_state(pdev
);
4332 pci_enable_wake(pdev
, PCI_D0
, 0);
4334 /* Re-enable all clocks */
4335 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
4336 hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
4337 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
4338 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
4342 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4344 for (i
= 0; i
< hw
->ports
; i
++) {
4345 struct net_device
*dev
= hw
->dev
[i
];
4346 if (netif_running(dev
)) {
4349 printk(KERN_ERR PFX
"%s: could not up: %d\n",
4355 sky2_set_multicast(dev
);
4359 netif_poll_enable(hw
->dev
[0]);
4363 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
4364 pci_disable_device(pdev
);
4369 static void sky2_shutdown(struct pci_dev
*pdev
)
4371 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4377 netif_poll_disable(hw
->dev
[0]);
4379 for (i
= 0; i
< hw
->ports
; i
++) {
4380 struct net_device
*dev
= hw
->dev
[i
];
4381 struct sky2_port
*sky2
= netdev_priv(dev
);
4385 sky2_wol_init(sky2
);
4392 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
4393 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
4395 pci_disable_device(pdev
);
4396 pci_set_power_state(pdev
, PCI_D3hot
);
4400 static struct pci_driver sky2_driver
= {
4402 .id_table
= sky2_id_table
,
4403 .probe
= sky2_probe
,
4404 .remove
= __devexit_p(sky2_remove
),
4406 .suspend
= sky2_suspend
,
4407 .resume
= sky2_resume
,
4409 .shutdown
= sky2_shutdown
,
4412 static int __init
sky2_init_module(void)
4415 return pci_register_driver(&sky2_driver
);
4418 static void __exit
sky2_cleanup_module(void)
4420 pci_unregister_driver(&sky2_driver
);
4421 sky2_debug_cleanup();
4424 module_init(sky2_init_module
);
4425 module_exit(sky2_cleanup_module
);
4427 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4428 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4429 MODULE_LICENSE("GPL");
4430 MODULE_VERSION(DRV_VERSION
);