drivers/ieee1394/pcilynx.h

   1 #ifndef __PCILYNX_H__
   2 #define __PCILYNX_H__
   3
   4
   5 #define PCILYNX_DRIVER_NAME      "pcilynx"
   6 #define PCILYNX_MAJOR            177
   7
   8 #define PCILYNX_MINOR_AUX_START  0
   9 #define PCILYNX_MINOR_ROM_START  16
  10 #define PCILYNX_MINOR_RAM_START  32
  11
  12 #define PCILYNX_MAX_REGISTER     0xfff
  13 #define PCILYNX_MAX_MEMORY       0xffff
  14
  15 #define PCI_DEVICE_ID_TI_PCILYNX 0x8000
  16 #define MAX_PCILYNX_CARDS        4
  17 #define LOCALRAM_SIZE            4096
  18
  19 #define NUM_ISORCV_PCL           4
  20 #define MAX_ISORCV_SIZE          2048
  21 #define ISORCV_PER_PAGE          (PAGE_SIZE / MAX_ISORCV_SIZE)
  22 #define ISORCV_PAGES             (NUM_ISORCV_PCL / ISORCV_PER_PAGE)
  23
  24 #define CHANNEL_LOCALBUS         0
  25 #define CHANNEL_ASYNC_RCV        1
  26 #define CHANNEL_ISO_RCV          2
  27 #define CHANNEL_ASYNC_SEND       3
  28 #define CHANNEL_ISO_SEND         4
  29
  30 #define PCILYNX_CONFIG_ROM_LENGTH   1024
  31
  32 typedef int pcl_t;
  33
  34 struct ti_lynx {
  35         int id; /* sequential card number */
  36
  37         spinlock_t lock;
  38
  39         struct pci_dev *dev;
  40
  41         struct {
  42                 unsigned reg_1394a:1;
  43                 u32 vendor;
  44                 u32 product;
  45         } phyic;
  46
  47         enum { clear, have_intr, have_aux_buf, have_pcl_mem,
  48                have_1394_buffers, have_iomappings, is_host } state;
  49
  50         /* remapped memory spaces */
  51         void __iomem *registers;
  52         void __iomem *local_rom;
  53         void __iomem *local_ram;
  54         void __iomem *aux_port;
  55         quadlet_t bus_info_block[5];
  56
  57         /*
  58          * use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for
  59          * LOCALRAM_SIZE * 8 PCLs (each sized 128 bytes);
  60          * the following is an allocation bitmap
  61          */
  62         u8 pcl_bmap[LOCALRAM_SIZE / 1024];
  63
  64         /* point to PCLs memory area if needed */
  65         void *pcl_mem;
  66         dma_addr_t pcl_mem_dma;
  67
  68         /* PCLs for local mem / aux transfers */
  69         pcl_t dmem_pcl;
  70
  71         /* IEEE-1394 part follows */
  72         struct hpsb_host *host;
  73
  74         int phyid, isroot;
  75         int selfid_size;
  76         int phy_reg0;
  77
  78         spinlock_t phy_reg_lock;
  79
  80         pcl_t rcv_pcl_start, rcv_pcl;
  81         void *rcv_page;
  82         dma_addr_t rcv_page_dma;
  83         int rcv_active;
  84
  85         struct lynx_send_data {
  86                 pcl_t pcl_start, pcl;
  87                 struct list_head queue;
  88                 struct list_head pcl_queue; /* this queue contains at most one packet */
  89                 spinlock_t queue_lock;
  90                 dma_addr_t header_dma, data_dma;
  91                 int channel;
  92         } async, iso_send;
  93
  94         struct {
  95                 pcl_t pcl[NUM_ISORCV_PCL];
  96                 u32 stat[NUM_ISORCV_PCL];
  97                 void *page[ISORCV_PAGES];
  98                 dma_addr_t page_dma[ISORCV_PAGES];
  99                 pcl_t pcl_start;
 100                 int chan_count;
 101                 int next, last, used, running;
 102                 struct tasklet_struct tq;
 103                 spinlock_t lock;
 104         } iso_rcv;
 105
 106         u32 i2c_driven_state; /* the state we currently drive the Serial EEPROM Control register */
 107 };
 108
 109 /* the per-file data structure for mem space access */
 110 struct memdata {
 111         struct ti_lynx *lynx;
 112         int cid;
 113         atomic_t aux_intr_last_seen;
 114         /* enum values are the same as LBUS_ADDR_SEL_* values below */
 115         enum { rom = 0x10000, aux = 0x20000, ram = 0 } type;
 116 };
 117
 118
 119
 120 /*
 121  * Register read and write helper functions.
 122  */
 123 static inline void reg_write(const struct ti_lynx *lynx, int offset, u32 data)
 124 {
 125         writel(data, lynx->registers + offset);
 126 }
 127
 128 static inline u32 reg_read(const struct ti_lynx *lynx, int offset)
 129 {
 130         return readl(lynx->registers + offset);
 131 }
 132
 133 static inline void reg_set_bits(const struct ti_lynx *lynx, int offset,
 134                                 u32 mask)
 135 {
 136         reg_write(lynx, offset, (reg_read(lynx, offset) | mask));
 137 }
 138
 139 static inline void reg_clear_bits(const struct ti_lynx *lynx, int offset,
 140                                   u32 mask)
 141 {
 142         reg_write(lynx, offset, (reg_read(lynx, offset) & ~mask));
 143 }
 144
 145
 146
 147 /* chip register definitions follow */
 148
 149 #define PCI_LATENCY_CACHELINE             0x0c
 150
 151 #define MISC_CONTROL                      0x40
 152 #define MISC_CONTROL_SWRESET              (1<<0)
 153
 154 #define SERIAL_EEPROM_CONTROL             0x44
 155
 156 #define PCI_INT_STATUS                    0x48
 157 #define PCI_INT_ENABLE                    0x4c
 158 /* status and enable have identical bit numbers */
 159 #define PCI_INT_INT_PEND                  (1<<31)
 160 #define PCI_INT_FORCED_INT                (1<<30)
 161 #define PCI_INT_SLV_ADR_PERR              (1<<28)
 162 #define PCI_INT_SLV_DAT_PERR              (1<<27)
 163 #define PCI_INT_MST_DAT_PERR              (1<<26)
 164 #define PCI_INT_MST_DEV_TIMEOUT           (1<<25)
 165 #define PCI_INT_INTERNAL_SLV_TIMEOUT      (1<<23)
 166 #define PCI_INT_AUX_TIMEOUT               (1<<18)
 167 #define PCI_INT_AUX_INT                   (1<<17)
 168 #define PCI_INT_1394                      (1<<16)
 169 #define PCI_INT_DMA4_PCL                  (1<<9)
 170 #define PCI_INT_DMA4_HLT                  (1<<8)
 171 #define PCI_INT_DMA3_PCL                  (1<<7)
 172 #define PCI_INT_DMA3_HLT                  (1<<6)
 173 #define PCI_INT_DMA2_PCL                  (1<<5)
 174 #define PCI_INT_DMA2_HLT                  (1<<4)
 175 #define PCI_INT_DMA1_PCL                  (1<<3)
 176 #define PCI_INT_DMA1_HLT                  (1<<2)
 177 #define PCI_INT_DMA0_PCL                  (1<<1)
 178 #define PCI_INT_DMA0_HLT                  (1<<0)
 179 /* all DMA interrupts combined: */
 180 #define PCI_INT_DMA_ALL                   0x3ff
 181
 182 #define PCI_INT_DMA_HLT(chan)             (1 << (chan * 2))
 183 #define PCI_INT_DMA_PCL(chan)             (1 << (chan * 2 + 1))
 184
 185 #define LBUS_ADDR                         0xb4
 186 #define LBUS_ADDR_SEL_RAM                 (0x0<<16)
 187 #define LBUS_ADDR_SEL_ROM                 (0x1<<16)
 188 #define LBUS_ADDR_SEL_AUX                 (0x2<<16)
 189 #define LBUS_ADDR_SEL_ZV                  (0x3<<16)
 190
 191 #define GPIO_CTRL_A                       0xb8
 192 #define GPIO_CTRL_B                       0xbc
 193 #define GPIO_DATA_BASE                    0xc0
 194
 195 #define DMA_BREG(base, chan)              (base + chan * 0x20)
 196 #define DMA_SREG(base, chan)              (base + chan * 0x10)
 197
 198 #define DMA0_PREV_PCL                     0x100
 199 #define DMA1_PREV_PCL                     0x120
 200 #define DMA2_PREV_PCL                     0x140
 201 #define DMA3_PREV_PCL                     0x160
 202 #define DMA4_PREV_PCL                     0x180
 203 #define DMA_PREV_PCL(chan)                (DMA_BREG(DMA0_PREV_PCL, chan))
 204
 205 #define DMA0_CURRENT_PCL                  0x104
 206 #define DMA1_CURRENT_PCL                  0x124
 207 #define DMA2_CURRENT_PCL                  0x144
 208 #define DMA3_CURRENT_PCL                  0x164
 209 #define DMA4_CURRENT_PCL                  0x184
 210 #define DMA_CURRENT_PCL(chan)             (DMA_BREG(DMA0_CURRENT_PCL, chan))
 211
 212 #define DMA0_CHAN_STAT                    0x10c
 213 #define DMA1_CHAN_STAT                    0x12c
 214 #define DMA2_CHAN_STAT                    0x14c
 215 #define DMA3_CHAN_STAT                    0x16c
 216 #define DMA4_CHAN_STAT                    0x18c
 217 #define DMA_CHAN_STAT(chan)               (DMA_BREG(DMA0_CHAN_STAT, chan))
 218 /* CHAN_STATUS registers share bits */
 219 #define DMA_CHAN_STAT_SELFID              (1<<31)
 220 #define DMA_CHAN_STAT_ISOPKT              (1<<30)
 221 #define DMA_CHAN_STAT_PCIERR              (1<<29)
 222 #define DMA_CHAN_STAT_PKTERR              (1<<28)
 223 #define DMA_CHAN_STAT_PKTCMPL             (1<<27)
 224 #define DMA_CHAN_STAT_SPECIALACK          (1<<14)
 225
 226
 227 #define DMA0_CHAN_CTRL                    0x110
 228 #define DMA1_CHAN_CTRL                    0x130
 229 #define DMA2_CHAN_CTRL                    0x150
 230 #define DMA3_CHAN_CTRL                    0x170
 231 #define DMA4_CHAN_CTRL                    0x190
 232 #define DMA_CHAN_CTRL(chan)               (DMA_BREG(DMA0_CHAN_CTRL, chan))
 233 /* CHAN_CTRL registers share bits */
 234 #define DMA_CHAN_CTRL_ENABLE              (1<<31)
 235 #define DMA_CHAN_CTRL_BUSY                (1<<30)
 236 #define DMA_CHAN_CTRL_LINK                (1<<29)
 237
 238 #define DMA0_READY                        0x114
 239 #define DMA1_READY                        0x134
 240 #define DMA2_READY                        0x154
 241 #define DMA3_READY                        0x174
 242 #define DMA4_READY                        0x194
 243 #define DMA_READY(chan)                   (DMA_BREG(DMA0_READY, chan))
 244
 245 #define DMA_GLOBAL_REGISTER               0x908
 246
 247 #define FIFO_SIZES                        0xa00
 248
 249 #define FIFO_CONTROL                      0xa10
 250 #define FIFO_CONTROL_GRF_FLUSH            (1<<4)
 251 #define FIFO_CONTROL_ITF_FLUSH            (1<<3)
 252 #define FIFO_CONTROL_ATF_FLUSH            (1<<2)
 253
 254 #define FIFO_XMIT_THRESHOLD               0xa14
 255
 256 #define DMA0_WORD0_CMP_VALUE              0xb00
 257 #define DMA1_WORD0_CMP_VALUE              0xb10
 258 #define DMA2_WORD0_CMP_VALUE              0xb20
 259 #define DMA3_WORD0_CMP_VALUE              0xb30
 260 #define DMA4_WORD0_CMP_VALUE              0xb40
 261 #define DMA_WORD0_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan))
 262
 263 #define DMA0_WORD0_CMP_ENABLE             0xb04
 264 #define DMA1_WORD0_CMP_ENABLE             0xb14
 265 #define DMA2_WORD0_CMP_ENABLE             0xb24
 266 #define DMA3_WORD0_CMP_ENABLE             0xb34
 267 #define DMA4_WORD0_CMP_ENABLE             0xb44
 268 #define DMA_WORD0_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD0_CMP_ENABLE,chan))
 269
 270 #define DMA0_WORD1_CMP_VALUE              0xb08
 271 #define DMA1_WORD1_CMP_VALUE              0xb18
 272 #define DMA2_WORD1_CMP_VALUE              0xb28
 273 #define DMA3_WORD1_CMP_VALUE              0xb38
 274 #define DMA4_WORD1_CMP_VALUE              0xb48
 275 #define DMA_WORD1_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan))
 276
 277 #define DMA0_WORD1_CMP_ENABLE             0xb0c
 278 #define DMA1_WORD1_CMP_ENABLE             0xb1c
 279 #define DMA2_WORD1_CMP_ENABLE             0xb2c
 280 #define DMA3_WORD1_CMP_ENABLE             0xb3c
 281 #define DMA4_WORD1_CMP_ENABLE             0xb4c
 282 #define DMA_WORD1_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD1_CMP_ENABLE,chan))
 283 /* word 1 compare enable flags */
 284 #define DMA_WORD1_CMP_MATCH_OTHERBUS      (1<<15)
 285 #define DMA_WORD1_CMP_MATCH_BROADCAST     (1<<14)
 286 #define DMA_WORD1_CMP_MATCH_BUS_BCAST     (1<<13)
 287 #define DMA_WORD1_CMP_MATCH_LOCAL_NODE    (1<<12)
 288 #define DMA_WORD1_CMP_MATCH_EXACT         (1<<11)
 289 #define DMA_WORD1_CMP_ENABLE_SELF_ID      (1<<10)
 290 #define DMA_WORD1_CMP_ENABLE_MASTER       (1<<8)
 291
 292 #define LINK_ID                           0xf00
 293 #define LINK_ID_BUS(id)                   (id<<22)
 294 #define LINK_ID_NODE(id)                  (id<<16)
 295
 296 #define LINK_CONTROL                      0xf04
 297 #define LINK_CONTROL_BUSY                 (1<<29)
 298 #define LINK_CONTROL_TX_ISO_EN            (1<<26)
 299 #define LINK_CONTROL_RX_ISO_EN            (1<<25)
 300 #define LINK_CONTROL_TX_ASYNC_EN          (1<<24)
 301 #define LINK_CONTROL_RX_ASYNC_EN          (1<<23)
 302 #define LINK_CONTROL_RESET_TX             (1<<21)
 303 #define LINK_CONTROL_RESET_RX             (1<<20)
 304 #define LINK_CONTROL_CYCMASTER            (1<<11)
 305 #define LINK_CONTROL_CYCSOURCE            (1<<10)
 306 #define LINK_CONTROL_CYCTIMEREN           (1<<9)
 307 #define LINK_CONTROL_RCV_CMP_VALID        (1<<7)
 308 #define LINK_CONTROL_SNOOP_ENABLE         (1<<6)
 309
 310 #define CYCLE_TIMER                       0xf08
 311
 312 #define LINK_PHY                          0xf0c
 313 #define LINK_PHY_READ                     (1<<31)
 314 #define LINK_PHY_WRITE                    (1<<30)
 315 #define LINK_PHY_ADDR(addr)               (addr<<24)
 316 #define LINK_PHY_WDATA(data)              (data<<16)
 317 #define LINK_PHY_RADDR(addr)              (addr<<8)
 318
 319
 320 #define LINK_INT_STATUS                   0xf14
 321 #define LINK_INT_ENABLE                   0xf18
 322 /* status and enable have identical bit numbers */
 323 #define LINK_INT_LINK_INT                 (1<<31)
 324 #define LINK_INT_PHY_TIMEOUT              (1<<30)
 325 #define LINK_INT_PHY_REG_RCVD             (1<<29)
 326 #define LINK_INT_PHY_BUSRESET             (1<<28)
 327 #define LINK_INT_TX_RDY                   (1<<26)
 328 #define LINK_INT_RX_DATA_RDY              (1<<25)
 329 #define LINK_INT_ISO_STUCK                (1<<20)
 330 #define LINK_INT_ASYNC_STUCK              (1<<19)
 331 #define LINK_INT_SENT_REJECT              (1<<17)
 332 #define LINK_INT_HDR_ERR                  (1<<16)
 333 #define LINK_INT_TX_INVALID_TC            (1<<15)
 334 #define LINK_INT_CYC_SECOND               (1<<11)
 335 #define LINK_INT_CYC_START                (1<<10)
 336 #define LINK_INT_CYC_DONE                 (1<<9)
 337 #define LINK_INT_CYC_PENDING              (1<<8)
 338 #define LINK_INT_CYC_LOST                 (1<<7)
 339 #define LINK_INT_CYC_ARB_FAILED           (1<<6)
 340 #define LINK_INT_GRF_OVERFLOW             (1<<5)
 341 #define LINK_INT_ITF_UNDERFLOW            (1<<4)
 342 #define LINK_INT_ATF_UNDERFLOW            (1<<3)
 343 #define LINK_INT_ISOARB_FAILED            (1<<0)
 344
 345 /* PHY specifics */
 346 #define PHY_VENDORID_TI                 0x800028
 347 #define PHY_PRODUCTID_TSB41LV03         0x000000
 348
 349
 350 /* this is the physical layout of a PCL, its size is 128 bytes */
 351 struct ti_pcl {
 352         u32 next;
 353         u32 async_error_next;
 354         u32 user_data;
 355         u32 pcl_status;
 356         u32 remaining_transfer_count;
 357         u32 next_data_buffer;
 358         struct {
 359                 u32 control;
 360                 u32 pointer;
 361         } buffer[13] __attribute__ ((packed));
 362 } __attribute__ ((packed));
 363
 364 #include <linux/stddef.h>
 365 #define pcloffs(MEMBER) (offsetof(struct ti_pcl, MEMBER))
 366
 367
 368 static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 369                            const struct ti_pcl *pcl)
 370 {
 371         memcpy_le32((u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
 372                     (u32 *)pcl, sizeof(struct ti_pcl));
 373 }
 374
 375 static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 376                            struct ti_pcl *pcl)
 377 {
 378         memcpy_le32((u32 *)pcl,
 379                     (u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
 380                     sizeof(struct ti_pcl));
 381 }
 382
 383 static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
 384 {
 385         return lynx->pcl_mem_dma + pclid * sizeof(struct ti_pcl);
 386 }
 387
 388
 389 #if defined (__BIG_ENDIAN)
 390 typedef struct ti_pcl pcltmp_t;
 391
 392 static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 393                                       pcltmp_t *tmp)
 394 {
 395         get_pcl(lynx, pclid, tmp);
 396         return tmp;
 397 }
 398
 399 static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 400                               pcltmp_t *tmp)
 401 {
 402         put_pcl(lynx, pclid, tmp);
 403 }
 404
 405 #else
 406 typedef int pcltmp_t; /* just a dummy */
 407
 408 static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 409                                       pcltmp_t *tmp)
 410 {
 411         return lynx->pcl_mem + pclid * sizeof(struct ti_pcl);
 412 }
 413
 414 static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
 415                               pcltmp_t *tmp)
 416 {
 417 }
 418 #endif
 419
 420
 421 static inline void run_sub_pcl(const struct ti_lynx *lynx, pcl_t pclid, int idx,
 422                                int dmachan)
 423 {
 424         reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20,
 425                   pcl_bus(lynx, pclid) + idx * 4);
 426         reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20,
 427                   DMA_CHAN_CTRL_ENABLE | DMA_CHAN_CTRL_LINK);
 428 }
 429
 430 static inline void run_pcl(const struct ti_lynx *lynx, pcl_t pclid, int dmachan)
 431 {
 432         run_sub_pcl(lynx, pclid, 0, dmachan);
 433 }
 434
 435 #define PCL_NEXT_INVALID (1<<0)
 436
 437 /* transfer commands */
 438 #define PCL_CMD_RCV            (0x1<<24)
 439 #define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
 440 #define PCL_CMD_XMT            (0x2<<24)
 441 #define PCL_CMD_UNFXMT         (0xc<<24)
 442 #define PCL_CMD_PCI_TO_LBUS    (0x8<<24)
 443 #define PCL_CMD_LBUS_TO_PCI    (0x9<<24)
 444
 445 /* aux commands */
 446 #define PCL_CMD_NOP            (0x0<<24)
 447 #define PCL_CMD_LOAD           (0x3<<24)
 448 #define PCL_CMD_STOREQ         (0x4<<24)
 449 #define PCL_CMD_STORED         (0xb<<24)
 450 #define PCL_CMD_STORE0         (0x5<<24)
 451 #define PCL_CMD_STORE1         (0x6<<24)
 452 #define PCL_CMD_COMPARE        (0xe<<24)
 453 #define PCL_CMD_SWAP_COMPARE   (0xf<<24)
 454 #define PCL_CMD_ADD            (0xd<<24)
 455 #define PCL_CMD_BRANCH         (0x7<<24)
 456
 457 /* BRANCH condition codes */
 458 #define PCL_COND_DMARDY_SET    (0x1<<20)
 459 #define PCL_COND_DMARDY_CLEAR  (0x2<<20)
 460
 461 #define PCL_GEN_INTR           (1<<19)
 462 #define PCL_LAST_BUFF          (1<<18)
 463 #define PCL_LAST_CMD           (PCL_LAST_BUFF)
 464 #define PCL_WAITSTAT           (1<<17)
 465 #define PCL_BIGENDIAN          (1<<16)
 466 #define PCL_ISOMODE            (1<<12)
 467
 468 #endif