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[SPARC64]: Always register a PROM based early console.
[linux-2.6/kmemtrace.git] / arch / sparc64 / mm / init.c
blob9e6bca266d88338df73baf4dd1079a5c17672b69
1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27
28 #include <asm/head.h>
29 #include <asm/system.h>
30 #include <asm/page.h>
31 #include <asm/pgalloc.h>
32 #include <asm/pgtable.h>
33 #include <asm/oplib.h>
34 #include <asm/iommu.h>
35 #include <asm/io.h>
36 #include <asm/uaccess.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
39 #include <asm/dma.h>
40 #include <asm/starfire.h>
41 #include <asm/tlb.h>
42 #include <asm/spitfire.h>
43 #include <asm/sections.h>
44 #include <asm/tsb.h>
45 #include <asm/hypervisor.h>
46 #include <asm/prom.h>
47 #include <asm/sstate.h>
48 #include <asm/mdesc.h>
49
50 #define MAX_PHYS_ADDRESS (1UL << 42UL)
51 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
52 #define KPTE_BITMAP_BYTES \
53 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
54
55 unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57 /* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 */
61 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
63 #ifndef CONFIG_DEBUG_PAGEALLOC
64 /* A special kernel TSB for 4MB and 256MB linear mappings.
65 * Space is allocated for this right after the trap table
66 * in arch/sparc64/kernel/head.S
67 */
68 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
69 #endif
70
71 #define MAX_BANKS 32
72
73 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
74 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
75 static int pavail_ents __initdata;
76 static int pavail_rescan_ents __initdata;
77
78 static int cmp_p64(const void *a, const void *b)
79 {
80 const struct linux_prom64_registers *x = a, *y = b;
81
82 if (x->phys_addr > y->phys_addr)
83 return 1;
84 if (x->phys_addr < y->phys_addr)
85 return -1;
86 return 0;
87 }
88
89 static void __init read_obp_memory(const char *property,
90 struct linux_prom64_registers *regs,
91 int *num_ents)
92 {
93 int node = prom_finddevice("/memory");
94 int prop_size = prom_getproplen(node, property);
95 int ents, ret, i;
96
97 ents = prop_size / sizeof(struct linux_prom64_registers);
98 if (ents > MAX_BANKS) {
99 prom_printf("The machine has more %s property entries than "
100 "this kernel can support (%d).\n",
101 property, MAX_BANKS);
102 prom_halt();
103 }
104
105 ret = prom_getproperty(node, property, (char *) regs, prop_size);
106 if (ret == -1) {
107 prom_printf("Couldn't get %s property from /memory.\n");
108 prom_halt();
109 }
110
111 /* Sanitize what we got from the firmware, by page aligning
112 * everything.
113 */
114 for (i = 0; i < ents; i++) {
115 unsigned long base, size;
116
117 base = regs[i].phys_addr;
118 size = regs[i].reg_size;
119
120 size &= PAGE_MASK;
121 if (base & ~PAGE_MASK) {
122 unsigned long new_base = PAGE_ALIGN(base);
123
124 size -= new_base - base;
125 if ((long) size < 0L)
126 size = 0UL;
127 base = new_base;
128 }
129 if (size == 0UL) {
130 /* If it is empty, simply get rid of it.
131 * This simplifies the logic of the other
132 * functions that process these arrays.
133 */
134 memmove(&regs[i], &regs[i + 1],
135 (ents - i - 1) * sizeof(regs[0]));
136 i--;
137 ents--;
138 continue;
139 }
140 regs[i].phys_addr = base;
141 regs[i].reg_size = size;
142 }
143
144 *num_ents = ents;
145
146 sort(regs, ents, sizeof(struct linux_prom64_registers),
147 cmp_p64, NULL);
148 }
149
150 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
151
152 /* Kernel physical address base and size in bytes. */
153 unsigned long kern_base __read_mostly;
154 unsigned long kern_size __read_mostly;
155
156 /* Initial ramdisk setup */
157 extern unsigned long sparc_ramdisk_image64;
158 extern unsigned int sparc_ramdisk_image;
159 extern unsigned int sparc_ramdisk_size;
160
161 struct page *mem_map_zero __read_mostly;
162
163 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
164
165 unsigned long sparc64_kern_pri_context __read_mostly;
166 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
167 unsigned long sparc64_kern_sec_context __read_mostly;
168
169 int bigkernel = 0;
170
171 #ifdef CONFIG_DEBUG_DCFLUSH
172 atomic_t dcpage_flushes = ATOMIC_INIT(0);
173 #ifdef CONFIG_SMP
174 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
175 #endif
176 #endif
177
178 inline void flush_dcache_page_impl(struct page *page)
179 {
180 BUG_ON(tlb_type == hypervisor);
181 #ifdef CONFIG_DEBUG_DCFLUSH
182 atomic_inc(&dcpage_flushes);
183 #endif
184
185 #ifdef DCACHE_ALIASING_POSSIBLE
186 __flush_dcache_page(page_address(page),
187 ((tlb_type == spitfire) &&
188 page_mapping(page) != NULL));
189 #else
190 if (page_mapping(page) != NULL &&
191 tlb_type == spitfire)
192 __flush_icache_page(__pa(page_address(page)));
193 #endif
194 }
195
196 #define PG_dcache_dirty PG_arch_1
197 #define PG_dcache_cpu_shift 32UL
198 #define PG_dcache_cpu_mask \
199 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
200
201 #define dcache_dirty_cpu(page) \
202 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
203
204 static inline void set_dcache_dirty(struct page *page, int this_cpu)
205 {
206 unsigned long mask = this_cpu;
207 unsigned long non_cpu_bits;
208
209 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
210 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
211
212 __asm__ __volatile__("1:\n\t"
213 "ldx [%2], %%g7\n\t"
214 "and %%g7, %1, %%g1\n\t"
215 "or %%g1, %0, %%g1\n\t"
216 "casx [%2], %%g7, %%g1\n\t"
217 "cmp %%g7, %%g1\n\t"
218 "membar #StoreLoad | #StoreStore\n\t"
219 "bne,pn %%xcc, 1b\n\t"
220 " nop"
221 : /* no outputs */
222 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
223 : "g1", "g7");
224 }
225
226 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
227 {
228 unsigned long mask = (1UL << PG_dcache_dirty);
229
230 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
231 "1:\n\t"
232 "ldx [%2], %%g7\n\t"
233 "srlx %%g7, %4, %%g1\n\t"
234 "and %%g1, %3, %%g1\n\t"
235 "cmp %%g1, %0\n\t"
236 "bne,pn %%icc, 2f\n\t"
237 " andn %%g7, %1, %%g1\n\t"
238 "casx [%2], %%g7, %%g1\n\t"
239 "cmp %%g7, %%g1\n\t"
240 "membar #StoreLoad | #StoreStore\n\t"
241 "bne,pn %%xcc, 1b\n\t"
242 " nop\n"
243 "2:"
244 : /* no outputs */
245 : "r" (cpu), "r" (mask), "r" (&page->flags),
246 "i" (PG_dcache_cpu_mask),
247 "i" (PG_dcache_cpu_shift)
248 : "g1", "g7");
249 }
250
251 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
252 {
253 unsigned long tsb_addr = (unsigned long) ent;
254
255 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
256 tsb_addr = __pa(tsb_addr);
257
258 __tsb_insert(tsb_addr, tag, pte);
259 }
260
261 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
262 unsigned long _PAGE_SZBITS __read_mostly;
263
264 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
265 {
266 struct mm_struct *mm;
267 struct tsb *tsb;
268 unsigned long tag, flags;
269 unsigned long tsb_index, tsb_hash_shift;
270
271 if (tlb_type != hypervisor) {
272 unsigned long pfn = pte_pfn(pte);
273 unsigned long pg_flags;
274 struct page *page;
275
276 if (pfn_valid(pfn) &&
277 (page = pfn_to_page(pfn), page_mapping(page)) &&
278 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
279 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
280 PG_dcache_cpu_mask);
281 int this_cpu = get_cpu();
282
283 /* This is just to optimize away some function calls
284 * in the SMP case.
285 */
286 if (cpu == this_cpu)
287 flush_dcache_page_impl(page);
288 else
289 smp_flush_dcache_page_impl(page, cpu);
290
291 clear_dcache_dirty_cpu(page, cpu);
292
293 put_cpu();
294 }
295 }
296
297 mm = vma->vm_mm;
298
299 tsb_index = MM_TSB_BASE;
300 tsb_hash_shift = PAGE_SHIFT;
301
302 spin_lock_irqsave(&mm->context.lock, flags);
303
304 #ifdef CONFIG_HUGETLB_PAGE
305 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
306 if ((tlb_type == hypervisor &&
307 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
308 (tlb_type != hypervisor &&
309 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
310 tsb_index = MM_TSB_HUGE;
311 tsb_hash_shift = HPAGE_SHIFT;
312 }
313 }
314 #endif
315
316 tsb = mm->context.tsb_block[tsb_index].tsb;
317 tsb += ((address >> tsb_hash_shift) &
318 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
319 tag = (address >> 22UL);
320 tsb_insert(tsb, tag, pte_val(pte));
321
322 spin_unlock_irqrestore(&mm->context.lock, flags);
323 }
324
325 void flush_dcache_page(struct page *page)
326 {
327 struct address_space *mapping;
328 int this_cpu;
329
330 if (tlb_type == hypervisor)
331 return;
332
333 /* Do not bother with the expensive D-cache flush if it
334 * is merely the zero page. The 'bigcore' testcase in GDB
335 * causes this case to run millions of times.
336 */
337 if (page == ZERO_PAGE(0))
338 return;
339
340 this_cpu = get_cpu();
341
342 mapping = page_mapping(page);
343 if (mapping && !mapping_mapped(mapping)) {
344 int dirty = test_bit(PG_dcache_dirty, &page->flags);
345 if (dirty) {
346 int dirty_cpu = dcache_dirty_cpu(page);
347
348 if (dirty_cpu == this_cpu)
349 goto out;
350 smp_flush_dcache_page_impl(page, dirty_cpu);
351 }
352 set_dcache_dirty(page, this_cpu);
353 } else {
354 /* We could delay the flush for the !page_mapping
355 * case too. But that case is for exec env/arg
356 * pages and those are %99 certainly going to get
357 * faulted into the tlb (and thus flushed) anyways.
358 */
359 flush_dcache_page_impl(page);
360 }
361
362 out:
363 put_cpu();
364 }
365
366 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
367 {
368 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
369 if (tlb_type == spitfire) {
370 unsigned long kaddr;
371
372 /* This code only runs on Spitfire cpus so this is
373 * why we can assume _PAGE_PADDR_4U.
374 */
375 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
376 unsigned long paddr, mask = _PAGE_PADDR_4U;
377
378 if (kaddr >= PAGE_OFFSET)
379 paddr = kaddr & mask;
380 else {
381 pgd_t *pgdp = pgd_offset_k(kaddr);
382 pud_t *pudp = pud_offset(pgdp, kaddr);
383 pmd_t *pmdp = pmd_offset(pudp, kaddr);
384 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
385
386 paddr = pte_val(*ptep) & mask;
387 }
388 __flush_icache_page(paddr);
389 }
390 }
391 }
392
393 void show_mem(void)
394 {
395 unsigned long total = 0, reserved = 0;
396 unsigned long shared = 0, cached = 0;
397 pg_data_t *pgdat;
398
399 printk(KERN_INFO "Mem-info:\n");
400 show_free_areas();
401 printk(KERN_INFO "Free swap: %6ldkB\n",
402 nr_swap_pages << (PAGE_SHIFT-10));
403 for_each_online_pgdat(pgdat) {
404 unsigned long i, flags;
405
406 pgdat_resize_lock(pgdat, &flags);
407 for (i = 0; i < pgdat->node_spanned_pages; i++) {
408 struct page *page = pgdat_page_nr(pgdat, i);
409 total++;
410 if (PageReserved(page))
411 reserved++;
412 else if (PageSwapCache(page))
413 cached++;
414 else if (page_count(page))
415 shared += page_count(page) - 1;
416 }
417 pgdat_resize_unlock(pgdat, &flags);
418 }
419
420 printk(KERN_INFO "%lu pages of RAM\n", total);
421 printk(KERN_INFO "%lu reserved pages\n", reserved);
422 printk(KERN_INFO "%lu pages shared\n", shared);
423 printk(KERN_INFO "%lu pages swap cached\n", cached);
424
425 printk(KERN_INFO "%lu pages dirty\n",
426 global_page_state(NR_FILE_DIRTY));
427 printk(KERN_INFO "%lu pages writeback\n",
428 global_page_state(NR_WRITEBACK));
429 printk(KERN_INFO "%lu pages mapped\n",
430 global_page_state(NR_FILE_MAPPED));
431 printk(KERN_INFO "%lu pages slab\n",
432 global_page_state(NR_SLAB_RECLAIMABLE) +
433 global_page_state(NR_SLAB_UNRECLAIMABLE));
434 printk(KERN_INFO "%lu pages pagetables\n",
435 global_page_state(NR_PAGETABLE));
436 }
437
438 void mmu_info(struct seq_file *m)
439 {
440 if (tlb_type == cheetah)
441 seq_printf(m, "MMU Type\t: Cheetah\n");
442 else if (tlb_type == cheetah_plus)
443 seq_printf(m, "MMU Type\t: Cheetah+\n");
444 else if (tlb_type == spitfire)
445 seq_printf(m, "MMU Type\t: Spitfire\n");
446 else if (tlb_type == hypervisor)
447 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
448 else
449 seq_printf(m, "MMU Type\t: ???\n");
450
451 #ifdef CONFIG_DEBUG_DCFLUSH
452 seq_printf(m, "DCPageFlushes\t: %d\n",
453 atomic_read(&dcpage_flushes));
454 #ifdef CONFIG_SMP
455 seq_printf(m, "DCPageFlushesXC\t: %d\n",
456 atomic_read(&dcpage_flushes_xcall));
457 #endif /* CONFIG_SMP */
458 #endif /* CONFIG_DEBUG_DCFLUSH */
459 }
460
461 struct linux_prom_translation {
462 unsigned long virt;
463 unsigned long size;
464 unsigned long data;
465 };
466
467 /* Exported for kernel TLB miss handling in ktlb.S */
468 struct linux_prom_translation prom_trans[512] __read_mostly;
469 unsigned int prom_trans_ents __read_mostly;
470
471 /* Exported for SMP bootup purposes. */
472 unsigned long kern_locked_tte_data;
473
474 /* The obp translations are saved based on 8k pagesize, since obp can
475 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
476 * HI_OBP_ADDRESS range are handled in ktlb.S.
477 */
478 static inline int in_obp_range(unsigned long vaddr)
479 {
480 return (vaddr >= LOW_OBP_ADDRESS &&
481 vaddr < HI_OBP_ADDRESS);
482 }
483
484 static int cmp_ptrans(const void *a, const void *b)
485 {
486 const struct linux_prom_translation *x = a, *y = b;
487
488 if (x->virt > y->virt)
489 return 1;
490 if (x->virt < y->virt)
491 return -1;
492 return 0;
493 }
494
495 /* Read OBP translations property into 'prom_trans[]'. */
496 static void __init read_obp_translations(void)
497 {
498 int n, node, ents, first, last, i;
499
500 node = prom_finddevice("/virtual-memory");
501 n = prom_getproplen(node, "translations");
502 if (unlikely(n == 0 || n == -1)) {
503 prom_printf("prom_mappings: Couldn't get size.\n");
504 prom_halt();
505 }
506 if (unlikely(n > sizeof(prom_trans))) {
507 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
508 prom_halt();
509 }
510
511 if ((n = prom_getproperty(node, "translations",
512 (char *)&prom_trans[0],
513 sizeof(prom_trans))) == -1) {
514 prom_printf("prom_mappings: Couldn't get property.\n");
515 prom_halt();
516 }
517
518 n = n / sizeof(struct linux_prom_translation);
519
520 ents = n;
521
522 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
523 cmp_ptrans, NULL);
524
525 /* Now kick out all the non-OBP entries. */
526 for (i = 0; i < ents; i++) {
527 if (in_obp_range(prom_trans[i].virt))
528 break;
529 }
530 first = i;
531 for (; i < ents; i++) {
532 if (!in_obp_range(prom_trans[i].virt))
533 break;
534 }
535 last = i;
536
537 for (i = 0; i < (last - first); i++) {
538 struct linux_prom_translation *src = &prom_trans[i + first];
539 struct linux_prom_translation *dest = &prom_trans[i];
540
541 *dest = *src;
542 }
543 for (; i < ents; i++) {
544 struct linux_prom_translation *dest = &prom_trans[i];
545 dest->virt = dest->size = dest->data = 0x0UL;
546 }
547
548 prom_trans_ents = last - first;
549
550 if (tlb_type == spitfire) {
551 /* Clear diag TTE bits. */
552 for (i = 0; i < prom_trans_ents; i++)
553 prom_trans[i].data &= ~0x0003fe0000000000UL;
554 }
555 }
556
557 static void __init hypervisor_tlb_lock(unsigned long vaddr,
558 unsigned long pte,
559 unsigned long mmu)
560 {
561 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
562
563 if (ret != 0) {
564 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
565 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
566 prom_halt();
567 }
568 }
569
570 static unsigned long kern_large_tte(unsigned long paddr);
571
572 static void __init remap_kernel(void)
573 {
574 unsigned long phys_page, tte_vaddr, tte_data;
575 int tlb_ent = sparc64_highest_locked_tlbent();
576
577 tte_vaddr = (unsigned long) KERNBASE;
578 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
579 tte_data = kern_large_tte(phys_page);
580
581 kern_locked_tte_data = tte_data;
582
583 /* Now lock us into the TLBs via Hypervisor or OBP. */
584 if (tlb_type == hypervisor) {
585 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
586 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
587 if (bigkernel) {
588 tte_vaddr += 0x400000;
589 tte_data += 0x400000;
590 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
591 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
592 }
593 } else {
594 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
595 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
596 if (bigkernel) {
597 tlb_ent -= 1;
598 prom_dtlb_load(tlb_ent,
599 tte_data + 0x400000,
600 tte_vaddr + 0x400000);
601 prom_itlb_load(tlb_ent,
602 tte_data + 0x400000,
603 tte_vaddr + 0x400000);
604 }
605 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
606 }
607 if (tlb_type == cheetah_plus) {
608 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
609 CTX_CHEETAH_PLUS_NUC);
610 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
611 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
612 }
613 }
614
615
616 static void __init inherit_prom_mappings(void)
617 {
618 read_obp_translations();
619
620 /* Now fixup OBP's idea about where we really are mapped. */
621 printk("Remapping the kernel... ");
622 remap_kernel();
623 printk("done.\n");
624 }
625
626 void prom_world(int enter)
627 {
628 if (!enter)
629 set_fs((mm_segment_t) { get_thread_current_ds() });
630
631 __asm__ __volatile__("flushw");
632 }
633
634 void __flush_dcache_range(unsigned long start, unsigned long end)
635 {
636 unsigned long va;
637
638 if (tlb_type == spitfire) {
639 int n = 0;
640
641 for (va = start; va < end; va += 32) {
642 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
643 if (++n >= 512)
644 break;
645 }
646 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
647 start = __pa(start);
648 end = __pa(end);
649 for (va = start; va < end; va += 32)
650 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
651 "membar #Sync"
652 : /* no outputs */
653 : "r" (va),
654 "i" (ASI_DCACHE_INVALIDATE));
655 }
656 }
657
658 /* get_new_mmu_context() uses "cache + 1". */
659 DEFINE_SPINLOCK(ctx_alloc_lock);
660 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
661 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
662 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
663 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
664
665 /* Caller does TLB context flushing on local CPU if necessary.
666 * The caller also ensures that CTX_VALID(mm->context) is false.
667 *
668 * We must be careful about boundary cases so that we never
669 * let the user have CTX 0 (nucleus) or we ever use a CTX
670 * version of zero (and thus NO_CONTEXT would not be caught
671 * by version mis-match tests in mmu_context.h).
672 *
673 * Always invoked with interrupts disabled.
674 */
675 void get_new_mmu_context(struct mm_struct *mm)
676 {
677 unsigned long ctx, new_ctx;
678 unsigned long orig_pgsz_bits;
679 unsigned long flags;
680 int new_version;
681
682 spin_lock_irqsave(&ctx_alloc_lock, flags);
683 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
684 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
685 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
686 new_version = 0;
687 if (new_ctx >= (1 << CTX_NR_BITS)) {
688 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
689 if (new_ctx >= ctx) {
690 int i;
691 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
692 CTX_FIRST_VERSION;
693 if (new_ctx == 1)
694 new_ctx = CTX_FIRST_VERSION;
695
696 /* Don't call memset, for 16 entries that's just
697 * plain silly...
698 */
699 mmu_context_bmap[0] = 3;
700 mmu_context_bmap[1] = 0;
701 mmu_context_bmap[2] = 0;
702 mmu_context_bmap[3] = 0;
703 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
704 mmu_context_bmap[i + 0] = 0;
705 mmu_context_bmap[i + 1] = 0;
706 mmu_context_bmap[i + 2] = 0;
707 mmu_context_bmap[i + 3] = 0;
708 }
709 new_version = 1;
710 goto out;
711 }
712 }
713 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
714 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
715 out:
716 tlb_context_cache = new_ctx;
717 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
718 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
719
720 if (unlikely(new_version))
721 smp_new_mmu_context_version();
722 }
723
724 /* Find a free area for the bootmem map, avoiding the kernel image
725 * and the initial ramdisk.
726 */
727 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
728 unsigned long end_pfn)
729 {
730 unsigned long avoid_start, avoid_end, bootmap_size;
731 int i;
732
733 bootmap_size = bootmem_bootmap_pages(end_pfn - start_pfn);
734 bootmap_size <<= PAGE_SHIFT;
735
736 avoid_start = avoid_end = 0;
737 #ifdef CONFIG_BLK_DEV_INITRD
738 avoid_start = initrd_start;
739 avoid_end = PAGE_ALIGN(initrd_end);
740 #endif
741
742 for (i = 0; i < pavail_ents; i++) {
743 unsigned long start, end;
744
745 start = pavail[i].phys_addr;
746 end = start + pavail[i].reg_size;
747
748 while (start < end) {
749 if (start >= kern_base &&
750 start < PAGE_ALIGN(kern_base + kern_size)) {
751 start = PAGE_ALIGN(kern_base + kern_size);
752 continue;
753 }
754 if (start >= avoid_start && start < avoid_end) {
755 start = avoid_end;
756 continue;
757 }
758
759 if ((end - start) < bootmap_size)
760 break;
761
762 if (start < kern_base &&
763 (start + bootmap_size) > kern_base) {
764 start = PAGE_ALIGN(kern_base + kern_size);
765 continue;
766 }
767
768 if (start < avoid_start &&
769 (start + bootmap_size) > avoid_start) {
770 start = avoid_end;
771 continue;
772 }
773
774 /* OK, it doesn't overlap anything, use it. */
775 return start >> PAGE_SHIFT;
776 }
777 }
778
779 prom_printf("Cannot find free area for bootmap, aborting.\n");
780 prom_halt();
781 }
782
783 static void __init trim_pavail(unsigned long *cur_size_p,
784 unsigned long *end_of_phys_p)
785 {
786 unsigned long to_trim = *cur_size_p - cmdline_memory_size;
787 unsigned long avoid_start, avoid_end;
788 int i;
789
790 to_trim = PAGE_ALIGN(to_trim);
791
792 avoid_start = avoid_end = 0;
793 #ifdef CONFIG_BLK_DEV_INITRD
794 avoid_start = initrd_start;
795 avoid_end = PAGE_ALIGN(initrd_end);
796 #endif
797
798 /* Trim some pavail[] entries in order to satisfy the
799 * requested "mem=xxx" kernel command line specification.
800 *
801 * We must not trim off the kernel image area nor the
802 * initial ramdisk range (if any). Also, we must not trim
803 * any pavail[] entry down to zero in order to preserve
804 * the invariant that all pavail[] entries have a non-zero
805 * size which is assumed by all of the code in here.
806 */
807 for (i = 0; i < pavail_ents; i++) {
808 unsigned long start, end, kern_end;
809 unsigned long trim_low, trim_high, n;
810
811 kern_end = PAGE_ALIGN(kern_base + kern_size);
812
813 trim_low = start = pavail[i].phys_addr;
814 trim_high = end = start + pavail[i].reg_size;
815
816 if (kern_base >= start &&
817 kern_base < end) {
818 trim_low = kern_base;
819 if (kern_end >= end)
820 continue;
821 }
822 if (kern_end >= start &&
823 kern_end < end) {
824 trim_high = kern_end;
825 }
826 if (avoid_start &&
827 avoid_start >= start &&
828 avoid_start < end) {
829 if (trim_low > avoid_start)
830 trim_low = avoid_start;
831 if (avoid_end >= end)
832 continue;
833 }
834 if (avoid_end &&
835 avoid_end >= start &&
836 avoid_end < end) {
837 if (trim_high < avoid_end)
838 trim_high = avoid_end;
839 }
840
841 if (trim_high <= trim_low)
842 continue;
843
844 if (trim_low == start && trim_high == end) {
845 /* Whole chunk is available for trimming.
846 * Trim all except one page, in order to keep
847 * entry non-empty.
848 */
849 n = (end - start) - PAGE_SIZE;
850 if (n > to_trim)
851 n = to_trim;
852
853 if (n) {
854 pavail[i].phys_addr += n;
855 pavail[i].reg_size -= n;
856 to_trim -= n;
857 }
858 } else {
859 n = (trim_low - start);
860 if (n > to_trim)
861 n = to_trim;
862
863 if (n) {
864 pavail[i].phys_addr += n;
865 pavail[i].reg_size -= n;
866 to_trim -= n;
867 }
868 if (to_trim) {
869 n = end - trim_high;
870 if (n > to_trim)
871 n = to_trim;
872 if (n) {
873 pavail[i].reg_size -= n;
874 to_trim -= n;
875 }
876 }
877 }
878
879 if (!to_trim)
880 break;
881 }
882
883 /* Recalculate. */
884 *cur_size_p = 0UL;
885 for (i = 0; i < pavail_ents; i++) {
886 *end_of_phys_p = pavail[i].phys_addr +
887 pavail[i].reg_size;
888 *cur_size_p += pavail[i].reg_size;
889 }
890 }
891
892 /* About pages_avail, this is the value we will use to calculate
893 * the zholes_size[] argument given to free_area_init_node(). The
894 * page allocator uses this to calculate nr_kernel_pages,
895 * nr_all_pages and zone->present_pages. On NUMA it is used
896 * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
897 *
898 * So this number should really be set to what the page allocator
899 * actually ends up with. This means:
900 * 1) It should include bootmem map pages, we'll release those.
901 * 2) It should not include the kernel image, except for the
902 * __init sections which we will also release.
903 * 3) It should include the initrd image, since we'll release
904 * that too.
905 */
906 static unsigned long __init bootmem_init(unsigned long *pages_avail,
907 unsigned long phys_base)
908 {
909 unsigned long bootmap_size, end_pfn;
910 unsigned long end_of_phys_memory = 0UL;
911 unsigned long bootmap_pfn, bytes_avail, size;
912 int i;
913
914 bytes_avail = 0UL;
915 for (i = 0; i < pavail_ents; i++) {
916 end_of_phys_memory = pavail[i].phys_addr +
917 pavail[i].reg_size;
918 bytes_avail += pavail[i].reg_size;
919 }
920
921 /* Determine the location of the initial ramdisk before trying
922 * to honor the "mem=xxx" command line argument. We must know
923 * where the kernel image and the ramdisk image are so that we
924 * do not trim those two areas from the physical memory map.
925 */
926
927 #ifdef CONFIG_BLK_DEV_INITRD
928 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
929 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
930 unsigned long ramdisk_image = sparc_ramdisk_image ?
931 sparc_ramdisk_image : sparc_ramdisk_image64;
932 ramdisk_image -= KERNBASE;
933 initrd_start = ramdisk_image + phys_base;
934 initrd_end = initrd_start + sparc_ramdisk_size;
935 if (initrd_end > end_of_phys_memory) {
936 printk(KERN_CRIT "initrd extends beyond end of memory "
937 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
938 initrd_end, end_of_phys_memory);
939 initrd_start = 0;
940 initrd_end = 0;
941 }
942 }
943 #endif
944
945 if (cmdline_memory_size &&
946 bytes_avail > cmdline_memory_size)
947 trim_pavail(&bytes_avail,
948 &end_of_phys_memory);
949
950 *pages_avail = bytes_avail >> PAGE_SHIFT;
951
952 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
953
954 /* Initialize the boot-time allocator. */
955 max_pfn = max_low_pfn = end_pfn;
956 min_low_pfn = (phys_base >> PAGE_SHIFT);
957
958 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
959
960 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
961 min_low_pfn, end_pfn);
962
963 /* Now register the available physical memory with the
964 * allocator.
965 */
966 for (i = 0; i < pavail_ents; i++)
967 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
968
969 #ifdef CONFIG_BLK_DEV_INITRD
970 if (initrd_start) {
971 size = initrd_end - initrd_start;
972
973 /* Reserve the initrd image area. */
974 reserve_bootmem(initrd_start, size, BOOTMEM_DEFAULT);
975
976 initrd_start += PAGE_OFFSET;
977 initrd_end += PAGE_OFFSET;
978 }
979 #endif
980 /* Reserve the kernel text/data/bss. */
981 reserve_bootmem(kern_base, kern_size, BOOTMEM_DEFAULT);
982 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
983
984 /* Add back in the initmem pages. */
985 size = ((unsigned long)(__init_end) & PAGE_MASK) -
986 PAGE_ALIGN((unsigned long)__init_begin);
987 *pages_avail += size >> PAGE_SHIFT;
988
989 /* Reserve the bootmem map. We do not account for it
990 * in pages_avail because we will release that memory
991 * in free_all_bootmem.
992 */
993 size = bootmap_size;
994 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size, BOOTMEM_DEFAULT);
995
996 for (i = 0; i < pavail_ents; i++) {
997 unsigned long start_pfn, end_pfn;
998
999 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
1000 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
1001 memory_present(0, start_pfn, end_pfn);
1002 }
1003
1004 sparse_init();
1005
1006 return end_pfn;
1007 }
1008
1009 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1010 static int pall_ents __initdata;
1011
1012 #ifdef CONFIG_DEBUG_PAGEALLOC
1013 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1014 {
1015 unsigned long vstart = PAGE_OFFSET + pstart;
1016 unsigned long vend = PAGE_OFFSET + pend;
1017 unsigned long alloc_bytes = 0UL;
1018
1019 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1020 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1021 vstart, vend);
1022 prom_halt();
1023 }
1024
1025 while (vstart < vend) {
1026 unsigned long this_end, paddr = __pa(vstart);
1027 pgd_t *pgd = pgd_offset_k(vstart);
1028 pud_t *pud;
1029 pmd_t *pmd;
1030 pte_t *pte;
1031
1032 pud = pud_offset(pgd, vstart);
1033 if (pud_none(*pud)) {
1034 pmd_t *new;
1035
1036 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1037 alloc_bytes += PAGE_SIZE;
1038 pud_populate(&init_mm, pud, new);
1039 }
1040
1041 pmd = pmd_offset(pud, vstart);
1042 if (!pmd_present(*pmd)) {
1043 pte_t *new;
1044
1045 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1046 alloc_bytes += PAGE_SIZE;
1047 pmd_populate_kernel(&init_mm, pmd, new);
1048 }
1049
1050 pte = pte_offset_kernel(pmd, vstart);
1051 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1052 if (this_end > vend)
1053 this_end = vend;
1054
1055 while (vstart < this_end) {
1056 pte_val(*pte) = (paddr | pgprot_val(prot));
1057
1058 vstart += PAGE_SIZE;
1059 paddr += PAGE_SIZE;
1060 pte++;
1061 }
1062 }
1063
1064 return alloc_bytes;
1065 }
1066
1067 extern unsigned int kvmap_linear_patch[1];
1068 #endif /* CONFIG_DEBUG_PAGEALLOC */
1069
1070 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1071 {
1072 const unsigned long shift_256MB = 28;
1073 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1074 const unsigned long size_256MB = (1UL << shift_256MB);
1075
1076 while (start < end) {
1077 long remains;
1078
1079 remains = end - start;
1080 if (remains < size_256MB)
1081 break;
1082
1083 if (start & mask_256MB) {
1084 start = (start + size_256MB) & ~mask_256MB;
1085 continue;
1086 }
1087
1088 while (remains >= size_256MB) {
1089 unsigned long index = start >> shift_256MB;
1090
1091 __set_bit(index, kpte_linear_bitmap);
1092
1093 start += size_256MB;
1094 remains -= size_256MB;
1095 }
1096 }
1097 }
1098
1099 static void __init init_kpte_bitmap(void)
1100 {
1101 unsigned long i;
1102
1103 for (i = 0; i < pall_ents; i++) {
1104 unsigned long phys_start, phys_end;
1105
1106 phys_start = pall[i].phys_addr;
1107 phys_end = phys_start + pall[i].reg_size;
1108
1109 mark_kpte_bitmap(phys_start, phys_end);
1110 }
1111 }
1112
1113 static void __init kernel_physical_mapping_init(void)
1114 {
1115 #ifdef CONFIG_DEBUG_PAGEALLOC
1116 unsigned long i, mem_alloced = 0UL;
1117
1118 for (i = 0; i < pall_ents; i++) {
1119 unsigned long phys_start, phys_end;
1120
1121 phys_start = pall[i].phys_addr;
1122 phys_end = phys_start + pall[i].reg_size;
1123
1124 mem_alloced += kernel_map_range(phys_start, phys_end,
1125 PAGE_KERNEL);
1126 }
1127
1128 printk("Allocated %ld bytes for kernel page tables.\n",
1129 mem_alloced);
1130
1131 kvmap_linear_patch[0] = 0x01000000; /* nop */
1132 flushi(&kvmap_linear_patch[0]);
1133
1134 __flush_tlb_all();
1135 #endif
1136 }
1137
1138 #ifdef CONFIG_DEBUG_PAGEALLOC
1139 void kernel_map_pages(struct page *page, int numpages, int enable)
1140 {
1141 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1142 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1143
1144 kernel_map_range(phys_start, phys_end,
1145 (enable ? PAGE_KERNEL : __pgprot(0)));
1146
1147 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1148 PAGE_OFFSET + phys_end);
1149
1150 /* we should perform an IPI and flush all tlbs,
1151 * but that can deadlock->flush only current cpu.
1152 */
1153 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1154 PAGE_OFFSET + phys_end);
1155 }
1156 #endif
1157
1158 unsigned long __init find_ecache_flush_span(unsigned long size)
1159 {
1160 int i;
1161
1162 for (i = 0; i < pavail_ents; i++) {
1163 if (pavail[i].reg_size >= size)
1164 return pavail[i].phys_addr;
1165 }
1166
1167 return ~0UL;
1168 }
1169
1170 static void __init tsb_phys_patch(void)
1171 {
1172 struct tsb_ldquad_phys_patch_entry *pquad;
1173 struct tsb_phys_patch_entry *p;
1174
1175 pquad = &__tsb_ldquad_phys_patch;
1176 while (pquad < &__tsb_ldquad_phys_patch_end) {
1177 unsigned long addr = pquad->addr;
1178
1179 if (tlb_type == hypervisor)
1180 *(unsigned int *) addr = pquad->sun4v_insn;
1181 else
1182 *(unsigned int *) addr = pquad->sun4u_insn;
1183 wmb();
1184 __asm__ __volatile__("flush %0"
1185 : /* no outputs */
1186 : "r" (addr));
1187
1188 pquad++;
1189 }
1190
1191 p = &__tsb_phys_patch;
1192 while (p < &__tsb_phys_patch_end) {
1193 unsigned long addr = p->addr;
1194
1195 *(unsigned int *) addr = p->insn;
1196 wmb();
1197 __asm__ __volatile__("flush %0"
1198 : /* no outputs */
1199 : "r" (addr));
1200
1201 p++;
1202 }
1203 }
1204
1205 /* Don't mark as init, we give this to the Hypervisor. */
1206 #ifndef CONFIG_DEBUG_PAGEALLOC
1207 #define NUM_KTSB_DESCR 2
1208 #else
1209 #define NUM_KTSB_DESCR 1
1210 #endif
1211 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1212 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1213
1214 static void __init sun4v_ktsb_init(void)
1215 {
1216 unsigned long ktsb_pa;
1217
1218 /* First KTSB for PAGE_SIZE mappings. */
1219 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1220
1221 switch (PAGE_SIZE) {
1222 case 8 * 1024:
1223 default:
1224 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1225 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1226 break;
1227
1228 case 64 * 1024:
1229 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1230 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1231 break;
1232
1233 case 512 * 1024:
1234 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1235 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1236 break;
1237
1238 case 4 * 1024 * 1024:
1239 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1240 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1241 break;
1242 };
1243
1244 ktsb_descr[0].assoc = 1;
1245 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1246 ktsb_descr[0].ctx_idx = 0;
1247 ktsb_descr[0].tsb_base = ktsb_pa;
1248 ktsb_descr[0].resv = 0;
1249
1250 #ifndef CONFIG_DEBUG_PAGEALLOC
1251 /* Second KTSB for 4MB/256MB mappings. */
1252 ktsb_pa = (kern_base +
1253 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1254
1255 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1256 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1257 HV_PGSZ_MASK_256MB);
1258 ktsb_descr[1].assoc = 1;
1259 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1260 ktsb_descr[1].ctx_idx = 0;
1261 ktsb_descr[1].tsb_base = ktsb_pa;
1262 ktsb_descr[1].resv = 0;
1263 #endif
1264 }
1265
1266 void __cpuinit sun4v_ktsb_register(void)
1267 {
1268 unsigned long pa, ret;
1269
1270 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1271
1272 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1273 if (ret != 0) {
1274 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1275 "errors with %lx\n", pa, ret);
1276 prom_halt();
1277 }
1278 }
1279
1280 /* paging_init() sets up the page tables */
1281
1282 extern void cheetah_ecache_flush_init(void);
1283 extern void sun4v_patch_tlb_handlers(void);
1284
1285 extern void cpu_probe(void);
1286 extern void central_probe(void);
1287
1288 static unsigned long last_valid_pfn;
1289 pgd_t swapper_pg_dir[2048];
1290
1291 static void sun4u_pgprot_init(void);
1292 static void sun4v_pgprot_init(void);
1293
1294 /* Dummy function */
1295 void __init setup_per_cpu_areas(void)
1296 {
1297 }
1298
1299 void __init paging_init(void)
1300 {
1301 unsigned long end_pfn, pages_avail, shift, phys_base;
1302 unsigned long real_end, i;
1303
1304 /* These build time checkes make sure that the dcache_dirty_cpu()
1305 * page->flags usage will work.
1306 *
1307 * When a page gets marked as dcache-dirty, we store the
1308 * cpu number starting at bit 32 in the page->flags. Also,
1309 * functions like clear_dcache_dirty_cpu use the cpu mask
1310 * in 13-bit signed-immediate instruction fields.
1311 */
1312 BUILD_BUG_ON(FLAGS_RESERVED != 32);
1313 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1314 ilog2(roundup_pow_of_two(NR_CPUS)) > FLAGS_RESERVED);
1315 BUILD_BUG_ON(NR_CPUS > 4096);
1316
1317 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1318 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1319
1320 sstate_booting();
1321
1322 /* Invalidate both kernel TSBs. */
1323 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1324 #ifndef CONFIG_DEBUG_PAGEALLOC
1325 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1326 #endif
1327
1328 if (tlb_type == hypervisor)
1329 sun4v_pgprot_init();
1330 else
1331 sun4u_pgprot_init();
1332
1333 if (tlb_type == cheetah_plus ||
1334 tlb_type == hypervisor)
1335 tsb_phys_patch();
1336
1337 if (tlb_type == hypervisor) {
1338 sun4v_patch_tlb_handlers();
1339 sun4v_ktsb_init();
1340 }
1341
1342 /* Find available physical memory... */
1343 read_obp_memory("available", &pavail[0], &pavail_ents);
1344
1345 phys_base = 0xffffffffffffffffUL;
1346 for (i = 0; i < pavail_ents; i++)
1347 phys_base = min(phys_base, pavail[i].phys_addr);
1348
1349 set_bit(0, mmu_context_bmap);
1350
1351 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1352
1353 real_end = (unsigned long)_end;
1354 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1355 bigkernel = 1;
1356 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1357 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1358 prom_halt();
1359 }
1360
1361 /* Set kernel pgd to upper alias so physical page computations
1362 * work.
1363 */
1364 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1365
1366 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1367
1368 /* Now can init the kernel/bad page tables. */
1369 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1370 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1371
1372 inherit_prom_mappings();
1373
1374 read_obp_memory("reg", &pall[0], &pall_ents);
1375
1376 init_kpte_bitmap();
1377
1378 /* Ok, we can use our TLB miss and window trap handlers safely. */
1379 setup_tba();
1380
1381 __flush_tlb_all();
1382
1383 if (tlb_type == hypervisor)
1384 sun4v_ktsb_register();
1385
1386 /* Setup bootmem... */
1387 pages_avail = 0;
1388 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1389
1390 max_mapnr = last_valid_pfn;
1391
1392 kernel_physical_mapping_init();
1393
1394 real_setup_per_cpu_areas();
1395
1396 prom_build_devicetree();
1397
1398 if (tlb_type == hypervisor)
1399 sun4v_mdesc_init();
1400
1401 {
1402 unsigned long zones_size[MAX_NR_ZONES];
1403 unsigned long zholes_size[MAX_NR_ZONES];
1404 int znum;
1405
1406 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1407 zones_size[znum] = zholes_size[znum] = 0;
1408
1409 zones_size[ZONE_NORMAL] = end_pfn;
1410 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1411
1412 free_area_init_node(0, &contig_page_data, zones_size,
1413 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1414 zholes_size);
1415 }
1416
1417 printk("Booting Linux...\n");
1418
1419 central_probe();
1420 cpu_probe();
1421 }
1422
1423 static void __init taint_real_pages(void)
1424 {
1425 int i;
1426
1427 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1428
1429 /* Find changes discovered in the physmem available rescan and
1430 * reserve the lost portions in the bootmem maps.
1431 */
1432 for (i = 0; i < pavail_ents; i++) {
1433 unsigned long old_start, old_end;
1434
1435 old_start = pavail[i].phys_addr;
1436 old_end = old_start +
1437 pavail[i].reg_size;
1438 while (old_start < old_end) {
1439 int n;
1440
1441 for (n = 0; n < pavail_rescan_ents; n++) {
1442 unsigned long new_start, new_end;
1443
1444 new_start = pavail_rescan[n].phys_addr;
1445 new_end = new_start +
1446 pavail_rescan[n].reg_size;
1447
1448 if (new_start <= old_start &&
1449 new_end >= (old_start + PAGE_SIZE)) {
1450 set_bit(old_start >> 22,
1451 sparc64_valid_addr_bitmap);
1452 goto do_next_page;
1453 }
1454 }
1455 reserve_bootmem(old_start, PAGE_SIZE, BOOTMEM_DEFAULT);
1456
1457 do_next_page:
1458 old_start += PAGE_SIZE;
1459 }
1460 }
1461 }
1462
1463 int __init page_in_phys_avail(unsigned long paddr)
1464 {
1465 int i;
1466
1467 paddr &= PAGE_MASK;
1468
1469 for (i = 0; i < pavail_rescan_ents; i++) {
1470 unsigned long start, end;
1471
1472 start = pavail_rescan[i].phys_addr;
1473 end = start + pavail_rescan[i].reg_size;
1474
1475 if (paddr >= start && paddr < end)
1476 return 1;
1477 }
1478 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1479 return 1;
1480 #ifdef CONFIG_BLK_DEV_INITRD
1481 if (paddr >= __pa(initrd_start) &&
1482 paddr < __pa(PAGE_ALIGN(initrd_end)))
1483 return 1;
1484 #endif
1485
1486 return 0;
1487 }
1488
1489 void __init mem_init(void)
1490 {
1491 unsigned long codepages, datapages, initpages;
1492 unsigned long addr, last;
1493 int i;
1494
1495 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1496 i += 1;
1497 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1498 if (sparc64_valid_addr_bitmap == NULL) {
1499 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1500 prom_halt();
1501 }
1502 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1503
1504 addr = PAGE_OFFSET + kern_base;
1505 last = PAGE_ALIGN(kern_size) + addr;
1506 while (addr < last) {
1507 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1508 addr += PAGE_SIZE;
1509 }
1510
1511 taint_real_pages();
1512
1513 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1514
1515 /* We subtract one to account for the mem_map_zero page
1516 * allocated below.
1517 */
1518 totalram_pages = num_physpages = free_all_bootmem() - 1;
1519
1520 /*
1521 * Set up the zero page, mark it reserved, so that page count
1522 * is not manipulated when freeing the page from user ptes.
1523 */
1524 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1525 if (mem_map_zero == NULL) {
1526 prom_printf("paging_init: Cannot alloc zero page.\n");
1527 prom_halt();
1528 }
1529 SetPageReserved(mem_map_zero);
1530
1531 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1532 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1533 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1534 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1535 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1536 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1537
1538 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1539 nr_free_pages() << (PAGE_SHIFT-10),
1540 codepages << (PAGE_SHIFT-10),
1541 datapages << (PAGE_SHIFT-10),
1542 initpages << (PAGE_SHIFT-10),
1543 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1544
1545 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1546 cheetah_ecache_flush_init();
1547 }
1548
1549 void free_initmem(void)
1550 {
1551 unsigned long addr, initend;
1552
1553 /*
1554 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1555 */
1556 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1557 initend = (unsigned long)(__init_end) & PAGE_MASK;
1558 for (; addr < initend; addr += PAGE_SIZE) {
1559 unsigned long page;
1560 struct page *p;
1561
1562 page = (addr +
1563 ((unsigned long) __va(kern_base)) -
1564 ((unsigned long) KERNBASE));
1565 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1566 p = virt_to_page(page);
1567
1568 ClearPageReserved(p);
1569 init_page_count(p);
1570 __free_page(p);
1571 num_physpages++;
1572 totalram_pages++;
1573 }
1574 }
1575
1576 #ifdef CONFIG_BLK_DEV_INITRD
1577 void free_initrd_mem(unsigned long start, unsigned long end)
1578 {
1579 if (start < end)
1580 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1581 for (; start < end; start += PAGE_SIZE) {
1582 struct page *p = virt_to_page(start);
1583
1584 ClearPageReserved(p);
1585 init_page_count(p);
1586 __free_page(p);
1587 num_physpages++;
1588 totalram_pages++;
1589 }
1590 }
1591 #endif
1592
1593 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1594 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1595 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1596 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1597 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1598 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1599
1600 pgprot_t PAGE_KERNEL __read_mostly;
1601 EXPORT_SYMBOL(PAGE_KERNEL);
1602
1603 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1604 pgprot_t PAGE_COPY __read_mostly;
1605
1606 pgprot_t PAGE_SHARED __read_mostly;
1607 EXPORT_SYMBOL(PAGE_SHARED);
1608
1609 pgprot_t PAGE_EXEC __read_mostly;
1610 unsigned long pg_iobits __read_mostly;
1611
1612 unsigned long _PAGE_IE __read_mostly;
1613 EXPORT_SYMBOL(_PAGE_IE);
1614
1615 unsigned long _PAGE_E __read_mostly;
1616 EXPORT_SYMBOL(_PAGE_E);
1617
1618 unsigned long _PAGE_CACHE __read_mostly;
1619 EXPORT_SYMBOL(_PAGE_CACHE);
1620
1621 #ifdef CONFIG_SPARSEMEM_VMEMMAP
1622
1623 #define VMEMMAP_CHUNK_SHIFT 22
1624 #define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
1625 #define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
1626 #define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
1627
1628 #define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
1629 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
1630 unsigned long vmemmap_table[VMEMMAP_SIZE];
1631
1632 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
1633 {
1634 unsigned long vstart = (unsigned long) start;
1635 unsigned long vend = (unsigned long) (start + nr);
1636 unsigned long phys_start = (vstart - VMEMMAP_BASE);
1637 unsigned long phys_end = (vend - VMEMMAP_BASE);
1638 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
1639 unsigned long end = VMEMMAP_ALIGN(phys_end);
1640 unsigned long pte_base;
1641
1642 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1643 _PAGE_CP_4U | _PAGE_CV_4U |
1644 _PAGE_P_4U | _PAGE_W_4U);
1645 if (tlb_type == hypervisor)
1646 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1647 _PAGE_CP_4V | _PAGE_CV_4V |
1648 _PAGE_P_4V | _PAGE_W_4V);
1649
1650 for (; addr < end; addr += VMEMMAP_CHUNK) {
1651 unsigned long *vmem_pp =
1652 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
1653 void *block;
1654
1655 if (!(*vmem_pp & _PAGE_VALID)) {
1656 block = vmemmap_alloc_block(1UL << 22, node);
1657 if (!block)
1658 return -ENOMEM;
1659
1660 *vmem_pp = pte_base | __pa(block);
1661
1662 printk(KERN_INFO "[%p-%p] page_structs=%lu "
1663 "node=%d entry=%lu/%lu\n", start, block, nr,
1664 node,
1665 addr >> VMEMMAP_CHUNK_SHIFT,
1666 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
1667 }
1668 }
1669 return 0;
1670 }
1671 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
1672
1673 static void prot_init_common(unsigned long page_none,
1674 unsigned long page_shared,
1675 unsigned long page_copy,
1676 unsigned long page_readonly,
1677 unsigned long page_exec_bit)
1678 {
1679 PAGE_COPY = __pgprot(page_copy);
1680 PAGE_SHARED = __pgprot(page_shared);
1681
1682 protection_map[0x0] = __pgprot(page_none);
1683 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1684 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1685 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1686 protection_map[0x4] = __pgprot(page_readonly);
1687 protection_map[0x5] = __pgprot(page_readonly);
1688 protection_map[0x6] = __pgprot(page_copy);
1689 protection_map[0x7] = __pgprot(page_copy);
1690 protection_map[0x8] = __pgprot(page_none);
1691 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1692 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1693 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1694 protection_map[0xc] = __pgprot(page_readonly);
1695 protection_map[0xd] = __pgprot(page_readonly);
1696 protection_map[0xe] = __pgprot(page_shared);
1697 protection_map[0xf] = __pgprot(page_shared);
1698 }
1699
1700 static void __init sun4u_pgprot_init(void)
1701 {
1702 unsigned long page_none, page_shared, page_copy, page_readonly;
1703 unsigned long page_exec_bit;
1704
1705 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1706 _PAGE_CACHE_4U | _PAGE_P_4U |
1707 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1708 _PAGE_EXEC_4U);
1709 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1710 _PAGE_CACHE_4U | _PAGE_P_4U |
1711 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1712 _PAGE_EXEC_4U | _PAGE_L_4U);
1713 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1714
1715 _PAGE_IE = _PAGE_IE_4U;
1716 _PAGE_E = _PAGE_E_4U;
1717 _PAGE_CACHE = _PAGE_CACHE_4U;
1718
1719 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1720 __ACCESS_BITS_4U | _PAGE_E_4U);
1721
1722 #ifdef CONFIG_DEBUG_PAGEALLOC
1723 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1724 0xfffff80000000000;
1725 #else
1726 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1727 0xfffff80000000000;
1728 #endif
1729 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1730 _PAGE_P_4U | _PAGE_W_4U);
1731
1732 /* XXX Should use 256MB on Panther. XXX */
1733 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1734
1735 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1736 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1737 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1738 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1739
1740
1741 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1742 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1743 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1744 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1745 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1746 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1747 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1748
1749 page_exec_bit = _PAGE_EXEC_4U;
1750
1751 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1752 page_exec_bit);
1753 }
1754
1755 static void __init sun4v_pgprot_init(void)
1756 {
1757 unsigned long page_none, page_shared, page_copy, page_readonly;
1758 unsigned long page_exec_bit;
1759
1760 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1761 _PAGE_CACHE_4V | _PAGE_P_4V |
1762 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1763 _PAGE_EXEC_4V);
1764 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1765 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1766
1767 _PAGE_IE = _PAGE_IE_4V;
1768 _PAGE_E = _PAGE_E_4V;
1769 _PAGE_CACHE = _PAGE_CACHE_4V;
1770
1771 #ifdef CONFIG_DEBUG_PAGEALLOC
1772 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1773 0xfffff80000000000;
1774 #else
1775 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1776 0xfffff80000000000;
1777 #endif
1778 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1779 _PAGE_P_4V | _PAGE_W_4V);
1780
1781 #ifdef CONFIG_DEBUG_PAGEALLOC
1782 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1783 0xfffff80000000000;
1784 #else
1785 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1786 0xfffff80000000000;
1787 #endif
1788 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1789 _PAGE_P_4V | _PAGE_W_4V);
1790
1791 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1792 __ACCESS_BITS_4V | _PAGE_E_4V);
1793
1794 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1795 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1796 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1797 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1798 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1799
1800 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1801 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1802 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1803 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1804 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1805 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1806 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1807
1808 page_exec_bit = _PAGE_EXEC_4V;
1809
1810 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1811 page_exec_bit);
1812 }
1813
1814 unsigned long pte_sz_bits(unsigned long sz)
1815 {
1816 if (tlb_type == hypervisor) {
1817 switch (sz) {
1818 case 8 * 1024:
1819 default:
1820 return _PAGE_SZ8K_4V;
1821 case 64 * 1024:
1822 return _PAGE_SZ64K_4V;
1823 case 512 * 1024:
1824 return _PAGE_SZ512K_4V;
1825 case 4 * 1024 * 1024:
1826 return _PAGE_SZ4MB_4V;
1827 };
1828 } else {
1829 switch (sz) {
1830 case 8 * 1024:
1831 default:
1832 return _PAGE_SZ8K_4U;
1833 case 64 * 1024:
1834 return _PAGE_SZ64K_4U;
1835 case 512 * 1024:
1836 return _PAGE_SZ512K_4U;
1837 case 4 * 1024 * 1024:
1838 return _PAGE_SZ4MB_4U;
1839 };
1840 }
1841 }
1842
1843 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1844 {
1845 pte_t pte;
1846
1847 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1848 pte_val(pte) |= (((unsigned long)space) << 32);
1849 pte_val(pte) |= pte_sz_bits(page_size);
1850
1851 return pte;
1852 }
1853
1854 static unsigned long kern_large_tte(unsigned long paddr)
1855 {
1856 unsigned long val;
1857
1858 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1859 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1860 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1861 if (tlb_type == hypervisor)
1862 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1863 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1864 _PAGE_EXEC_4V | _PAGE_W_4V);
1865
1866 return val | paddr;
1867 }
1868
1869 /* If not locked, zap it. */
1870 void __flush_tlb_all(void)
1871 {
1872 unsigned long pstate;
1873 int i;
1874
1875 __asm__ __volatile__("flushw\n\t"
1876 "rdpr %%pstate, %0\n\t"
1877 "wrpr %0, %1, %%pstate"
1878 : "=r" (pstate)
1879 : "i" (PSTATE_IE));
1880 if (tlb_type == hypervisor) {
1881 sun4v_mmu_demap_all();
1882 } else if (tlb_type == spitfire) {
1883 for (i = 0; i < 64; i++) {
1884 /* Spitfire Errata #32 workaround */
1885 /* NOTE: Always runs on spitfire, so no
1886 * cheetah+ page size encodings.
1887 */
1888 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1889 "flush %%g6"
1890 : /* No outputs */
1891 : "r" (0),
1892 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1893
1894 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1895 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1896 "membar #Sync"
1897 : /* no outputs */
1898 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1899 spitfire_put_dtlb_data(i, 0x0UL);
1900 }
1901
1902 /* Spitfire Errata #32 workaround */
1903 /* NOTE: Always runs on spitfire, so no
1904 * cheetah+ page size encodings.
1905 */
1906 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1907 "flush %%g6"
1908 : /* No outputs */
1909 : "r" (0),
1910 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1911
1912 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1913 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1914 "membar #Sync"
1915 : /* no outputs */
1916 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1917 spitfire_put_itlb_data(i, 0x0UL);
1918 }
1919 }
1920 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1921 cheetah_flush_dtlb_all();
1922 cheetah_flush_itlb_all();
1923 }
1924 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1925 : : "r" (pstate));
1926 }
1927
1928 #ifdef CONFIG_MEMORY_HOTPLUG
1929
1930 void online_page(struct page *page)
1931 {
1932 ClearPageReserved(page);
1933 init_page_count(page);
1934 __free_page(page);
1935 totalram_pages++;
1936 num_physpages++;
1937 }
1938
1939 #endif /* CONFIG_MEMORY_HOTPLUG */
kmemtrace - Kernel memory tracer