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[SPARC64]: Always register a PROM based early console.
[linux-2.6/kmemtrace.git] / arch / sparc64 / kernel / prom.c
blob68964ddcde1e53bd5ce77207815cfe0bbc2068f3
1 /*
2 * Procedures for creating, accessing and interpreting the device tree.
3 *
4 * Paul Mackerras August 1996.
5 * Copyright (C) 1996-2005 Paul Mackerras.
6 *
7 * Adapted for 64bit PowerPC by Dave Engebretsen and Peter Bergner.
8 * {engebret|bergner}@us.ibm.com
9 *
10 * Adapted for sparc64 by David S. Miller davem@davemloft.net
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/mm.h>
22 #include <linux/bootmem.h>
23 #include <linux/module.h>
24
25 #include <asm/prom.h>
26 #include <asm/of_device.h>
27 #include <asm/oplib.h>
28 #include <asm/irq.h>
29 #include <asm/asi.h>
30 #include <asm/upa.h>
31 #include <asm/smp.h>
32
33 extern struct device_node *allnodes; /* temporary while merging */
34
35 extern rwlock_t devtree_lock; /* temporary while merging */
36
37 struct device_node *of_find_node_by_phandle(phandle handle)
38 {
39 struct device_node *np;
40
41 for (np = allnodes; np != 0; np = np->allnext)
42 if (np->node == handle)
43 break;
44
45 return np;
46 }
47 EXPORT_SYMBOL(of_find_node_by_phandle);
48
49 int of_getintprop_default(struct device_node *np, const char *name, int def)
50 {
51 struct property *prop;
52 int len;
53
54 prop = of_find_property(np, name, &len);
55 if (!prop || len != 4)
56 return def;
57
58 return *(int *) prop->value;
59 }
60 EXPORT_SYMBOL(of_getintprop_default);
61
62 int of_set_property(struct device_node *dp, const char *name, void *val, int len)
63 {
64 struct property **prevp;
65 void *new_val;
66 int err;
67
68 new_val = kmalloc(len, GFP_KERNEL);
69 if (!new_val)
70 return -ENOMEM;
71
72 memcpy(new_val, val, len);
73
74 err = -ENODEV;
75
76 write_lock(&devtree_lock);
77 prevp = &dp->properties;
78 while (*prevp) {
79 struct property *prop = *prevp;
80
81 if (!strcasecmp(prop->name, name)) {
82 void *old_val = prop->value;
83 int ret;
84
85 ret = prom_setprop(dp->node, name, val, len);
86 err = -EINVAL;
87 if (ret >= 0) {
88 prop->value = new_val;
89 prop->length = len;
90
91 if (OF_IS_DYNAMIC(prop))
92 kfree(old_val);
93
94 OF_MARK_DYNAMIC(prop);
95
96 err = 0;
97 }
98 break;
99 }
100 prevp = &(*prevp)->next;
101 }
102 write_unlock(&devtree_lock);
103
104 /* XXX Upate procfs if necessary... */
105
106 return err;
107 }
108 EXPORT_SYMBOL(of_set_property);
109
110 int of_find_in_proplist(const char *list, const char *match, int len)
111 {
112 while (len > 0) {
113 int l;
114
115 if (!strcmp(list, match))
116 return 1;
117 l = strlen(list) + 1;
118 list += l;
119 len -= l;
120 }
121 return 0;
122 }
123 EXPORT_SYMBOL(of_find_in_proplist);
124
125 static unsigned int prom_early_allocated;
126
127 static void * __init prom_early_alloc(unsigned long size)
128 {
129 void *ret;
130
131 ret = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL);
132 if (ret != NULL)
133 memset(ret, 0, size);
134
135 prom_early_allocated += size;
136
137 return ret;
138 }
139
140 #ifdef CONFIG_PCI
141 /* PSYCHO interrupt mapping support. */
142 #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
143 #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
144 static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
145 {
146 unsigned int bus = (ino & 0x10) >> 4;
147 unsigned int slot = (ino & 0x0c) >> 2;
148
149 if (bus == 0)
150 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
151 else
152 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
153 }
154
155 #define PSYCHO_IMAP_SCSI 0x1000UL
156 #define PSYCHO_IMAP_ETH 0x1008UL
157 #define PSYCHO_IMAP_BPP 0x1010UL
158 #define PSYCHO_IMAP_AU_REC 0x1018UL
159 #define PSYCHO_IMAP_AU_PLAY 0x1020UL
160 #define PSYCHO_IMAP_PFAIL 0x1028UL
161 #define PSYCHO_IMAP_KMS 0x1030UL
162 #define PSYCHO_IMAP_FLPY 0x1038UL
163 #define PSYCHO_IMAP_SHW 0x1040UL
164 #define PSYCHO_IMAP_KBD 0x1048UL
165 #define PSYCHO_IMAP_MS 0x1050UL
166 #define PSYCHO_IMAP_SER 0x1058UL
167 #define PSYCHO_IMAP_TIM0 0x1060UL
168 #define PSYCHO_IMAP_TIM1 0x1068UL
169 #define PSYCHO_IMAP_UE 0x1070UL
170 #define PSYCHO_IMAP_CE 0x1078UL
171 #define PSYCHO_IMAP_A_ERR 0x1080UL
172 #define PSYCHO_IMAP_B_ERR 0x1088UL
173 #define PSYCHO_IMAP_PMGMT 0x1090UL
174 #define PSYCHO_IMAP_GFX 0x1098UL
175 #define PSYCHO_IMAP_EUPA 0x10a0UL
176
177 static unsigned long __psycho_onboard_imap_off[] = {
178 /*0x20*/ PSYCHO_IMAP_SCSI,
179 /*0x21*/ PSYCHO_IMAP_ETH,
180 /*0x22*/ PSYCHO_IMAP_BPP,
181 /*0x23*/ PSYCHO_IMAP_AU_REC,
182 /*0x24*/ PSYCHO_IMAP_AU_PLAY,
183 /*0x25*/ PSYCHO_IMAP_PFAIL,
184 /*0x26*/ PSYCHO_IMAP_KMS,
185 /*0x27*/ PSYCHO_IMAP_FLPY,
186 /*0x28*/ PSYCHO_IMAP_SHW,
187 /*0x29*/ PSYCHO_IMAP_KBD,
188 /*0x2a*/ PSYCHO_IMAP_MS,
189 /*0x2b*/ PSYCHO_IMAP_SER,
190 /*0x2c*/ PSYCHO_IMAP_TIM0,
191 /*0x2d*/ PSYCHO_IMAP_TIM1,
192 /*0x2e*/ PSYCHO_IMAP_UE,
193 /*0x2f*/ PSYCHO_IMAP_CE,
194 /*0x30*/ PSYCHO_IMAP_A_ERR,
195 /*0x31*/ PSYCHO_IMAP_B_ERR,
196 /*0x32*/ PSYCHO_IMAP_PMGMT,
197 /*0x33*/ PSYCHO_IMAP_GFX,
198 /*0x34*/ PSYCHO_IMAP_EUPA,
199 };
200 #define PSYCHO_ONBOARD_IRQ_BASE 0x20
201 #define PSYCHO_ONBOARD_IRQ_LAST 0x34
202 #define psycho_onboard_imap_offset(__ino) \
203 __psycho_onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
204
205 #define PSYCHO_ICLR_A_SLOT0 0x1400UL
206 #define PSYCHO_ICLR_SCSI 0x1800UL
207
208 #define psycho_iclr_offset(ino) \
209 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
210 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
211
212 static unsigned int psycho_irq_build(struct device_node *dp,
213 unsigned int ino,
214 void *_data)
215 {
216 unsigned long controller_regs = (unsigned long) _data;
217 unsigned long imap, iclr;
218 unsigned long imap_off, iclr_off;
219 int inofixup = 0;
220
221 ino &= 0x3f;
222 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
223 /* PCI slot */
224 imap_off = psycho_pcislot_imap_offset(ino);
225 } else {
226 /* Onboard device */
227 if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
228 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
229 prom_halt();
230 }
231 imap_off = psycho_onboard_imap_offset(ino);
232 }
233
234 /* Now build the IRQ bucket. */
235 imap = controller_regs + imap_off;
236
237 iclr_off = psycho_iclr_offset(ino);
238 iclr = controller_regs + iclr_off;
239
240 if ((ino & 0x20) == 0)
241 inofixup = ino & 0x03;
242
243 return build_irq(inofixup, iclr, imap);
244 }
245
246 static void __init psycho_irq_trans_init(struct device_node *dp)
247 {
248 const struct linux_prom64_registers *regs;
249
250 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
251 dp->irq_trans->irq_build = psycho_irq_build;
252
253 regs = of_get_property(dp, "reg", NULL);
254 dp->irq_trans->data = (void *) regs[2].phys_addr;
255 }
256
257 #define sabre_read(__reg) \
258 ({ u64 __ret; \
259 __asm__ __volatile__("ldxa [%1] %2, %0" \
260 : "=r" (__ret) \
261 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
262 : "memory"); \
263 __ret; \
264 })
265
266 struct sabre_irq_data {
267 unsigned long controller_regs;
268 unsigned int pci_first_busno;
269 };
270 #define SABRE_CONFIGSPACE 0x001000000UL
271 #define SABRE_WRSYNC 0x1c20UL
272
273 #define SABRE_CONFIG_BASE(CONFIG_SPACE) \
274 (CONFIG_SPACE | (1UL << 24))
275 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
276 (((unsigned long)(BUS) << 16) | \
277 ((unsigned long)(DEVFN) << 8) | \
278 ((unsigned long)(REG)))
279
280 /* When a device lives behind a bridge deeper in the PCI bus topology
281 * than APB, a special sequence must run to make sure all pending DMA
282 * transfers at the time of IRQ delivery are visible in the coherency
283 * domain by the cpu. This sequence is to perform a read on the far
284 * side of the non-APB bridge, then perform a read of Sabre's DMA
285 * write-sync register.
286 */
287 static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
288 {
289 unsigned int phys_hi = (unsigned int) (unsigned long) _arg1;
290 struct sabre_irq_data *irq_data = _arg2;
291 unsigned long controller_regs = irq_data->controller_regs;
292 unsigned long sync_reg = controller_regs + SABRE_WRSYNC;
293 unsigned long config_space = controller_regs + SABRE_CONFIGSPACE;
294 unsigned int bus, devfn;
295 u16 _unused;
296
297 config_space = SABRE_CONFIG_BASE(config_space);
298
299 bus = (phys_hi >> 16) & 0xff;
300 devfn = (phys_hi >> 8) & 0xff;
301
302 config_space |= SABRE_CONFIG_ENCODE(bus, devfn, 0x00);
303
304 __asm__ __volatile__("membar #Sync\n\t"
305 "lduha [%1] %2, %0\n\t"
306 "membar #Sync"
307 : "=r" (_unused)
308 : "r" ((u16 *) config_space),
309 "i" (ASI_PHYS_BYPASS_EC_E_L)
310 : "memory");
311
312 sabre_read(sync_reg);
313 }
314
315 #define SABRE_IMAP_A_SLOT0 0x0c00UL
316 #define SABRE_IMAP_B_SLOT0 0x0c20UL
317 #define SABRE_IMAP_SCSI 0x1000UL
318 #define SABRE_IMAP_ETH 0x1008UL
319 #define SABRE_IMAP_BPP 0x1010UL
320 #define SABRE_IMAP_AU_REC 0x1018UL
321 #define SABRE_IMAP_AU_PLAY 0x1020UL
322 #define SABRE_IMAP_PFAIL 0x1028UL
323 #define SABRE_IMAP_KMS 0x1030UL
324 #define SABRE_IMAP_FLPY 0x1038UL
325 #define SABRE_IMAP_SHW 0x1040UL
326 #define SABRE_IMAP_KBD 0x1048UL
327 #define SABRE_IMAP_MS 0x1050UL
328 #define SABRE_IMAP_SER 0x1058UL
329 #define SABRE_IMAP_UE 0x1070UL
330 #define SABRE_IMAP_CE 0x1078UL
331 #define SABRE_IMAP_PCIERR 0x1080UL
332 #define SABRE_IMAP_GFX 0x1098UL
333 #define SABRE_IMAP_EUPA 0x10a0UL
334 #define SABRE_ICLR_A_SLOT0 0x1400UL
335 #define SABRE_ICLR_B_SLOT0 0x1480UL
336 #define SABRE_ICLR_SCSI 0x1800UL
337 #define SABRE_ICLR_ETH 0x1808UL
338 #define SABRE_ICLR_BPP 0x1810UL
339 #define SABRE_ICLR_AU_REC 0x1818UL
340 #define SABRE_ICLR_AU_PLAY 0x1820UL
341 #define SABRE_ICLR_PFAIL 0x1828UL
342 #define SABRE_ICLR_KMS 0x1830UL
343 #define SABRE_ICLR_FLPY 0x1838UL
344 #define SABRE_ICLR_SHW 0x1840UL
345 #define SABRE_ICLR_KBD 0x1848UL
346 #define SABRE_ICLR_MS 0x1850UL
347 #define SABRE_ICLR_SER 0x1858UL
348 #define SABRE_ICLR_UE 0x1870UL
349 #define SABRE_ICLR_CE 0x1878UL
350 #define SABRE_ICLR_PCIERR 0x1880UL
351
352 static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
353 {
354 unsigned int bus = (ino & 0x10) >> 4;
355 unsigned int slot = (ino & 0x0c) >> 2;
356
357 if (bus == 0)
358 return SABRE_IMAP_A_SLOT0 + (slot * 8);
359 else
360 return SABRE_IMAP_B_SLOT0 + (slot * 8);
361 }
362
363 static unsigned long __sabre_onboard_imap_off[] = {
364 /*0x20*/ SABRE_IMAP_SCSI,
365 /*0x21*/ SABRE_IMAP_ETH,
366 /*0x22*/ SABRE_IMAP_BPP,
367 /*0x23*/ SABRE_IMAP_AU_REC,
368 /*0x24*/ SABRE_IMAP_AU_PLAY,
369 /*0x25*/ SABRE_IMAP_PFAIL,
370 /*0x26*/ SABRE_IMAP_KMS,
371 /*0x27*/ SABRE_IMAP_FLPY,
372 /*0x28*/ SABRE_IMAP_SHW,
373 /*0x29*/ SABRE_IMAP_KBD,
374 /*0x2a*/ SABRE_IMAP_MS,
375 /*0x2b*/ SABRE_IMAP_SER,
376 /*0x2c*/ 0 /* reserved */,
377 /*0x2d*/ 0 /* reserved */,
378 /*0x2e*/ SABRE_IMAP_UE,
379 /*0x2f*/ SABRE_IMAP_CE,
380 /*0x30*/ SABRE_IMAP_PCIERR,
381 /*0x31*/ 0 /* reserved */,
382 /*0x32*/ 0 /* reserved */,
383 /*0x33*/ SABRE_IMAP_GFX,
384 /*0x34*/ SABRE_IMAP_EUPA,
385 };
386 #define SABRE_ONBOARD_IRQ_BASE 0x20
387 #define SABRE_ONBOARD_IRQ_LAST 0x30
388 #define sabre_onboard_imap_offset(__ino) \
389 __sabre_onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
390
391 #define sabre_iclr_offset(ino) \
392 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
393 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
394
395 static int sabre_device_needs_wsync(struct device_node *dp)
396 {
397 struct device_node *parent = dp->parent;
398 const char *parent_model, *parent_compat;
399
400 /* This traversal up towards the root is meant to
401 * handle two cases:
402 *
403 * 1) non-PCI bus sitting under PCI, such as 'ebus'
404 * 2) the PCI controller interrupts themselves, which
405 * will use the sabre_irq_build but do not need
406 * the DMA synchronization handling
407 */
408 while (parent) {
409 if (!strcmp(parent->type, "pci"))
410 break;
411 parent = parent->parent;
412 }
413
414 if (!parent)
415 return 0;
416
417 parent_model = of_get_property(parent,
418 "model", NULL);
419 if (parent_model &&
420 (!strcmp(parent_model, "SUNW,sabre") ||
421 !strcmp(parent_model, "SUNW,simba")))
422 return 0;
423
424 parent_compat = of_get_property(parent,
425 "compatible", NULL);
426 if (parent_compat &&
427 (!strcmp(parent_compat, "pci108e,a000") ||
428 !strcmp(parent_compat, "pci108e,a001")))
429 return 0;
430
431 return 1;
432 }
433
434 static unsigned int sabre_irq_build(struct device_node *dp,
435 unsigned int ino,
436 void *_data)
437 {
438 struct sabre_irq_data *irq_data = _data;
439 unsigned long controller_regs = irq_data->controller_regs;
440 const struct linux_prom_pci_registers *regs;
441 unsigned long imap, iclr;
442 unsigned long imap_off, iclr_off;
443 int inofixup = 0;
444 int virt_irq;
445
446 ino &= 0x3f;
447 if (ino < SABRE_ONBOARD_IRQ_BASE) {
448 /* PCI slot */
449 imap_off = sabre_pcislot_imap_offset(ino);
450 } else {
451 /* onboard device */
452 if (ino > SABRE_ONBOARD_IRQ_LAST) {
453 prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
454 prom_halt();
455 }
456 imap_off = sabre_onboard_imap_offset(ino);
457 }
458
459 /* Now build the IRQ bucket. */
460 imap = controller_regs + imap_off;
461
462 iclr_off = sabre_iclr_offset(ino);
463 iclr = controller_regs + iclr_off;
464
465 if ((ino & 0x20) == 0)
466 inofixup = ino & 0x03;
467
468 virt_irq = build_irq(inofixup, iclr, imap);
469
470 /* If the parent device is a PCI<->PCI bridge other than
471 * APB, we have to install a pre-handler to ensure that
472 * all pending DMA is drained before the interrupt handler
473 * is run.
474 */
475 regs = of_get_property(dp, "reg", NULL);
476 if (regs && sabre_device_needs_wsync(dp)) {
477 irq_install_pre_handler(virt_irq,
478 sabre_wsync_handler,
479 (void *) (long) regs->phys_hi,
480 (void *) irq_data);
481 }
482
483 return virt_irq;
484 }
485
486 static void __init sabre_irq_trans_init(struct device_node *dp)
487 {
488 const struct linux_prom64_registers *regs;
489 struct sabre_irq_data *irq_data;
490 const u32 *busrange;
491
492 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
493 dp->irq_trans->irq_build = sabre_irq_build;
494
495 irq_data = prom_early_alloc(sizeof(struct sabre_irq_data));
496
497 regs = of_get_property(dp, "reg", NULL);
498 irq_data->controller_regs = regs[0].phys_addr;
499
500 busrange = of_get_property(dp, "bus-range", NULL);
501 irq_data->pci_first_busno = busrange[0];
502
503 dp->irq_trans->data = irq_data;
504 }
505
506 /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
507 * imap/iclr registers are per-PBM.
508 */
509 #define SCHIZO_IMAP_BASE 0x1000UL
510 #define SCHIZO_ICLR_BASE 0x1400UL
511
512 static unsigned long schizo_imap_offset(unsigned long ino)
513 {
514 return SCHIZO_IMAP_BASE + (ino * 8UL);
515 }
516
517 static unsigned long schizo_iclr_offset(unsigned long ino)
518 {
519 return SCHIZO_ICLR_BASE + (ino * 8UL);
520 }
521
522 static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs,
523 unsigned int ino)
524 {
525
526 return pbm_regs + schizo_iclr_offset(ino);
527 }
528
529 static unsigned long schizo_ino_to_imap(unsigned long pbm_regs,
530 unsigned int ino)
531 {
532 return pbm_regs + schizo_imap_offset(ino);
533 }
534
535 #define schizo_read(__reg) \
536 ({ u64 __ret; \
537 __asm__ __volatile__("ldxa [%1] %2, %0" \
538 : "=r" (__ret) \
539 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
540 : "memory"); \
541 __ret; \
542 })
543 #define schizo_write(__reg, __val) \
544 __asm__ __volatile__("stxa %0, [%1] %2" \
545 : /* no outputs */ \
546 : "r" (__val), "r" (__reg), \
547 "i" (ASI_PHYS_BYPASS_EC_E) \
548 : "memory")
549
550 static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
551 {
552 unsigned long sync_reg = (unsigned long) _arg2;
553 u64 mask = 1UL << (ino & IMAP_INO);
554 u64 val;
555 int limit;
556
557 schizo_write(sync_reg, mask);
558
559 limit = 100000;
560 val = 0;
561 while (--limit) {
562 val = schizo_read(sync_reg);
563 if (!(val & mask))
564 break;
565 }
566 if (limit <= 0) {
567 printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n",
568 val, mask);
569 }
570
571 if (_arg1) {
572 static unsigned char cacheline[64]
573 __attribute__ ((aligned (64)));
574
575 __asm__ __volatile__("rd %%fprs, %0\n\t"
576 "or %0, %4, %1\n\t"
577 "wr %1, 0x0, %%fprs\n\t"
578 "stda %%f0, [%5] %6\n\t"
579 "wr %0, 0x0, %%fprs\n\t"
580 "membar #Sync"
581 : "=&r" (mask), "=&r" (val)
582 : "0" (mask), "1" (val),
583 "i" (FPRS_FEF), "r" (&cacheline[0]),
584 "i" (ASI_BLK_COMMIT_P));
585 }
586 }
587
588 struct schizo_irq_data {
589 unsigned long pbm_regs;
590 unsigned long sync_reg;
591 u32 portid;
592 int chip_version;
593 };
594
595 static unsigned int schizo_irq_build(struct device_node *dp,
596 unsigned int ino,
597 void *_data)
598 {
599 struct schizo_irq_data *irq_data = _data;
600 unsigned long pbm_regs = irq_data->pbm_regs;
601 unsigned long imap, iclr;
602 int ign_fixup;
603 int virt_irq;
604 int is_tomatillo;
605
606 ino &= 0x3f;
607
608 /* Now build the IRQ bucket. */
609 imap = schizo_ino_to_imap(pbm_regs, ino);
610 iclr = schizo_ino_to_iclr(pbm_regs, ino);
611
612 /* On Schizo, no inofixup occurs. This is because each
613 * INO has it's own IMAP register. On Psycho and Sabre
614 * there is only one IMAP register for each PCI slot even
615 * though four different INOs can be generated by each
616 * PCI slot.
617 *
618 * But, for JBUS variants (essentially, Tomatillo), we have
619 * to fixup the lowest bit of the interrupt group number.
620 */
621 ign_fixup = 0;
622
623 is_tomatillo = (irq_data->sync_reg != 0UL);
624
625 if (is_tomatillo) {
626 if (irq_data->portid & 1)
627 ign_fixup = (1 << 6);
628 }
629
630 virt_irq = build_irq(ign_fixup, iclr, imap);
631
632 if (is_tomatillo) {
633 irq_install_pre_handler(virt_irq,
634 tomatillo_wsync_handler,
635 ((irq_data->chip_version <= 4) ?
636 (void *) 1 : (void *) 0),
637 (void *) irq_data->sync_reg);
638 }
639
640 return virt_irq;
641 }
642
643 static void __init __schizo_irq_trans_init(struct device_node *dp,
644 int is_tomatillo)
645 {
646 const struct linux_prom64_registers *regs;
647 struct schizo_irq_data *irq_data;
648
649 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
650 dp->irq_trans->irq_build = schizo_irq_build;
651
652 irq_data = prom_early_alloc(sizeof(struct schizo_irq_data));
653
654 regs = of_get_property(dp, "reg", NULL);
655 dp->irq_trans->data = irq_data;
656
657 irq_data->pbm_regs = regs[0].phys_addr;
658 if (is_tomatillo)
659 irq_data->sync_reg = regs[3].phys_addr + 0x1a18UL;
660 else
661 irq_data->sync_reg = 0UL;
662 irq_data->portid = of_getintprop_default(dp, "portid", 0);
663 irq_data->chip_version = of_getintprop_default(dp, "version#", 0);
664 }
665
666 static void __init schizo_irq_trans_init(struct device_node *dp)
667 {
668 __schizo_irq_trans_init(dp, 0);
669 }
670
671 static void __init tomatillo_irq_trans_init(struct device_node *dp)
672 {
673 __schizo_irq_trans_init(dp, 1);
674 }
675
676 static unsigned int pci_sun4v_irq_build(struct device_node *dp,
677 unsigned int devino,
678 void *_data)
679 {
680 u32 devhandle = (u32) (unsigned long) _data;
681
682 return sun4v_build_irq(devhandle, devino);
683 }
684
685 static void __init pci_sun4v_irq_trans_init(struct device_node *dp)
686 {
687 const struct linux_prom64_registers *regs;
688
689 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
690 dp->irq_trans->irq_build = pci_sun4v_irq_build;
691
692 regs = of_get_property(dp, "reg", NULL);
693 dp->irq_trans->data = (void *) (unsigned long)
694 ((regs->phys_addr >> 32UL) & 0x0fffffff);
695 }
696
697 struct fire_irq_data {
698 unsigned long pbm_regs;
699 u32 portid;
700 };
701
702 #define FIRE_IMAP_BASE 0x001000
703 #define FIRE_ICLR_BASE 0x001400
704
705 static unsigned long fire_imap_offset(unsigned long ino)
706 {
707 return FIRE_IMAP_BASE + (ino * 8UL);
708 }
709
710 static unsigned long fire_iclr_offset(unsigned long ino)
711 {
712 return FIRE_ICLR_BASE + (ino * 8UL);
713 }
714
715 static unsigned long fire_ino_to_iclr(unsigned long pbm_regs,
716 unsigned int ino)
717 {
718 return pbm_regs + fire_iclr_offset(ino);
719 }
720
721 static unsigned long fire_ino_to_imap(unsigned long pbm_regs,
722 unsigned int ino)
723 {
724 return pbm_regs + fire_imap_offset(ino);
725 }
726
727 static unsigned int fire_irq_build(struct device_node *dp,
728 unsigned int ino,
729 void *_data)
730 {
731 struct fire_irq_data *irq_data = _data;
732 unsigned long pbm_regs = irq_data->pbm_regs;
733 unsigned long imap, iclr;
734 unsigned long int_ctrlr;
735
736 ino &= 0x3f;
737
738 /* Now build the IRQ bucket. */
739 imap = fire_ino_to_imap(pbm_regs, ino);
740 iclr = fire_ino_to_iclr(pbm_regs, ino);
741
742 /* Set the interrupt controller number. */
743 int_ctrlr = 1 << 6;
744 upa_writeq(int_ctrlr, imap);
745
746 /* The interrupt map registers do not have an INO field
747 * like other chips do. They return zero in the INO
748 * field, and the interrupt controller number is controlled
749 * in bits 6 to 9. So in order for build_irq() to get
750 * the INO right we pass it in as part of the fixup
751 * which will get added to the map register zero value
752 * read by build_irq().
753 */
754 ino |= (irq_data->portid << 6);
755 ino -= int_ctrlr;
756 return build_irq(ino, iclr, imap);
757 }
758
759 static void __init fire_irq_trans_init(struct device_node *dp)
760 {
761 const struct linux_prom64_registers *regs;
762 struct fire_irq_data *irq_data;
763
764 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
765 dp->irq_trans->irq_build = fire_irq_build;
766
767 irq_data = prom_early_alloc(sizeof(struct fire_irq_data));
768
769 regs = of_get_property(dp, "reg", NULL);
770 dp->irq_trans->data = irq_data;
771
772 irq_data->pbm_regs = regs[0].phys_addr;
773 irq_data->portid = of_getintprop_default(dp, "portid", 0);
774 }
775 #endif /* CONFIG_PCI */
776
777 #ifdef CONFIG_SBUS
778 /* INO number to IMAP register offset for SYSIO external IRQ's.
779 * This should conform to both Sunfire/Wildfire server and Fusion
780 * desktop designs.
781 */
782 #define SYSIO_IMAP_SLOT0 0x2c00UL
783 #define SYSIO_IMAP_SLOT1 0x2c08UL
784 #define SYSIO_IMAP_SLOT2 0x2c10UL
785 #define SYSIO_IMAP_SLOT3 0x2c18UL
786 #define SYSIO_IMAP_SCSI 0x3000UL
787 #define SYSIO_IMAP_ETH 0x3008UL
788 #define SYSIO_IMAP_BPP 0x3010UL
789 #define SYSIO_IMAP_AUDIO 0x3018UL
790 #define SYSIO_IMAP_PFAIL 0x3020UL
791 #define SYSIO_IMAP_KMS 0x3028UL
792 #define SYSIO_IMAP_FLPY 0x3030UL
793 #define SYSIO_IMAP_SHW 0x3038UL
794 #define SYSIO_IMAP_KBD 0x3040UL
795 #define SYSIO_IMAP_MS 0x3048UL
796 #define SYSIO_IMAP_SER 0x3050UL
797 #define SYSIO_IMAP_TIM0 0x3060UL
798 #define SYSIO_IMAP_TIM1 0x3068UL
799 #define SYSIO_IMAP_UE 0x3070UL
800 #define SYSIO_IMAP_CE 0x3078UL
801 #define SYSIO_IMAP_SBERR 0x3080UL
802 #define SYSIO_IMAP_PMGMT 0x3088UL
803 #define SYSIO_IMAP_GFX 0x3090UL
804 #define SYSIO_IMAP_EUPA 0x3098UL
805
806 #define bogon ((unsigned long) -1)
807 static unsigned long sysio_irq_offsets[] = {
808 /* SBUS Slot 0 --> 3, level 1 --> 7 */
809 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
810 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
811 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
812 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
813 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
814 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
815 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
816 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
817
818 /* Onboard devices (not relevant/used on SunFire). */
819 SYSIO_IMAP_SCSI,
820 SYSIO_IMAP_ETH,
821 SYSIO_IMAP_BPP,
822 bogon,
823 SYSIO_IMAP_AUDIO,
824 SYSIO_IMAP_PFAIL,
825 bogon,
826 bogon,
827 SYSIO_IMAP_KMS,
828 SYSIO_IMAP_FLPY,
829 SYSIO_IMAP_SHW,
830 SYSIO_IMAP_KBD,
831 SYSIO_IMAP_MS,
832 SYSIO_IMAP_SER,
833 bogon,
834 bogon,
835 SYSIO_IMAP_TIM0,
836 SYSIO_IMAP_TIM1,
837 bogon,
838 bogon,
839 SYSIO_IMAP_UE,
840 SYSIO_IMAP_CE,
841 SYSIO_IMAP_SBERR,
842 SYSIO_IMAP_PMGMT,
843 SYSIO_IMAP_GFX,
844 SYSIO_IMAP_EUPA,
845 };
846
847 #undef bogon
848
849 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
850
851 /* Convert Interrupt Mapping register pointer to associated
852 * Interrupt Clear register pointer, SYSIO specific version.
853 */
854 #define SYSIO_ICLR_UNUSED0 0x3400UL
855 #define SYSIO_ICLR_SLOT0 0x3408UL
856 #define SYSIO_ICLR_SLOT1 0x3448UL
857 #define SYSIO_ICLR_SLOT2 0x3488UL
858 #define SYSIO_ICLR_SLOT3 0x34c8UL
859 static unsigned long sysio_imap_to_iclr(unsigned long imap)
860 {
861 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
862 return imap + diff;
863 }
864
865 static unsigned int sbus_of_build_irq(struct device_node *dp,
866 unsigned int ino,
867 void *_data)
868 {
869 unsigned long reg_base = (unsigned long) _data;
870 const struct linux_prom_registers *regs;
871 unsigned long imap, iclr;
872 int sbus_slot = 0;
873 int sbus_level = 0;
874
875 ino &= 0x3f;
876
877 regs = of_get_property(dp, "reg", NULL);
878 if (regs)
879 sbus_slot = regs->which_io;
880
881 if (ino < 0x20)
882 ino += (sbus_slot * 8);
883
884 imap = sysio_irq_offsets[ino];
885 if (imap == ((unsigned long)-1)) {
886 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
887 ino);
888 prom_halt();
889 }
890 imap += reg_base;
891
892 /* SYSIO inconsistency. For external SLOTS, we have to select
893 * the right ICLR register based upon the lower SBUS irq level
894 * bits.
895 */
896 if (ino >= 0x20) {
897 iclr = sysio_imap_to_iclr(imap);
898 } else {
899 sbus_level = ino & 0x7;
900
901 switch(sbus_slot) {
902 case 0:
903 iclr = reg_base + SYSIO_ICLR_SLOT0;
904 break;
905 case 1:
906 iclr = reg_base + SYSIO_ICLR_SLOT1;
907 break;
908 case 2:
909 iclr = reg_base + SYSIO_ICLR_SLOT2;
910 break;
911 default:
912 case 3:
913 iclr = reg_base + SYSIO_ICLR_SLOT3;
914 break;
915 };
916
917 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
918 }
919 return build_irq(sbus_level, iclr, imap);
920 }
921
922 static void __init sbus_irq_trans_init(struct device_node *dp)
923 {
924 const struct linux_prom64_registers *regs;
925
926 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
927 dp->irq_trans->irq_build = sbus_of_build_irq;
928
929 regs = of_get_property(dp, "reg", NULL);
930 dp->irq_trans->data = (void *) (unsigned long) regs->phys_addr;
931 }
932 #endif /* CONFIG_SBUS */
933
934
935 static unsigned int central_build_irq(struct device_node *dp,
936 unsigned int ino,
937 void *_data)
938 {
939 struct device_node *central_dp = _data;
940 struct of_device *central_op = of_find_device_by_node(central_dp);
941 struct resource *res;
942 unsigned long imap, iclr;
943 u32 tmp;
944
945 if (!strcmp(dp->name, "eeprom")) {
946 res = &central_op->resource[5];
947 } else if (!strcmp(dp->name, "zs")) {
948 res = &central_op->resource[4];
949 } else if (!strcmp(dp->name, "clock-board")) {
950 res = &central_op->resource[3];
951 } else {
952 return ino;
953 }
954
955 imap = res->start + 0x00UL;
956 iclr = res->start + 0x10UL;
957
958 /* Set the INO state to idle, and disable. */
959 upa_writel(0, iclr);
960 upa_readl(iclr);
961
962 tmp = upa_readl(imap);
963 tmp &= ~0x80000000;
964 upa_writel(tmp, imap);
965
966 return build_irq(0, iclr, imap);
967 }
968
969 static void __init central_irq_trans_init(struct device_node *dp)
970 {
971 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
972 dp->irq_trans->irq_build = central_build_irq;
973
974 dp->irq_trans->data = dp;
975 }
976
977 struct irq_trans {
978 const char *name;
979 void (*init)(struct device_node *);
980 };
981
982 #ifdef CONFIG_PCI
983 static struct irq_trans __initdata pci_irq_trans_table[] = {
984 { "SUNW,sabre", sabre_irq_trans_init },
985 { "pci108e,a000", sabre_irq_trans_init },
986 { "pci108e,a001", sabre_irq_trans_init },
987 { "SUNW,psycho", psycho_irq_trans_init },
988 { "pci108e,8000", psycho_irq_trans_init },
989 { "SUNW,schizo", schizo_irq_trans_init },
990 { "pci108e,8001", schizo_irq_trans_init },
991 { "SUNW,schizo+", schizo_irq_trans_init },
992 { "pci108e,8002", schizo_irq_trans_init },
993 { "SUNW,tomatillo", tomatillo_irq_trans_init },
994 { "pci108e,a801", tomatillo_irq_trans_init },
995 { "SUNW,sun4v-pci", pci_sun4v_irq_trans_init },
996 { "pciex108e,80f0", fire_irq_trans_init },
997 };
998 #endif
999
1000 static unsigned int sun4v_vdev_irq_build(struct device_node *dp,
1001 unsigned int devino,
1002 void *_data)
1003 {
1004 u32 devhandle = (u32) (unsigned long) _data;
1005
1006 return sun4v_build_irq(devhandle, devino);
1007 }
1008
1009 static void __init sun4v_vdev_irq_trans_init(struct device_node *dp)
1010 {
1011 const struct linux_prom64_registers *regs;
1012
1013 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
1014 dp->irq_trans->irq_build = sun4v_vdev_irq_build;
1015
1016 regs = of_get_property(dp, "reg", NULL);
1017 dp->irq_trans->data = (void *) (unsigned long)
1018 ((regs->phys_addr >> 32UL) & 0x0fffffff);
1019 }
1020
1021 static void __init irq_trans_init(struct device_node *dp)
1022 {
1023 #ifdef CONFIG_PCI
1024 const char *model;
1025 int i;
1026 #endif
1027
1028 #ifdef CONFIG_PCI
1029 model = of_get_property(dp, "model", NULL);
1030 if (!model)
1031 model = of_get_property(dp, "compatible", NULL);
1032 if (model) {
1033 for (i = 0; i < ARRAY_SIZE(pci_irq_trans_table); i++) {
1034 struct irq_trans *t = &pci_irq_trans_table[i];
1035
1036 if (!strcmp(model, t->name))
1037 return t->init(dp);
1038 }
1039 }
1040 #endif
1041 #ifdef CONFIG_SBUS
1042 if (!strcmp(dp->name, "sbus") ||
1043 !strcmp(dp->name, "sbi"))
1044 return sbus_irq_trans_init(dp);
1045 #endif
1046 if (!strcmp(dp->name, "fhc") &&
1047 !strcmp(dp->parent->name, "central"))
1048 return central_irq_trans_init(dp);
1049 if (!strcmp(dp->name, "virtual-devices") ||
1050 !strcmp(dp->name, "niu"))
1051 return sun4v_vdev_irq_trans_init(dp);
1052 }
1053
1054 static int is_root_node(const struct device_node *dp)
1055 {
1056 if (!dp)
1057 return 0;
1058
1059 return (dp->parent == NULL);
1060 }
1061
1062 /* The following routines deal with the black magic of fully naming a
1063 * node.
1064 *
1065 * Certain well known named nodes are just the simple name string.
1066 *
1067 * Actual devices have an address specifier appended to the base name
1068 * string, like this "foo@addr". The "addr" can be in any number of
1069 * formats, and the platform plus the type of the node determine the
1070 * format and how it is constructed.
1071 *
1072 * For children of the ROOT node, the naming convention is fixed and
1073 * determined by whether this is a sun4u or sun4v system.
1074 *
1075 * For children of other nodes, it is bus type specific. So
1076 * we walk up the tree until we discover a "device_type" property
1077 * we recognize and we go from there.
1078 *
1079 * As an example, the boot device on my workstation has a full path:
1080 *
1081 * /pci@1e,600000/ide@d/disk@0,0:c
1082 */
1083 static void __init sun4v_path_component(struct device_node *dp, char *tmp_buf)
1084 {
1085 struct linux_prom64_registers *regs;
1086 struct property *rprop;
1087 u32 high_bits, low_bits, type;
1088
1089 rprop = of_find_property(dp, "reg", NULL);
1090 if (!rprop)
1091 return;
1092
1093 regs = rprop->value;
1094 if (!is_root_node(dp->parent)) {
1095 sprintf(tmp_buf, "%s@%x,%x",
1096 dp->name,
1097 (unsigned int) (regs->phys_addr >> 32UL),
1098 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1099 return;
1100 }
1101
1102 type = regs->phys_addr >> 60UL;
1103 high_bits = (regs->phys_addr >> 32UL) & 0x0fffffffUL;
1104 low_bits = (regs->phys_addr & 0xffffffffUL);
1105
1106 if (type == 0 || type == 8) {
1107 const char *prefix = (type == 0) ? "m" : "i";
1108
1109 if (low_bits)
1110 sprintf(tmp_buf, "%s@%s%x,%x",
1111 dp->name, prefix,
1112 high_bits, low_bits);
1113 else
1114 sprintf(tmp_buf, "%s@%s%x",
1115 dp->name,
1116 prefix,
1117 high_bits);
1118 } else if (type == 12) {
1119 sprintf(tmp_buf, "%s@%x",
1120 dp->name, high_bits);
1121 }
1122 }
1123
1124 static void __init sun4u_path_component(struct device_node *dp, char *tmp_buf)
1125 {
1126 struct linux_prom64_registers *regs;
1127 struct property *prop;
1128
1129 prop = of_find_property(dp, "reg", NULL);
1130 if (!prop)
1131 return;
1132
1133 regs = prop->value;
1134 if (!is_root_node(dp->parent)) {
1135 sprintf(tmp_buf, "%s@%x,%x",
1136 dp->name,
1137 (unsigned int) (regs->phys_addr >> 32UL),
1138 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1139 return;
1140 }
1141
1142 prop = of_find_property(dp, "upa-portid", NULL);
1143 if (!prop)
1144 prop = of_find_property(dp, "portid", NULL);
1145 if (prop) {
1146 unsigned long mask = 0xffffffffUL;
1147
1148 if (tlb_type >= cheetah)
1149 mask = 0x7fffff;
1150
1151 sprintf(tmp_buf, "%s@%x,%x",
1152 dp->name,
1153 *(u32 *)prop->value,
1154 (unsigned int) (regs->phys_addr & mask));
1155 }
1156 }
1157
1158 /* "name@slot,offset" */
1159 static void __init sbus_path_component(struct device_node *dp, char *tmp_buf)
1160 {
1161 struct linux_prom_registers *regs;
1162 struct property *prop;
1163
1164 prop = of_find_property(dp, "reg", NULL);
1165 if (!prop)
1166 return;
1167
1168 regs = prop->value;
1169 sprintf(tmp_buf, "%s@%x,%x",
1170 dp->name,
1171 regs->which_io,
1172 regs->phys_addr);
1173 }
1174
1175 /* "name@devnum[,func]" */
1176 static void __init pci_path_component(struct device_node *dp, char *tmp_buf)
1177 {
1178 struct linux_prom_pci_registers *regs;
1179 struct property *prop;
1180 unsigned int devfn;
1181
1182 prop = of_find_property(dp, "reg", NULL);
1183 if (!prop)
1184 return;
1185
1186 regs = prop->value;
1187 devfn = (regs->phys_hi >> 8) & 0xff;
1188 if (devfn & 0x07) {
1189 sprintf(tmp_buf, "%s@%x,%x",
1190 dp->name,
1191 devfn >> 3,
1192 devfn & 0x07);
1193 } else {
1194 sprintf(tmp_buf, "%s@%x",
1195 dp->name,
1196 devfn >> 3);
1197 }
1198 }
1199
1200 /* "name@UPA_PORTID,offset" */
1201 static void __init upa_path_component(struct device_node *dp, char *tmp_buf)
1202 {
1203 struct linux_prom64_registers *regs;
1204 struct property *prop;
1205
1206 prop = of_find_property(dp, "reg", NULL);
1207 if (!prop)
1208 return;
1209
1210 regs = prop->value;
1211
1212 prop = of_find_property(dp, "upa-portid", NULL);
1213 if (!prop)
1214 return;
1215
1216 sprintf(tmp_buf, "%s@%x,%x",
1217 dp->name,
1218 *(u32 *) prop->value,
1219 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1220 }
1221
1222 /* "name@reg" */
1223 static void __init vdev_path_component(struct device_node *dp, char *tmp_buf)
1224 {
1225 struct property *prop;
1226 u32 *regs;
1227
1228 prop = of_find_property(dp, "reg", NULL);
1229 if (!prop)
1230 return;
1231
1232 regs = prop->value;
1233
1234 sprintf(tmp_buf, "%s@%x", dp->name, *regs);
1235 }
1236
1237 /* "name@addrhi,addrlo" */
1238 static void __init ebus_path_component(struct device_node *dp, char *tmp_buf)
1239 {
1240 struct linux_prom64_registers *regs;
1241 struct property *prop;
1242
1243 prop = of_find_property(dp, "reg", NULL);
1244 if (!prop)
1245 return;
1246
1247 regs = prop->value;
1248
1249 sprintf(tmp_buf, "%s@%x,%x",
1250 dp->name,
1251 (unsigned int) (regs->phys_addr >> 32UL),
1252 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1253 }
1254
1255 /* "name@bus,addr" */
1256 static void __init i2c_path_component(struct device_node *dp, char *tmp_buf)
1257 {
1258 struct property *prop;
1259 u32 *regs;
1260
1261 prop = of_find_property(dp, "reg", NULL);
1262 if (!prop)
1263 return;
1264
1265 regs = prop->value;
1266
1267 /* This actually isn't right... should look at the #address-cells
1268 * property of the i2c bus node etc. etc.
1269 */
1270 sprintf(tmp_buf, "%s@%x,%x",
1271 dp->name, regs[0], regs[1]);
1272 }
1273
1274 /* "name@reg0[,reg1]" */
1275 static void __init usb_path_component(struct device_node *dp, char *tmp_buf)
1276 {
1277 struct property *prop;
1278 u32 *regs;
1279
1280 prop = of_find_property(dp, "reg", NULL);
1281 if (!prop)
1282 return;
1283
1284 regs = prop->value;
1285
1286 if (prop->length == sizeof(u32) || regs[1] == 1) {
1287 sprintf(tmp_buf, "%s@%x",
1288 dp->name, regs[0]);
1289 } else {
1290 sprintf(tmp_buf, "%s@%x,%x",
1291 dp->name, regs[0], regs[1]);
1292 }
1293 }
1294
1295 /* "name@reg0reg1[,reg2reg3]" */
1296 static void __init ieee1394_path_component(struct device_node *dp, char *tmp_buf)
1297 {
1298 struct property *prop;
1299 u32 *regs;
1300
1301 prop = of_find_property(dp, "reg", NULL);
1302 if (!prop)
1303 return;
1304
1305 regs = prop->value;
1306
1307 if (regs[2] || regs[3]) {
1308 sprintf(tmp_buf, "%s@%08x%08x,%04x%08x",
1309 dp->name, regs[0], regs[1], regs[2], regs[3]);
1310 } else {
1311 sprintf(tmp_buf, "%s@%08x%08x",
1312 dp->name, regs[0], regs[1]);
1313 }
1314 }
1315
1316 static void __init __build_path_component(struct device_node *dp, char *tmp_buf)
1317 {
1318 struct device_node *parent = dp->parent;
1319
1320 if (parent != NULL) {
1321 if (!strcmp(parent->type, "pci") ||
1322 !strcmp(parent->type, "pciex"))
1323 return pci_path_component(dp, tmp_buf);
1324 if (!strcmp(parent->type, "sbus"))
1325 return sbus_path_component(dp, tmp_buf);
1326 if (!strcmp(parent->type, "upa"))
1327 return upa_path_component(dp, tmp_buf);
1328 if (!strcmp(parent->type, "ebus"))
1329 return ebus_path_component(dp, tmp_buf);
1330 if (!strcmp(parent->name, "usb") ||
1331 !strcmp(parent->name, "hub"))
1332 return usb_path_component(dp, tmp_buf);
1333 if (!strcmp(parent->type, "i2c"))
1334 return i2c_path_component(dp, tmp_buf);
1335 if (!strcmp(parent->type, "firewire"))
1336 return ieee1394_path_component(dp, tmp_buf);
1337 if (!strcmp(parent->type, "virtual-devices"))
1338 return vdev_path_component(dp, tmp_buf);
1339
1340 /* "isa" is handled with platform naming */
1341 }
1342
1343 /* Use platform naming convention. */
1344 if (tlb_type == hypervisor)
1345 return sun4v_path_component(dp, tmp_buf);
1346 else
1347 return sun4u_path_component(dp, tmp_buf);
1348 }
1349
1350 static char * __init build_path_component(struct device_node *dp)
1351 {
1352 char tmp_buf[64], *n;
1353
1354 tmp_buf[0] = '\0';
1355 __build_path_component(dp, tmp_buf);
1356 if (tmp_buf[0] == '\0')
1357 strcpy(tmp_buf, dp->name);
1358
1359 n = prom_early_alloc(strlen(tmp_buf) + 1);
1360 strcpy(n, tmp_buf);
1361
1362 return n;
1363 }
1364
1365 static char * __init build_full_name(struct device_node *dp)
1366 {
1367 int len, ourlen, plen;
1368 char *n;
1369
1370 plen = strlen(dp->parent->full_name);
1371 ourlen = strlen(dp->path_component_name);
1372 len = ourlen + plen + 2;
1373
1374 n = prom_early_alloc(len);
1375 strcpy(n, dp->parent->full_name);
1376 if (!is_root_node(dp->parent)) {
1377 strcpy(n + plen, "/");
1378 plen++;
1379 }
1380 strcpy(n + plen, dp->path_component_name);
1381
1382 return n;
1383 }
1384
1385 static unsigned int unique_id;
1386
1387 static struct property * __init build_one_prop(phandle node, char *prev, char *special_name, void *special_val, int special_len)
1388 {
1389 static struct property *tmp = NULL;
1390 struct property *p;
1391
1392 if (tmp) {
1393 p = tmp;
1394 memset(p, 0, sizeof(*p) + 32);
1395 tmp = NULL;
1396 } else {
1397 p = prom_early_alloc(sizeof(struct property) + 32);
1398 p->unique_id = unique_id++;
1399 }
1400
1401 p->name = (char *) (p + 1);
1402 if (special_name) {
1403 strcpy(p->name, special_name);
1404 p->length = special_len;
1405 p->value = prom_early_alloc(special_len);
1406 memcpy(p->value, special_val, special_len);
1407 } else {
1408 if (prev == NULL) {
1409 prom_firstprop(node, p->name);
1410 } else {
1411 prom_nextprop(node, prev, p->name);
1412 }
1413 if (strlen(p->name) == 0) {
1414 tmp = p;
1415 return NULL;
1416 }
1417 p->length = prom_getproplen(node, p->name);
1418 if (p->length <= 0) {
1419 p->length = 0;
1420 } else {
1421 p->value = prom_early_alloc(p->length + 1);
1422 prom_getproperty(node, p->name, p->value, p->length);
1423 ((unsigned char *)p->value)[p->length] = '\0';
1424 }
1425 }
1426 return p;
1427 }
1428
1429 static struct property * __init build_prop_list(phandle node)
1430 {
1431 struct property *head, *tail;
1432
1433 head = tail = build_one_prop(node, NULL,
1434 ".node", &node, sizeof(node));
1435
1436 tail->next = build_one_prop(node, NULL, NULL, NULL, 0);
1437 tail = tail->next;
1438 while(tail) {
1439 tail->next = build_one_prop(node, tail->name,
1440 NULL, NULL, 0);
1441 tail = tail->next;
1442 }
1443
1444 return head;
1445 }
1446
1447 static char * __init get_one_property(phandle node, const char *name)
1448 {
1449 char *buf = "<NULL>";
1450 int len;
1451
1452 len = prom_getproplen(node, name);
1453 if (len > 0) {
1454 buf = prom_early_alloc(len);
1455 prom_getproperty(node, name, buf, len);
1456 }
1457
1458 return buf;
1459 }
1460
1461 static struct device_node * __init create_node(phandle node, struct device_node *parent)
1462 {
1463 struct device_node *dp;
1464
1465 if (!node)
1466 return NULL;
1467
1468 dp = prom_early_alloc(sizeof(*dp));
1469 dp->unique_id = unique_id++;
1470 dp->parent = parent;
1471
1472 kref_init(&dp->kref);
1473
1474 dp->name = get_one_property(node, "name");
1475 dp->type = get_one_property(node, "device_type");
1476 dp->node = node;
1477
1478 dp->properties = build_prop_list(node);
1479
1480 irq_trans_init(dp);
1481
1482 return dp;
1483 }
1484
1485 static struct device_node * __init build_tree(struct device_node *parent, phandle node, struct device_node ***nextp)
1486 {
1487 struct device_node *ret = NULL, *prev_sibling = NULL;
1488 struct device_node *dp;
1489
1490 while (1) {
1491 dp = create_node(node, parent);
1492 if (!dp)
1493 break;
1494
1495 if (prev_sibling)
1496 prev_sibling->sibling = dp;
1497
1498 if (!ret)
1499 ret = dp;
1500 prev_sibling = dp;
1501
1502 *(*nextp) = dp;
1503 *nextp = &dp->allnext;
1504
1505 dp->path_component_name = build_path_component(dp);
1506 dp->full_name = build_full_name(dp);
1507
1508 dp->child = build_tree(dp, prom_getchild(node), nextp);
1509
1510 node = prom_getsibling(node);
1511 }
1512
1513 return ret;
1514 }
1515
1516 static const char *get_mid_prop(void)
1517 {
1518 return (tlb_type == spitfire ? "upa-portid" : "portid");
1519 }
1520
1521 struct device_node *of_find_node_by_cpuid(int cpuid)
1522 {
1523 struct device_node *dp;
1524 const char *mid_prop = get_mid_prop();
1525
1526 for_each_node_by_type(dp, "cpu") {
1527 int id = of_getintprop_default(dp, mid_prop, -1);
1528 const char *this_mid_prop = mid_prop;
1529
1530 if (id < 0) {
1531 this_mid_prop = "cpuid";
1532 id = of_getintprop_default(dp, this_mid_prop, -1);
1533 }
1534
1535 if (id < 0) {
1536 prom_printf("OF: Serious problem, cpu lacks "
1537 "%s property", this_mid_prop);
1538 prom_halt();
1539 }
1540 if (cpuid == id)
1541 return dp;
1542 }
1543 return NULL;
1544 }
1545
1546 static void __init of_fill_in_cpu_data(void)
1547 {
1548 struct device_node *dp;
1549 const char *mid_prop = get_mid_prop();
1550
1551 ncpus_probed = 0;
1552 for_each_node_by_type(dp, "cpu") {
1553 int cpuid = of_getintprop_default(dp, mid_prop, -1);
1554 const char *this_mid_prop = mid_prop;
1555 struct device_node *portid_parent;
1556 int portid = -1;
1557
1558 portid_parent = NULL;
1559 if (cpuid < 0) {
1560 this_mid_prop = "cpuid";
1561 cpuid = of_getintprop_default(dp, this_mid_prop, -1);
1562 if (cpuid >= 0) {
1563 int limit = 2;
1564
1565 portid_parent = dp;
1566 while (limit--) {
1567 portid_parent = portid_parent->parent;
1568 if (!portid_parent)
1569 break;
1570 portid = of_getintprop_default(portid_parent,
1571 "portid", -1);
1572 if (portid >= 0)
1573 break;
1574 }
1575 }
1576 }
1577
1578 if (cpuid < 0) {
1579 prom_printf("OF: Serious problem, cpu lacks "
1580 "%s property", this_mid_prop);
1581 prom_halt();
1582 }
1583
1584 ncpus_probed++;
1585
1586 #ifdef CONFIG_SMP
1587 if (cpuid >= NR_CPUS) {
1588 printk(KERN_WARNING "Ignoring CPU %d which is "
1589 ">= NR_CPUS (%d)\n",
1590 cpuid, NR_CPUS);
1591 continue;
1592 }
1593 #else
1594 /* On uniprocessor we only want the values for the
1595 * real physical cpu the kernel booted onto, however
1596 * cpu_data() only has one entry at index 0.
1597 */
1598 if (cpuid != real_hard_smp_processor_id())
1599 continue;
1600 cpuid = 0;
1601 #endif
1602
1603 cpu_data(cpuid).clock_tick =
1604 of_getintprop_default(dp, "clock-frequency", 0);
1605
1606 if (portid_parent) {
1607 cpu_data(cpuid).dcache_size =
1608 of_getintprop_default(dp, "l1-dcache-size",
1609 16 * 1024);
1610 cpu_data(cpuid).dcache_line_size =
1611 of_getintprop_default(dp, "l1-dcache-line-size",
1612 32);
1613 cpu_data(cpuid).icache_size =
1614 of_getintprop_default(dp, "l1-icache-size",
1615 8 * 1024);
1616 cpu_data(cpuid).icache_line_size =
1617 of_getintprop_default(dp, "l1-icache-line-size",
1618 32);
1619 cpu_data(cpuid).ecache_size =
1620 of_getintprop_default(dp, "l2-cache-size", 0);
1621 cpu_data(cpuid).ecache_line_size =
1622 of_getintprop_default(dp, "l2-cache-line-size", 0);
1623 if (!cpu_data(cpuid).ecache_size ||
1624 !cpu_data(cpuid).ecache_line_size) {
1625 cpu_data(cpuid).ecache_size =
1626 of_getintprop_default(portid_parent,
1627 "l2-cache-size",
1628 (4 * 1024 * 1024));
1629 cpu_data(cpuid).ecache_line_size =
1630 of_getintprop_default(portid_parent,
1631 "l2-cache-line-size", 64);
1632 }
1633
1634 cpu_data(cpuid).core_id = portid + 1;
1635 cpu_data(cpuid).proc_id = portid;
1636 #ifdef CONFIG_SMP
1637 sparc64_multi_core = 1;
1638 #endif
1639 } else {
1640 cpu_data(cpuid).dcache_size =
1641 of_getintprop_default(dp, "dcache-size", 16 * 1024);
1642 cpu_data(cpuid).dcache_line_size =
1643 of_getintprop_default(dp, "dcache-line-size", 32);
1644
1645 cpu_data(cpuid).icache_size =
1646 of_getintprop_default(dp, "icache-size", 16 * 1024);
1647 cpu_data(cpuid).icache_line_size =
1648 of_getintprop_default(dp, "icache-line-size", 32);
1649
1650 cpu_data(cpuid).ecache_size =
1651 of_getintprop_default(dp, "ecache-size",
1652 (4 * 1024 * 1024));
1653 cpu_data(cpuid).ecache_line_size =
1654 of_getintprop_default(dp, "ecache-line-size", 64);
1655
1656 cpu_data(cpuid).core_id = 0;
1657 cpu_data(cpuid).proc_id = -1;
1658 }
1659
1660 #ifdef CONFIG_SMP
1661 cpu_set(cpuid, cpu_present_map);
1662 cpu_set(cpuid, cpu_possible_map);
1663 #endif
1664 }
1665
1666 smp_fill_in_sib_core_maps();
1667 }
1668
1669 struct device_node *of_console_device;
1670 EXPORT_SYMBOL(of_console_device);
1671
1672 char *of_console_path;
1673 EXPORT_SYMBOL(of_console_path);
1674
1675 char *of_console_options;
1676 EXPORT_SYMBOL(of_console_options);
1677
1678 static void __init of_console_init(void)
1679 {
1680 char *msg = "OF stdout device is: %s\n";
1681 struct device_node *dp;
1682 const char *type;
1683 phandle node;
1684
1685 of_console_path = prom_early_alloc(256);
1686 if (prom_ihandle2path(prom_stdout, of_console_path, 256) < 0) {
1687 prom_printf("Cannot obtain path of stdout.\n");
1688 prom_halt();
1689 }
1690 of_console_options = strrchr(of_console_path, ':');
1691 if (of_console_options) {
1692 of_console_options++;
1693 if (*of_console_options == '\0')
1694 of_console_options = NULL;
1695 }
1696
1697 node = prom_inst2pkg(prom_stdout);
1698 if (!node) {
1699 prom_printf("Cannot resolve stdout node from "
1700 "instance %08x.\n", prom_stdout);
1701 prom_halt();
1702 }
1703
1704 dp = of_find_node_by_phandle(node);
1705 type = of_get_property(dp, "device_type", NULL);
1706 if (!type) {
1707 prom_printf("Console stdout lacks device_type property.\n");
1708 prom_halt();
1709 }
1710
1711 if (strcmp(type, "display") && strcmp(type, "serial")) {
1712 prom_printf("Console device_type is neither display "
1713 "nor serial.\n");
1714 prom_halt();
1715 }
1716
1717 of_console_device = dp;
1718
1719 printk(msg, of_console_path);
1720 }
1721
1722 void __init prom_build_devicetree(void)
1723 {
1724 struct device_node **nextp;
1725
1726 allnodes = create_node(prom_root_node, NULL);
1727 allnodes->path_component_name = "";
1728 allnodes->full_name = "/";
1729
1730 nextp = &allnodes->allnext;
1731 allnodes->child = build_tree(allnodes,
1732 prom_getchild(allnodes->node),
1733 &nextp);
1734 of_console_init();
1735
1736 printk("PROM: Built device tree with %u bytes of memory.\n",
1737 prom_early_allocated);
1738
1739 if (tlb_type != hypervisor)
1740 of_fill_in_cpu_data();
1741 }
kmemtrace - Kernel memory tracer