1 /* linux/arch/arm/mach-s3c2410/irq.c
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk>
23 * Fixed compile warnings
25 * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn>
26 * Fixed s3c_extirq_type
28 * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
29 * Addition of ADC/TC demux
31 * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de>
32 * Fix for set_irq_type() on low EINT numbers
34 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
35 * Tidy up KF's patch and sort out new release
37 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
38 * Add support for power management controls
40 * 04-Nov-2004 Ben Dooks
41 * Fix standard IRQ wake for EINT0..4 and RTC
43 * 22-Feb-2005 Ben Dooks
44 * Fixed edge-triggering on ADC IRQ
46 * 28-Jun-2005 Ben Dooks
49 * 25-Jul-2005 Ben Dooks
50 * Split the S3C2440 IRQ code to seperate file
53 #include <linux/init.h>
54 #include <linux/module.h>
55 #include <linux/interrupt.h>
56 #include <linux/ioport.h>
57 #include <linux/ptrace.h>
58 #include <linux/sysdev.h>
60 #include <asm/hardware.h>
64 #include <asm/mach/irq.h>
66 #include <asm/arch/regs-irq.h>
67 #include <asm/arch/regs-gpio.h>
73 /* wakeup irq control */
77 /* state for IRQs over sleep */
79 /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
81 * set bit to 1 in allow bitfield to enable the wakeup settings on it
84 unsigned long s3c_irqwake_intallow
= 1L << (IRQ_RTC
- IRQ_EINT0
) | 0xfL
;
85 unsigned long s3c_irqwake_intmask
= 0xffffffffL
;
86 unsigned long s3c_irqwake_eintallow
= 0x0000fff0L
;
87 unsigned long s3c_irqwake_eintmask
= 0xffffffffL
;
90 s3c_irq_wake(unsigned int irqno
, unsigned int state
)
92 unsigned long irqbit
= 1 << (irqno
- IRQ_EINT0
);
94 if (!(s3c_irqwake_intallow
& irqbit
))
97 printk(KERN_INFO
"wake %s for irq %d\n",
98 state
? "enabled" : "disabled", irqno
);
101 s3c_irqwake_intmask
|= irqbit
;
103 s3c_irqwake_intmask
&= ~irqbit
;
109 s3c_irqext_wake(unsigned int irqno
, unsigned int state
)
111 unsigned long bit
= 1L << (irqno
- EXTINT_OFF
);
113 if (!(s3c_irqwake_eintallow
& bit
))
116 printk(KERN_INFO
"wake %s for irq %d\n",
117 state
? "enabled" : "disabled", irqno
);
120 s3c_irqwake_eintmask
|= bit
;
122 s3c_irqwake_eintmask
&= ~bit
;
128 #define s3c_irqext_wake NULL
129 #define s3c_irq_wake NULL
134 s3c_irq_mask(unsigned int irqno
)
140 mask
= __raw_readl(S3C2410_INTMSK
);
141 mask
|= 1UL << irqno
;
142 __raw_writel(mask
, S3C2410_INTMSK
);
146 s3c_irq_ack(unsigned int irqno
)
148 unsigned long bitval
= 1UL << (irqno
- IRQ_EINT0
);
150 __raw_writel(bitval
, S3C2410_SRCPND
);
151 __raw_writel(bitval
, S3C2410_INTPND
);
155 s3c_irq_maskack(unsigned int irqno
)
157 unsigned long bitval
= 1UL << (irqno
- IRQ_EINT0
);
160 mask
= __raw_readl(S3C2410_INTMSK
);
161 __raw_writel(mask
|bitval
, S3C2410_INTMSK
);
163 __raw_writel(bitval
, S3C2410_SRCPND
);
164 __raw_writel(bitval
, S3C2410_INTPND
);
169 s3c_irq_unmask(unsigned int irqno
)
173 if (irqno
!= IRQ_TIMER4
&& irqno
!= IRQ_EINT8t23
)
174 irqdbf2("s3c_irq_unmask %d\n", irqno
);
178 mask
= __raw_readl(S3C2410_INTMSK
);
179 mask
&= ~(1UL << irqno
);
180 __raw_writel(mask
, S3C2410_INTMSK
);
183 struct irqchip s3c_irq_level_chip
= {
184 .ack
= s3c_irq_maskack
,
185 .mask
= s3c_irq_mask
,
186 .unmask
= s3c_irq_unmask
,
187 .set_wake
= s3c_irq_wake
190 static struct irqchip s3c_irq_chip
= {
192 .mask
= s3c_irq_mask
,
193 .unmask
= s3c_irq_unmask
,
194 .set_wake
= s3c_irq_wake
198 s3c_irqext_mask(unsigned int irqno
)
204 mask
= __raw_readl(S3C24XX_EINTMASK
);
205 mask
|= ( 1UL << irqno
);
206 __raw_writel(mask
, S3C24XX_EINTMASK
);
208 if (irqno
<= (IRQ_EINT7
- EXTINT_OFF
)) {
209 /* check to see if all need masking */
211 if ((mask
& (0xf << 4)) == (0xf << 4)) {
212 /* all masked, mask the parent */
213 s3c_irq_mask(IRQ_EINT4t7
);
216 /* todo: the same check as above for the rest of the irq regs...*/
222 s3c_irqext_ack(unsigned int irqno
)
228 bit
= 1UL << (irqno
- EXTINT_OFF
);
231 mask
= __raw_readl(S3C24XX_EINTMASK
);
233 __raw_writel(bit
, S3C24XX_EINTPEND
);
235 req
= __raw_readl(S3C24XX_EINTPEND
);
238 /* not sure if we should be acking the parent irq... */
240 if (irqno
<= IRQ_EINT7
) {
241 if ((req
& 0xf0) == 0)
242 s3c_irq_ack(IRQ_EINT4t7
);
245 s3c_irq_ack(IRQ_EINT8t23
);
250 s3c_irqext_unmask(unsigned int irqno
)
256 mask
= __raw_readl(S3C24XX_EINTMASK
);
257 mask
&= ~( 1UL << irqno
);
258 __raw_writel(mask
, S3C24XX_EINTMASK
);
260 s3c_irq_unmask((irqno
<= (IRQ_EINT7
- EXTINT_OFF
)) ? IRQ_EINT4t7
: IRQ_EINT8t23
);
264 s3c_irqext_type(unsigned int irq
, unsigned int type
)
266 void __iomem
*extint_reg
;
267 void __iomem
*gpcon_reg
;
268 unsigned long gpcon_offset
, extint_offset
;
269 unsigned long newvalue
= 0, value
;
271 if ((irq
>= IRQ_EINT0
) && (irq
<= IRQ_EINT3
))
273 gpcon_reg
= S3C2410_GPFCON
;
274 extint_reg
= S3C24XX_EXTINT0
;
275 gpcon_offset
= (irq
- IRQ_EINT0
) * 2;
276 extint_offset
= (irq
- IRQ_EINT0
) * 4;
278 else if ((irq
>= IRQ_EINT4
) && (irq
<= IRQ_EINT7
))
280 gpcon_reg
= S3C2410_GPFCON
;
281 extint_reg
= S3C24XX_EXTINT0
;
282 gpcon_offset
= (irq
- (EXTINT_OFF
)) * 2;
283 extint_offset
= (irq
- (EXTINT_OFF
)) * 4;
285 else if ((irq
>= IRQ_EINT8
) && (irq
<= IRQ_EINT15
))
287 gpcon_reg
= S3C2410_GPGCON
;
288 extint_reg
= S3C24XX_EXTINT1
;
289 gpcon_offset
= (irq
- IRQ_EINT8
) * 2;
290 extint_offset
= (irq
- IRQ_EINT8
) * 4;
292 else if ((irq
>= IRQ_EINT16
) && (irq
<= IRQ_EINT23
))
294 gpcon_reg
= S3C2410_GPGCON
;
295 extint_reg
= S3C24XX_EXTINT2
;
296 gpcon_offset
= (irq
- IRQ_EINT8
) * 2;
297 extint_offset
= (irq
- IRQ_EINT16
) * 4;
301 /* Set the GPIO to external interrupt mode */
302 value
= __raw_readl(gpcon_reg
);
303 value
= (value
& ~(3 << gpcon_offset
)) | (0x02 << gpcon_offset
);
304 __raw_writel(value
, gpcon_reg
);
306 /* Set the external interrupt to pointed trigger type */
310 printk(KERN_WARNING
"No edge setting!\n");
314 newvalue
= S3C2410_EXTINT_RISEEDGE
;
318 newvalue
= S3C2410_EXTINT_FALLEDGE
;
322 newvalue
= S3C2410_EXTINT_BOTHEDGE
;
326 newvalue
= S3C2410_EXTINT_LOWLEV
;
330 newvalue
= S3C2410_EXTINT_HILEV
;
334 printk(KERN_ERR
"No such irq type %d", type
);
338 value
= __raw_readl(extint_reg
);
339 value
= (value
& ~(7 << extint_offset
)) | (newvalue
<< extint_offset
);
340 __raw_writel(value
, extint_reg
);
345 static struct irqchip s3c_irqext_chip
= {
346 .mask
= s3c_irqext_mask
,
347 .unmask
= s3c_irqext_unmask
,
348 .ack
= s3c_irqext_ack
,
349 .set_type
= s3c_irqext_type
,
350 .set_wake
= s3c_irqext_wake
353 static struct irqchip s3c_irq_eint0t4
= {
355 .mask
= s3c_irq_mask
,
356 .unmask
= s3c_irq_unmask
,
357 .set_wake
= s3c_irq_wake
,
358 .set_type
= s3c_irqext_type
,
361 /* mask values for the parent registers for each of the interrupt types */
363 #define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
364 #define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
365 #define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
366 #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
372 s3c_irq_uart0_mask(unsigned int irqno
)
374 s3c_irqsub_mask(irqno
, INTMSK_UART0
, 7);
378 s3c_irq_uart0_unmask(unsigned int irqno
)
380 s3c_irqsub_unmask(irqno
, INTMSK_UART0
);
384 s3c_irq_uart0_ack(unsigned int irqno
)
386 s3c_irqsub_maskack(irqno
, INTMSK_UART0
, 7);
389 static struct irqchip s3c_irq_uart0
= {
390 .mask
= s3c_irq_uart0_mask
,
391 .unmask
= s3c_irq_uart0_unmask
,
392 .ack
= s3c_irq_uart0_ack
,
398 s3c_irq_uart1_mask(unsigned int irqno
)
400 s3c_irqsub_mask(irqno
, INTMSK_UART1
, 7 << 3);
404 s3c_irq_uart1_unmask(unsigned int irqno
)
406 s3c_irqsub_unmask(irqno
, INTMSK_UART1
);
410 s3c_irq_uart1_ack(unsigned int irqno
)
412 s3c_irqsub_maskack(irqno
, INTMSK_UART1
, 7 << 3);
415 static struct irqchip s3c_irq_uart1
= {
416 .mask
= s3c_irq_uart1_mask
,
417 .unmask
= s3c_irq_uart1_unmask
,
418 .ack
= s3c_irq_uart1_ack
,
424 s3c_irq_uart2_mask(unsigned int irqno
)
426 s3c_irqsub_mask(irqno
, INTMSK_UART2
, 7 << 6);
430 s3c_irq_uart2_unmask(unsigned int irqno
)
432 s3c_irqsub_unmask(irqno
, INTMSK_UART2
);
436 s3c_irq_uart2_ack(unsigned int irqno
)
438 s3c_irqsub_maskack(irqno
, INTMSK_UART2
, 7 << 6);
441 static struct irqchip s3c_irq_uart2
= {
442 .mask
= s3c_irq_uart2_mask
,
443 .unmask
= s3c_irq_uart2_unmask
,
444 .ack
= s3c_irq_uart2_ack
,
447 /* ADC and Touchscreen */
450 s3c_irq_adc_mask(unsigned int irqno
)
452 s3c_irqsub_mask(irqno
, INTMSK_ADCPARENT
, 3 << 9);
456 s3c_irq_adc_unmask(unsigned int irqno
)
458 s3c_irqsub_unmask(irqno
, INTMSK_ADCPARENT
);
462 s3c_irq_adc_ack(unsigned int irqno
)
464 s3c_irqsub_ack(irqno
, INTMSK_ADCPARENT
, 3 << 9);
467 static struct irqchip s3c_irq_adc
= {
468 .mask
= s3c_irq_adc_mask
,
469 .unmask
= s3c_irq_adc_unmask
,
470 .ack
= s3c_irq_adc_ack
,
473 /* irq demux for adc */
474 static void s3c_irq_demux_adc(unsigned int irq
,
475 struct irqdesc
*desc
,
476 struct pt_regs
*regs
)
478 unsigned int subsrc
, submsk
;
479 unsigned int offset
= 9;
480 struct irqdesc
*mydesc
;
482 /* read the current pending interrupts, and the mask
483 * for what it is available */
485 subsrc
= __raw_readl(S3C2410_SUBSRCPND
);
486 submsk
= __raw_readl(S3C2410_INTSUBMSK
);
494 mydesc
= irq_desc
+ IRQ_TC
;
495 desc_handle_irq(IRQ_TC
, mydesc
, regs
);
498 mydesc
= irq_desc
+ IRQ_ADC
;
499 desc_handle_irq(IRQ_ADC
, mydesc
, regs
);
504 static void s3c_irq_demux_uart(unsigned int start
,
505 struct pt_regs
*regs
)
507 unsigned int subsrc
, submsk
;
508 unsigned int offset
= start
- IRQ_S3CUART_RX0
;
509 struct irqdesc
*desc
;
511 /* read the current pending interrupts, and the mask
512 * for what it is available */
514 subsrc
= __raw_readl(S3C2410_SUBSRCPND
);
515 submsk
= __raw_readl(S3C2410_INTSUBMSK
);
517 irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
518 start
, offset
, subsrc
, submsk
);
525 desc
= irq_desc
+ start
;
528 desc_handle_irq(start
, desc
, regs
);
533 desc_handle_irq(start
+1, desc
, regs
);
538 desc_handle_irq(start
+2, desc
, regs
);
542 /* uart demux entry points */
545 s3c_irq_demux_uart0(unsigned int irq
,
546 struct irqdesc
*desc
,
547 struct pt_regs
*regs
)
550 s3c_irq_demux_uart(IRQ_S3CUART_RX0
, regs
);
554 s3c_irq_demux_uart1(unsigned int irq
,
555 struct irqdesc
*desc
,
556 struct pt_regs
*regs
)
559 s3c_irq_demux_uart(IRQ_S3CUART_RX1
, regs
);
563 s3c_irq_demux_uart2(unsigned int irq
,
564 struct irqdesc
*desc
,
565 struct pt_regs
*regs
)
568 s3c_irq_demux_uart(IRQ_S3CUART_RX2
, regs
);
572 s3c_irq_demux_extint8(unsigned int irq
,
573 struct irqdesc
*desc
,
574 struct pt_regs
*regs
)
576 unsigned long eintpnd
= __raw_readl(S3C24XX_EINTPEND
);
577 unsigned long eintmsk
= __raw_readl(S3C24XX_EINTMASK
);
580 eintpnd
&= ~0xff; /* ignore lower irqs */
582 /* we may as well handle all the pending IRQs here */
585 irq
= __ffs(eintpnd
);
586 eintpnd
&= ~(1<<irq
);
588 irq
+= (IRQ_EINT4
- 4);
589 desc_handle_irq(irq
, irq_desc
+ irq
, regs
);
595 s3c_irq_demux_extint4t7(unsigned int irq
,
596 struct irqdesc
*desc
,
597 struct pt_regs
*regs
)
599 unsigned long eintpnd
= __raw_readl(S3C24XX_EINTPEND
);
600 unsigned long eintmsk
= __raw_readl(S3C24XX_EINTMASK
);
603 eintpnd
&= 0xff; /* only lower irqs */
605 /* we may as well handle all the pending IRQs here */
608 irq
= __ffs(eintpnd
);
609 eintpnd
&= ~(1<<irq
);
611 irq
+= (IRQ_EINT4
- 4);
613 desc_handle_irq(irq
, irq_desc
+ irq
, regs
);
619 static struct sleep_save irq_save
[] = {
620 SAVE_ITEM(S3C2410_INTMSK
),
621 SAVE_ITEM(S3C2410_INTSUBMSK
),
624 /* the extint values move between the s3c2410/s3c2440 and the s3c2412
625 * so we use an array to hold them, and to calculate the address of
626 * the register at run-time
629 static unsigned long save_extint
[3];
630 static unsigned long save_eintflt
[4];
631 static unsigned long save_eintmask
;
633 int s3c24xx_irq_suspend(struct sys_device
*dev
, pm_message_t state
)
637 for (i
= 0; i
< ARRAY_SIZE(save_extint
); i
++)
638 save_extint
[i
] = __raw_readl(S3C24XX_EXTINT0
+ (i
*4));
640 for (i
= 0; i
< ARRAY_SIZE(save_eintflt
); i
++)
641 save_eintflt
[i
] = __raw_readl(S3C24XX_EINFLT0
+ (i
*4));
643 s3c2410_pm_do_save(irq_save
, ARRAY_SIZE(irq_save
));
644 save_eintmask
= __raw_readl(S3C24XX_EINTMASK
);
649 int s3c24xx_irq_resume(struct sys_device
*dev
)
653 for (i
= 0; i
< ARRAY_SIZE(save_extint
); i
++)
654 __raw_writel(save_extint
[i
], S3C24XX_EXTINT0
+ (i
*4));
656 for (i
= 0; i
< ARRAY_SIZE(save_eintflt
); i
++)
657 __raw_writel(save_eintflt
[i
], S3C24XX_EINFLT0
+ (i
*4));
659 s3c2410_pm_do_restore(irq_save
, ARRAY_SIZE(irq_save
));
660 __raw_writel(save_eintmask
, S3C24XX_EINTMASK
);
666 #define s3c24xx_irq_suspend NULL
667 #define s3c24xx_irq_resume NULL
672 * Initialise S3C2410 IRQ system
675 void __init
s3c24xx_init_irq(void)
682 irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
684 /* first, clear all interrupts pending... */
687 for (i
= 0; i
< 4; i
++) {
688 pend
= __raw_readl(S3C24XX_EINTPEND
);
690 if (pend
== 0 || pend
== last
)
693 __raw_writel(pend
, S3C24XX_EINTPEND
);
694 printk("irq: clearing pending ext status %08x\n", (int)pend
);
699 for (i
= 0; i
< 4; i
++) {
700 pend
= __raw_readl(S3C2410_INTPND
);
702 if (pend
== 0 || pend
== last
)
705 __raw_writel(pend
, S3C2410_SRCPND
);
706 __raw_writel(pend
, S3C2410_INTPND
);
707 printk("irq: clearing pending status %08x\n", (int)pend
);
712 for (i
= 0; i
< 4; i
++) {
713 pend
= __raw_readl(S3C2410_SUBSRCPND
);
715 if (pend
== 0 || pend
== last
)
718 printk("irq: clearing subpending status %08x\n", (int)pend
);
719 __raw_writel(pend
, S3C2410_SUBSRCPND
);
723 /* register the main interrupts */
725 irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
727 for (irqno
= IRQ_EINT4t7
; irqno
<= IRQ_ADCPARENT
; irqno
++) {
728 /* set all the s3c2410 internal irqs */
731 /* deal with the special IRQs (cascaded) */
739 set_irq_chip(irqno
, &s3c_irq_level_chip
);
740 set_irq_handler(irqno
, do_level_IRQ
);
749 //irqdbf("registering irq %d (s3c irq)\n", irqno);
750 set_irq_chip(irqno
, &s3c_irq_chip
);
751 set_irq_handler(irqno
, do_edge_IRQ
);
752 set_irq_flags(irqno
, IRQF_VALID
);
756 /* setup the cascade irq handlers */
758 set_irq_chained_handler(IRQ_EINT4t7
, s3c_irq_demux_extint4t7
);
759 set_irq_chained_handler(IRQ_EINT8t23
, s3c_irq_demux_extint8
);
761 set_irq_chained_handler(IRQ_UART0
, s3c_irq_demux_uart0
);
762 set_irq_chained_handler(IRQ_UART1
, s3c_irq_demux_uart1
);
763 set_irq_chained_handler(IRQ_UART2
, s3c_irq_demux_uart2
);
764 set_irq_chained_handler(IRQ_ADCPARENT
, s3c_irq_demux_adc
);
766 /* external interrupts */
768 for (irqno
= IRQ_EINT0
; irqno
<= IRQ_EINT3
; irqno
++) {
769 irqdbf("registering irq %d (ext int)\n", irqno
);
770 set_irq_chip(irqno
, &s3c_irq_eint0t4
);
771 set_irq_handler(irqno
, do_edge_IRQ
);
772 set_irq_flags(irqno
, IRQF_VALID
);
775 for (irqno
= IRQ_EINT4
; irqno
<= IRQ_EINT23
; irqno
++) {
776 irqdbf("registering irq %d (extended s3c irq)\n", irqno
);
777 set_irq_chip(irqno
, &s3c_irqext_chip
);
778 set_irq_handler(irqno
, do_edge_IRQ
);
779 set_irq_flags(irqno
, IRQF_VALID
);
782 /* register the uart interrupts */
784 irqdbf("s3c2410: registering external interrupts\n");
786 for (irqno
= IRQ_S3CUART_RX0
; irqno
<= IRQ_S3CUART_ERR0
; irqno
++) {
787 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno
);
788 set_irq_chip(irqno
, &s3c_irq_uart0
);
789 set_irq_handler(irqno
, do_level_IRQ
);
790 set_irq_flags(irqno
, IRQF_VALID
);
793 for (irqno
= IRQ_S3CUART_RX1
; irqno
<= IRQ_S3CUART_ERR1
; irqno
++) {
794 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno
);
795 set_irq_chip(irqno
, &s3c_irq_uart1
);
796 set_irq_handler(irqno
, do_level_IRQ
);
797 set_irq_flags(irqno
, IRQF_VALID
);
800 for (irqno
= IRQ_S3CUART_RX2
; irqno
<= IRQ_S3CUART_ERR2
; irqno
++) {
801 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno
);
802 set_irq_chip(irqno
, &s3c_irq_uart2
);
803 set_irq_handler(irqno
, do_level_IRQ
);
804 set_irq_flags(irqno
, IRQF_VALID
);
807 for (irqno
= IRQ_TC
; irqno
<= IRQ_ADC
; irqno
++) {
808 irqdbf("registering irq %d (s3c adc irq)\n", irqno
);
809 set_irq_chip(irqno
, &s3c_irq_adc
);
810 set_irq_handler(irqno
, do_edge_IRQ
);
811 set_irq_flags(irqno
, IRQF_VALID
);
814 irqdbf("s3c2410: registered interrupt handlers\n");