include/asm-blackfin/mach-bf537/mem_map.h

   1 /*
   2  * file:         include/asm-blackfin/mach-bf537/mem_map.h
   3  * based on:
   4  * author:
   5  *
   6  * created:
   7  * description:
   8  *      Memory MAP Common header file for blackfin BF537/6/4 of processors.
   9  * rev:
  10  *
  11  * modified:
  12  *
  13  * bugs:         enter bugs at http://blackfin.uclinux.org/
  14  *
  15  * this program is free software; you can redistribute it and/or modify
  16  * it under the terms of the gnu general public license as published by
  17  * the free software foundation; either version 2, or (at your option)
  18  * any later version.
  19  *
  20  * this program is distributed in the hope that it will be useful,
  21  * but without any warranty; without even the implied warranty of
  22  * merchantability or fitness for a particular purpose.  see the
  23  * gnu general public license for more details.
  24  *
  25  * you should have received a copy of the gnu general public license
  26  * along with this program; see the file copying.
  27  * if not, write to the free software foundation,
  28  * 59 temple place - suite 330, boston, ma 02111-1307, usa.
  29  */
  30
  31 #ifndef _MEM_MAP_537_H_
  32 #define _MEM_MAP_537_H_
  33
  34 #define COREMMR_BASE           0xFFE00000        /* Core MMRs */
  35 #define SYSMMR_BASE            0xFFC00000        /* System MMRs */
  36
  37 /* Async Memory Banks */
  38 #define ASYNC_BANK3_BASE        0x20300000       /* Async Bank 3 */
  39 #define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
  40 #define ASYNC_BANK2_BASE        0x20200000       /* Async Bank 2 */
  41 #define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
  42 #define ASYNC_BANK1_BASE        0x20100000       /* Async Bank 1 */
  43 #define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
  44 #define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
  45 #define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
  46
  47 /* Boot ROM Memory */
  48
  49 #define BOOT_ROM_START          0xEF000000
  50
  51 /* Level 1 Memory */
  52
  53 /* Memory Map for ADSP-BF537 processors */
  54
  55 #ifdef CONFIG_BFIN_ICACHE
  56 #define BFIN_ICACHESIZE (16*1024)
  57 #else
  58 #define BFIN_ICACHESIZE (0*1024)
  59 #endif
  60
  61
  62 #ifdef CONFIG_BF537
  63 #define L1_CODE_START       0xFFA00000
  64 #define L1_DATA_A_START     0xFF800000
  65 #define L1_DATA_B_START     0xFF900000
  66
  67 #define L1_CODE_LENGTH      0xC000
  68
  69 #ifdef CONFIG_BFIN_DCACHE
  70
  71 #ifdef CONFIG_BFIN_DCACHE_BANKA
  72 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
  73 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  74 #define L1_DATA_B_LENGTH      0x8000
  75 #define BFIN_DCACHESIZE (16*1024)
  76 #define BFIN_DSUPBANKS  1
  77 #else
  78 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
  79 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  80 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
  81 #define BFIN_DCACHESIZE (32*1024)
  82 #define BFIN_DSUPBANKS  2
  83 #endif
  84
  85 #else
  86 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
  87 #define L1_DATA_A_LENGTH      0x8000
  88 #define L1_DATA_B_LENGTH      0x8000
  89 #define BFIN_DCACHESIZE (0*1024)
  90 #define BFIN_DSUPBANKS  0
  91 #endif /*CONFIG_BFIN_DCACHE*/
  92
  93 #endif /*CONFIG_BF537*/
  94
  95 /* Memory Map for ADSP-BF536 processors */
  96
  97 #ifdef CONFIG_BF536
  98 #define L1_CODE_START       0xFFA00000
  99 #define L1_DATA_A_START     0xFF804000
 100 #define L1_DATA_B_START     0xFF904000
 101
 102 #define L1_CODE_LENGTH      0xC000
 103
 104
 105 #ifdef CONFIG_BFIN_DCACHE
 106
 107 #ifdef CONFIG_BFIN_DCACHE_BANKA
 108 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
 109 #define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
 110 #define L1_DATA_B_LENGTH      0x4000
 111 #define BFIN_DCACHESIZE (16*1024)
 112 #define BFIN_DSUPBANKS  1
 113
 114 #else
 115 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
 116 #define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
 117 #define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
 118 #define BFIN_DCACHESIZE (32*1024)
 119 #define BFIN_DSUPBANKS  2
 120 #endif
 121
 122 #else
 123 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
 124 #define L1_DATA_A_LENGTH      0x4000
 125 #define L1_DATA_B_LENGTH      0x4000
 126 #define BFIN_DCACHESIZE (0*1024)
 127 #define BFIN_DSUPBANKS  0
 128 #endif /*CONFIG_BFIN_DCACHE*/
 129
 130 #endif
 131
 132 /* Memory Map for ADSP-BF534 processors */
 133
 134 #ifdef CONFIG_BF534
 135 #define L1_CODE_START       0xFFA00000
 136 #define L1_DATA_A_START     0xFF800000
 137 #define L1_DATA_B_START     0xFF900000
 138
 139 #define L1_CODE_LENGTH      0xC000
 140
 141 #ifdef CONFIG_BFIN_DCACHE
 142
 143 #ifdef CONFIG_BFIN_DCACHE_BANKA
 144 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
 145 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 146 #define L1_DATA_B_LENGTH      0x8000
 147 #define BFIN_DCACHESIZE (16*1024)
 148 #define BFIN_DSUPBANKS  1
 149
 150 #else
 151 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
 152 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 153 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
 154 #define BFIN_DCACHESIZE (32*1024)
 155 #define BFIN_DSUPBANKS  2
 156 #endif
 157
 158 #else
 159 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
 160 #define L1_DATA_A_LENGTH      0x8000
 161 #define L1_DATA_B_LENGTH      0x8000
 162 #define BFIN_DCACHESIZE (0*1024)
 163 #define BFIN_DSUPBANKS  0
 164 #endif /*CONFIG_BFIN_DCACHE*/
 165
 166 #endif
 167
 168 /* Scratch Pad Memory */
 169
 170 #if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
 171 #define L1_SCRATCH_START        0xFFB00000
 172 #define L1_SCRATCH_LENGTH       0x1000
 173 #endif
 174
 175 #endif                          /* _MEM_MAP_537_H_ */