include/asm-blackfin/mach-bf537/mem_init.h

   1 /*
   2  * File:         include/asm-blackfin/mach-bf537/mem_init.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Rev:
  10  *
  11  * Modified:
  12  *               Copyright 2004-2006 Analog Devices Inc.
  13  *
  14  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; see the file COPYING.
  28  * If not, write to the Free Software Foundation,
  29  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 #if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
  33 #if (CONFIG_SCLK_HZ > 119402985)
  34 #define SDRAM_tRP       TRP_2
  35 #define SDRAM_tRP_num   2
  36 #define SDRAM_tRAS      TRAS_7
  37 #define SDRAM_tRAS_num  7
  38 #define SDRAM_tRCD      TRCD_2
  39 #define SDRAM_tWR       TWR_2
  40 #endif
  41 #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
  42 #define SDRAM_tRP       TRP_2
  43 #define SDRAM_tRP_num   2
  44 #define SDRAM_tRAS      TRAS_6
  45 #define SDRAM_tRAS_num  6
  46 #define SDRAM_tRCD      TRCD_2
  47 #define SDRAM_tWR       TWR_2
  48 #endif
  49 #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
  50 #define SDRAM_tRP       TRP_2
  51 #define SDRAM_tRP_num   2
  52 #define SDRAM_tRAS      TRAS_5
  53 #define SDRAM_tRAS_num  5
  54 #define SDRAM_tRCD      TRCD_2
  55 #define SDRAM_tWR       TWR_2
  56 #endif
  57 #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
  58 #define SDRAM_tRP       TRP_2
  59 #define SDRAM_tRP_num   2
  60 #define SDRAM_tRAS      TRAS_4
  61 #define SDRAM_tRAS_num  4
  62 #define SDRAM_tRCD      TRCD_2
  63 #define SDRAM_tWR       TWR_2
  64 #endif
  65 #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
  66 #define SDRAM_tRP       TRP_2
  67 #define SDRAM_tRP_num   2
  68 #define SDRAM_tRAS      TRAS_3
  69 #define SDRAM_tRAS_num  3
  70 #define SDRAM_tRCD      TRCD_2
  71 #define SDRAM_tWR       TWR_2
  72 #endif
  73 #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
  74 #define SDRAM_tRP       TRP_1
  75 #define SDRAM_tRP_num   1
  76 #define SDRAM_tRAS      TRAS_4
  77 #define SDRAM_tRAS_num  3
  78 #define SDRAM_tRCD      TRCD_1
  79 #define SDRAM_tWR       TWR_2
  80 #endif
  81 #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
  82 #define SDRAM_tRP       TRP_1
  83 #define SDRAM_tRP_num   1
  84 #define SDRAM_tRAS      TRAS_3
  85 #define SDRAM_tRAS_num  3
  86 #define SDRAM_tRCD      TRCD_1
  87 #define SDRAM_tWR       TWR_2
  88 #endif
  89 #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
  90 #define SDRAM_tRP       TRP_1
  91 #define SDRAM_tRP_num   1
  92 #define SDRAM_tRAS      TRAS_2
  93 #define SDRAM_tRAS_num  2
  94 #define SDRAM_tRCD      TRCD_1
  95 #define SDRAM_tWR       TWR_2
  96 #endif
  97 #if (CONFIG_SCLK_HZ <= 29850746)
  98 #define SDRAM_tRP       TRP_1
  99 #define SDRAM_tRP_num   1
 100 #define SDRAM_tRAS      TRAS_1
 101 #define SDRAM_tRAS_num  1
 102 #define SDRAM_tRCD      TRCD_1
 103 #define SDRAM_tWR       TWR_2
 104 #endif
 105 #endif
 106
 107 #if (CONFIG_MEM_MT48LC16M16A2TG_75)
 108   /*SDRAM INFORMATION: */
 109 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 110 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 111 #define SDRAM_CL    CL_3
 112 #endif
 113
 114 #if (CONFIG_MEM_MT48LC16M8A2TG_75)
 115   /*SDRAM INFORMATION: */
 116 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 117 #define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
 118 #define SDRAM_CL    CL_3
 119 #endif
 120
 121 #if (CONFIG_MEM_MT48LC32M8A2_75)
 122   /*SDRAM INFORMATION: */
 123 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 124 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 125 #define SDRAM_CL    CL_3
 126 #endif
 127
 128 #if (CONFIG_MEM_MT48LC64M4A2FB_7E)
 129   /*SDRAM INFORMATION: */
 130 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 131 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 132 #define SDRAM_CL    CL_3
 133 #endif
 134
 135 #if (CONFIG_MEM_GENERIC_BOARD)
 136   /*SDRAM INFORMATION: Modify this for your board */
 137 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 138 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 139 #define SDRAM_CL    CL_3
 140 #endif
 141
 142 #if (CONFIG_MEM_SIZE == 128)
 143 #define SDRAM_SIZE      EBSZ_128
 144 #endif
 145 #if (CONFIG_MEM_SIZE == 64)
 146 #define SDRAM_SIZE      EBSZ_64
 147 #endif
 148 #if (CONFIG_MEM_SIZE == 32)
 149 #define SDRAM_SIZE      EBSZ_32
 150 #endif
 151 #if (CONFIG_MEM_SIZE == 16)
 152 #define SDRAM_SIZE      EBSZ_16
 153 #endif
 154 #if (CONFIG_MEM_ADD_WIDTH == 11)
 155 #define SDRAM_WIDTH     EBCAW_11
 156 #endif
 157 #if (CONFIG_MEM_ADD_WIDTH == 10)
 158 #define SDRAM_WIDTH     EBCAW_10
 159 #endif
 160 #if (CONFIG_MEM_ADD_WIDTH == 9)
 161 #define SDRAM_WIDTH     EBCAW_9
 162 #endif
 163 #if (CONFIG_MEM_ADD_WIDTH == 8)
 164 #define SDRAM_WIDTH     EBCAW_8
 165 #endif
 166
 167 #define mem_SDBCTL      (SDRAM_WIDTH | SDRAM_SIZE | EBE)
 168
 169 /* Equation from section 17 (p17-46) of BF533 HRM */
 170 #define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
 171
 172 /* Enable SCLK Out */
 173 #define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
 174
 175 #if defined CONFIG_CLKIN_HALF
 176 #define CLKIN_HALF       1
 177 #else
 178 #define CLKIN_HALF       0
 179 #endif
 180
 181 #if defined CONFIG_PLL_BYPASS
 182 #define PLL_BYPASS      1
 183 #else
 184 #define PLL_BYPASS       0
 185 #endif
 186
 187 /***************************************Currently Not Being Used *********************************/
 188 #define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 189 #define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 190 #define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
 191 #define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 192 #define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 193
 194 #if (flash_EBIU_AMBCTL_TT > 3)
 195 #define flash_EBIU_AMBCTL0_TT   B0TT_4
 196 #endif
 197 #if (flash_EBIU_AMBCTL_TT == 3)
 198 #define flash_EBIU_AMBCTL0_TT   B0TT_3
 199 #endif
 200 #if (flash_EBIU_AMBCTL_TT == 2)
 201 #define flash_EBIU_AMBCTL0_TT   B0TT_2
 202 #endif
 203 #if (flash_EBIU_AMBCTL_TT < 2)
 204 #define flash_EBIU_AMBCTL0_TT   B0TT_1
 205 #endif
 206
 207 #if (flash_EBIU_AMBCTL_ST > 3)
 208 #define flash_EBIU_AMBCTL0_ST   B0ST_4
 209 #endif
 210 #if (flash_EBIU_AMBCTL_ST == 3)
 211 #define flash_EBIU_AMBCTL0_ST   B0ST_3
 212 #endif
 213 #if (flash_EBIU_AMBCTL_ST == 2)
 214 #define flash_EBIU_AMBCTL0_ST   B0ST_2
 215 #endif
 216 #if (flash_EBIU_AMBCTL_ST < 2)
 217 #define flash_EBIU_AMBCTL0_ST   B0ST_1
 218 #endif
 219
 220 #if (flash_EBIU_AMBCTL_HT > 2)
 221 #define flash_EBIU_AMBCTL0_HT   B0HT_3
 222 #endif
 223 #if (flash_EBIU_AMBCTL_HT == 2)
 224 #define flash_EBIU_AMBCTL0_HT   B0HT_2
 225 #endif
 226 #if (flash_EBIU_AMBCTL_HT == 1)
 227 #define flash_EBIU_AMBCTL0_HT   B0HT_1
 228 #endif
 229 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
 230 #define flash_EBIU_AMBCTL0_HT   B0HT_0
 231 #endif
 232 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
 233 #define flash_EBIU_AMBCTL0_HT   B0HT_1
 234 #endif
 235
 236 #if (flash_EBIU_AMBCTL_WAT > 14)
 237 #define flash_EBIU_AMBCTL0_WAT  B0WAT_15
 238 #endif
 239 #if (flash_EBIU_AMBCTL_WAT == 14)
 240 #define flash_EBIU_AMBCTL0_WAT  B0WAT_14
 241 #endif
 242 #if (flash_EBIU_AMBCTL_WAT == 13)
 243 #define flash_EBIU_AMBCTL0_WAT  B0WAT_13
 244 #endif
 245 #if (flash_EBIU_AMBCTL_WAT == 12)
 246 #define flash_EBIU_AMBCTL0_WAT  B0WAT_12
 247 #endif
 248 #if (flash_EBIU_AMBCTL_WAT == 11)
 249 #define flash_EBIU_AMBCTL0_WAT  B0WAT_11
 250 #endif
 251 #if (flash_EBIU_AMBCTL_WAT == 10)
 252 #define flash_EBIU_AMBCTL0_WAT  B0WAT_10
 253 #endif
 254 #if (flash_EBIU_AMBCTL_WAT == 9)
 255 #define flash_EBIU_AMBCTL0_WAT  B0WAT_9
 256 #endif
 257 #if (flash_EBIU_AMBCTL_WAT == 8)
 258 #define flash_EBIU_AMBCTL0_WAT  B0WAT_8
 259 #endif
 260 #if (flash_EBIU_AMBCTL_WAT == 7)
 261 #define flash_EBIU_AMBCTL0_WAT  B0WAT_7
 262 #endif
 263 #if (flash_EBIU_AMBCTL_WAT == 6)
 264 #define flash_EBIU_AMBCTL0_WAT  B0WAT_6
 265 #endif
 266 #if (flash_EBIU_AMBCTL_WAT == 5)
 267 #define flash_EBIU_AMBCTL0_WAT  B0WAT_5
 268 #endif
 269 #if (flash_EBIU_AMBCTL_WAT == 4)
 270 #define flash_EBIU_AMBCTL0_WAT  B0WAT_4
 271 #endif
 272 #if (flash_EBIU_AMBCTL_WAT == 3)
 273 #define flash_EBIU_AMBCTL0_WAT  B0WAT_3
 274 #endif
 275 #if (flash_EBIU_AMBCTL_WAT == 2)
 276 #define flash_EBIU_AMBCTL0_WAT  B0WAT_2
 277 #endif
 278 #if (flash_EBIU_AMBCTL_WAT == 1)
 279 #define flash_EBIU_AMBCTL0_WAT  B0WAT_1
 280 #endif
 281
 282 #if (flash_EBIU_AMBCTL_RAT > 14)
 283 #define flash_EBIU_AMBCTL0_RAT  B0RAT_15
 284 #endif
 285 #if (flash_EBIU_AMBCTL_RAT == 14)
 286 #define flash_EBIU_AMBCTL0_RAT  B0RAT_14
 287 #endif
 288 #if (flash_EBIU_AMBCTL_RAT == 13)
 289 #define flash_EBIU_AMBCTL0_RAT  B0RAT_13
 290 #endif
 291 #if (flash_EBIU_AMBCTL_RAT == 12)
 292 #define flash_EBIU_AMBCTL0_RAT  B0RAT_12
 293 #endif
 294 #if (flash_EBIU_AMBCTL_RAT == 11)
 295 #define flash_EBIU_AMBCTL0_RAT  B0RAT_11
 296 #endif
 297 #if (flash_EBIU_AMBCTL_RAT == 10)
 298 #define flash_EBIU_AMBCTL0_RAT  B0RAT_10
 299 #endif
 300 #if (flash_EBIU_AMBCTL_RAT == 9)
 301 #define flash_EBIU_AMBCTL0_RAT  B0RAT_9
 302 #endif
 303 #if (flash_EBIU_AMBCTL_RAT == 8)
 304 #define flash_EBIU_AMBCTL0_RAT  B0RAT_8
 305 #endif
 306 #if (flash_EBIU_AMBCTL_RAT == 7)
 307 #define flash_EBIU_AMBCTL0_RAT  B0RAT_7
 308 #endif
 309 #if (flash_EBIU_AMBCTL_RAT == 6)
 310 #define flash_EBIU_AMBCTL0_RAT  B0RAT_6
 311 #endif
 312 #if (flash_EBIU_AMBCTL_RAT == 5)
 313 #define flash_EBIU_AMBCTL0_RAT  B0RAT_5
 314 #endif
 315 #if (flash_EBIU_AMBCTL_RAT == 4)
 316 #define flash_EBIU_AMBCTL0_RAT  B0RAT_4
 317 #endif
 318 #if (flash_EBIU_AMBCTL_RAT == 3)
 319 #define flash_EBIU_AMBCTL0_RAT  B0RAT_3
 320 #endif
 321 #if (flash_EBIU_AMBCTL_RAT == 2)
 322 #define flash_EBIU_AMBCTL0_RAT  B0RAT_2
 323 #endif
 324 #if (flash_EBIU_AMBCTL_RAT == 1)
 325 #define flash_EBIU_AMBCTL0_RAT  B0RAT_1
 326 #endif
 327
 328 #define flash_EBIU_AMBCTL0  \
 329         (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
 330          flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)