include/asm-x86_64/dma.h

   1 /* $Id: dma.h,v 1.1.1.1 2001/04/19 20:00:38 ak Exp $
   2  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   3  * Written by Hennus Bergman, 1992.
   4  * High DMA channel support & info by Hannu Savolainen
   5  * and John Boyd, Nov. 1992.
   6  */
   7
   8 #ifndef _ASM_DMA_H
   9 #define _ASM_DMA_H
  10
  11 #include <linux/config.h>
  12 #include <linux/spinlock.h>     /* And spinlocks */
  13 #include <asm/io.h>             /* need byte IO */
  14 #include <linux/delay.h>
  15
  16
  17 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  18 #define dma_outb        outb_p
  19 #else
  20 #define dma_outb        outb
  21 #endif
  22
  23 #define dma_inb         inb
  24
  25 /*
  26  * NOTES about DMA transfers:
  27  *
  28  *  controller 1: channels 0-3, byte operations, ports 00-1F
  29  *  controller 2: channels 4-7, word operations, ports C0-DF
  30  *
  31  *  - ALL registers are 8 bits only, regardless of transfer size
  32  *  - channel 4 is not used - cascades 1 into 2.
  33  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  34  *  - channels 5-7 are word - addresses/counts are for physical words
  35  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  36  *  - transfer count loaded to registers is 1 less than actual count
  37  *  - controller 2 offsets are all even (2x offsets for controller 1)
  38  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  39  *  - page registers for 0-3 use bit 0, represent 64K pages
  40  *
  41  * DMA transfers are limited to the lower 16MB of _physical_ memory.
  42  * Note that addresses loaded into registers must be _physical_ addresses,
  43  * not logical addresses (which may differ if paging is active).
  44  *
  45  *  Address mapping for channels 0-3:
  46  *
  47  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  48  *    |  ...  |   |  ... |   |  ... |
  49  *    |  ...  |   |  ... |   |  ... |
  50  *    |  ...  |   |  ... |   |  ... |
  51  *   P7  ...  P0  A7 ... A0  A7 ... A0
  52  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  53  *
  54  *  Address mapping for channels 5-7:
  55  *
  56  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  57  *    |  ...  |   \   \   ... \  \  \  ... \  \
  58  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  59  *    |  ...  |     \   \   ... \  \  \  ... \
  60  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  61  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  62  *
  63  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  64  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  65  * the hardware level, so odd-byte transfers aren't possible).
  66  *
  67  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  68  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  69  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  70  *
  71  */
  72
  73 #define MAX_DMA_CHANNELS        8
  74
  75
  76 /* 16MB ISA DMA zone */
  77 #define MAX_DMA_PFN   ((16*1024*1024) >> PAGE_SHIFT)
  78
  79 /* 4GB broken PCI/AGP hardware bus master zone */
  80 #define MAX_DMA32_PFN ((4UL*1024*1024*1024) >> PAGE_SHIFT)
  81
  82 /* Compat define for old dma zone */
  83 #define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))
  84
  85 /* 8237 DMA controllers */
  86 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
  87 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
  88
  89 /* DMA controller registers */
  90 #define DMA1_CMD_REG            0x08    /* command register (w) */
  91 #define DMA1_STAT_REG           0x08    /* status register (r) */
  92 #define DMA1_REQ_REG            0x09    /* request register (w) */
  93 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
  94 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
  95 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
  96 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
  97 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
  98 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
  99 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
 100
 101 #define DMA2_CMD_REG            0xD0    /* command register (w) */
 102 #define DMA2_STAT_REG           0xD0    /* status register (r) */
 103 #define DMA2_REQ_REG            0xD2    /* request register (w) */
 104 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 105 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
 106 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 107 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 108 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 109 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 110 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 111
 112 #define DMA_ADDR_0              0x00    /* DMA address registers */
 113 #define DMA_ADDR_1              0x02
 114 #define DMA_ADDR_2              0x04
 115 #define DMA_ADDR_3              0x06
 116 #define DMA_ADDR_4              0xC0
 117 #define DMA_ADDR_5              0xC4
 118 #define DMA_ADDR_6              0xC8
 119 #define DMA_ADDR_7              0xCC
 120
 121 #define DMA_CNT_0               0x01    /* DMA count registers */
 122 #define DMA_CNT_1               0x03
 123 #define DMA_CNT_2               0x05
 124 #define DMA_CNT_3               0x07
 125 #define DMA_CNT_4               0xC2
 126 #define DMA_CNT_5               0xC6
 127 #define DMA_CNT_6               0xCA
 128 #define DMA_CNT_7               0xCE
 129
 130 #define DMA_PAGE_0              0x87    /* DMA page registers */
 131 #define DMA_PAGE_1              0x83
 132 #define DMA_PAGE_2              0x81
 133 #define DMA_PAGE_3              0x82
 134 #define DMA_PAGE_5              0x8B
 135 #define DMA_PAGE_6              0x89
 136 #define DMA_PAGE_7              0x8A
 137
 138 #define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
 139 #define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
 140 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 141
 142 #define DMA_AUTOINIT    0x10
 143
 144
 145 extern spinlock_t  dma_spin_lock;
 146
 147 static __inline__ unsigned long claim_dma_lock(void)
 148 {
 149         unsigned long flags;
 150         spin_lock_irqsave(&dma_spin_lock, flags);
 151         return flags;
 152 }
 153
 154 static __inline__ void release_dma_lock(unsigned long flags)
 155 {
 156         spin_unlock_irqrestore(&dma_spin_lock, flags);
 157 }
 158
 159 /* enable/disable a specific DMA channel */
 160 static __inline__ void enable_dma(unsigned int dmanr)
 161 {
 162         if (dmanr<=3)
 163                 dma_outb(dmanr,  DMA1_MASK_REG);
 164         else
 165                 dma_outb(dmanr & 3,  DMA2_MASK_REG);
 166 }
 167
 168 static __inline__ void disable_dma(unsigned int dmanr)
 169 {
 170         if (dmanr<=3)
 171                 dma_outb(dmanr | 4,  DMA1_MASK_REG);
 172         else
 173                 dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 174 }
 175
 176 /* Clear the 'DMA Pointer Flip Flop'.
 177  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 178  * Use this once to initialize the FF to a known state.
 179  * After that, keep track of it. :-)
 180  * --- In order to do that, the DMA routines below should ---
 181  * --- only be used while holding the DMA lock ! ---
 182  */
 183 static __inline__ void clear_dma_ff(unsigned int dmanr)
 184 {
 185         if (dmanr<=3)
 186                 dma_outb(0,  DMA1_CLEAR_FF_REG);
 187         else
 188                 dma_outb(0,  DMA2_CLEAR_FF_REG);
 189 }
 190
 191 /* set mode (above) for a specific DMA channel */
 192 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 193 {
 194         if (dmanr<=3)
 195                 dma_outb(mode | dmanr,  DMA1_MODE_REG);
 196         else
 197                 dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 198 }
 199
 200 /* Set only the page register bits of the transfer address.
 201  * This is used for successive transfers when we know the contents of
 202  * the lower 16 bits of the DMA current address register, but a 64k boundary
 203  * may have been crossed.
 204  */
 205 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
 206 {
 207         switch(dmanr) {
 208                 case 0:
 209                         dma_outb(pagenr, DMA_PAGE_0);
 210                         break;
 211                 case 1:
 212                         dma_outb(pagenr, DMA_PAGE_1);
 213                         break;
 214                 case 2:
 215                         dma_outb(pagenr, DMA_PAGE_2);
 216                         break;
 217                 case 3:
 218                         dma_outb(pagenr, DMA_PAGE_3);
 219                         break;
 220                 case 5:
 221                         dma_outb(pagenr & 0xfe, DMA_PAGE_5);
 222                         break;
 223                 case 6:
 224                         dma_outb(pagenr & 0xfe, DMA_PAGE_6);
 225                         break;
 226                 case 7:
 227                         dma_outb(pagenr & 0xfe, DMA_PAGE_7);
 228                         break;
 229         }
 230 }
 231
 232
 233 /* Set transfer address & page bits for specific DMA channel.
 234  * Assumes dma flipflop is clear.
 235  */
 236 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
 237 {
 238         set_dma_page(dmanr, a>>16);
 239         if (dmanr <= 3)  {
 240             dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 241             dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 242         }  else  {
 243             dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 244             dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 245         }
 246 }
 247
 248
 249 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 250  * a specific DMA channel.
 251  * You must ensure the parameters are valid.
 252  * NOTE: from a manual: "the number of transfers is one more
 253  * than the initial word count"! This is taken into account.
 254  * Assumes dma flip-flop is clear.
 255  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 256  */
 257 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 258 {
 259         count--;
 260         if (dmanr <= 3)  {
 261             dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 262             dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 263         } else {
 264             dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 265             dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 266         }
 267 }
 268
 269
 270 /* Get DMA residue count. After a DMA transfer, this
 271  * should return zero. Reading this while a DMA transfer is
 272  * still in progress will return unpredictable results.
 273  * If called before the channel has been used, it may return 1.
 274  * Otherwise, it returns the number of _bytes_ left to transfer.
 275  *
 276  * Assumes DMA flip-flop is clear.
 277  */
 278 static __inline__ int get_dma_residue(unsigned int dmanr)
 279 {
 280         unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 281                                          : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 282
 283         /* using short to get 16-bit wrap around */
 284         unsigned short count;
 285
 286         count = 1 + dma_inb(io_port);
 287         count += dma_inb(io_port) << 8;
 288
 289         return (dmanr<=3)? count : (count<<1);
 290 }
 291
 292
 293 /* These are in kernel/dma.c: */
 294 extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 295 extern void free_dma(unsigned int dmanr);       /* release it again */
 296
 297 /* From PCI */
 298
 299 #ifdef CONFIG_PCI
 300 extern int isa_dma_bridge_buggy;
 301 #else
 302 #define isa_dma_bridge_buggy    (0)
 303 #endif
 304
 305 #endif /* _ASM_DMA_H */