drivers/net/ibm_newemac/core.h

   1 /*
   2  * drivers/net/ibm_newemac/core.h
   3  *
   4  * Driver for PowerPC 4xx on-chip ethernet controller.
   5  *
   6  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
   7  *                <benh@kernel.crashing.org>
   8  *
   9  * Based on the arch/ppc version of the driver:
  10  *
  11  * Copyright (c) 2004, 2005 Zultys Technologies.
  12  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  13  *
  14  * Based on original work by
  15  *      Armin Kuster <akuster@mvista.com>
  16  *      Johnnie Peters <jpeters@mvista.com>
  17  *      Copyright 2000, 2001 MontaVista Softare Inc.
  18  *
  19  * This program is free software; you can redistribute  it and/or modify it
  20  * under  the terms of  the GNU General  Public License as published by the
  21  * Free Software Foundation;  either version 2 of the  License, or (at your
  22  * option) any later version.
  23  *
  24  */
  25 #ifndef __IBM_NEWEMAC_CORE_H
  26 #define __IBM_NEWEMAC_CORE_H
  27
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/list.h>
  31 #include <linux/kernel.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/spinlock.h>
  36
  37 #include <asm/of_platform.h>
  38 #include <asm/io.h>
  39 #include <asm/dcr.h>
  40
  41 #include "emac.h"
  42 #include "phy.h"
  43 #include "zmii.h"
  44 #include "rgmii.h"
  45 #include "mal.h"
  46 #include "tah.h"
  47 #include "debug.h"
  48
  49 #define NUM_TX_BUFF                     CONFIG_IBM_NEW_EMAC_TXB
  50 #define NUM_RX_BUFF                     CONFIG_IBM_NEW_EMAC_RXB
  51
  52 /* Simple sanity check */
  53 #if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
  54 #error Invalid number of buffer descriptors (greater than 256)
  55 #endif
  56
  57 #define EMAC_MIN_MTU                    46
  58
  59 /* Maximum L2 header length (VLAN tagged, no FCS) */
  60 #define EMAC_MTU_OVERHEAD               (6 * 2 + 2 + 4)
  61
  62 /* RX BD size for the given MTU */
  63 static inline int emac_rx_size(int mtu)
  64 {
  65         if (mtu > ETH_DATA_LEN)
  66                 return MAL_MAX_RX_SIZE;
  67         else
  68                 return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
  69 }
  70
  71 #define EMAC_DMA_ALIGN(x)               ALIGN((x), dma_get_cache_alignment())
  72
  73 #define EMAC_RX_SKB_HEADROOM            \
  74         EMAC_DMA_ALIGN(CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM)
  75
  76 /* Size of RX skb for the given MTU */
  77 static inline int emac_rx_skb_size(int mtu)
  78 {
  79         int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
  80         return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM;
  81 }
  82
  83 /* RX DMA sync size */
  84 static inline int emac_rx_sync_size(int mtu)
  85 {
  86         return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2);
  87 }
  88
  89 /* Driver statistcs is split into two parts to make it more cache friendly:
  90  *   - normal statistics (packet count, etc)
  91  *   - error statistics
  92  *
  93  * When statistics is requested by ethtool, these parts are concatenated,
  94  * normal one goes first.
  95  *
  96  * Please, keep these structures in sync with emac_stats_keys.
  97  */
  98
  99 /* Normal TX/RX Statistics */
 100 struct emac_stats {
 101         u64 rx_packets;
 102         u64 rx_bytes;
 103         u64 tx_packets;
 104         u64 tx_bytes;
 105         u64 rx_packets_csum;
 106         u64 tx_packets_csum;
 107 };
 108
 109 /* Error statistics */
 110 struct emac_error_stats {
 111         u64 tx_undo;
 112
 113         /* Software RX Errors */
 114         u64 rx_dropped_stack;
 115         u64 rx_dropped_oom;
 116         u64 rx_dropped_error;
 117         u64 rx_dropped_resize;
 118         u64 rx_dropped_mtu;
 119         u64 rx_stopped;
 120         /* BD reported RX errors */
 121         u64 rx_bd_errors;
 122         u64 rx_bd_overrun;
 123         u64 rx_bd_bad_packet;
 124         u64 rx_bd_runt_packet;
 125         u64 rx_bd_short_event;
 126         u64 rx_bd_alignment_error;
 127         u64 rx_bd_bad_fcs;
 128         u64 rx_bd_packet_too_long;
 129         u64 rx_bd_out_of_range;
 130         u64 rx_bd_in_range;
 131         /* EMAC IRQ reported RX errors */
 132         u64 rx_parity;
 133         u64 rx_fifo_overrun;
 134         u64 rx_overrun;
 135         u64 rx_bad_packet;
 136         u64 rx_runt_packet;
 137         u64 rx_short_event;
 138         u64 rx_alignment_error;
 139         u64 rx_bad_fcs;
 140         u64 rx_packet_too_long;
 141         u64 rx_out_of_range;
 142         u64 rx_in_range;
 143
 144         /* Software TX Errors */
 145         u64 tx_dropped;
 146         /* BD reported TX errors */
 147         u64 tx_bd_errors;
 148         u64 tx_bd_bad_fcs;
 149         u64 tx_bd_carrier_loss;
 150         u64 tx_bd_excessive_deferral;
 151         u64 tx_bd_excessive_collisions;
 152         u64 tx_bd_late_collision;
 153         u64 tx_bd_multple_collisions;
 154         u64 tx_bd_single_collision;
 155         u64 tx_bd_underrun;
 156         u64 tx_bd_sqe;
 157         /* EMAC IRQ reported TX errors */
 158         u64 tx_parity;
 159         u64 tx_underrun;
 160         u64 tx_sqe;
 161         u64 tx_errors;
 162 };
 163
 164 #define EMAC_ETHTOOL_STATS_COUNT        ((sizeof(struct emac_stats) + \
 165                                           sizeof(struct emac_error_stats)) \
 166                                          / sizeof(u64))
 167
 168 struct emac_instance {
 169         struct net_device               *ndev;
 170         struct resource                 rsrc_regs;
 171         struct emac_regs                __iomem *emacp;
 172         struct of_device                *ofdev;
 173         struct device_node              **blist; /* bootlist entry */
 174
 175         /* MAL linkage */
 176         u32                             mal_ph;
 177         struct of_device                *mal_dev;
 178         u32                             mal_rx_chan;
 179         u32                             mal_tx_chan;
 180         struct mal_instance             *mal;
 181         struct mal_commac               commac;
 182
 183         /* PHY infos */
 184         u32                             phy_mode;
 185         u32                             phy_map;
 186         u32                             phy_address;
 187         u32                             phy_feat_exc;
 188         struct mii_phy                  phy;
 189         struct mutex                    link_lock;
 190         struct delayed_work             link_work;
 191         int                             link_polling;
 192
 193         /* Shared MDIO if any */
 194         u32                             mdio_ph;
 195         struct of_device                *mdio_dev;
 196         struct emac_instance            *mdio_instance;
 197         struct mutex                    mdio_lock;
 198
 199         /* ZMII infos if any */
 200         u32                             zmii_ph;
 201         u32                             zmii_port;
 202         struct of_device                *zmii_dev;
 203
 204         /* RGMII infos if any */
 205         u32                             rgmii_ph;
 206         u32                             rgmii_port;
 207         struct of_device                *rgmii_dev;
 208
 209         /* TAH infos if any */
 210         u32                             tah_ph;
 211         u32                             tah_port;
 212         struct of_device                *tah_dev;
 213
 214         /* IRQs */
 215         int                             wol_irq;
 216         int                             emac_irq;
 217
 218         /* OPB bus frequency in Mhz */
 219         u32                             opb_bus_freq;
 220
 221         /* Cell index within an ASIC (for clk mgmnt) */
 222         u32                             cell_index;
 223
 224         /* Max supported MTU */
 225         u32                             max_mtu;
 226
 227         /* Feature bits (from probe table) */
 228         unsigned int                    features;
 229
 230         /* Tx and Rx fifo sizes & other infos in bytes */
 231         u32                             tx_fifo_size;
 232         u32                             tx_fifo_size_gige;
 233         u32                             rx_fifo_size;
 234         u32                             rx_fifo_size_gige;
 235         u32                             fifo_entry_size;
 236         u32                             mal_burst_size; /* move to MAL ? */
 237
 238         /* Descriptor management
 239          */
 240         struct mal_descriptor           *tx_desc;
 241         int                             tx_cnt;
 242         int                             tx_slot;
 243         int                             ack_slot;
 244
 245         struct mal_descriptor           *rx_desc;
 246         int                             rx_slot;
 247         struct sk_buff                  *rx_sg_skb;     /* 1 */
 248         int                             rx_skb_size;
 249         int                             rx_sync_size;
 250
 251         struct sk_buff                  *tx_skb[NUM_TX_BUFF];
 252         struct sk_buff                  *rx_skb[NUM_RX_BUFF];
 253
 254         /* Stats
 255          */
 256         struct emac_error_stats         estats;
 257         struct net_device_stats         nstats;
 258         struct emac_stats               stats;
 259
 260         /* Misc
 261          */
 262         int                             reset_failed;
 263         int                             stop_timeout;   /* in us */
 264         int                             no_mcast;
 265         int                             mcast_pending;
 266         int                             opened;
 267         struct work_struct              reset_work;
 268         spinlock_t                      lock;
 269 };
 270
 271 /*
 272  * Features of various EMAC implementations
 273  */
 274
 275 /*
 276  * No flow control on 40x according to the original driver
 277  */
 278 #define EMAC_FTR_NO_FLOW_CONTROL_40x    0x00000001
 279 /*
 280  * Cell is an EMAC4
 281  */
 282 #define EMAC_FTR_EMAC4                  0x00000002
 283 /*
 284  * For the 440SPe, AMCC inexplicably changed the polarity of
 285  * the "operation complete" bit in the MII control register.
 286  */
 287 #define EMAC_FTR_STACR_OC_INVERT        0x00000004
 288 /*
 289  * Set if we have a TAH.
 290  */
 291 #define EMAC_FTR_HAS_TAH                0x00000008
 292 /*
 293  * Set if we have a ZMII.
 294  */
 295 #define EMAC_FTR_HAS_ZMII               0x00000010
 296 /*
 297  * Set if we have a RGMII.
 298  */
 299 #define EMAC_FTR_HAS_RGMII              0x00000020
 300 /*
 301  * Set if we have new type STACR with STAOPC
 302  */
 303 #define EMAC_FTR_HAS_NEW_STACR          0x00000040
 304
 305
 306 /* Right now, we don't quite handle the always/possible masks on the
 307  * most optimal way as we don't have a way to say something like
 308  * always EMAC4. Patches welcome.
 309  */
 310 enum {
 311         EMAC_FTRS_ALWAYS        = 0,
 312
 313         EMAC_FTRS_POSSIBLE      =
 314 #ifdef CONFIG_IBM_NEW_EMAC_EMAC4
 315             EMAC_FTR_EMAC4      | EMAC_FTR_HAS_NEW_STACR        |
 316             EMAC_FTR_STACR_OC_INVERT    |
 317 #endif
 318 #ifdef CONFIG_IBM_NEW_EMAC_TAH
 319             EMAC_FTR_HAS_TAH    |
 320 #endif
 321 #ifdef CONFIG_IBM_NEW_EMAC_ZMII
 322             EMAC_FTR_HAS_ZMII   |
 323 #endif
 324 #ifdef CONFIG_IBM_NEW_EMAC_RGMII
 325             EMAC_FTR_HAS_RGMII  |
 326 #endif
 327             0,
 328 };
 329
 330 static inline int emac_has_feature(struct emac_instance *dev,
 331                                    unsigned long feature)
 332 {
 333         return (EMAC_FTRS_ALWAYS & feature) ||
 334                (EMAC_FTRS_POSSIBLE & dev->features & feature);
 335 }
 336
 337
 338 /* Ethtool get_regs complex data.
 339  * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
 340  * when available.
 341  *
 342  * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
 343  * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
 344  * Each register component is preceded with emac_ethtool_regs_subhdr.
 345  * Order of the optional headers follows their relative bit posititions
 346  * in emac_ethtool_regs_hdr.components
 347  */
 348 #define EMAC_ETHTOOL_REGS_ZMII          0x00000001
 349 #define EMAC_ETHTOOL_REGS_RGMII         0x00000002
 350 #define EMAC_ETHTOOL_REGS_TAH           0x00000004
 351
 352 struct emac_ethtool_regs_hdr {
 353         u32 components;
 354 };
 355
 356 struct emac_ethtool_regs_subhdr {
 357         u32 version;
 358         u32 index;
 359 };
 360
 361 #endif /* __IBM_NEWEMAC_CORE_H */